Semiconductor equipment

Abstract

There is a demand for semiconductor devices that can operate with high reliability. [Solution] The semiconductor device includes a first sense circuit SC connected between the first control terminal G and the first carrier injection terminal S of a first transistor, and a second sense circuit SC connected between the second control terminal G and the second carrier injection terminal S of a second transistor. A DC signal or AC signal can be transmitted between the reference potential VL of the first driver 22L and the reference potential VL of the second driver 23L. The reference potential VL of the first driver 22L and the terminal (P3) on the first carrier injection terminal S side of the first sense circuit SC are not directly connected via wiring or resistors, and the reference potential VL of the second driver 23L and the terminal (P3) on the second carrier injection terminal S side of the second sense circuit SC are not directly connected via wiring or resistors.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a switching element.

Prior Art Document

Patent Document

[0003]

Patent Document 1

[0004] [Summary] This disclosure provides a semiconductor device capable of performing highly reliable operation.

[0005] The semiconductor device according to this disclosure includes a switching circuit including a transistor group including a first transistor and a second transistor, a first driver including a first output terminal connected to a first control terminal of the first transistor, a second driver including a second output terminal connected to a second control terminal of the second transistor, a first sense circuit connected between a first control terminal of the first transistor and a first carrier injection terminal, and a second sense circuit connected between a second control terminal of the second transistor and a second carrier injection terminal, wherein a DC signal or an AC signal can be transmitted between a reference potential of the first driver and a reference potential of the second driver, and the reference potential of the first driver and a terminal on the first carrier injection terminal side of the first sense circuit are not directly connected via a wiring or a resistor, and the reference potential of the second driver and a terminal on the second carrier injection terminal side of the second sense circuit are not directly connected via a wiring or a resistor.

Brief Description of Drawings

[0006] [Figure 1] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment. [Figure 2] Figure 2 is a perspective view of a part of the semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a plan view of the semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a circuit diagram of a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a circuit diagram of a semiconductor device according to the first embodiment. [Figure 6] Figure 6 shows circuit diagrams of various detection circuits in a semiconductor device (Figures 6(A), 6(B), and 6(C)). [Figure 7] Figure 7 shows the circuit diagram including the amplifier and sense circuit (Figures 7(A), 7(B), and 7(C)). [Figure 8] Figure 8 is a partial circuit diagram of a module having the first type of connection structure. [Figure 9] Figure 9 is a partial circuit diagram of a module having a second type of connection structure. [Figure 10] Figure 10 is a partial circuit diagram of a module having a third type of connection structure. [Figure 11] Figure 11 shows circuit diagrams of various sense circuits (Figures 11(A), 11(B), 11(C), 11(D), 11(E), and 11(F)). [Figure 12] Figure 12 is a circuit diagram including the amplifier and sense circuit (Figures 12(A), 12(B), and 12(C)). [Figure 13] Figure 13 is a circuit diagram including the amplifier and sense circuit (Figure 13(A), Figure 13(B)). [Figure 14] Figure 14 is a circuit diagram showing an example of the connection between multiple control elements and power supply terminals. [Figure 15] Figure 15 is a block diagram of a motor drive system with modules. [Figure 16] Figure 16 is a block diagram of a voltage converter with modules. [Figure 17] Figure 17 is a plan view of a semiconductor device according to the first embodiment. [Figure 18] FIG. 18 is a bottom view of the semiconductor device according to the first embodiment. [Figure 19] FIG. 19 is a partial bottom view of the semiconductor device according to the first embodiment. [Figure 20] FIG. 20 is a longitudinal sectional view of the semiconductor device according to the first embodiment. [Figure 21] FIG. 21 is an enlarged sectional view of a part of the semiconductor device according to the first embodiment. [Figure 22] FIG. 22 is a longitudinal sectional view of the semiconductor device cut along the longitudinal direction of the control board. [Figure 23] FIG. 23 is a longitudinal sectional view of a part of the control board. [Figure 24] FIG. 24 is a longitudinal sectional view of a part of the control board. [Figure 25] FIG. 25 is a longitudinal sectional view of a part of the control board. [Figure 26] FIG. 26 is a perspective view of the semiconductor device according to the second embodiment. [Figure 27] FIG. 27 is a partial perspective view of the semiconductor device according to the second embodiment. [Figure 28] FIG. 28 is a plan view of the semiconductor device according to the second embodiment. [Figure 29] FIG. 29 is a circuit diagram of the semiconductor device according to the second embodiment. [Figure 30] FIG. 30 is a plan view of the semiconductor device according to the second embodiment. [Figure 31] FIG. 31 is a bottom view of the semiconductor device according to the second embodiment. [Figure 32] FIG. 32 is a partial bottom view of the semiconductor device according to the second embodiment. [Figure 33] FIG. 33 is a circuit diagram (FIGS. 33(A), FIGS. 33(B), FIGS. 33(C)) of a transistor applicable as a switching element.

[0007] [Detailed Description] Various exemplary embodiments will be described in detail below with reference to the drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] Figure 1 is a perspective view of the semiconductor device A1 according to the first embodiment.

[0009] The semiconductor device A1 constitutes a module with thickness. In this example, the semiconductor device A1 can be configured as an IPM (Intelligent Power Module). The thickness direction of the module is defined as "z". The first side in the thickness direction z is called the z1 side, and the second side opposite to the first side in the z direction is called the z2 side. Furthermore, one direction perpendicular to the thickness direction z is defined as the first direction "x". The first side of the first direction x is called the x1 side, and the second side opposite to the x1 side is called the x2 side. The direction perpendicular to the thickness direction z and the first direction x is defined as the second direction y. The first side of the second direction y is called the y1 side, and the second side opposite to the y1 side is called the y2 side. x1 and y1 are mutually orthogonal, y1 and z1 are mutually orthogonal, and z1 and x1 are mutually orthogonal, and these can constitute a three-dimensional Cartesian coordinate system.

[0010] The semiconductor device A1 includes a sealing resin 9. The main resin surface 91 of the sealing resin 9 faces the first side z1 in the thickness direction z. The first resin side surface 93 faces the first side x1 in the first direction x. The third resin side surface 95 faces the first side y1 in the second direction y. The main resin surface 91, the resin back surface 92 (see Figure 18), the first resin side surface 93, the second resin side surface 94 (see Figure 17), the third resin side surface 95, and the fourth resin side surface 96 (see Figure 17) may have various shapes such as flat surfaces, curved surfaces, and bent surfaces. The second conductive layer 62 may be exposed from the resin back surface 92.

[0011] The sealing resin 9 includes an insulating resin such as epoxy resin. The planar shape of the sealing resin 9 is generally rectangular. The main resin surface 91 of the sealing resin 9 is perpendicular to the thickness direction of the module. Multiple leads (41L, 42L, 33, 37, 32, 36, 31, 35, 42U, 41U) extend from one side surface in the width direction of the sealing resin 9 (first resin side surface 93). Multiple leads (45U, 46U, 43U, 44U, 5) extend from the other side surface in the width direction of the sealing resin 9 (second resin side surface opposite to the first resin side surface 93), and this side surface has a recess (921). The third resin side surface 95 of the sealing resin 9 has multiple recesses (951, 931). The side surface of the sealing resin 9 opposite to the third resin side surface 95 also has multiple recesses (961, 941).

[0012] Figure 2 is a perspective view of a part of the semiconductor device according to the first embodiment. This figure shows the semiconductor device shown in Figure 1 with the sealing resin 9 removed.

[0013] The semiconductor device A1 comprises a main board 6 and a control board 7.

[0014] A first upper arm switching element 11U, a first lower arm switching element 11L, a second upper arm switching element 12U, a second lower arm switching element 12L, a third upper arm switching element 13U, and a third lower arm switching element 13L are fixed to the main substrate 6. The switching elements are transistors. If the transistors are field-effect transistors (FETs), and if they are N-channel type FETs, the drain (carrier receiving terminal) is fixed to each electrode provided on the main substrate 6, and the source (carrier injection terminal) and gate (control terminal) are exposed on the opposite side. The switching elements in this example are N-channel type FETs. The semiconductor device A1 can realize a three-phase electrical circuit equipped with six transistors as switching elements. The transistors formed on the main substrate 6 can be made of silicon (Si), but for high-voltage applications, they can also be made of silicon carbide (SiC) or gallium nitride (GaN). MOS (metal oxide semiconductor) type FETs can also be used as transistors.

[0015] A first upper arm control element 21U, a first lower arm control element 21L, a second upper arm control element 22U, a second lower arm control element 22L, a third upper arm control element 23U, and a third lower arm control element 23L are fixed to the control board 7. Each of these control elements is a circuit chip and can be made from semiconductor chips. An example of the control board 7 is a printed circuit board (PCB).

[0016] The semiconductor chip formed on the control substrate 7 can be made of silicon (Si). The energy band gap of the semiconductor material (SiC or GaN) constituting the transistor formed on the main substrate 6 may be set higher than the energy band gap of the semiconductor material (Si) constituting the transistor included in the semiconductor chip formed on the control substrate 7. The semiconductor materials used for the main substrate 6 and the control substrate 7 may be the same. Other compound semiconductor materials can also be used as the semiconductor material constituting the transistor.

[0017] The lead group in semiconductor device A1 includes, for example, a first main power lead 31, a main ground lead 33, a first output lead 35, a plurality of control leads 5, a first upper arm secondary control power lead 41U, a first upper arm secondary control ground lead 42U, a second main power lead 32, a second output lead 36, a third output lead 37, a lower arm secondary control power lead 41L, a lower arm secondary control ground lead 42L, a second upper arm secondary control power lead 43U, a second upper arm secondary control ground lead 44U, a third upper arm secondary control power lead 45U, and a third upper arm secondary control ground lead 46U.

[0018] The semiconductor device A1 may be equipped with a sensor 18, such as a thermistor, if necessary.

[0019] The control board 7 may have support leads 78 and support leads 79. The support leads 78 and support leads 79 are fixed near both ends in the second direction y of the main surface 7a of the control board 7. Various methods such as joining, engaging, and fitting may be used to fix the support leads 78 and support leads 79. The support leads 78 and support leads 79 may be used, for example, in a manufacturing method of a semiconductor device A1, for the purpose of enabling the control board 7 to be supported via a lead frame (not shown) by fixing the support leads 78 and support leads 79, which form part of a lead frame, to the control board 7. This lead frame may include, for example, a plurality of control leads 5. The control board 7 may have a first side surface 7c and a second side surface 7d. The first side surface 7c and the second side surface 7d are located at the ends in the second direction y, and their positions in the y direction are different.

[0020] Figure 3 is a plan view of the semiconductor device according to the first embodiment. Note that only the outline of the sealing resin 9 is shown so that the inside of the module is visible.

[0021] The main board 6 has multiple island-shaped electrodes (WLD11, WUD11, WLD12, WUD13, WLD13, WGND2) on one side of an insulating board. These electrodes (WLD11, WUD11, WLD12, WUD13, WLD13) are arranged in order along the longitudinal direction of the module. The first lower arm switching element 11L is fixed to the first electrode (WLD11). The first upper arm switching element 11U is fixed to the second electrode (WUD11). The second lower arm switching element 12L is fixed to the third electrode (WLD12). The second upper arm switching element 12U and the third upper arm switching element 13U are fixed to the fourth electrode (WUD13). The third lower arm switching element 13L is fixed to the fifth electrode (WLD13).

[0022] The sixth electrode (WGND2) provides the ground potential (GND2) in the switching circuit. The sources of the switching elements (11L, 12L, 13L) that make up the lower arm are connected to the sixth electrode (WGND2) via bonding wires (WLS11, WLS12, WLS13), respectively. The bonding wire is a wiring. The bonding wire in this description may include metals such as Al (aluminum), Au (gold), Cu (copper), or alloys thereof. In place of the bonding wire, other conductive members such as metal plate members or pattern wiring may be used.

[0023] The island-shaped electrodes (WLD11, WUD11, WLD12, WUD13, WLD13, WGND2) are electrode patterns, each connected to a lead (35, 31, 36, 32, 37, 33).

[0024] Lead (35) is connected to the node between the first upper arm switching element 11U and the first lower arm switching element 11L, and can be used as the output terminal for one of the three phases (U, V, W) when outputting a drive signal. Similarly, lead (36) is connected to the node between the second upper arm switching element 12U and the second lower arm switching element 12L, and can be used as the output terminal for one of the three phases (U, V, W) when outputting a drive signal. Similarly, lead (37) is connected to the node between the third upper arm switching element 13U and the third lower arm switching element 13L, and can be used as the output terminal for one of the three phases (U, V, W) when outputting a drive signal.

[0025] Next, we will explain the connection relationships of each switching element.

[0026] The gate of the first lower arm switching element 11L is connected to the wiring of the control board 7 via a bonding wire (WLGS11), and this wiring is connected to the amplifier output terminal (one end of the sense circuit (see Figure 4)) in the first lower arm control element 21L. The source of the first lower arm switching element 11L is connected to the wiring of the control board 7 via a bonding wire (WLSS11), and this wiring is connected to the other end of the sense circuit in the first lower arm control element 21L. The drain of the first lower arm switching element 11L is fixed to an electrode (WLD11) on the main board 6 and electrically connected. The source of the first lower arm switching element 11L is connected to an electrode at ground potential (WGND2) via a bonding wire (WLS11).

[0027] The gate of the first upper arm switching element 11U is connected to the wiring of the control board 7 via a bonding wire (WUGS11), and this wiring is connected to the amplifier output terminal (one end of the sense circuit) in the first upper arm control element 21U. The source of the first upper arm switching element 11U is connected to the wiring of the control board 7 via a bonding wire (WUSS11), and this wiring is connected to the other end of the sense circuit in the first upper arm control element 21U. The drain of the first upper arm switching element 11U is fixed to an electrode (WUD11) on the main board 6 and electrically connected. The source of the first upper arm switching element 11U is connected to the drain of the first lower arm switching element 11L via a bonding wire (W11) and an electrode (WLD11).

[0028] The gate of the second lower arm switching element 12L is connected to the wiring of the control board 7 via a bonding wire (WLGS12), and this wiring is connected to the amplifier output terminal (one end of the sense circuit) in the second lower arm control element 22L. The source of the second lower arm switching element 12L is connected to the wiring of the control board 7 via a bonding wire (WLSS12), and this wiring is connected to the other end of the sense circuit in the second lower arm control element 22L. The drain of the second lower arm switching element 12L is fixed to an electrode (WLD12) on the main board 6 and electrically connected. The source of the second lower arm switching element 12L is connected to an electrode (WGND2) at ground potential via a bonding wire (WLS12).

[0029] The gate of the second upper arm switching element 12U is connected to the wiring of the control board 7 via a bonding wire (WUGS12), and this wiring is connected to the amplifier output terminal (one end of the sense circuit) in the second upper arm control element 22U. The source of the second upper arm switching element 12U is connected to the wiring of the control board 7 via a bonding wire (WUSS12), and this wiring is connected to the other end of the sense circuit in the second upper arm control element 22U. The drain of the second upper arm switching element 12U is fixed to an electrode (WUD13) on the main board 6 and electrically connected. The source of the second upper arm switching element 12U is connected to the drain of the second lower arm switching element 12L via a bonding wire (W22) and an electrode (WLD12).

[0030] The gate of the third upper arm switching element 13U is connected to the wiring of the control board 7 via a bonding wire (WUGS13), and this wiring is connected to the amplifier output terminal (one end of the sense circuit) in the third upper arm control element 23U. The source of the third upper arm switching element 13U is connected to the wiring of the control board 7 via a bonding wire (WUSS13), and this wiring is connected to the other end of the sense circuit in the third upper arm control element 23U. The drain of the third upper arm switching element 13U is fixed to an electrode (WUD13) on the main board 6 and electrically connected. The source of the third upper arm switching element 13U is connected to the drain of the third lower arm switching element 13L via a bonding wire (W33) and an electrode (WLD13).

[0031] The gate of the third lower arm switching element 13L is connected to the wiring of the control board 7 via a bonding wire (WLGS13), and this wiring is connected to the amplifier output terminal (one end of the sense circuit) in the third lower arm control element 23L. The source of the third lower arm switching element 13L is connected to the wiring of the control board 7 via a bonding wire (WLSS13), and this wiring is connected to the other end of the sense circuit in the third lower arm control element 23L. The drain of the third lower arm switching element 13L is fixed to an electrode (WLD13) on the main board 6 and electrically connected. The source of the third lower arm switching element 13L is connected to an electrode (WGND2) at ground potential via a bonding wire (WLS13).

[0032] The input lead (51) is supplied with the first power supply potential VS1. The lead (51) is connected to the wiring of the control board 7 via a bonding wire (WVS1), and through this wiring it is connected to the power lines of each control element (21L, 21U, 22L, 22U, 23L, 23U).

[0033] The input lead (52) is supplied with a first ground potential (GND1). The lead (52) is connected to the wiring of the control board 7 via a bonding wire (WGND1), and through the wiring is connected to the ground lines of each control element (21L, 21U, 22L, 22U, 23L, 23U).

[0034] Depending on the structure of the control elements (21L, 21U, 22L, 22U, 23L, 23U), additional power lines can be provided. For example, if each control element (21L, 21U, 22L, 22U, 23L, 23U) is equipped with a coil, power can be supplied to the secondary coil separately from the primary coil.

[0035] Lead (41L) is connected to the wiring of the control board 7 via bonding wire (W41L), and power potential may be supplied to the control elements (21L, 22L, 23L) on the lower arm side via this wiring. Lead (42L) is connected to the wiring of the control board 7 via bonding wire (W42L), and ground potential may be supplied to the control elements (21L, 22L, 23L) on the lower arm side via this wiring.

[0036] Similarly, the leads (41U, 43U, 45U) are connected to the wiring of the control board 7 via bonding wires (W41U, W43U, W45U), and a power supply potential (VS3) may be supplied to the secondary coils of the upper arm control elements (21U, 22U, 23U) via these wires as needed. The leads (42U, 44U, 46U) are connected to the wiring of the control board 7 via bonding wires (W42U, W44U, W46U), and a ground potential (GND3) may be supplied to the secondary coils of the upper arm control elements (21U, 22U, 23U) via these wires as needed.

[0037] The other leads (532, 53b, 53c, 531, 537, 534, 538, 533, 539, 535, 53a, 536) are also connected to the wiring of the control board 7 via bonding wires (87).

[0038] A pair of electrodes (first temperature measuring unit 618 and second temperature measuring unit 619) may be fixed on an insulating substrate constituting the main board 6, and these electrodes may be joined by a sensor 18. If the sensor 18 is a thermistor, the temperature of the main board 6 can be monitored. The first temperature measuring unit 618 and the second temperature measuring unit 619 are connected to the control board 7 via bonding wires, and temperature detection outputs can be taken from leads (53b, 53c).

[0039] Figure 4 is a circuit diagram of a semiconductor device according to the first embodiment.

[0040] The input lead (51) is supplied with the first power supply potential VS1, and the lead (52) is supplied with the first ground potential (GND1). The first power supply potential VS1 is supplied to multiple control elements on the lower arm side (21L, 22L, 23L) and multiple control elements on the upper arm side (21U, 22U, 23U). The first ground potential (GND1) is also supplied to multiple control elements on the lower arm side (21L, 22L, 23L) and multiple control elements on the upper arm side (21U, 22U, 23U). The first ground potential GND1 can also be supplied from other leads (537, 539, 53a, etc.).

[0041] Each control element (21U, 22U, 23U, 21L, 22L, 23L) contains an amplifier (AP(21U), AP(22U), AP(23U), AP(21L), AP(22L), AP(23L)). Each amplifier (AP(21U), AP(22U), AP(23U), AP(21L), AP(22L), AP(23L)) may include a regulator and protection circuit, and the amplifier output is input to the control terminal (gate G) of the corresponding switching element (11U, 12U, 13U, 11L, 12L, 13L).

[0042] The carrier injection terminal (source S) of each switching element (11U, 12U, 13U, 11L, 12L, 13L) is connected to the control terminal (gate G) of each switching element via the corresponding sense circuit (SC(21U), SC(22U), SC(23U), SC(21L), SC(22L), SC(23L)).

[0043] Multiple switching elements (11U, 12U, 13U, 11L, 12L, 13L) constitute a switching circuit applicable to an inverter or DC / DC converter. The carrier receiving terminal (drain D) of the upper arm switching elements (11U, 12U, 13U) is connected to the second power supply potential (VS2). The carrier injection terminal (source S) of the lower arm switching elements (11L, 12L, 13L) is connected to the second ground potential (GND2). The carrier injection terminal (source S) of the upper arm switching elements (11U, 12U, 13U) is connected to the carrier receiving terminal (drain D) of the lower arm switching elements (11L, 12L, 13L). The upper arm switching elements and the lower arm switching elements in each channel providing three phases can constitute a half-bridge circuit.

[0044] Furthermore, a parasitic diode (not shown) is connected between the source S and drain D of each transistor, with its anode connected to source S and its cathode connected to drain D.

[0045] When control signals for output signal generation are input to the amplifiers of each control element (AP(21U), AP(22U), AP(23U), AP(21L), AP(22L), AP(23L)) via each lead (531, 533, 535, 532, 534, 536), each amplifier outputs a switching signal to the gate G of each switching element (11U, 12U, 13U, 11L, 12L, 13L). By controlling the ON / OFF state of each switching element (11U, 12U, 13U, 11L, 12L, 13L), a three-phase output signal is output from the output terminals (35, 36, 37). The output signal output from the module can be used as a motor drive signal. Alternatively, by placing a transformer, rectifier, and smoothing circuit downstream of the module, it can be used as a DC / DC converter. When used in a DC / DC converter, four switching elements may be used to obtain a two-phase output signal.

[0046] The sources S of the switching elements (11L, 12L, 13L) on the lower arm side are connected to sense circuits (SC(21L), SC(22L), SC(23L)), respectively. Each sense circuit is a circuit that includes at least one element selected from a group of elements consisting of capacitors, resistors, and Zener diodes. In the case of a circuit where the source S and sense circuit are not connected, the sense circuit is connected between the ground potential on the amplifier side and the gate G of the switching element. In this case, at the moment a current I flows through each switching element, the potential of the source S of the switching element fluctuates due to the parasitic resistance in the current path and the inductance of bonding wires and frames, etc. This change in potential (ΔV) is the product of the change in current I over time (dI / dt) and the inductance L (= L × (dI / dt)). Therefore, in the case of a circuit where the source S and sense circuit are not connected, the change in potential (ΔV) can be reduced by performing the switching slowly.

[0047] On the other hand, in the module of this embodiment, one terminal of the sense circuit SC is connected to the source S, and the source-side terminal of the sense circuit SC is not directly connected to the ground potential of the amplifier AP via wiring or a resistor. The other terminal of the sense circuit SC is connected to the gate G. That is, changes in the state of the source S are transmitted to the gate G via the sense circuit SC. The sense circuit SC is also part of the gate driver including the amplifier AP, and the potential of one terminal of the sense circuit SC is applied to the output signal of the amplifier AP and input to the gate G. The sense circuit SC detects the potential change of the source S and corrects the output signal of the amplifier AP input to the gate G according to the detected amount. As a result, the effect of potential changes (ΔV) can be suppressed even without slow switching, enabling high-speed operation of the switching element.

[0048] The connection relationships of the switching elements on the upper arm side (11U, 12U, 13U) are the same as those of the switching elements on the lower arm side. However, the potential applied to the gate G on the upper arm side can be higher than the potential applied to the gate G on the lower arm side. Therefore, the output voltage of the amplifiers on the upper arm side (AP(21U), AP(22U), AP(23U)) can be made higher than the output voltage of the amplifiers on the lower arm side, or the input voltage to these amplifiers can be set higher than the input voltage to the amplifiers on the lower arm side.

[0049] Let's consider three-phase AC voltages with phase differences of 120 degrees. When generating three-phase AC voltages using pulse width modulation (PWM), a larger pulse width results in a higher amplitude of the AC voltage, while a smaller pulse width results in a lower amplitude. Let's assume a case where a load (e.g., a motor or transformer coil) is connected to the output terminals of the module. The direction of the current flowing from the output terminals to the coil is defined as positive, and conversely, the direction of the current flowing from the coil to the output terminals is defined as negative. When three-phase AC voltages (U, V, W) are output from the three output terminals (35, 36, 37) of the module, for example, a positive current flows in the V-phase voltage, and negative currents flow in the U-phase and W-phase voltages. Here, in the channels where a positive current is flowing and the channels where a negative current is flowing, the switching elements on the lower arm corresponding to these channels may be turned ON simultaneously.

[0050] For example, consider the case where the lower arm switching element (12L) corresponding to the V-phase output terminal (36) and the lower arm switching element (13L) corresponding to the W-phase output terminal (37) are turned ON simultaneously. A positive current flows in the V-phase and a negative current flows in the W-phase. Let the position of the source S of the switching element (12L) be point "A". Let the position of the source S of the switching element (13L) be point "B". Let the position of the lead (33) connected to the second ground potential GND2 be point "N".

[0051] Assume that the potential at point A is negative relative to the potential at point N, and that current flows from point N through point A to the output terminal (36) of the V phase, resulting in a positive current flowing towards the load. Assume that the potential at point B is positive relative to the potential at point N, and that a negative current flows from the load to the output terminal (37) of the W phase, passes through point B, and reaches point N.

[0052] Point A is connected to one end of the sense circuit SC(22L), but the other end of the sense circuit SC(22L) is not directly connected to the first ground potential GND1 on the amplifier AP(22L) side via wiring or a resistor. Similarly, point B is connected to one end of the sense circuit SC(23L), but the other end of the sense circuit SC(23L) is not directly connected to the first ground potential GND1 on the amplifier AP(23L) side via wiring or a resistor. In other words, the separation between points A and B results in a very large impedance between them.

[0053] On the other hand, in a comparative structure that can be compared with the embodiment, points A and B are connected via wiring (resistance / inductance) which acts as a parasitic element to which the first ground potential GND1 is supplied. In this case, current flows between points A and B through the parasitic element. In the case of a discrete circuit structure without element integration, even in the comparative structure, the parasitic impedance between points A and B was sufficiently large, and the current between points A and B could be suppressed. However, with modularization, such suppression is becoming more difficult. Generally, the parasitic resistance value connected to source S is on the order of mΩ, and the parasitic resistance value connected to the power line including the first ground potential is also on the order of mΩ. Therefore, the ratio of the current flowing on the power line side to the current flowing through the second ground potential GND2 between points A and B is inversely proportional to the resistance values ​​in these paths. Thus, in the comparative structure, the current flowing on the power line side becomes large enough that it cannot be ignored. For example, if the current flowing through each switching element is on the order of tens of amperes, the current flowing on the power line side will be on the order of amperes. Furthermore, even when the switching element (12L) on point A is OFF, if the switching element (13L) on point B is ON and a potential difference is generated between point B and point N, the potential at point A will also fluctuate, and current will flow from point B to points A and N.

[0054] In the comparative structure, a resistor can be inserted between one end of the sense circuit and the first ground potential GND1 on the amplifier side to suppress current via parasitic impedance. However, even in this case, for example, if the switching element (13L) is turned ON and the potential at point N rises, the source potential (point A) of the OFF switching element (12L) rises, and the gate potential of the switching element (12L) attempts to rise via the sense circuit. In this case, the amplifier AP (22L) connected to the switching element (12L) may attempt to lower the output potential to gate G and try to flow a large current to the first ground potential GND1 side. Such unintended currents reduce the reliability of operation in the semiconductor device.

[0055] Unlike the comparative structure described above, the module of this embodiment does not have the source terminal of the sense circuit SC directly connected to the ground potential of the amplifier AP via wiring or a resistor. Therefore, it is possible to suppress the flow of unintended current in the comparative structure and enable reliable operation.

[0056] Figure 5 is a circuit diagram of a semiconductor device according to the first embodiment.

[0057] In this example, only lead (52) is connected to the first ground potential GND1. The rest of the structure is the same as that shown in Figure 4.

[0058] As described above, semiconductor device A1 (Figures 1-5) includes a switching circuit equipped with a group of transistors (switching elements (11U, 12U, 13U, 11L, 12L, 13L)). The two transistors on the lower arm side are designated as the first transistor (12L) and the second transistor (13L). Semiconductor device A1 includes a printed circuit board (control board 7) equipped with a first driver (22L), a second driver (23L), a first sense circuit (SC(22L)), and a second sense circuit (SC(23L)), an insulating heat dissipation circuit board (main board 6) equipped with a switching circuit (switching elements (11U, 11L, 12U, 12L, 13U, 13L)), and an outer casing (sealing resin 9) covering the printed circuit board and the insulating heat dissipation circuit board. The material of the outer casing is not limited to resin; any insulating material such as glass or ceramic may be used.

[0059] The switching circuit of the semiconductor device includes a first transistor (12L) whose first carrier injection terminal (S) is connected to a second ground potential (GND2), a second transistor (13L) whose second carrier injection terminal (S) is connected to a second ground potential (GND2), a third transistor (12U) whose third carrier injection terminal (S) is connected to the first carrier receiving terminal (drain D) of the first transistor (12L) and whose third carrier receiving terminal (D) is connected to a second power supply potential (VS2), and a fourth transistor (13U) whose fourth carrier injection terminal (S) is connected to the second carrier receiving terminal (D) of the second transistor (13L) and whose fourth carrier receiving terminal (D) is connected to a power supply potential (VS2).

[0060] Furthermore, the switching circuit of the semiconductor device (switching elements (11U, 11L, 12U, 12L, 13U, 13L)) includes a fifth transistor (11L) whose fifth carrier injection terminal (S) is connected to ground potential, and a sixth transistor (11U) whose sixth carrier injection terminal (S) is connected to the fifth carrier receiving terminal (D) of the fifth transistor (11L), and whose sixth carrier receiving terminal (D) is connected to power supply potential (VS2).

[0061] Figure 6 shows circuit diagrams of various detection circuits in a semiconductor device (Figures 6(A), 6(B), and 6(C)).

[0062] Figure 6(A) shows an example in which a sensor 18 is connected between a pair of leads (53b, 53c). A thermistor can be used as the sensor 18. A thermistor is an element whose resistance changes significantly with temperature changes. Thermistor materials include metal oxides, perovskite oxides, polymers containing conductive fillers, or semiconductors such as silicon and GaAs.

[0063] Figure 6(B) shows a lead (537) connected to the first monitor node 18A in the circuit within the main board 6 or the control board 7. The first monitor node 18A is a node that can detect a short circuit between two points. For example, it monitors the potential of one node of a bypass capacitor connected between the power supply potential and ground potential that supplies power to the amplifier. If the bypass capacitor shorts out, the potential will fluctuate significantly, allowing the short circuit to be detected.

[0064] Figure 6(C) shows a lead (539) connected to the second monitor node 18B in the circuit within the main board 6 or the control board 7. The second monitor node 18B is a node that can detect abnormalities when they occur. For example, it can monitor the power supply potential of an amplifier and determine that an abnormality has occurred if the power supply potential falls outside the specified range.

[0065] Figure 7 shows the circuit diagram including the amplifier and sense circuit (Figures 7(A), 7(B), and 7(C)).

[0066] In these diagrams, the switching element (Q) represents one of the switching elements (11U, 12U, 13U, 11L, 12L, 13L). The sense circuit SC represents one of the sense circuits (SC(21U), SC(22U), SC(23U), SC(21L), SC(22L), SC(23L)). The amplifier AP represents one of the amplifiers (AP(21U), AP(22U), AP(23U), AP(21L), AP(22L), AP(23L)). The amplifier AP is assumed to be an amplifier having an output terminal connected to gate G, and to be connected to a low-potential VL (reference potential) ground potential and a high-potential VH power line, and to be in operation. A simple example of the structure of amplifier AP is a CMOS (complementary metal-oxide-semiconductor) inverter. A CMOS operational amplifier can also be used as amplifier AP. Numerous amplifiers are known, and the ideal structure of an amplifier AP is not particularly limited.

[0067] Figure 7(A) shows the first type of connection structure shown in the above diagram. In this connection structure, the bypass capacitor C2 shown in Figures 7(B) and 7(C) is not connected between the ground line and the power line of amplifier AP, but it may be connected. The first point P1 on the ground line of amplifier AP is not directly connected to the third point P3, which is one end of the sense circuit SC connected to the source S of the switching element Q. Of course, the first point P1 can be connected to the third point P3 via the output terminal of amplifier AP and the other end of the sense circuit SC, but this connection is not a direct connection via wiring or resistors. The output signal SOUT of amplifier AP is input to the gate G of switching element Q via the fourth point P4. The source S of switching element Q is connected to the second ground potential GND2. The presence of the sense circuit SC between the source S and the gate G enables high-speed switching that suppresses the effects of potential fluctuations in the source S. Since the third point P3 and the first point P1 are not directly connected, unintended currents mediated by the aforementioned parasitic elements can be suppressed, thereby improving the reliability of the semiconductor device's operation.

[0068] Figure 7(B) shows the second type of connection structure. In this connection structure, the first point P1 on the ground line of amplifier AP and the third point P3, which is one end of the sense circuit SC, are connected via the first capacitor C1. A bypass capacitor C2 is connected between the ground line of amplifier AP and the power supply line. Similar to the connection structure in Figure 7(A), the sense circuit SC is interposed between the source S and the gate G, enabling high-speed switching that suppresses the effects of potential fluctuations in the source S. Since the third point P3 and the first point P1 are connected via the first capacitor C1, unintended currents through the aforementioned parasitic elements are suppressed, improving the reliability of the semiconductor device's operation. The first capacitor C1 can transmit AC components between the first point P1 and the third point P3. The capacitance (C1) of the first capacitor C1 can be set to, for example, (1pF ≤ C1 ≤ 4700pF), but is not limited to this. When the potential of the source S of the switching element fluctuates, the first capacitor C1 transmits the high-frequency component to the first point P1, thereby suppressing the effects of the fluctuation.

[0069] Figure 7(C) shows the third type of connection structure. In this connection structure, the second point P2 on the power line of amplifier AP and the third point P3, which is one end of the sense circuit SC, are connected via a capacitor (C1A). A bypass capacitor C2 is connected between the ground line of amplifier AP and the power line.

[0070] In the connection structure shown in Figure 7(C), similar to the connection structure in Figure 7(A), the sense circuit SC is interposed between the source S and the gate G, enabling high-speed switching while suppressing the effects of potential fluctuations in the source S. Since the third point P3 and the first point P1 are not directly connected, unintended currents mediated by the aforementioned parasitic elements are suppressed, improving the reliability of the semiconductor device's operation.

[0071] Capacitor (C1A) can transmit the AC component from the third point P3 to the second point P2. The AC component transmitted to the second point P2 can then be routed to the ground line via the bypass capacitor C2. When the potential of the source S of the switching element fluctuates, capacitor (C1A) transmits the high-frequency component to the second point P2, suppressing the effects of the fluctuation. The capacitance range of capacitor (C1A) and the capacitance range of bypass capacitor C2 can be set to be the same as, for example, the capacitance range of (C1).

[0072] The above structure prevents unintended current from flowing to a switching element in another channel that is turned OFF when a switching element in one channel is turned ON. Since unintended current can lead to malfunctions of switching elements, suppressing this can improve the reliability of the semiconductor device.

[0073] As described above, semiconductor device A1 (Figures 1-5) includes a switching circuit (circuit on the main board 6, inverter (converter)) equipped with a group of transistors (switching elements (11U, 12U, 13U, 11L, 12L, 13L)) consisting of multiple transistors. Above, semiconductor device A1 equipped with a current suppression structure between node A and node B was disclosed. If the two transistors on the lower arm side of Figure 3 are the first transistor (12L) and the second transistor (13L), then the semiconductor device includes a switching circuit equipped with a group of transistors including the first transistor (12L) and the second transistor (13L). Furthermore, semiconductor device A1 includes a first driver (control element (22L)) equipped with a first output terminal connected to the first control terminal (G) of the first transistor (12L), and a second driver (control element (23L)) equipped with a second output terminal connected to the second control terminal (G) of the second transistor (13L).

[0074] Furthermore, semiconductor device A1 includes a first sense circuit (SC(22L)) connected between the first control terminal (G) and the first carrier injection terminal (S) of the first transistor (12L), and a second sense circuit (SC(23L)) connected between the second control terminal (G) and the second carrier injection terminal (S) of the second transistor (13L). Here, as shown in Figures 7(A) to 7(C), a DC signal or an AC signal can be transmitted between the reference potential (low potential VL) of the first amplifier AP (first driver (22L)) and the reference potential VL of the second amplifier AP (second driver (23L)). Also, the reference potential (VL) of the first amplifier AP (first driver (22L)) and the terminal (third point P3) on the first carrier injection terminal (S) side of the first sense circuit (SC(22L)) are not directly connected via wiring or resistors. The reference potential (VL) of the second amplifier AP (second driver (23L)) and the terminal (third point P3) on the second carrier injection terminal (S) side of the second sense circuit (SC (23L)) are not directly connected via wiring or resistors. The structures in Figures 7(A) to 7(C) can be applied to all connections between drivers and switching elements.

[0075] The reference potential (VL) of the first driver (22L) and the terminal on the first carrier injection terminal (S) side of the first sense circuit (SC(22L)) are connected via the first capacitor C1 (Figure 7), and the reference potential (VL) of the second driver (23L) and the terminal on the second carrier injection terminal (S) side of the second sense circuit (SC(23L)) are connected via the second capacitor (first capacitor C1: Figure 7).

[0076] The power supply potential (VH) of the first driver (22L) is connected to the terminal on the first carrier injection terminal (S) side of the first sense circuit (SC(22L)) via the first capacitor (capacitor C1A: Figure 7(C)), and the power supply potential (VH) of the second driver (23L) is connected to the terminal on the second carrier injection terminal (S) side of the second sense circuit (SC(23L)) via the second capacitor (capacitor C1A: Figure 7(C)).

[0077] The first driver (22L) is equipped with a first bypass capacitor (C2: Figures 7(B) and 7(C)) connected between its power supply potential (VH) and the reference potential (VL), and the second driver (23L) is equipped with a second bypass capacitor (C2: Figures 7(B) and 7(C)) connected between its power supply potential (VH) and the reference potential (VL).

[0078] The reference potential (VL) of the first driver (22L) and the reference potential (VL) of the second driver (23L) are connected in a manner that allows for the transmission of DC signals. The other drivers (21L, 21U, 22U, 23U) are also connected in a manner that allows for the transmission of DC signals between their corresponding reference potentials (VL). These connections may also be made in a manner that allows for the transmission of AC signals.

[0079] Figure 8 is a partial circuit diagram of a module having the first type of connection structure (Figure 7(A)).

[0080] The diagram shows the lower arm-side switching elements (12L, 13L) connected to some of the module's output terminals (36, 37), and the control elements (22L, 23L) that control them. Each control element (22L, 23L) contains an amplifier (AP(22L), AP(23L)). The amplifiers (AP(22L), AP(23L)) may contain other elements, but at a minimum, they are equipped with output amplifiers (OAP(22L), OAP(23L)) on the gate G side of the switching elements. In this example, the output amplifiers (OAP(22L), OAP(23L)) are inverters in which a first transistor Q1, which is an N-channel FET, and a second transistor Q2, which is a P-channel FET, are connected in series. The FETs can be MOS-type FETs, and the output amplifiers (OAP(22L), OAP(23L)) can be CMOS inverters. The output amplifiers (OAP(22L), OAP(23L)) can employ structures such as buffer amplifiers, operational amplifiers, or operational amplifiers including CMOS.

[0081] The source of the first transistor Q1 (e.g., NMOS-FET) in the output amplifier is connected to a low-potential VL ground line (first ground potential GND1). The source of the second transistor Q2 (e.g., PMOS-FET) is connected to a high-potential VH power supply line (first power supply potential VS1). The first transistor Q1 and the second transistor Q2 are connected in series, and their nodes become the output terminals of the output amplifier, connected to the gates G of their respective switching elements (12L, 13L). The gates of the first transistor Q1 and the second transistor Q2 are connected to the input terminals of the output amplifiers (OAP(22L), OAP(23L)), and control signals are applied from leads (534, 536). When the first transistor Q1 is ON, the second transistor Q2 is OFF, and the output potential of the output amplifier is low-potential VL. When the first transistor Q1 is OFF, the second transistor Q2 is ON, and the output potential of the output amplifier is high-potential VH. This output potential is transmitted to the gate G. When a high potential VH is applied to gate G, the switching elements (12L, 13L) turn ON. When a low potential VL is applied to gate G, the switching elements (12L, 13L) turn OFF.

[0082] Each sense circuit (SC(22L), SC(23L)) is equipped with a sense circuit capacitor C, a resistor R, and a Zener diode ZD. The source S of the switching elements (12L, 13L) is connected to one end of the sense circuit (SC(22L), SC(23L)). The other end of the sense circuit (SC(22L), SC(23L)) is connected to the gate G of the switching element (12L, 13L). Since the potential of the source S is not directly connected to the first ground line that provides the low potential VL of the amplifier, this has the effect of preventing unwanted current from flowing, as described above.

[0083] When the potential of the source S of the switching element fluctuates, the sense circuit capacitor C transmits high-frequency components to the gate G of the switching element, suppressing the effects of fluctuations in the gate-source voltage (Vgs). The exemplary range of capacitance (C) of the sense circuit capacitor C is 1pf ≤ C ≤ 4700pf, but it is not limited to this range.

[0084] The resistor R transmits the DC component of the potential of the source S to the gate G. Even when the power is off, the resistor R short-circuits the source S and gate G, determining their potentials. An example range for the resistance value (R) of the resistor R is 10kΩ ≤ R ≤ 100kΩ, but it is not limited to this range. The Zener diode ZD breaks down when the gate breakdown voltage of the switching element is about to be exceeded, and reduces the difference in gate-source voltage (Vgs) by flowing a reverse current. If the voltage becomes negative, it reduces the difference in gate-source voltage (Vgs) by flowing a forward current.

[0085] Figure 9 is a partial circuit diagram of a module having a second type of connection structure (Figure 7(B)).

[0086] One difference from the structure shown in Figure 8 of the same figure is that a first capacitor C1 is connected between the ground line that provides the low potential VL in the output amplifier (OAP(22L), OAP(23L)) and one end of the source S side of the sense circuit (SC(22L), SC(23L)). Another difference is that a bypass capacitor C2 is connected between the ground line that provides the low potential VL in the output amplifier (OAP(22L), OAP(23L)) and the power supply line that provides the high potential VH. The rest of the structure is the same as that shown in Figure 8. The effect of this structure is as explained in Figure 7(B).

[0087] Figure 10 is a partial circuit diagram of a module having a third type of connection structure (Figure 7(C)).

[0088] One difference from the structure shown in Figure 8 of the same figure is that a capacitor (C1A) is connected between the power supply line that provides the high potential VH in the output amplifier (OAP(22L), OAP(23L)) and one end of the source S side of the sense circuit (SC(22L), SC(23L)). Another difference is that a bypass capacitor C2 is connected between the ground line that provides the low potential VL in the output amplifier (OAP(22L), OAP(23L)) and the power supply line that provides the high potential VH. The rest of the structure is the same as that shown in Figure 8. The effect of this structure is as explained in Figure 7(C).

[0089] Figure 11 shows circuit diagrams of various sense circuits (Figures 11(A), 11(B), 11(C), 11(D), 11(E), and 11(F)).

[0090] The sense circuit SC represents one of the sense circuits (SC(21U), SC(22U), SC(23U), SC(21L), SC(22L), SC(23L)).

[0091] The sense circuit SC in Figure 11(A) includes a sense circuit capacitor C connected between the gate G and source S of the switching element. This structure makes it possible to suppress the effects of AC fluctuations in the potential of the source S.

[0092] The sense circuit SC in Figure 11(B) includes a resistor R connected between the gate G and source S of the switching element. This structure makes it possible to suppress the effects of DC fluctuations in the potential of the source S.

[0093] The sense circuit SC in Figure 11(C) includes a Zener diode ZD connected between the gate G and source S of the switching element. With this structure, if the gate breakdown voltage of the switching element is about to be exceeded, it breaks down and allows a reverse current to flow, thereby reducing the difference in gate-source voltage (Vgs). If the voltage becomes negative, it allows a forward current to flow, thereby reducing the difference in gate-source voltage (Vgs).

[0094] The sense circuit SC in Figure 11(D) includes a sense circuit capacitor C and a resistor R connected in parallel between the gate G and source S of the switching element. This structure makes it possible to suppress the effects of AC and DC fluctuations in the potential of the source S.

[0095] The sense circuit SC in Figure 11(E) includes a resistor R and a Zener diode ZD connected in parallel between the gate G and source S of the switching element. This structure suppresses the effects of DC fluctuations in the potential of the source S, while also suppressing effects such as when the difference between the potential of the gate G and the potential of the source S exceeds a threshold.

[0096] The sense circuit SC in Figure 11(F) includes a sense circuit capacitor C and a Zener diode ZD connected in parallel between the gate G and source S of the switching element. This structure suppresses the effects of AC fluctuations in the potential of the source S, while also suppressing effects such as when the difference between the potential of the gate G and the potential of the source S exceeds a threshold.

[0097] Furthermore, as shown in Figures 9 and 10 above, if the sense circuit SC includes a sense circuit capacitor C, a resistor R, and a Zener diode ZD, it is possible to suppress the effects of AC and DC fluctuations in the potential of the source S, while also suppressing effects such as when the difference between the potential of the gate G and the potential of the source S exceeds a threshold.

[0098] The semiconductor device described above includes a first sense circuit (SC(22L)) which comprises a capacitor for the first sense circuit (SC(22L)) connected between the first control terminal (G) and the first carrier injection terminal (S) of the first transistor (12L), and a second sense circuit (SC(23L)) which comprises a capacitor for the second sense circuit (SC(23L)) connected between the second control terminal (G) and the second carrier injection terminal (S) of the second transistor (13L).

[0099] The semiconductor device described above includes a first sense circuit (SC(22L)) comprising a first resistor (R: Figure 11) connected between the first control terminal (G) and the first carrier injection terminal (S) of the first transistor (12L), and a second sense circuit SC(23L) comprising a second resistor (R: Figure 11) connected between the second control terminal (G) and the second carrier injection terminal (S) of the second transistor (13L).

[0100] The semiconductor device described above includes a first sense circuit (SC(22L)) comprising a first Zener diode (ZD: Figure 11) having a cathode connected to the first control terminal (G) of the first transistor (12L) and an anode connected to the first carrier injection terminal (S), and a second sense circuit (SC(23L)) comprising a second Zener diode (ZD: Figure 11) having a cathode connected to the second control terminal (G) of the second transistor (13L) and an anode connected to the second carrier injection terminal (S).

[0101] The semiconductor device described above includes a first sense circuit (SC(22L)) comprising: a first sense circuit (SC(22L)) capacitor (C: Figure 11) connected between the first control terminal (G) and the first carrier injection terminal (S) of the first transistor (12L); a first resistor (R: Figure 11) connected between the first control terminal (G) and the first carrier injection terminal (S) of the first transistor (12L); and a first Zener diode (ZD: Figure 11) having a cathode connected to the first control terminal (G) of the first transistor (12L) and an anode connected to the first carrier injection terminal (S). The second sense circuit (SC(23L)) comprises a capacitor (C: Figure 11) for the second sense circuit (SC(23L)) connected between the second control terminal (G) and the second carrier injection terminal (S) of the second transistor (13L), a second resistor (R: Figure 11) connected between the second control terminal (G) and the second carrier injection terminal (S) of the second transistor (13L), and a second Zener diode (ZD: Figure 11) having a cathode connected to the second control terminal (G) of the second transistor (13L) and an anode connected to the second carrier injection terminal (S).

[0102] Figure 12 is a circuit diagram including the amplifier and sense circuit (Figures 12(A), 12(B), and 12(C)).

[0103] In these figures, the switching element (Q) represents one of the switching elements (11U, 12U, 13U, 11L, 12L, 13L). The sense circuit SC represents one of the sense circuits (SC(21U), SC(22U), SC(23U), SC(21L), SC(22L), SC(23L)). The amplifier AP represents one of the amplifiers (AP(21U), AP(22U), AP(23U), AP(21L), AP(22L), AP(23L)). Amplifier AP is an amplifier having at least an output terminal connected to gate G. Amplifier AP is a gate driver in terms of driving gate G.

[0104] The amplifier AP in Figure 12(A) is equipped with a power supply line that provides a high potential VH for driving the output amplifier OAP and a ground line that provides a low potential VL. The power supply line is connected to the first power supply potential VS1 via a regulator RG, and the ground line is connected to the first ground potential GND1.

[0105] An example of a regulator RG is a three-terminal regulator, which has an input terminal to which the first power supply potential VS1 is input, an output terminal to which a high potential VH voltage is output, and a control terminal connected to a reference potential (first ground potential GND1). An example of a three-terminal regulator is a circuit including a transistor, for example, the collector can be the input terminal, the base the control terminal, and the emitter the output terminal. A first protection circuit PC1 (e.g., a diode) is connected between the output terminal of regulator RG and the ground potential to suppress negative voltage on the output terminal side. A second protection circuit PC2 (e.g., a diode) is connected between the input terminal and the output terminal of regulator RG to suppress reverse current. The output amplifier OAP receives an input signal SIN via a signal processing circuit SP, separate from the power supply. The input signal SIN is a control signal for controlling the switching of the switching element Q. Depending on the type of control signal, the function of the signal processing circuit SP may be simply a buffer amplifier. The signal processing circuit SP can, if necessary, modulate the input signal SIN into a signal suitable for switching the switching element Q.

[0106] The amplifier AP in Figure 12(B) is equipped with a power line that provides a high potential VH for driving the output amplifier OAP and a ground line that provides a low potential VL. The power line is connected to the first power supply potential VS1 via a regulator RG, and the ground line is connected to the first ground potential GND1. The function of the signal processing circuit SP can be the same as in the case of Figure 12(A). The regulator RG only needs to be structured to receive the first power supply potential VS1 and the first ground potential GND1 as inputs and stably output the high potential VH and the low potential VL. In other words, the regulator RG may have a built-in transformer and protection circuit.

[0107] The amplifier AP in Figure 12(C) is an isolated gate driver. The source S of the switching element Q is connected to the gate G via a sense circuit SC, thereby suppressing the effects of fluctuations in source potential and enabling high-speed switching. The source terminal of the sense circuit SC is not directly connected to the ground potential of the output amplifier OAP. Amplifier AP comprises an input amplifier IPA, a signal coupler CPL, and an output amplifier OAP. When a transformer with a coil pair is used, the signal coupler CPL may include an encoder ENG that modulates and transmits the input signal SIN to the input coil and a decoder DEC that demodulates the output signal from the output coil. Amplifier AP may also include a third protection circuit PC3 and a fourth protection circuit PC4. The third and fourth protection circuits PC3 and PC4 may be, for example, protection circuits that include UVLO (Control Power Supply Voltage Dropout Prevention Function) and TSD (Thermal Shutdown Protection Function). These protection circuits can be attached to, for example, the input amplifier or decoder. Note that a structure using a pair of capacitors instead of a transformer is also known as an isolated gate driver.

[0108] Figure 13 is a circuit diagram including the amplifier and sense circuit (Figure 13(A), Figure 13(B)).

[0109] The amplifier AP in Figure 13(A) is the same as the amplifier AP in Figure 12(B) but without the regulator RG. The function of the regulator RG can also be implemented using an external component.

[0110] The amplifier AP in Figure 13(B) is the same as the amplifier AP in Figure 13(A) but without the signal processing circuit SP. The function of the signal processing circuit SP can also be implemented using components outside the module.

[0111] Figure 14 is a circuit diagram showing an example of the connection between multiple control elements and power supply terminals.

[0112] An example is shown where the amplifier AP within the control element is an isolated gate driver. The input side of each control element (21U, 22U, 23U, 21L, 22L, 23L) is supplied with the first power supply potential VS1 and the first ground potential GND1. The output side of each control element on the lower arm (21L, 22L, 23L) is supplied with the third power supply potential VS3 from lead (41L) and the third ground potential GND3 from lead (42L).

[0113] The output side of the upper arm control element 21U (amplifier AP(21U)) is supplied with a third power supply potential VS3 from lead (41U) and a third ground potential GND3 from lead (42U). The output side of the upper arm control element 22U (amplifier AP(22U)) is supplied with a third power supply potential VS3 from lead (43U) and a third ground potential GND3 from lead (44U). The output side of the upper arm control element 23U (amplifier AP(23U)) is supplied with a third power supply potential VS3 from lead (45U) and a third ground potential GND3 from lead (46U). The power supply potential and ground potential on the output side can be used as potentials to drive the output amplifier at least. The power supply potential and ground potential can be used to operate other signal couplers and protection circuits.

[0114] In the case of an isolated gate driver, the transformer structure enables signal transmission and reception while isolating the primary side (input side) and the secondary side (output side). The isolated gate driver has a primary power electrode to which the first power supply potential VS1 is input, a primary ground electrode to which the first ground potential GND1 is input, and a primary control electrode to which the input signal SIN as a control signal is input on the primary side. The isolated gate driver has a secondary power electrode, a secondary ground electrode, and a secondary output electrode to which the output signal SOUT is output.

[0115] The primary power supply electrode and the primary ground electrode are electrodes to which power is supplied to realize primary-side signal processing and other functions in the first upper arm control element 21U. The voltage supplied to the primary power supply electrode may be, for example, 1.8V, 3.3V, or 5.0V. The primary control electrode receives a control signal that forms the basis for controlling the first upper arm switching element 11U.

[0116] The secondary power supply electrode and secondary ground electrode supply power to the first upper arm control element 21U so that it can output a control signal to the control terminal (gate G) of the first upper arm switching element 11U. The voltage supplied to the secondary power supply electrode varies depending on the specific type and specifications of the first upper arm switching element 11U, and is, for example, higher than the voltage supplied to the primary power supply electrode. The secondary output electrode is the electrode to which the control signal is output to the control terminal (gate G) of the first upper arm switching element 11U.

[0117] The first lower arm control element 21L, the second upper arm control element 22U, the second lower arm control element 22L, the third upper arm control element 23U, and the third lower arm control element 23L each output control signals to the control terminals (gate G) of the first lower arm switching element 11L, the second upper arm switching element 12U, the second lower arm switching element 12L, the third upper arm switching element 13U, and the third lower arm switching element 13L, respectively. These control elements (21L, 22U, 22L, 23U, 23L) control the switching operation of their respective switching elements (11L, 12U, 12L, 13U, 13L). The control elements (21L, 22U, 22L, 23U, 23L) may have the same configuration as the first upper arm control element 21U, or they may have a different configuration. In this example, each control element (21L, 22U, 22L, 23U, 23L) has a configuration common to the first upper arm control element 21U.

[0118] The main board 6 is equipped with a pair of switching elements (11U, 11L). The main board 6 may also be equipped with a further pair of switching elements (12U, 12L) and a pair of switching elements (13U, 13L).

[0119] Figure 15 is a block diagram of a motor drive system with modules.

[0120] The motor drive unit comprises a power supply VS, a semiconductor device A1 (module A1), a control circuit CONT, and a motor M1. The motor M1, for example, has three coils connected in a star configuration, but may also have delta-connected coils. A switching circuit, composed of switching elements included in module A1, outputs a three-phase drive signal (U, V, W). The three-phase drive signal (U, V, W) output from module A1 is supplied to one end of each coil of the motor M1. The power supply VS can be a DC power supply and has the function of supplying the aforementioned power supply potential and ground potential to the module. The control circuit CONT generates the control signals input to module A1. Since module A1 operates with high reliability, the reliability of the motor drive unit is also high.

[0121] Figure 16 is a block diagram of a voltage converter with modules.

[0122] The voltage converter comprises a power supply VS, a semiconductor device A1 (module A1), a transformer TR, a rectifier REC, and a smoothing circuit SMC. The power supply VS can be a DC power supply and has the function of supplying the aforementioned power supply potential and ground potential to the module. The control circuit CONT generates the control signal to be input to module A1. The voltage converter can function as a DC / DC converter. Module A1 can output multi-phase signals, but when used as a DC / DC converter, it is common to use two switching elements in the upper arm and two switching elements in the lower arm. The switching circuit composed of the switching elements included in module A1 performs DC / AC conversion and applies an AC voltage to the primary coil of the transformer TR, which is composed of a transformer. The AC voltage output from the secondary coil of the transformer TR is rectified by the rectifier REC and converted into a voltage waveform close to a DC voltage. The output of the rectifier REC is smoothed by the smoothing circuit SMC and converted into a DC voltage.

[0123] Figure 17 is a plan view of a semiconductor device according to the first embodiment.

[0124] The sealing resin 9 includes an insulating resin such as epoxy resin. The sealing resin 9 may have a resin main surface 91, a resin back surface 92, a resin first side surface 93, a resin second side surface 94, a resin third side surface 95, and a resin fourth side surface 96. Multiple recesses (911) are formed between leads on the resin first side surface 93 of the semiconductor device A1. Multiple recesses (921) are formed on the resin second side surface 94. Multiple recesses (931, 951) are formed on the resin third side surface 95, and a support lead 78 provided on the control substrate 7 is located in the depth of the recess (951). Multiple recesses (941, 961) are formed on the resin fourth side surface 96, and a support lead 79 provided on the control substrate 7 is located in the depth of the recess (961).

[0125] Figure 18 is a bottom view of a semiconductor device according to the first embodiment.

[0126] The second resin side surface 94 faces the second side x2 in the first direction x. The fourth resin side surface 96 faces the second side y2 in the second direction y. The back surface 92 of the resin faces the second side z2 in the thickness direction z (see Figure 1). A rectangular second conductive layer 62 is exposed on the back surface 92 of the sealing resin 9. The second conductive layer 62 is provided on the back side of the main substrate 6 and can dissipate heat.

[0127] Figure 19 is a bottom view of a part of a semiconductor device according to the first embodiment.

[0128] The figure shows the semiconductor device A1 constituting the module with the sealing resin 9 removed, but the outline of the sealing resin 9 is shown by a dashed line. The insulating layer 60 that constitutes part of the main substrate 6 is rectangular in shape, and a second conductive layer 62 is formed on the insulating layer 60. Multiple electronic components 25 are formed on the back surface 7b of the control substrate 7. The electronic components 25 are components that are provided as needed, and can be omitted if not needed. The electronic components 25 may have an insulating covering that covers all or part of them. The covering can be formed by, for example, a resist film or ink.

[0129] Figure 20 is a longitudinal cross-sectional view of a semiconductor device according to the first embodiment. This figure is a longitudinal cross-sectional view of the semiconductor device A1 taken across in the width direction (x), and this longitudinal cross-section is cut at a position including the control element (21L) and the switching element (11L).

[0130] The main board 6 in this example includes an insulating heat dissipation circuit board. The main board 6 comprises an insulating layer 60, a first conductive layer 61 provided on one side of the insulating layer 60, and a second conductive layer 62 provided on the other side. The control board 7 and control elements (21L) are embedded in the sealing resin 9. The switching elements (11L) are embedded in the sealing resin 9, but the surface of the second conductive layer 62 is exposed to the outside. Each of the multiple control leads 5 may include a terminal portion 501 and a pad portion 502. The terminal portion 501 is located outside the sealing resin 9 and extends along the thickness direction z. The pad portion 502 is covered by the sealing resin 9. A typical bonding wire connecting the control board 7 and the leads 5 (pad portion 502) is referred to as the bonding wire (87). The basic connection structure passing through all leads provided on the side surface (94) is the same as this.

[0131] The lead (35) has a terminal portion 301 and a joint portion 302. The terminal portion 301 is located outside the sealing resin 9 and extends along the thickness direction z. The joint portion 302 is electrically bonded to the electrode (WLD11). In this figure, a general bonding wire connecting the switching element (11L) and the control board 7 is shown as bonding wire (83). In detail, the bonding wire (83) in this example is the bonding wire (WLGS11 or WLSS11) shown in Figure 3. The basic connection structure passing through all leads provided on the side surface (93) is the same. That is, the basic connection relationship in the longitudinal cross-sectional structure at locations including other control elements (21U, 22U, 23U, 22L, 23L) and switching elements (11U, 12U, 13U, 12L, 13L) is the same as the connection relationship in this figure.

[0132] Figure 21 is an enlarged cross-sectional view of a part of the semiconductor device according to the first embodiment.

[0133] A switching element (11L) is fixed to the first conductive layer 61 (electrode) of the main substrate 6 via a conductive bonding material 19. The switching element may be solid-phase diffusion bonded to the lower electrode. The switching element (11L) comprises a first electrode 101 formed on the lower side of the semiconductor substrate SB, and a second electrode 102 and a third electrode 103 formed on the upper side. The first electrode 101 is the drain electrode, the second electrode 102 is the source electrode, and the third electrode 103 is the gate electrode. The longitudinal cross-sectional structure of the other switching elements (11U, 12U, 13U, 12L, 13L) is the same as the longitudinal cross-sectional structure of this switching element (11L). The first conductive layer 61 of the main substrate 6 can constitute the electrodes (WLD11, WUD11, WLD12, WUD13, WLD13) shown in Figure 3, and each switching element is fixed to these electrodes via a conductive bonding material 19. The positions of the second electrode 102 and the third electrode 103 formed on the upper surface can be made different from those of the switching element (11L) depending on the arrangement of each switching element.

[0134] The first conductive layer 61 may contain metals such as Cu (copper) and Ni (nickel), or alloys thereof. The second conductive layer 62 is located on the second side z2 in the thickness direction z of the insulating layer 60. The second conductive layer 62 may contain metals such as Cu (copper) and Ni (nickel), or alloys thereof. A main substrate 6 with this configuration constitutes an insulating heat dissipation circuit board. An insulating heat dissipation circuit board is a substrate in which conductive layers such as copper are bonded to both sides of an insulating substrate made of a material such as ceramic. As an insulating heat dissipation circuit board, an AMB substrate bonded using the Active Metal Brazing (AMB) method, or a DCB substrate bonded using the Direct Bonded Copper (DBC) method, etc., can be used.

[0135] Figure 22 is a longitudinal cross-sectional view of the semiconductor device, cut along the longitudinal direction of the control board.

[0136] Multiple control elements (21L, 21U, 22L, 22U, 23U, 23L) are arranged in alignment along the longitudinal direction of the control board 7. The control board 7 may include an insulating substrate containing resin. Electronic components 25 can be mounted on the back side of the control board 7 as needed. The electronic components 25 are embedded in the sealing resin 9.

[0137] Figure 23 is a longitudinal cross-sectional view of a portion of the control board.

[0138] The control substrate 7 may have one or more first insulating layers 701, one or more second insulating layers 702, a main surface conductive layer 711, a back surface conductive layer 712, and one or more intermediate conductive layers 713. In the illustrated example, the control substrate 7 has a first insulating layer 701, two second insulating layers 702, a main surface conductive layer 711, a back surface conductive layer 712, and two intermediate conductive layers 713. The specific laminated structure of the control substrate 7 is not limited in any way. For example, the control substrate 7 may have a laminated structure having multiple second insulating layers 702 located on both sides of the first insulating layer 701 in the thickness direction z. Alternatively, the control substrate 7 may have a laminated structure having multiple first insulating layers 701. Intermediate conductive layers 713 may be provided between multiple second insulating layers 702 or multiple first insulating layers 701.

[0139] The first insulating layer 701 and the second insulating layer 702 each contain an insulating material and are laminated in the thickness direction z. The insulating material contained in the first insulating layer 701 is not limited in any way, but for example, a material harder than the insulating material contained in each second insulating layer 702 may be used. Examples of insulating materials contained in the first insulating layer 701 include resin. Examples of insulating materials contained in each second insulating layer 702 include resin. The thickness of the first insulating layer 701 may be thicker or thinner than the thickness of each second insulating layer 702, or they may be about the same.

[0140] The main surface conductive layer 711, the back surface conductive layer 712, and the two intermediate conductive layers 713 each have conductivity and may contain metals such as Cu (copper), Ni (nickel), Au (gold), or alloys thereof.

[0141] The first side surface 7c includes an inclined portion located on the first side z1 in the thickness direction z and an upright portion located on the second side z2 in the thickness direction z. The inclined portion may be, for example, a trace of a V-shaped groove formed in the substrate material for forming the control substrate 7. The upright portion may be a portion that was broken by bending or the like when cutting the control substrate 7 from the substrate material. In another embodiment, the first side surface 7c may have a V-shaped cross-sectional shape with two inclined portions located on both sides in the thickness direction z.

[0142] Figure 24 is a longitudinal cross-sectional view of a portion of the control board.

[0143] The second side surface 7d may have an uneven shape. In the illustrated example, the second side surface 7d may be wave-shaped, folded-line-shaped, or wedge-shaped. The second side surface 7d may be formed, for example, by machining the substrate material for forming the control substrate 7. The uneven shape of the second side surface 7d is assumed to be due to various factors, for example, the difference in hardness between the first insulating layer 701 and the second insulating layer 702, which is presumed to cause a difference in the amount of deflection when machining is performed. In the illustrated example, the first insulating layer 701 is bulging and the second insulating layer 702 is recessed.

[0144] Figure 25 is a longitudinal cross-sectional view of a portion of the control board.

[0145] The control board 7 in this example includes two first insulating layers 701 and one second insulating layer 702. The two first insulating layers 701 are located on both sides of the second insulating layer 702 in the thickness direction z. The insulating material contained in the first insulating layers 701 is harder than the insulating material contained in each of the second insulating layers 702. On the second side surface 7d, the two first insulating layers 701 bulge out, and the second insulating layer 702 is recessed. By using the control board in this example, the semiconductor device A1 can be miniaturized. The specific configuration of the uneven shape of the second side surface 7d is not limited in any way.

[0146] The above describes a semiconductor device A1 using six switching elements. Below, a semiconductor device using four switching elements will be described. The semiconductor device A2 of this embodiment can be said to have a two-phase configuration, in contrast to the three-phase configuration of semiconductor device A1.

[0147] Figure 26 is a perspective view of the semiconductor device according to the second embodiment.

[0148] The semiconductor device A2 according to the second embodiment differs from the semiconductor device according to the first embodiment in that it does not have leads (45U, 46U, 32, 37).

[0149] Figure 27 is a perspective view of a part of the semiconductor device according to the second embodiment.

[0150] The semiconductor device A2 according to the second embodiment differs from the semiconductor device according to the first embodiment in that it does not have control elements (23L, 23U), switching elements (13L, 13U), or leads connected thereto.

[0151] The semiconductor device A2 includes a first upper arm switching element 11U, a first lower arm switching element 11L, a second upper arm switching element 12U, and a second lower arm switching element 12L, and a first upper arm control element 21U, a first lower arm control element 21L, a second upper arm control element 22U, and a second lower arm control element 22L. The semiconductor device A2 also includes a first main power lead 31, a main ground lead 33, a first output lead 35, and a second output lead 36, a first upper arm secondary side control power lead 41U, a first upper arm secondary side control ground lead 42U, a second upper arm secondary side control power lead 43U, a second upper arm secondary side control ground lead 44U, a lower arm secondary side control power lead 41L, and a lower arm secondary side control ground lead 42L, and a plurality of control leads 5.

[0152] Figure 28 is a plan view of the semiconductor device according to the second embodiment. Note that only the outline of the sealing resin 9 is shown so that the inside of the module is visible.

[0153] In this embodiment, the drain of the first upper arm switching element 11U (first electrode 101 (Figure 21)) and the drain of the second upper arm switching element 12U (first electrode 101 (Figure 21)) are electrically connected on the electrode (WUD11) made of the first conductive layer 61 (see Figure 21). The connection relationships and positional relationships of the other components may be generally the same as those of semiconductor device A1.

[0154] The main board 6 has multiple island-shaped electrodes (WLD11, WUD11, WLD12, WGND2) on one side of an insulating board. These electrodes (WLD11, WUD11, WLD12) are arranged in order along the longitudinal direction of the module. The first lower arm switching element 11L is fixed to the first electrode (WLD11). The first upper arm switching element 11U and the second upper arm switching element 12U are fixed to the second electrode (WUD11). The second lower arm switching element 12L is fixed to the third electrode (WLD12).

[0155] The sixth electrode (WGND2) provides the ground potential (GND2) in the switching circuit. The sources of the switching elements (11L, 12L) that make up the lower arm are connected to the sixth electrode (WGND2) via bonding wires (WLS11, WLS12), respectively. The bonding wire is a wiring.

[0156] The island-shaped electrodes (WLD11, WUD11, WLD12, WGND2) are electrode patterns, each connected to a lead (35, 31, 36, 33).

[0157] Lead (35) is connected to the node between the first upper arm switching element 11U and the first lower arm switching element 11L, and can be used as the output terminal for one of the two phases when outputting a two-phase drive signal. Similarly, lead (36) is connected to the node between the second upper arm switching element 12U and the second lower arm switching element 12L, and can be used as the output terminal for the other phase when outputting a two-phase drive signal.

[0158] Next, we will explain the connection relationships of each switching element.

[0159] The gate of the first lower arm switching element 11L is connected to the wiring of the control board 7 via a bonding wire (WLGS11), and this wiring is connected to the amplifier output terminal (one end of the sense circuit (see Figure 4)) in the first lower arm control element 21L. The source of the first lower arm switching element 11L is connected to the wiring of the control board 7 via a bonding wire (WLSS11), and this wiring is connected to the other end of the sense circuit in the first lower arm control element 21L. The drain of the first lower arm switching element 11L is fixed to an electrode (WLD11) on the main board 6 and electrically connected. The source of the first lower arm switching element 11L is connected to an electrode at ground potential (WGND2) via a bonding wire (WLS11).

[0160] The gate of the first upper arm switching element 11U is connected to the wiring of the control board 7 via a bonding wire (WUGS11), and this wiring is connected to the amplifier output terminal (one end of the sense circuit) in the first upper arm control element 21U. The source of the first upper arm switching element 11U is connected to the wiring of the control board 7 via a bonding wire (WUSS11), and this wiring is connected to the other end of the sense circuit in the first upper arm control element 21U. The drain of the first upper arm switching element 11U is fixed to an electrode (WUD11) on the main board 6 and electrically connected. The source of the first upper arm switching element 11U is connected to the drain of the first lower arm switching element 11L via a bonding wire (W11) and an electrode (WLD11).

[0161] The gate of the second upper arm switching element 12U is connected to the wiring of the control board 7 via a bonding wire (WUGS12), and this wiring is connected to the amplifier output terminal (one end of the sense circuit) in the second upper arm control element 22U. The source of the second upper arm switching element 12U is connected to the wiring of the control board 7 via a bonding wire (WUSS12), and this wiring is connected to the other end of the sense circuit in the second upper arm control element 22U. The drain of the second upper arm switching element 12U is fixed to an electrode (WUD11) on the main board 6 and electrically connected. The source of the second upper arm switching element 12U is connected to the drain of the second lower arm switching element 12L via a bonding wire (W22) and an electrode (WLD12).

[0162] The gate of the second lower arm switching element 12L is connected to the wiring of the control board 7 via a bonding wire (WLGS12), and this wiring is connected to the amplifier output terminal (one end of the sense circuit) in the second lower arm control element 22L. The source of the second lower arm switching element 12L is connected to the wiring of the control board 7 via a bonding wire (WLSS12), and this wiring is connected to the other end of the sense circuit in the second lower arm control element 22L. The drain of the second lower arm switching element 12L is fixed to an electrode (WLD12) on the main board 6 and electrically connected. The source of the second lower arm switching element 12L is connected to an electrode (WGND2) at ground potential via a bonding wire (WLS12).

[0163] Lead (51), to which the input power supply potential (VS1) is supplied, is connected to the wiring of the control board 7 via a bonding wire (WVS1), and through this wiring is connected to the power lines of each control element (21L, 21U, 22L, 22U). Lead (52), to which the input ground potential (GND1) is supplied, is connected to the wiring of the control board 7 via a bonding wire (WGND1), and through this wiring is connected to the ground lines of each control element (21L, 21U, 22L, 22U).

[0164] Depending on the structure of the control elements (21L, 21U, 22L, 22U), additional power lines can be provided. For example, if each control element (21L, 21U, 22L, 22U) is equipped with a coil, power can be supplied to the secondary coil separately from the primary coil.

[0165] Lead (41L) is connected to the wiring of the control board 7 via bonding wire (W41L), and a power potential may be supplied to the control elements (21L, 22L) on the lower arm side via this wiring. Lead (42L) is connected to the wiring of the control board 7 via bonding wire (W42L), and a ground potential may be supplied to the control elements (21L, 22L) on the lower arm side via this wiring.

[0166] Similarly, the leads (41U, 43U) are connected to the wiring of the control board 7 via bonding wires (W41U, W43U), respectively, and the power supply potential (VS3) may be supplied to the secondary coils of the upper arm control elements (21U, 22U) via these wires. The leads (42U, 44U) are connected to the wiring of the control board 7 via bonding wires (W42U, W44U), respectively, and the ground potential (GND3) may be supplied to the secondary coils of the upper arm control elements (21U, 22U) via these wires.

[0167] The other leads (534, 533, 53b, 53c, 532, 531, 539, 536, 535, 53a, 538, 537) are also connected to the wiring of the control board 7 via bonding wires (87).

[0168] A pair of electrodes (first temperature measuring unit 618 and second temperature measuring unit 619) may be fixed on an insulating substrate constituting the main board 6, and these electrodes may be joined by a sensor 18. If the sensor 18 is a thermistor, the temperature of the main board 6 can be monitored. The first temperature measuring unit 618 and the second temperature measuring unit 619 are connected to the control board 7 via bonding wires, and temperature detection outputs can be taken from leads (53b, 53c). The position of the source S of the switching element (11L) is denoted as point "A". The position of the source S of the switching element (12L) is denoted as point "B". The position of the lead (33) connected to the second ground potential GND2 is denoted as point "N". The behavior of the potential and current between these points is the same as in the first embodiment.

[0169] Figure 29 is a circuit diagram of a semiconductor device according to the second embodiment.

[0170] The semiconductor device of the second embodiment is obtained by removing the third row of switching elements (13U, 13L), their corresponding control elements (23U, 23L), and their leads from the semiconductor device of the first embodiment. The other structures are the same as those of the first embodiment.

[0171] Figure 30 is a plan view of a semiconductor device according to the second embodiment.

[0172] The semiconductor device A2 according to the second embodiment differs from the semiconductor device according to the first embodiment in that it does not have leads (45U, 46U, 32, 37).

[0173] Figure 31 is a bottom view of the semiconductor device according to the second embodiment.

[0174] A rectangular second conductive layer 62 is exposed on the back surface 92 of the sealing resin 9. The second conductive layer 62 is provided on the back side of the main substrate 6 and can dissipate heat.

[0175] Figure 32 is a bottom view of a part of the semiconductor device according to the second embodiment.

[0176] The figure shows the semiconductor device A1 that constitutes the module with the sealing resin 9 removed, but the outline of the sealing resin 9 is shown by a dashed line. The insulating layer 60 that constitutes part of the main substrate 6 is rectangular in shape, and a second conductive layer 62 is formed on the insulating layer 60. Multiple electronic components 25 are formed on the back surface 7b of the control substrate 7. The electronic components 25 are components that are provided as needed, and can be omitted if they are not needed.

[0177] Figure 33 shows circuit diagrams of transistors that can be used as switching elements (Figures 33(A), 33(B), and 33(C)).

[0178] In these diagrams, the switching element (Q) represents one of the switching elements (11U, 12U, 13U, 11L, 12L, 13L). The sense circuit SC represents one of the sense circuits (SC(21U), SC(22U), SC(23U), SC(21L), SC(22L), SC(23L)).

[0179] In the semiconductor device described above, each switching element (11U, 12U, 13U, 11L, 12L, 13L) is a transistor.

[0180] In the example described above, an N-channel FET is shown as shown in Figure 33(A). The first transistor (12L) is a field-effect transistor, the first control terminal (G) is the gate of the first transistor (12L), and the first carrier injection terminal (S) is the source of the first transistor (12L). The second transistor (13L) is a field-effect transistor, the second control terminal (G) is the gate of the second transistor (13L), and the second carrier injection terminal (S) is the source of the second transistor (13L). The field-effect transistor is an N-channel transistor. The field-effect transistor can be a MOS (metal oxide semiconductor) field-effect transistor.

[0181] These transistors can also be replaced with other transistors. As shown in Figure 33(B), NPN bipolar transistors may be used as these transistors. In the case of bipolar transistors, the control terminal of the transistor is the base, the carrier injection terminal is the emitter, and the carrier receiving terminal is the collector. The emitter can be connected to the third point P3 shown in Figure 7, and the base can be connected to the fourth point P4. The first transistor (12L) is a bipolar transistor, the first control terminal is the base of the first transistor (Q:12L), and the first carrier injection terminal is the emitter of the first transistor (12L). The second transistor (13L) is a bipolar transistor, the second control terminal is the base of the second transistor (13L), and the second carrier injection terminal is the emitter of the second transistor (13L). The bipolar transistors can be NPN type transistors.

[0182] As shown in Figure 33(C), N-channel IGBTs (Insulated Gate Bipolar Transistors) may be used as these transistors. In the case of IGBTs, the control terminal of the transistor is the gate, the carrier injection terminal is the emitter, and the carrier receiving terminal is the collector. The emitter can be connected to the third point P3 shown in Figure 7, and the gate can be connected to the fourth point P4. The first transistor (12L) is an insulated gate bipolar transistor (IGBT), the first control terminal (G) is the gate of the first transistor (12L), and the first carrier injection terminal is the emitter of the first transistor (12L). The second transistor (13L) is an insulated gate bipolar transistor, the second control terminal (G) is the gate of the second transistor (13L), and the second carrier injection terminal is the emitter of the second transistor (13L). The insulated gate bipolar transistor may be an N-channel type transistor.

[0183] The number of switching elements and control elements included in the semiconductor device of this disclosure is not limited in any way. The shape and arrangement of the electrodes on which the switching elements are placed can be modified in various ways. For example, the electrode to which the second ground potential GND2 is applied (WGND2) can be placed closer to the leads (35, 36, etc.) than to each switching element. In such a structure, each switching element is closer to the control board 7, and the length of the bonding wire can be shortened. When the electrode (WGND2) is brought closer to the leads (35, 36, etc.), the positions of the other electrodes (WLD11, WUD11, WLD12) must be shifted closer to the control board 7. Furthermore, the planar shape of such electrodes can be branched as needed. The semiconductor device of this disclosure is not limited to the embodiments described above. The specific configuration of each part of the semiconductor device of this disclosure can be modified in various ways.

[0184] For example, the gap along the y-direction between leads (35, 31, 36, 32, 37, 33) connected to electrodes positioned below the switching element may be 3.4 mm or more and 36.0 mm or less, but is not limited to these values. The gap along the y-direction between leads (5) with a width in the y-direction smaller than these leads may be, for example, 0.2 mm or more and 3.0 mm or less. The gaps along the y-direction between leads (41L, 42L), between leads (41U, 42U), between leads (43U, 44U), and between leads (45U, 46U) may be, for example, 0.2 mm or more and 3.0 mm or less, but is not limited to these values. Furthermore, in this device, the circuit structure of parts other than the sense circuit connection may refer to the circuit structure disclosed in U.S. Patent No. 11398818.

[0185] (Note) As described above, the various embodiments in this disclosure may be defined as follows:

[0186] [A1] A switching circuit (circuit on the main board 6) comprising a group of transistors including a first transistor (12L) and a second transistor (13L); a first driver (control element (22L)) comprising a first output terminal (fourth point P4) connected to the first control terminal (G) of the first transistor (12L); a second driver (control element (23L)) comprising a second output terminal (fourth point P4) connected to the second control terminal (G) of the second transistor (13L); a first sense circuit (SC(22L)) connected between the first control terminal (G) and the first carrier injection terminal (S) of the first transistor (12L); and the second control terminal (G) and the second carrier injection terminal of the second transistor (13L) A semiconductor device comprising: a second sense circuit (SC(23L)) connected to an input terminal (S); wherein a DC signal or AC signal can be transmitted between the reference potential (low potential VL) of the first driver (22L) and the reference potential VL of the second driver (23L); the reference potential (VL) of the first driver (22L) and the terminal (third point P3) on the first carrier injection terminal (S) side of the first sense circuit (SC(22L)) are not directly connected via wiring or resistors; and the reference potential (VL) of the second driver (23L) and the terminal (third point P3) on the second carrier injection terminal (S) side of the second sense circuit (SC(23L)) are not directly connected via wiring or resistors.

[0187] [A2] The reference potential (VL) of the first driver (22L) and the terminal on the first carrier injection terminal (S) side of the first sense circuit (SC(22L)) are connected via a first capacitor C1 (Figure 7), and the reference potential (VL) of the second driver (23L) and the terminal on the second carrier injection terminal (S) side of the second sense circuit (SC(23L)) are connected via a second capacitor (first capacitor C1: Figure 7), as described in [A1].

[0188] [A3] The power supply potential (VH) of the first driver (22L) and the terminal on the first carrier injection terminal (S) side of the first sense circuit (SC(22L)) are connected via a first capacitor (capacitor C1A: Figure 7), and the power supply potential (VH) of the second driver (23L) and the terminal on the second carrier injection terminal (S) side of the second sense circuit (SC(23L)) are connected via a second capacitor (capacitor C1A: Figure 7), as described in [A1].

[0189] [A4] The semiconductor device according to any one of [A1] to [A3], wherein the first driver (22L) comprises a first bypass capacitor (C2: Figure 7) connected between its power supply potential (VH) and a reference potential (VL), and the second driver (23L) comprises a second bypass capacitor (C2: Figure 7) connected between its power supply potential (VH) and a reference potential (VL).

[0190] [A5] The reference potential (VL) of the first driver (22L) and the reference potential (VL) of the second driver (23L) are connected in such a way that a DC signal can be transmitted between them, as described in any one of [A1] to [A3].

[0191] [A6] The semiconductor device according to any one of [A1] to [A3], wherein the first sense circuit (SC(22L)) comprises a capacitor for the first sense circuit (SC(22L)) connected between the first control terminal (G) and the first carrier injection terminal (S) of the first transistor (12L), and the second sense circuit (SC(23L)) comprises a capacitor for the second sense circuit (SC(23L)) connected between the second control terminal (G) and the second carrier injection terminal (S) of the second transistor (13L).

[0192] [A7] The semiconductor device according to any one of [A1] to [A3], wherein the first sense circuit (SC(22L)) comprises a first resistor (R: Figure 11) connected between the first control terminal (G) and the first carrier injection terminal (S) of the first transistor (12L), and the second sense circuit SC(23L) comprises a second resistor (R: Figure 11) connected between the second control terminal (G) and the second carrier injection terminal (S) of the second transistor (13L).

[0193] [A8] The semiconductor device according to any one of [A1] to [A3], wherein the first sense circuit (SC(22L)) comprises a first Zener diode (ZD: Figure 11) having a cathode connected to the first control terminal (G) of the first transistor (12L) and an anode connected to the first carrier injection terminal (S), and the second sense circuit (SC(23L)) comprises a second Zener diode (ZD: Figure 11) having a cathode connected to the second control terminal (G) of the second transistor (13L) and an anode connected to the second carrier injection terminal (S).

[0194] [A9] The first sense circuit (SC(22L)) comprises a capacitor (C: Figure 11) for the first sense circuit (SC(22L)) connected between the first control terminal (G) and the first carrier injection terminal (S) of the first transistor (12L), a first resistor (R: Figure 11) connected between the first control terminal (G) and the first carrier injection terminal (S) of the first transistor (12L), and a first Zener diode (ZD: Figure 11) having a cathode connected to the first control terminal (G) of the first transistor (12L) and an anode connected to the first carrier injection terminal (S), and the second sense circuit (SC(2 The semiconductor device according to any one of [A1] to [A3], comprising: 3L)) a capacitor (C: Figure 11) for a second sense circuit (SC(23L)) connected between the second control terminal (G) and the second carrier injection terminal (S) of the second transistor (13L); a second resistor (R: Figure 11) connected between the second control terminal (G) and the second carrier injection terminal (S) of the second transistor (13L); and a second Zener diode (ZD: Figure 11) having a cathode connected to the second control terminal (G) of the second transistor (13L) and an anode connected to the second carrier injection terminal (S).

[0195] [A10] The semiconductor device according to any one of [A1] to [A3], wherein the first transistor (12L) is a field-effect transistor, the first control terminal (G) is the gate of the first transistor (12L), the first carrier injection terminal (S) is the source of the first transistor (12L), the second transistor (13L) is a field-effect transistor, the second control terminal (G) is the gate of the second transistor (13L), and the second carrier injection terminal (S) is the source of the second transistor (13L).

[0196] [A11] The semiconductor device according to any one of [A1] to [A3], wherein the first transistor (12L) is a bipolar transistor, the first control terminal is the base of the first transistor (Q:12L) (Figure 33(B)), the first carrier injection terminal is the emitter of the first transistor (12L) (Figure 33(B)), the second transistor (13L) is a bipolar transistor, the second control terminal is the base of the second transistor (13L) (Figure 33(B)), and the second carrier injection terminal is the emitter of the second transistor (13L) (Figure 33(B)).

[0197] [A12] The semiconductor device according to any one of [A1] to [A3], wherein the first transistor (12L) is an insulated-gate bipolar transistor (IGBT), the first control terminal (G) is the gate of the first transistor (12L) (Figure 33(C)), the first carrier injection terminal is the emitter of the first transistor (12L) (Figure 33(C)), the second transistor (13L) is an insulated-gate bipolar transistor, the second control terminal (G) is the gate of the second transistor (13L), and the second carrier injection terminal is the emitter of the second transistor (13L) (Figure 33(C)).

[0198] [A13] A semiconductor device according to any one of [A1] to [A3], comprising: a printed circuit board (control board 7) equipped with a first driver (22L), a second driver (23L), a first sense circuit (SC(22L)), and a second sense circuit (SC(23L)); an insulating heat dissipation circuit board (main board 6) equipped with a switching circuit (switching elements (11U, 11L, 12U, 12L, 13U, 13L)); and an outer casing (sealing resin 9) covering the printed circuit board and the insulating heat dissipation circuit board. The material of the outer casing is not limited to resin, but may be glass or ceramic as long as it is an insulating material.

[0199] [A14] The switching circuit is a semiconductor device according to any one of [A1] to [A3], comprising: a first transistor (12L) whose first carrier injection terminal (S) is connected to ground potential (GND2); a second transistor (13L) whose second carrier injection terminal (S) is connected to ground potential (GND2); a third transistor (12U) whose third carrier injection terminal (S) is connected to the first carrier receiving terminal (drain D) of the first transistor (12L) and whose third carrier receiving terminal (D) is connected to power supply potential (VS2); and a fourth transistor (13U) whose fourth carrier injection terminal (S) is connected to the second carrier receiving terminal (D) of the second transistor (13L) and whose fourth carrier receiving terminal (D) is connected to power supply potential (VS2).

[0200] [A15] The switching circuit (switching elements (11U, 11L, 12U, 12L, 13U, 13L)) comprises a fifth transistor (11L) whose fifth carrier injection terminal (S) is connected to ground potential, and a sixth transistor (11U) whose sixth carrier injection terminal (S) is connected to the fifth carrier receiving terminal (D) of the fifth transistor (11L), and whose sixth carrier receiving terminal (D) is connected to power supply potential (VS2), as described in [A14].

[0201] [A16] A field-effect transistor is a semiconductor device described in "A10" which is an N-channel type transistor.

[0202] [A17] A field-effect transistor is a semiconductor device described in [A16], which is a MOS (metal oxide semiconductor) field-effect transistor.

[0203] [A18] A bipolar transistor is a semiconductor device described in "A11" which is an NPN type transistor.

[0204] [A19] An insulated gate bipolar transistor is a semiconductor device described in "A12" which is an N-channel type transistor.

[0205] [A20] A motor drive system comprising a semiconductor device described in any one of the above items [A1] to [A19] and a motor connected to the semiconductor device.

[0206] [A21] A DC / DC converter comprising a semiconductor device as described in any one of the above [A1] to [A19], a transformer connected downstream of the semiconductor device, a rectifier connected downstream of the transformer, and a smoothing circuit connected downstream of the rectifier.

[0207] [A22] A device equipped with the motor drive system described in [A20] above. Examples of such devices include vehicles, trains, machine tools, and robots.

[0208] [A23] A device equipped with the DC / DC converter described in [A21] above. Examples of such devices include computers, servers, mobile phones, home appliances, vehicles, trains, machine tools, and robots.

[0209] Furthermore, within the range of various parameters, the range of any parameter P is P min ≦P≦P max If given by, (P min +ΔP)≦P≦(P max -ΔP), ΔP=(P max -P min You may set it to (10 + 90 × X%)kΩ ≤ R ≤ (100 - 90 × X%)kΩ.

[0210] While various exemplary embodiments have been described above, the invention is not limited to these exemplary embodiments, and various omissions, substitutions, and modifications may be made. Furthermore, elements from different embodiments can be combined to form other embodiments. From the above description, it will be understood that the various embodiments of this disclosure are described herein for explanatory purposes and can be modified in various ways without departing from the scope and spirit of this disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the appended claims. [Explanation of Symbols]

[0211] 5…Control Lead 6… Main board 7…Control board 7a…main surface 7c…1st side 7d…Second side 9…Sealing resin 11L…First lower arm switching element 11U…First upper arm switching element 12L…Second lower arm switching element 12U…Second upper arm switching element 13L…Third lower arm switching element 13U…Third upper arm switching element 18...Sensor 18A...First monitor node 18B...Second monitor node 19...Conductive bonding material 21L...First lower arm control element 21U...First upper arm control element 22L…Second lower arm control element 22U...Second upper arm control element 23L…Third lower arm control element 23U…Third upper arm control element 25…Electronic components 31...First main power lead 32...Second main power lead 33...Main Ground Lead 35…First output lead 36…Second output lead 37…Third output lead 41L...Lower arm secondary side control power lead 41U…First upper arm secondary side control power lead 42L... Lower arm secondary side control ground lead 42U…First upper arm secondary side control ground lead 43U…Second upper arm secondary side control power lead 44U…Second upper arm secondary side control ground lead 45U…Third upper arm secondary side control power lead 46U...Third upper arm secondary side control ground lead 60...Insulating layer 61...First conductive layer 62...Second conductive layer 78,79… Leading in support 91... Main resin surface 92…Resin back 93... First side of resin 94... Second side of resin 95... Third side of resin 96... Fourth side of resin 101...1st electrode 102…Second electrode 103…Third electrode 301,501...Terminal section 302…Joint part 502...Pad section 618...First temperature sensing unit 619... Second temperature sensing unit 701...First insulating layer 702...Second insulating layer 711... Main surface conductive layer 712... back surface conductive layer 713...Intermediate conductive layer A1... Semiconductor device A2…Semiconductor device AP... Amplifier C... Capacitor C1...First capacitor C2...Bypass capacitor CONT…control circuit CPL…Signal combiner D...Drain DEC… Decoder ENG… Encoder G...Gate GND1…First ground potential GND2...Second ground potential GND3...Third ground potential IPA…Input Amplifier M1...motor OAP…Output Amplifier P1…1st point P2…Second point P3…3rd point P4…4th point PC1…1st protection circuit PC2…Second protection circuit PC3…Third protection circuit PC4…4th protection circuit Q... Switching element Q1…First transistor Q2…2nd transistor R…Resistor REC…Rectifier RG... Regulator S... Source SB… Semiconductor substrate SC...Sense Circuit SIN...Input signal SMC…Smoothing circuit SOUT…Output signal SP... Signal processing circuit TR... Transformer VL…Low potential VH…High potential VS…Power supply VS1...1st power supply potential VS3...Third power supply potential x…first direction y...Second direction z...thickness direction ZD... Zener diode

Claims

1. A switching circuit comprising a group of transistors including a first transistor and a second transistor, A first driver having a first output terminal connected to the first control terminal of the first transistor, A second driver having a second output terminal connected to the second control terminal of the second transistor, A first sense circuit connected between the first control terminal and the first carrier injection terminal of the first transistor, A second sense circuit is connected between the second control terminal and the second carrier injection terminal of the second transistor, Equipped with, A DC signal or an AC signal can be transmitted between the reference potential of the first driver and the reference potential of the second driver. The reference potential of the first driver and the terminal on the first carrier injection terminal side of the first sense circuit are not directly connected via wiring or resistors. The reference potential of the second driver and the terminal on the second carrier injection terminal side of the second sense circuit are not directly connected via wiring or resistors. Semiconductor equipment.

2. The reference potential of the first driver and the terminal on the first carrier injection terminal side of the first sense circuit are connected via a first capacitor. The reference potential of the second driver and the terminal on the second carrier injection terminal side of the second sense circuit are connected via a second capacitor. The semiconductor device according to claim 1.

3. The power supply potential of the first driver and the terminal on the first carrier injection terminal side of the first sense circuit are connected via a first capacitor. The power supply potential of the second driver and the terminal on the second carrier injection terminal side of the second sense circuit are connected via the second capacitor. The semiconductor device according to claim 1.

4. The first driver includes a first bypass capacitor connected between its power supply potential and a reference potential. The second driver includes a second bypass capacitor connected between its power supply potential and a reference potential. The semiconductor device according to any one of claims 1 to 3.

5. The reference potential of the first driver and the reference potential of the second driver are connected in such a way that a DC signal can be transmitted between them. The semiconductor device according to any one of claims 1 to 3.

6. The first sense circuit includes a capacitor for the first sense circuit connected between the first control terminal and the first carrier injection terminal of the first transistor. The second sense circuit includes a capacitor for the second sense circuit connected between the second control terminal and the second carrier injection terminal of the second transistor. The semiconductor device according to any one of claims 1 to 3.

7. The first sense circuit includes a first resistor connected between the first control terminal and the first carrier injection terminal of the first transistor. The second sense circuit includes a second resistor connected between the second control terminal and the second carrier injection terminal of the second transistor. The semiconductor device according to any one of claims 1 to 3.

8. The first sense circuit includes a first Zener diode having a cathode connected to the first control terminal of the first transistor and an anode connected to the first carrier injection terminal. The second sense circuit includes a second Zener diode having a cathode connected to the second control terminal of the second transistor and an anode connected to the second carrier injection terminal. The semiconductor device according to any one of claims 1 to 3.

9. The first sense circuit is, A capacitor for the first sense circuit is connected between the first control terminal and the first carrier injection terminal of the first transistor, A first resistor connected between the first control terminal and the first carrier injection terminal of the first transistor, A first Zener diode having a cathode connected to the first control terminal of the first transistor and an anode connected to the first carrier injection terminal, Equipped with, The second sense circuit is, A capacitor for the second sense circuit is connected between the second control terminal and the second carrier injection terminal of the second transistor, A second resistor connected between the second control terminal and the second carrier injection terminal of the second transistor, A second Zener diode having a cathode connected to the second control terminal of the second transistor and an anode connected to the second carrier injection terminal, Equipped with, The semiconductor device according to any one of claims 1 to 3.

10. The first transistor is a field-effect transistor, The first control terminal is the gate of the first transistor, The first carrier injection terminal is the source of the first transistor, The second transistor is a field-effect transistor, The second control terminal is the gate of the second transistor, The second carrier injection terminal is the source of the second transistor. The semiconductor device according to any one of claims 1 to 3.

11. The first transistor is a bipolar transistor, The first control terminal is the base of the first transistor, The first carrier injection terminal is the emitter of the first transistor, The aforementioned second transistor is a bipolar transistor, The second control terminal is the base of the second transistor, The second carrier injection terminal is the emitter of the second transistor. The semiconductor device according to any one of claims 1 to 3.

12. The first transistor is an insulated gate bipolar transistor, The first control terminal is the gate of the first transistor, The first carrier injection terminal is the emitter of the first transistor, The second transistor is the insulated gate bipolar transistor, The second control terminal is the gate of the second transistor, The second carrier injection terminal is the emitter of the second transistor. The semiconductor device according to any one of claims 1 to 3.

13. A printed circuit board comprising the first driver, the second driver, the first sense circuit, and the second sense circuit, An insulating heat dissipation circuit board equipped with the aforementioned switching circuit, An outer casing covering the printed circuit board and the insulating heat dissipation circuit board, Equipped with, The semiconductor device according to any one of claims 1 to 3.

14. The aforementioned switching circuit is The first transistor, whose first carrier injection terminal is connected to the ground potential, The second transistor, to which the second carrier injection terminal is connected to the ground potential, A third transistor has its third carrier injection terminal connected to the first carrier receiving terminal of the first transistor, and its third carrier receiving terminal connected to the power supply potential. A fourth transistor, the second carrier receiving terminal of the second transistor, has its own fourth carrier injection terminal connected to the second carrier receiving terminal of the second transistor, and its own fourth carrier receiving terminal is connected to the power supply potential, Equipped with, The semiconductor device according to any one of claims 1 to 3.

15. The aforementioned switching circuit is A fifth transistor, whose fifth carrier injection terminal is connected to ground potential, A sixth transistor, whose fifth carrier receiving terminal is connected to its own sixth carrier injection terminal, and whose own sixth carrier receiving terminal is connected to the power supply potential, Equipped with, The semiconductor device according to claim 14.

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