Position synchronous circuit

Abstract

This invention provides a phase-locked circuit that can reduce noise generated by operation. [Solution] The phase-locked circuit includes a voltage-controlled oscillator that outputs a clock with a frequency corresponding to the input voltage; a first frequency divider that extracts a clock with a desired frequency by dividing the frequency of the clock output from the voltage-controlled oscillator; a second frequency divider that extracts a clock for comparison with a reference clock by dividing the frequency of the clock output from the voltage-controlled oscillator; a reset circuit that generates a reset release timing signal indicating the timing to release the reset of the first frequency divider based on at least the clock output from the voltage-controlled oscillator and the clock extracted by the second frequency divider; and a selector that selects one signal with a value corresponding to a specific set value from among the reset release timing signals and outputs the selected signal to the first frequency divider.

Description

Technical Field

[0001] The present invention relates to a phase synchronization circuit.

Background Art

[0002] [[ID=十二]]Generally, a phase-locked loop (PLL) is composed of a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage control oscillator (VCO), a feedback (FB) divider, etc. The PLL may be used particularly for frequency multiplication (see, for example, Patent Document 1). In this case, an oscillator with high frequency accuracy is input to the PLL as a reference clock, frequency multiplication is performed according to the division ratio of the FB divider, and an output divider is used for the output of the VCO to obtain a desired frequency after the PLL is locked (synchronized). For example, when the reference clock (REF_CLK) is 50 MHz and the FB divider divides by 20, the output clock (VCO_OUT) of the VCO after PLL locking is 1 GHz. By setting the output divider to divide by 4, divide by 2, or divide by 1 (through), three types of frequencies, 250 MHz, 500 MHz, and 1 GHz, can be obtained. The local oscillator used in a wireless device is realized by a PLL having such a configuration.

Prior Art Documents

Patent Documents

[0003] [[ID=2十二]]

Patent Document 1

[0004] [Summary] However, in the conventional technology, since the high-speed operating FB divider and output divider operate simultaneously, large noise is generated in power supply, GND, etc., deteriorating the noise of PLL_OUT which is the desired output clock.

[0005] This disclosure aims to provide a phase-locked circuit that can reduce noise generated by operation, taking the above circumstances into consideration.

[0006] The phase-locked circuit according to this disclosure includes: a voltage-controlled oscillator that outputs a clock with a frequency corresponding to an input voltage; a first frequency divider that extracts a clock with a desired frequency by dividing the frequency of the clock output from the voltage-controlled oscillator; a second frequency divider that extracts a clock for comparison with a reference clock by dividing the frequency of the clock output from the voltage-controlled oscillator; a reset circuit that generates a reset release timing signal indicating the timing to release the reset of the first frequency divider based on at least the clock output from the voltage-controlled oscillator and the clock extracted by the second frequency divider; and a selector that selects one signal with a value corresponding to a specific set value from among the reset release timing signals and outputs the selected signal to the first frequency divider. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a phase-locked circuit 100 according to an embodiment of this disclosure. [Figure 2] Figure 2 shows an example configuration of RESET_DELAY7. [Figure 3] Figure 3 is a timing chart illustrating the operation of the phase-locked circuit 100. [Figure 4] Figure 4 is a timing chart illustrating the operation of the phase-locked circuit 100. [Figure 5] Figure 5 shows an example of the configuration of RESET_DELAY7A related to a modified example. [Figure 6] Figure 6 is a timing chart illustrating the operation of a phase-locked circuit 100 equipped with a modified RESET_DELAY7A. [Figure 7] Figure 7 is a timing chart illustrating the operation of a phase-locked circuit 100 equipped with a modified RESET_DELAY7A. [Figure 8]Figure 8 is a timing chart illustrating the operation of a phase-locked circuit 100 equipped with a modified RESET_DELAY7A. [Figure 9] Figure 9 is a timing chart illustrating the operation of a modified phase-locked circuit 100 equipped with RESET_DELAY7A.

[0008] [Detailed explanation] The embodiments of the present invention will be described in detail below with reference to the drawings.

[0009] [Embodiment] Figure 1 shows an example configuration of a phase-locked circuit 100 according to an embodiment of this disclosure. The phase-locked circuit 100 includes a PFD1, CP2, Loop_Filter3, VCO4, output frequency divider5, FB frequency divider6, RESET_DELAY7, and SELECTOR8. Hereinafter, the phase-locked circuit 100 may be simply referred to as PLL.

[0010] PFD1 detects the phase and frequency difference between the clock inputs to in1 and in2. Specifically, PFD1 detects the phase and frequency difference between REF_CLK input to in1 and the output (FB_CLK) of the FB divider 6 in the PLL loop input to in2.

[0011] CP2 takes the phase and frequency shift detected by PFD1 as input and supplies current to the subsequent Loop_Filter3.

[0012] Loop_Filter3 converts the current from CP2 into a voltage and removes unwanted ripple.

[0013] VCO4 is a self-propelled oscillator that takes the voltage from which unwanted ripple has been removed by Loop_Filter3 as input, and its frequency is variable depending on the input voltage. In other words, VCO4 is an oscillator that outputs a frequency corresponding to the input voltage.

[0014] The output frequency divider 5 is a first frequency divider that divides the lock frequency of the PLL, that is, the output frequency of the VCO 4, to extract a desired frequency clock (PLL_OUT).

[0015] The FB frequency divider 6 is a frequency divider within the loop of the PLL, and is a second frequency divider that divides the output clock (VCO_OUT) of the VCO 4 to extract a clock FB_CLK for comparison with the phase and frequency of the REF_CLK.

[0016] The RESET_DELAY 7 is a circuit that generates the reset release timing of the output frequency divider 5. Specifically, the RESET_DELAY 7 is a reset circuit that generates a reset release timing signal (Q1 to QN: N is a natural number of 1 or more) indicating the timing to release the reset of the output frequency divider 5 based on at least the clock output from the VCO 4 and the clock extracted by the FB frequency divider 6.

[0017] The SELECTOR 8 is a circuit that selects any one of Q1 to QN. For example, it selects a signal corresponding to a value corresponding to the set value of RST_SEL from Q1 to QN, and outputs the selected signal (RSTN) to the output frequency divider 5.

[0018] FIG. 2 is a diagram showing a configuration example of the RESET_DELAY 7. The RESET_DELAY 7 may include an SR latch 7a and a plurality of D-type flip-flops (D-FF7b_1 to 7b_n: n is a natural number of 1 or more) constituting a shift register.

[0019] When a high-level signal is input to the set input S of the SR latch 7a, it becomes SET, outputs a high-level signal, that is, makes the output Q high level. When a low-level signal is input to the reset input RN, it becomes RESET, outputs a low-level signal, that is, makes the output Q low level. The shift register sequentially shifts the output of the SR latch 7a in synchronization with the VCO_OUT.

[0020] (Schematic operation of RESET_DELAY 7) Here, the general operation of RESET_DELAY7 will be described. When the level of the ENABLE signal shown in FIG. 1 changes from the low level (L) to the high level (H), the phase-locked loop circuit 100 starts operating. When FB_CLK becomes H, fb_clk_in, which is the input of RESET_DELAY7 shown in FIG. 1, becomes H. That is, FB_CLK is input to DELAY7. As a result, the SR latch 7a enters the SET state, and the output of Q transitions from L to H.

[0021] When this high-level (H) output is input to the subsequent shift register that operates with the output clock (VCO_OUT) of VCO4, Q1, Q2, Q3, ··· QN are sequentially output from the shift register. Q1 can be interpreted as the output of the first stage of the shift register. Similarly, Q2, Q3, and QN can be interpreted as the outputs of the second stage, the third stage, and the Nth stage of the shift register, respectively. Q1 to QN are output with a delay corresponding to the output clock of VCO4 (1 to n clocks).

[0022] SELECTOR8 shown in FIG. 1 selects one of Q1 to QN and transmits the selected signal (RSTN) to the output divider circuit 5. As a result, at the timing when the signal is selected by SELECTOR8 (reset release timing), the reset of the output divider circuit 5 is released.

[0023] Next, the operation of the phase-locked loop circuit 100 will be described with reference to FIGS. 3 and 4. FIGS. 3 and 4 are timing charts for explaining the operation of the phase-locked loop circuit 100. FIG. 3 shows the timing chart immediately after the phase-locked loop circuit 100 becomes ENABLE, and FIG. 4 shows the timing chart after the phase-locked loop circuit 100 is locked. Here, for simplicity of explanation, the case where the FB divider 6 in FIG. 1 divides by 20, the output divider 5 divides by 4, and the shift register of RESET_DELAY7 has a four-stage configuration will be described.

[0024] As shown in Figure 3, when REF_CLK is input and the level of the ENABLE signal changes from L to H, each block constituting the phase-locked circuit 100 enters the ENABLE state and starts operation. VCO4 starts self-oscillating, for example at time t1, and outputs a clock. FB divider 6 divides the output clock of VCO4 (VCO_OUT) and outputs the divided clock as FB_CLK.

[0025] Immediately after startup, FB_CLK does not match REF_CLK because the phase-lock circuit 100 is not yet locked. For example, when FB_CLK changes from L to H at time t2, after a certain period has elapsed from time t1, fb_clk_in of RESET_DELAY7 in Figure 1 becomes H, the SR latch 7a shown in Figure 2 enters the SET state, and the input to the shift register after the SR latch 7a is set to H.

[0026] Subsequently, when VCO_OUT is input, Q1 in the first stage of the shift register transitions to H. Similarly, Q2 to Q4 transition to H in response to VCO_OUT. Q1 is delayed by 1 CLK of VCO_OUT relative to FB_CLK, Q2 by 2 CLK, Q3 by 3 CLK, and Q4 by 4 CLK. SELECTOR8 (see Figure 1) in the subsequent stage selects one of Q1 to Q4, and the selected signal is input to the rn terminal (L reset) of the output frequency divider 5. For example, if SELECTOR8 selects a 4 CLK delay for Q4, the reset of the output frequency divider 5 is released and operation begins after a delay of 4 CLK of VCO_OUT from FB_CLK.

[0027] As shown in Figure 4, after the phase-lock circuit 100 locks at time t3, REF_CLK and FB_CLK are in phase and frequency matching. Furthermore, the relationship between FB_CLK and PLL_OUT does not change from the delay relationship shown in Figure 3. In other words, the phase relationship between FB_CLK and PLL_OUT is maintained even after locking.

[0028] Here, if, for example, Q1 is selected at time t4, the rising edge of PLL_OUT, the falling edge of REF_CLK, and the falling edge of FB_CLK overlap, which can increase noise from the power supply, GND, etc. Similarly, if Q1 is selected at time t5, the falling edge of PLL_OUT, the rising edge of REF_CLK, and the rising edge of FB_CLK overlap, which can also increase noise from the power supply, GND, etc.

[0029] At time t4, if Q3 is selected, for example, the falling edge of PLL_OUT, the falling edge of REF_CLK, and the falling edge of FB_CLK will overlap, which can similarly increase noise from the power supply, ground, etc. Similarly, at time t5, if Q3 is selected, the rising edge of PLL_OUT, the rising edge of REF_CLK, and the rising edge of FB_CLK will overlap, which can also similarly increase noise from the power supply, ground, etc.

[0030] In contrast, if, for example, Q2 is selected at time t4, no voltage change occurs in PLL_OUT. Therefore, the rising or falling edge of PLL_OUT does not overlap with the rising or falling edges of REF_CLK and FB_CLK, and the aforementioned noise can be suppressed. The same applies if Q4 is selected at time t4, or if, for example, Q2 or Q4 is selected at time t5.

[0031] As described above, when the output frequency divider 5 divides the frequency by 4, there are four possible phase relationships with respect to the clock phase of FB_CLK. According to this disclosure, by selecting a phase relationship that does not overlap with the edges of REF_CLK and FB_CLK, it becomes possible to suppress noise from the power supply, GND, etc.

[0032] [Differentiation] Figure 5 shows an example configuration of RESET_DELAY7A according to a modified example. RESET_DELAY7A may include a clock inverting circuit 7c in addition to the SR latch 7a and D-FF7b_1~7b_n. The clock inverting circuit 7c may be interpreted as a circuit that inverts the clock included in VCO_OUT. For example, when the level of the clock inverting control signal (SEL_INV) is set to L, the clock inverting circuit 7c selects and outputs the rising edge of the clock included in VCO_OUT. On the other hand, when the level of SEL_INV is set to H, the clock inverting circuit 7c selects and outputs the falling edge of the clock included in VCO_OUT.

[0033] Thus, the clock inverting circuit 7c has a clock inverting function that inverts the clock of VCO_OUT. When a high level (H) fb_clk_in is input to RESET_DELAY7A, the subsequent shift register can select the rising edge or falling edge of the clock, making it possible to set the output timing of the shift register to half of the VCO output period. This makes it possible to adjust the reset release timing of the output frequency divider 5 more precisely.

[0034] Figures 6 to 9 are timing charts illustrating the operation of a modified phase-locked circuit 100 equipped with RESET_DELAY7A. Figure 6 shows the timing chart when SEL_INV is at a low level (L) immediately after the phase-locked circuit 100 is ENABLE, i.e., when the clock inversion function is OFF and the rising edge clock is used. The operation in this case is the same as in Figure 3.

[0035] Figure 7 shows the timing chart when SEL_INV is high (H) immediately after the phase-lock circuit 100 is ENABLE, meaning the clock inversion function is ON and the falling-edge clock is used. In this case, PLL_OUT is output at the timing of the falling-edge clock of VCO_OUT.

[0036] Figure 8 shows the timing chart when SEL_INV=L after the phase-lock circuit 100 is locked, and the operation in this case is the same as in Figure 4.

[0037] Figure 9 shows the timing chart when SEL_INV=H after the phase-lock circuit 100 is locked. In this case, PLL_OUT is output at the falling edge clock timing of VCO_OUT.

[0038] As described above, the phase-lock circuit 100 is equipped with RESET_DELAY7 (RESET_DELAY7A) and SELECTOR8, and by adjusting the reset release time of the output frequency divider 5, it is possible to adjust the edge of the output of the output frequency divider 5 (PLL_OUT) so that it does not overlap with the edge of REF_CLK and the edge of FB_CLK, thereby suppressing noise from the power supply, GND, etc. caused by edge overlap, and suppressing noise in PLL_OUT.

[0039] Furthermore, by adding the clock inverting circuit 7c, it becomes possible to adjust the reset release timing of the output frequency divider 5 with an accuracy of half the clock period of PLL_OUT, allowing for more precise adjustment of the complex noise control.

[0040] For simplicity, this disclosure describes the case where the FB divider 6 divides the frequency by 20, the output divider 5 divides the frequency by 4, and the internal shift register of RESET_DELAY7 (RESET_DELAY7A) has a 4-stage configuration. However, it is possible to accommodate different frequencies of division as needed.

[0041] Although this disclosure describes an integer PLL, the configuration described herein is also applicable to fractional PLLs.

[0042] The embodiments described above are merely illustrative, and any modifications or improvements may be applied.

[0043] Furthermore, one or more elements included in one of the above multiple embodiments can be combined with one or more elements included in other embodiments of the above multiple embodiments.

[0044] (Additional notes) (Note 1) A voltage-controlled oscillator that outputs a clock with a frequency corresponding to the input voltage, A first frequency divider extracts a clock of a desired frequency by dividing the frequency of the clock output from the voltage-controlled oscillator, A second frequency divider extracts a clock for comparison with a reference clock by dividing the frequency of the clock output from the voltage-controlled oscillator, A reset circuit that generates a reset release timing signal indicating the timing to release the reset of the first frequency divider, based at least on the clock output from the voltage-controlled oscillator and the clock extracted by the second frequency divider, A selector that selects one signal from the reset release timing signals that corresponds to a specific set value and outputs the selected signal to the first frequency divider, A phase-locked circuit equipped with the following features. (Note 2) The aforementioned reset circuit is A latch that outputs a high-level signal when a high-level signal is input to the set input, and outputs a low-level signal when a low-level signal is input to the reset input. A shift register that sequentially shifts the output of the latch in synchronization with the clock output from the voltage-controlled oscillator, A phase-locked circuit as described in Appendix 1, including the one described in Appendix 1. (Note 3) The system further includes a selection circuit that selects the rising edge or falling edge of the clock based on a clock inversion control signal that inverts the clock output from the voltage-controlled oscillator. The shift register is a phase-locked circuit as described in Appendix 1 or 2, which sequentially shifts the output of the latch in synchronization with the rising or falling edge of the clock selected by the selection circuit. [Explanation of Symbols]

[0045] 1 PFD 2 CP 3 Loop Filter 4 VCO 5. Output frequency divider 6 FB frequency divider 7 RESET_DELAY 7A RESET_DELAY 7a SR latch 7b_1~7b_n D-FF 7c Clock Inverter Circuit 8 SELECTOR 100 phase synchronized circuit

Claims

1. A voltage-controlled oscillator that outputs a clock with a frequency corresponding to the input voltage, A first frequency divider extracts a clock of a desired frequency by dividing the frequency of the clock output from the voltage-controlled oscillator, A second frequency divider extracts a clock for comparison with a reference clock by dividing the frequency of the clock output from the voltage-controlled oscillator, A reset circuit that generates a reset release timing signal indicating the timing to release the reset of the first frequency divider, based at least on the clock output from the voltage-controlled oscillator and the clock extracted by the second frequency divider, A selector that selects one signal from the reset release timing signals that corresponds to a specific set value and outputs the selected signal to the first frequency divider, A phase-locked circuit equipped with the following features.

2. The aforementioned reset circuit is A latch that outputs a high-level signal when a high-level signal is input to the set input, and outputs a low-level signal when a low-level signal is input to the reset input. A shift register that sequentially shifts the output of the latch in synchronization with the clock output from the voltage-controlled oscillator, The phase-locked circuit according to claim 1, including the above.

3. The system further includes a selection circuit that selects the rising edge or falling edge of the clock based on a clock inversion control signal that inverts the clock output from the voltage-controlled oscillator. The phase-synchronous circuit according to claim 2, wherein the shift register sequentially shifts the output of the latch in synchronization with the rising edge or falling edge of the clock selected by the selection circuit.

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