Multilayer electronic components

Abstract

We provide stacked electronic components with excellent high-temperature reliability. [Solution] In a stacked electronic component, the dielectric layer 111 includes a central portion CP containing first dielectric crystal grains separated from the internal electrodes 121 and 122, and interface portions IP1 and IP2 disposed between the internal electrodes and the central portion and containing second dielectric crystal grains. When the average size of the first dielectric crystal grain G1 is Gs1, the average size of the second dielectric crystal grain G2 is Gs2, the number of moles of Dy per 100 moles of Ti in the central portion is Mdy1, and the number of moles of Dy per 100 moles of Ti in the interface portion is Mdy2, then Gs2 / Gs1 < 1, Mdy1 ≤ 0.1 and 0.1

Description

[Technical Field]

[0001] This invention relates to a stacked electronic component. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC), a type of multilayer electronic component, is a chip-type capacitor that is mounted on the printed circuit boards of various electronic products such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and plays the role of charging or discharging electricity.

[0003] Multilayer ceramic capacitors offer the advantages of being small yet guaranteeing high capacitance and being easy to mount, making them suitable for use as components in various electronic devices. As electronic devices such as computers and mobile devices become smaller and more powerful, the demand for smaller and / or higher-capacitance multilayer ceramic capacitors is increasing.

[0004] Furthermore, as the operating environments for multilayer ceramic capacitors become more diverse, reliability at high temperatures is also required.

[0005] Adding Dy to the dielectric layer makes it easier to ensure reliability in high-temperature environments, but there was a risk of reduced capacitance in the multilayer ceramic capacitor.

[0006] Therefore, there is a need to develop new multilayer ceramic capacitors with structures that offer excellent high-temperature reliability and high capacitance. [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] One of the several objects of the present invention is to provide a multilayer electronic component with excellent reliability.

[0008] One of the several objects of the present invention is to provide a multilayer electronic component with excellent high-temperature reliability.

[0009] One of the several objects of the present invention is to provide a multilayer electronic component capable of ensuring a high capacitance.

[0010] However, the object of the present invention is not limited to the above content and can be more easily understood in the process of explaining the specific embodiments of the present invention.

Means for Solving the Problems

[0011] A multilayer electronic component according to an embodiment of the present invention includes a main body including a dielectric layer and internal electrodes alternately arranged with the dielectric layer, and external electrodes arranged on the main body. The dielectric layer includes a central portion spaced from the internal electrodes and including first dielectric crystal grains, and an interface portion arranged between the internal electrodes and the central portion and including second dielectric crystal grains. When the average size of the first dielectric crystal grains is Gs1, the average size of the second dielectric crystal grains is Gs2, the number of moles of Dy per 100 moles of Ti in the central portion is Mdy1, and the number of moles of Dy per 100 moles of Ti in the interface portion is Mdy2, Gs2 / Gs1 < 1, Mdy1 ≤ 0.1, and 0.1 < Mdy2 < 0.7 can be satisfied.

Effects of the Invention

[0012] As one of the several effects of the present invention, by controlling the average size and Dy content of the dielectric crystal grains in the interface portion and the central portion of the dielectric layer, the reliability of the multilayer electronic component can be improved.

[0013] However, the various and beneficial advantages and effects of the present invention are not limited to the above content and can be more easily understood in the process of explaining the specific embodiments of the present invention.

Brief Description of the Drawings

[0014] [Figure 1] Briefly shows the perspective view of a laminated electronic component-related to an embodiment of the present invention. [Figure 2] Briefly shows the sectional view taken along the line I-I' of FIG. 1. [Figure 3] Briefly shows the sectional view taken along the line II-II' of FIG. 1. [Figure 4] Shows the disassembled body of FIG. 1. [Figure 5] Is an enlarged view of the K1 region of FIG. 2.

Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Also, the embodiments of the present invention are provided to more fully explain the present invention to ordinary technicians. Therefore, the shape and size of elements in the drawings can be exaggerated for a clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0016] And, in order to clearly explain the present invention in the drawings, parts not related to the explanation are omitted, and the sizes and thicknesses of each configuration shown in the drawings are arbitrarily shown for the convenience of explanation, so the present invention is not necessarily limited to what is shown in the drawings. In addition, for components having the same function within the scope of the same idea, the same reference numerals are used for explanation. Furthermore, throughout the specification, when a certain part says that a certain component "includes", this means that other components can be further included, rather than excluding other components, unless otherwise stated.

[0017] In the drawings, the X direction can be defined as the first direction, the stacking direction or the thickness T direction, the Y direction as the second direction or the length L direction, and the Z direction as the third direction or the width W direction.

[0018] Multilayer electronic component FIG. 1 schematically shows a perspective view of a multilayer electronic component according to an embodiment of the present invention. FIG. 2 schematically shows a cross-sectional view taken along the line I-I' of FIG. 1. FIG. 3 schematically shows a cross-sectional view taken along the line II-II' of FIG. 1. FIG. 4 shows the main body of FIG. 1 disassembled. FIG. 5 is an enlarged view of the K1 region of FIG. 2.

[0019] Hereinafter, referring to FIGS. 1 to 5, a multilayer electronic component 100 according to an embodiment of the present invention will be described in detail. Further, as an example of the multilayer electronic component, a multilayer ceramic capacitor (hereinafter referred to as "MLCC") will be described. However, the present invention is not limited thereto, and it can also be applied to various multilayer electronic components using a ceramic material, such as an inductor, a piezoelectric element, a varistor, or a thermistor.

[0020] A multilayer electronic component 100 according to an embodiment of the present invention includes a main body 110 including a dielectric layer 111 and internal electrodes 121 and 122 alternately arranged with the dielectric layer, and external electrodes 131 and 132 arranged on the main body. The dielectric layer 111 includes a central portion CP spaced apart from the internal electrodes and including first dielectric crystal grains G1, and interface portions IP1 and IP2 arranged between the internal electrodes and the central portion and including second dielectric crystal grains G2. When the average size of the first dielectric crystal grains is Gs1, the average size of the second dielectric crystal grains is Gs2, the number of moles of Dy per 100 moles of Ti in the central portion is Mdy1, and the number of moles of Dy per 100 moles of Ti in the interface portion is Mdy2, Gs2 / Gs1 < 1, Mdy1 ≦ 0.1, and 0.1 < Mdy2 < 0.7 can be satisfied.

[0021] When Dy is added to the dielectric layer, it is easy to ensure reliability in a high-temperature environment, but there is a risk that the capacitance of the multilayer ceramic capacitor may decrease.

[0022] According to one embodiment of the present invention, by increasing the Dy content of the interface IP1 and IP2 compared to the central CP, and reducing the average size of the dielectric crystal grains, it is possible to improve the high-temperature reliability of the stacked electronic component 100 while suppressing the decrease in capacitance due to the addition of Dy.

[0023] The following describes the various components included in the stacked electronic component 100 according to one embodiment of the present invention.

[0024] The main body 110 may have dielectric layers 111 and internal electrodes 121 and 122 stacked alternately.

[0025] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be a hexahedron or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 is not a perfectly straight hexahedron, but can be substantially hexahedron-shaped.

[0026] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2 and connected to the third surface 3 and the fourth surface 4 and facing each other in a third direction.

[0027] Due to the overlap of margin regions on the dielectric layer 111 where internal electrodes 121 and 122 are not placed, a step difference is generated due to the thickness of the internal electrodes 121 and 122, and the corners connecting the first surface with the third, fourth, and fifth surfaces and / or the corners connecting the second surface with the third, fourth, and fifth surfaces may have a form that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, due to the contraction behavior during the sintering process of the main body, the corners connecting the first surface 1 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 and / or the corners connecting the second surface 2 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 may have a form that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, in order to prevent chipping defects, the corners connecting each face of the main body 110 can be rounded by performing a separate process to round the corners connecting the first face with the third, fourth, fifth, and sixth faces, and / or the corners connecting the second face with the third, fourth, fifth, and sixth faces.

[0028] On the other hand, in order to suppress the step difference caused by the internal electrodes 121 and 122, if the internal electrodes after lamination are cut so that they are exposed on the fifth surface 5 and sixth surface 6 of the main body, and then a single dielectric layer or two or more dielectric layers are laminated on both sides of the capacitance forming portion Ac in the third direction (width direction) to form side margin portions 114 and 115, the portions connecting the first surface with the fifth and sixth surfaces, and the portions connecting the second surface with the fifth and sixth surfaces, do not need to have a contracted form.

[0029] The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM). There is no particular limit to the number of dielectric layers stacked, and it can be determined considering the size of the multilayer electronic component. For example, the main body can be formed by stacking 400 or more dielectric layers.

[0030] Referring to FIG. 5, the dielectric layer 111 is separated from the internal electrodes 121 and 122, and can include a central portion CP including the first dielectric crystal grains G1 and interface portions IP1 and IP2 disposed between the internal electrodes 121 and 122 and the central portion CP and including the second dielectric crystal grains G2.

[0031] Also, when the average size of the first dielectric crystal grains G1 is Gs1, the average size of the second dielectric crystal grains G2 is Gs2, the number of moles of Dy with respect to 100 moles of Ti in the central portion CP is Mdy1, and the number of moles of Dy with respect to 100 moles of Ti in the interface portions IP1 and IP2 is Mdy2, Gs2 / Gs1 < 1, Mdy1 ≤ 0.1, and 0.1 < Mdy < 0.7 can be satisfied. Thereby, while suppressing the capacitance reduction due to the addition of Dy, high-temperature reliability can be ensured.

[0032] When the average size (Gs1) of the first dielectric crystal grains is smaller than the average size (Gs2) of the second dielectric crystal grains, it may be difficult to ensure high-temperature reliability.

[0033] When Mdy1 exceeds 0.1, the capacitance may decrease. On the other hand, the central portion CP does not necessarily have to contain Dy, and the central portion CP may not contain Dy, and thus, Mdy1 may be 0.

[0034] When Mdy2 is 0.1 or less, it may be difficult to ensure high-temperature reliability, and when Mdy2 is 0.7 or more, there is a possibility that the capacitance may decrease. Therefore, it is preferable to satisfy 0.1 < Mdy2 < 0.7, and more preferably, 0.2 ≤ Mdy2 ≤ 0.6 can be satisfied.

[0035] In one embodiment, Gs1 and Gs2 can satisfy Gs2 / Gs1 < 0.7. Thereby, the effect of suppressing the capacitance reduction and improving the high-temperature reliability of the present invention can be further improved.

[0036] On the other hand, the specific ranges of Gs1 and Gs2 do not need to be particularly limited.

[0037] For example, in one embodiment, Gs2 may be between 50 nm and 180 nm, and Gs1 may be between 100 nm and 300 nm. This further enhances the effect of suppressing capacity degradation and improving high-temperature reliability of the present invention.

[0038] In one embodiment, Gs1 and Gs2 can satisfy the condition Gs1-Gs2 > 70 nm. This further enhances the effect of suppressing capacity degradation and improving high-temperature reliability of the present invention.

[0039] On the other hand, the average size of the first dielectric crystal grains (Gs1), the average size of the second dielectric crystal grains (Gs2), the number of moles of Dy per 100 moles of Ti in the central region (Mdy1), and the number of moles of Dy per 100 moles of Ti in the interface region (Mdy2) may be measured from image images obtained by observing the cross-sections of the main body 110 in the first and second directions using SEM-EDS (Scanning Electron Microscope-Energy Dispersive X-ray Spectrometer), TEM-EDS (Transmission Electron Microscope-Energy Dispersive X-ray Spectrometer), STEM-EDS (Scanning Transmission Electron Microscope-Energy Dispersive X-ray Spectrometer), or FE-SEM-EDS (Field Emission-scanning Electron Microscope-Energy Dispersive X-ray Spectrometer).

[0040] More specifically, the multilayer electronic component 100 is polished up to the halfway point in the third direction to expose the cross-sections of the multilayer electronic component 100 in the first and second directions. Then, using FE-SEM-EDS (acceleration voltage: 2kV, magnification: 50,000x), the average size of the dielectric crystal grains can be measured at the interface and the central part of the dielectric layer located in the central part of the first direction of the capacitance-forming portion Ac. Because the size of the dielectric crystal grains changes abruptly at the boundary between the interface and the central part, the interface and the central part can be easily distinguished from the image scanned by the SEM. The size of the dielectric crystal grains may also be measured by measuring the equivalent diameter of a circle using image analysis software (ImageJ), and the sizes of 30 or more dielectric crystal grains at the interface and the central part can be averaged to obtain Gs1 and Gs2.

[0041] Furthermore, the content (mol%) of Dy and Ti is measured in both the interface and the central region. This allows us to calculate the number of moles of Dy per 100 moles of Ti in the interface and central region, respectively, and determine Mdy1 and Mdy2.

[0042] On the other hand, by selecting 10 dielectric layers located in the upper, central, and lower parts of the capacitance-forming section Ac in the first direction, and calculating Gs1, Gs2, Mdy1, and Mdy2 for a total of 30 dielectric layers, the average value of these values ​​can be calculated to further generalize Gs1, Gs2, Mdy1, and Mdy2.

[0043] In one embodiment, the internal electrodes 121 and 122 include a first internal electrode 121 and a second internal electrode 122 that are alternately arranged with a dielectric layer 111 in between, and the interface portions IP1 and IP2 may include a first interface portion IP1 arranged between the central portion CP and the first internal electrode 121, and a second interface portion IP2 arranged between the central portion CP and the second internal electrode 122.

[0044] In one embodiment, when the average thickness of the first interface IP1 is tdi1, the average thickness of the second interface IP2 is tdi2, and the average thickness of the central CP is tdc, the conditions tdi1 / tdc ≤ 0.05 and tdi2 / tdc ≤ 0.05 can be satisfied. If tdi1 / tdc is greater than 0.05 or tdi2 / tdc is greater than 0.05, the capacity degradation suppression effect according to the present invention may be insufficient.

[0045] On the other hand, there is no need to specifically limit the scope of each of tdi1, tdi2, and tdc.

[0046] For example, in one embodiment, tdi1 and tdi2 may each be between 50 nm and 500 nm.

[0047] In one embodiment, the above TDC may be 1000 nm or more.

[0048] In one embodiment, the sum of tdi1, tdi2, and tdc may be 1.05 μm or more and 10 μm or less. Here, the sum of tdi1, tdi2, and tdc can represent the average thickness td of the dielectric layer.

[0049] Here, tdi1, tdi2, and tdc can represent the thickness in the first direction. tdi1, tdi2, and tdc can be measured by scanning the cross-sections of the main body 110 in the first and second directions with a scanning electron microscope (SEM) at 10,000x magnification. The thicknesses of the first interface IP1, the second interface IP2, and the central CP can be measured at 30 equally spaced points in the second direction, and their average values ​​can be calculated. These 30 equally spaced points can be specified by the capacitance forming section Ac, which will be described later. Furthermore, by extending this average value measurement to 10 dielectric layers 111 and measuring the average values, tdi1, tdi2, and tdc can be further generalized.

[0050] The method for forming the dielectric layer 111 is not particularly limited.

[0051] For example, a ceramic slurry containing a ceramic powder for the central part, a ceramic powder for the interface part having a smaller average particle size than the ceramic powder for the central part, an organic solvent, and a binder is applied onto a carrier film to provide a ceramic green sheet. At this time, the ceramic green sheet can be manufactured such that the ceramic powder for the interface part, the ceramic powder for the central part, and the ceramic powder for the interface part are arranged in this order. At this time, the ceramic green sheet can be manufactured such that the ceramic powder for the interface part, the ceramic powder for the central part, and the ceramic powder for the interface part are laminated in this order. Further, the ceramic green sheet can be manufactured such that the Dy content in the region where the ceramic powder for the interface part is disposed is higher than the Dy content in the region where the ceramic powder for the central part is disposed. Thereafter, a dielectric layer can be formed by sintering the ceramic green sheet.

[0052] For example, the ceramic powder for the central part can have a particle size of 100 nm or more and 250 nm or less, and the ceramic powder for the interface part can have a particle size of 70% or less than the particle size of the ceramic powder for the central part.

[0053] The ceramic powder for the central part and the ceramic powder for the interface part are not particularly limited as long as a sufficient capacitance can be obtained. For example, a barium titanate (BaTiO3)-based powder can be used as the ceramic powder for the central part and the ceramic powder for the interface part. As a more specific example, the ceramic powder for the central part and the ceramic powder for the interface part are BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), and Ba(Ti 1-y Zr y )O3 (0 < y < 1), and one or more of them may be used.

[0054] Therefore, in one embodiment, the dielectric layer 111 may contain, as a main component, one or more of BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), and Ba(Ti 1-y Zr y )O3 (0 < y < 1). Here, the main component can be defined as having 30 moles or less of the remaining components excluding the main component per 100 moles of the main component.

[0055] The main body 110 may include a capacitance forming portion Ac that is disposed inside the main body 110 and in which a capacitance is formed by including a first internal electrode 121 and a second internal electrode 122 that are disposed to face each other with the dielectric layer 111 interposed therebetween, and cover portions 112 and 113 formed above and below the capacitance forming portion Ac in a first direction.

[0056] Further, the capacitance forming portion Ac is a portion that contributes to the formation of the capacitance of the capacitor, and can be formed by repeatedly laminating a plurality of first internal electrodes 121 and second internal electrodes 122 with the dielectric layer 111 interposed therebetween.

[0057] The cover portions 112 and 113 may include an upper cover portion 112 disposed above the capacitance forming portion Ac in a first direction and a lower cover portion 113 disposed below the capacitance forming portion Ac in a first direction.

[0058] The upper cover portion 112 and the lower cover portion 113 can be formed by laminating a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming portion Ac, respectively, and can basically serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0059] The upper cover portion 112 and the lower cover portion 113 described above do not include internal electrodes and may contain the same material as the dielectric layer 111.

[0060] In other words, the upper cover portion 112 and the lower cover portion 113 can include ceramic materials, for example, barium titanate (BaTiO3) based ceramic materials.

[0061] On the other hand, the thickness of the cover portions 112 and 113 is not particularly limited. However, in order to more easily achieve miniaturization and high capacitance of the stacked electronic component, the thickness tc of the cover portions 112 and 113 may be 15 μm or less.

[0062] The average thickness tc of the cover portions 112 and 113 can represent the size in the first direction, and can be the average value of the sizes of the cover portions 112 and 113 in the first direction measured at five equally spaced points on the upper or lower part of the volume forming portion Ac.

[0063] Furthermore, margin portions 114 and 115 may be arranged on the side surface of the volume-forming portion Ac.

[0064] The margin portions 114 and 115 may include a first margin portion 114 located on the fifth surface 5 of the main body 110 and a second margin portion 115 located on the sixth surface 6. That is, the margin portions 114 and 115 may be located on both end surfaces in the width direction of the ceramic main body 110.

[0065] As shown in Figure 5, the margin portions 114 and 115 can refer to the regions between the interface between both ends of the first internal electrode 121 and the second internal electrode 122 and the body 110 in a cross-section obtained by cutting the body 110 in the width-thickness (WT) direction.

[0066] The margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0067] The margin portions 114 and 115 may be formed by applying a conductive paste to the ceramic green sheet, except for the areas where the margin portions are formed, to form internal electrodes.

[0068] Furthermore, in order to suppress the step caused by the internal electrodes 121 and 122, after cutting the laminated internal electrodes so that they are exposed on the fifth and sixth surfaces 5 and 6 of the main body, a single dielectric layer or two or more dielectric layers can be laminated in the third direction (width direction) on both sides of the capacitance forming portion Ac to form margin portions 114 and 115.

[0069] On the other hand, the width of the margin portions 114 and 115 does not need to be particularly limited. However, in order to more easily achieve miniaturization and high capacitance of the multilayer electronic component, the average width of the margin portions 114 and 115 may be 15 μm or less.

[0070] The average width of the margin portions 114 and 115 can represent the average size MW1 in the third direction of the region where the internal electrode is separated from the fifth surface and the average size MW2 in the third direction of the region where the internal electrode is separated from the sixth surface, and can be the average value of the sizes of the margin portions 114 and 115 in the third direction measured at five equally spaced points on the side surface of the capacitance forming portion Ac.

[0071] Therefore, in one embodiment, the average sizes MW1 and MW2 in the third direction of the regions where the internal electrodes 121 and 122 are separated from the fifth and sixth surfaces may each be 15 μm or less.

[0072] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122. The first internal electrode 121 and the second internal electrode 122 are arranged alternately so as to face each other across the dielectric layer 111 that constitutes the main body 110, and can be exposed on the third surface 3 and the fourth surface 4 of the main body 110, respectively.

[0073] The first internal electrode 121 is exposed via the third surface 3, separated from the fourth surface 4, and the second internal electrode 122 can be exposed via the fourth surface 4, separated from the third surface 3. The first external electrode 131 is positioned on the third surface 3 of the main body and connected to the first internal electrode 121, and the second external electrode 132 is positioned on the fourth surface 4 of the main body and connected to the second internal electrode 122.

[0074] In other words, the first internal electrode 121 is not connected to the second external electrode 132 but is connected to the first external electrode 131, and the second internal electrode 122 is not connected to the first external electrode 131 but is connected to the second external electrode 132. Therefore, the first internal electrode 121 can be formed at a certain distance from the fourth surface 4, and the second internal electrode 122 can be formed at a certain distance from the third surface 3. Furthermore, the first internal electrode 121 and the second internal electrode 122 may be arranged at a distance from the fifth and sixth surfaces of the main body 110.

[0075] The conductive metals contained in the internal electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, In, Sn, Al, W, Ti, and their alloys, and the present invention is not limited thereto.

[0076] The average thickness te of the internal electrodes does not need to be particularly limited. In this case, the thickness of the internal electrodes 121 and 122 can represent the size of the internal electrodes 121 and 122 in the first direction.

[0077] However, in order to more easily achieve miniaturization and high capacitance of the multilayer electronic component, the average thickness of the internal electrodes 121 and 122 may be 0.4 μm or less.

[0078] Here, the average thickness te of the internal electrodes can be measured by scanning the cross-sections of the main body 110 in the first and second directions with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the thickness of one internal electrode 121, 122 can be measured at multiple points, for example, 30 points equally spaced in the second direction, and the average value can be measured. The 30 equally spaced points can be specified in the capacitance forming section Ac. Furthermore, by extending this average value measurement to 10 internal electrodes 121, 122 and measuring the average value, the average thickness of the internal electrodes 121, 122 can be further generalized.

[0079] External electrodes 131 and 132 may be arranged on the third surface 3 and fourth surface 4 of the main body 110.

[0080] The external electrodes 131 and 132 are arranged on the third surface 3 and fourth surface 4 of the main body 110, respectively, and may include a first external electrode 131 and a second external electrode 132 that are connected to a first internal electrode 121 and a second internal electrode 122, respectively.

[0081] Referring to Figure 1, the external electrodes 131 and 132 can be positioned to cover both end faces of the side margin portions 114 and 115 in the second direction.

[0082] In this embodiment, a structure in which the stacked electronic component 100 has two external electrodes 131 and 132 is described, but the number and shape of the external electrodes 131 and 132 can be changed according to the form of the internal electrodes 121 and 122 or other purposes.

[0083] On the other hand, the external electrodes 131 and 132 may be formed using any material that has electrical conductivity, such as metal, and the specific material may be determined by considering electrical properties, structural stability, etc., and may also have a multilayer structure.

[0084] For example, the external electrodes 131 and 132 may include electrode layers 131a and 132a placed on the main body 110, and plating layers 131b and 132b formed on the electrode layers 131a and 132a.

[0085] As a more specific example for electrode layers 131a and 132a, electrode layers 131a and 132a may be firing electrodes containing conductive metal and glass, or resin-based electrodes containing conductive metal and resin.

[0086] Furthermore, the electrode layers 131a and 132a may be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body. Also, the electrode layers 131a and 132a may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto a fired electrode.

[0087] While any material with excellent electrical conductivity can be used as the conductive metal in the electrode layers 131a and 132a, it is not particularly limited. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and their alloys.

[0088] The plating layers 131b and 132b play a role in improving mounting characteristics. The types of plating layers 131b and 132b are not particularly limited and may be plating layers containing one or more of Ni, Sn, Pd, and their alloys, and may be formed in multiple layers.

[0089] As a more specific example for the plating layers 131b and 132b, the plating layers 131b and 132b may be Ni plating layers or Sn plating layers, and may be in a form in which Ni plating layers and Sn plating layers are formed sequentially on the electrode layers 131a and 132a, or may be in a form in which Sn plating layers, Ni plating layers, and Sn plating layers are formed sequentially. Furthermore, the plating layers 131b and 132b may include multiple Ni plating layers and / or multiple Sn plating layers.

[0090] The size of the multilayer electronic component 100 is not particularly limited. For example, the size of the multilayer electronic component 100 may be 0201 (length x width, 0.2 mm x 0.1 mm), 0603 (length x width, 0.6 mm x 0.3 mm), 1005 (length x width, 1.0 mm x 0.5 mm), etc.

[0091] Manufacturing method for multilayer electronic components The following describes an example of a method for manufacturing a stacked electronic component 100 according to one embodiment of the present invention. However, the method for manufacturing the stacked electronic component 100 of the present invention is not limited thereto.

[0092] First, a ceramic slurry containing a central ceramic powder, an interface ceramic powder with a smaller average particle size than the central ceramic powder, an organic solvent, and a binder is applied to a carrier film to form a ceramic green sheet. At this time, the ceramic green sheet can be manufactured so that the interface ceramic powder is arranged in the order of central ceramic powder, interface ceramic powder, and interface ceramic powder. At this time, the ceramic green sheet can be manufactured so that the interface ceramic powder is layered in the order of central ceramic powder, interface ceramic powder, and interface ceramic powder. Furthermore, the ceramic green sheet can be manufactured so that the Dy content in the region where the interface ceramic powder is arranged is higher than that in the region where the central ceramic powder is arranged.

[0093] For example, the ceramic powder for the central part may have a particle size of 100 nm to 250 nm, and the ceramic powder for the interface may have a particle size of 70% or less of the particle size of the ceramic powder for the central part.

[0094] Subsequently, a conductive paste for internal electrodes containing metal powder, binder, organic solvent, etc., is printed onto the ceramic green sheet to a predetermined thickness using screen printing or gravure printing to form an internal electrode pattern, thereby producing a ceramic green sheet for the capacitance forming section.

[0095] A laminate can be obtained by stacking ceramic green sheets for the volume-forming section in the X direction. In this case, ceramic green sheets without internal electrode patterns can be stacked on the upper and lower parts of the laminate to form cover sections 112 and 113 after sintering.

[0096] Subsequently, the laminate is cut to have a predetermined chip size. At this time, the ends of the internal electrode pattern are exposed on both sides of the cut chip facing the third direction.

[0097] Next, the margin-forming sheet can be attached to both sides of the cut chip in the third direction and then fired to form the main body 110 and the side margin portions 114 and 115. The firing temperature may be, for example, 1000°C or more and 1400°C or less, but the present invention is not limited thereto.

[0098] The sheet used for forming the margin area is not particularly limited, and the general ceramic green sheet described above can be used.

[0099] Next, external electrodes 131 and 132 are formed. For example, if the base electrode layers 131a and 132a include a fired electrode layer, the main body 110 can be dipped in a conductive paste for external electrodes containing metal powder, glass frit, binder, and organic solvent, and then the conductive paste for external electrodes can be fired at a temperature of 500°C to 900°C to form a fired electrode layer.

[0100] For example, if the base electrode layers 131a and 132a include a resin electrode layer, the main body can be dipped in a conductive resin composition containing metal powder, resin, binder, and organic solvent, and then cured at a temperature of 250°C to 550°C to form the resin electrode layer.

[0101] Furthermore, electroplating and / or electroless plating may be performed to form plating layers 131b and 132b on the underlying electrode layers 131a and 132a.

[0102] (Example of experiment) Using the manufacturing method described above, sample chips of size 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm, thickness: approximately 0.5 mm) were prepared.

[0103] Sample chips were fabricated such that the average size of the first dielectric crystal grain (Gs1), the average size of the second dielectric crystal grain (Gs2), the number of moles of Dy per 100 moles of Ti in the central region (Mdy1), and the number of moles of Dy per 100 moles of Ti in the interface region (Mdy2) all satisfy Table 1 below.

[0104] The average size of the first dielectric grain (Gs1), the average size of the second dielectric grain (Gs2), the number of moles of Dy per 100 moles of Ti in the central region (Mdy1), and the number of moles of Dy per 100 moles of Ti at the interface (Mdy2) were measured by analyzing the cross-sections in the first and second directions of the sample tip, polished to the halfway point in the third direction, using FE-SEM-EDS (acceleration voltage: 2kV, magnification: 50,000x).

[0105] The capacitance of the sample chips was measured using an LCR meter at 1 kHz, and the relative values ​​are shown in Table 1 below.

[0106] Furthermore, for each sample chip with a test number, a high-temperature load test was performed under conditions of 150°C and 100V. The time at which the insulation resistance became 10kΩ or less was measured as the MTTF (Mean Time To Failure), and this is listed in Table 1 below.

[0107] [Table 1]

[0108] Referring to Table 1, it can be seen that test number 1, where Mdy1 and Mdy2 are 0, has the best capacity but poor high-temperature reliability. Test numbers 2 and 3, which have small amounts of Dy added, also show poor high-temperature reliability. In the case of test numbers 5 to 7, it can be seen that the amount of Dy added was large, resulting in a decrease in capacity.

[0109] On the other hand, in the case of Test No. 4 that satisfies all of Gs2 / Gs1 < 1, Mdy1 ≤ 0.1, and 0.1 < Mdy2 < 0.7, it can be confirmed that the capacity degradation is suppressed while the high-temperature reliability is excellent.

[0110] As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited by the above-described embodiments and the attached drawings, but is limited by the attached claims. Therefore, various forms of substitution, modification, and change can be made by those having ordinary knowledge in the technical field within the scope not departing from the technical idea of the present invention described in the claims, and it can be said that these also belong to the scope of the present invention.

[0111] In addition, the expression "one embodiment" used in the present invention does not mean the same embodiment, but is provided to emphasize and explain each unique feature that is different from each other. However, the above-presented one embodiment does not exclude being realized in combination with the features of other embodiments. For example, even if a matter described in a specific one embodiment is not described in another one embodiment, it can be understood and related to the description of another one embodiment as long as there is no description contrary to or inconsistent with that matter in the other one embodiment.

[0112] The terms used in the present invention are merely used to explain one embodiment and are not intended to limit the present invention. At this time, the singular expression includes the plural expression unless the context clearly indicates a different meaning.

Explanation of Reference Numerals

[0113] 100: Multilayer electronic component 110: Body 111: Dielectric layer IP1, IP2: Interface part CP: Central part 112, 113: Cover part 114, 115: Margin part 121, 122: Internal electrode 131, 132: External electrode 131a, 132a: Electrode layer 131b, 132b: Plating layer

Claims

1. A body including a dielectric layer and internal electrodes arranged alternately with the dielectric layer, The body includes an external electrode disposed on the main body, The dielectric layer includes a central portion separated from the internal electrode and containing first dielectric crystal grains, and an interface portion disposed between the internal electrode and the central portion and containing second dielectric crystal grains. When the average size of the first dielectric crystal grains is Gs1, the average size of the second dielectric crystal grains is Gs2, the number of moles of Dy per 100 moles of Ti in the central portion is Mdy1, and the number of moles of Dy per 100 moles of Ti in the interface portion is Mdy2, A multilayer electronic component satisfying Gs2 / Gs1 < 1, Mdy1 ≤ 0.1, and 0.1 < Mdy2 < 0.

7.

2. The stacked electronic component according to claim 1, wherein Gs1 and Gs2 satisfy Gs2 / Gs1 < 0.

7.

3. The Gs2 is between 50 nm and 180 nm. The multilayer electronic component according to claim 1, wherein Gs1 is 100 nm or more and 300 nm or less.

4. The stacked electronic component according to claim 1, wherein Gs1 and Gs2 satisfy Gs1 - Gs2 > 70 nm.

5. The stacked electronic component according to claim 1, wherein Mdy2 is 0.2 or more and 0.6 or less.

6. The stacked electronic component according to claim 1, wherein Mdy1 is 0.

7. The internal electrodes include first internal electrodes and second internal electrodes that are alternately arranged with the dielectric layer in between. The laminated electronic component according to claim 1, wherein the interface portion includes a first interface portion disposed between the central portion and the first internal electrode, and a second interface portion disposed between the central portion and the second internal electrode.

8. When the average thickness of the first interface is tdi1, the average thickness of the second interface is tdi2, and the average thickness of the central part is tdc, A stacked electronic component according to claim 7, satisfying tdi1 / tdc ≤ 0.05 and tdi2 / tdc ≤ 0.

05.

9. The stacked electronic component according to claim 8, wherein tdi1 and tdi2 are each 50 nm or more and 500 nm or less.

10. The stacked electronic component according to claim 8, wherein the TDC is 1000 nm or more.

11. The stacked electronic component according to claim 8, wherein the sum of tdi1, tdi2, and tdc is 1.05 μm or more and 10 μm or less.

12. The dielectric layer is BaTiO ３ , (Ba １－ｘ Ca ｘ )TiO ３ (0 < x < 1), Ba(Ti １－ｙ Ca ｙ )O ３ (0 < y < 1), (Ba １－ｘ Ca ｘ )(Ti １－ｙ Zr ｙ )O ３ (0 < x < 1, 0 < y < 1) and Ba(Ti １－ｙ Zr ｙ )O ３ The multilayer electronic component according to any one of claims 1 to 11, which contains one or more of them as main components.

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