Display panels and display devices

Abstract

This invention provides a display panel and display device that solve the technical problem of tip discharge occurring between the edge of a signal line and the active layer in conventional display devices, causing display abnormalities. [Solution] The display panel has a drive circuit layer which includes multiple light emission control lines, multiple reset control lines, multiple light emission transfer lines, and multiple reset transfer lines, with one light emission transfer line connected to one light emission control line, one reset transfer line connected to one reset control line, and at least one light emission transfer line having a cutout, and / or at least one reset transfer line having a cutout, thereby reducing the impedance of the light emission control lines and reset control lines, and distributing static electricity to multiple parts of the light emission transfer lines and / or distributing static electricity to multiple parts of the reset transfer lines, thereby avoiding the accumulation of static electricity, reducing the risk of electric shock caused by tip discharge, and improving the yield of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to display panels and display devices.

Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used due to advantages such as self-emission, wide color gamut, low power consumption, and flexible display. OLED display devices are driven using pixel drive circuits. However, during the use of OLED display devices, the impedance of some signal lines is large, which easily leads to large signal delays, and furthermore, problems such as insufficient charging or mischarging of pixels easily occur, and display defects easily occur. In order to reduce the impedance of signal lines, some signal lines are designed with a double-layer structure, that is, two parts of the signal line are formed by two film layers to reduce the impedance of the signal line. However, during actual use, since the edge of the signal line is relatively thin, after static electricity accumulates on the signal line, tip discharge easily occurs between the edge of the signal line and the active layer. Furthermore, in order to connect the active layer and the signal line, the transistor cannot be turned off, and bright spots occur on the display panel, causing display anomalies.

[0003] Therefore, conventional display devices have the technical problem that tip discharge occurs between the edge of the signal line and the active layer, causing display anomalies.

Summary of the Invention

[0004] Embodiments of the present application provide a display panel and a display device for solving the technical problem that tip discharge occurs between the edge of the signal line and the active layer in conventional display devices, causing display anomalies.

[0005] To achieve the above object, the display panel according to the first aspect of the present application includes a substrate, The substrate includes a drive circuit layer installed on one side thereof, the drive circuit layer includes a plurality of light emission control lines, a plurality of reset control lines, a plurality of light emission transfer lines, and a plurality of reset transfer lines, one of the light emission transfer lines being connected to one of the light emission control lines, and one of the reset transfer lines being connected to one of the reset control lines. A display panel characterized in that at least one of the light-emitting transfer lines is provided with a cutout, and / or at least one of the reset transfer lines is provided with a cutout.

[0006] According to a second aspect of the present application, a display device is provided that includes a display panel as described in any of the above embodiments.

[0007] Embodiments of the present invention provide a display panel and a display device, the display panel having a drive circuit layer comprising a plurality of light emission control lines, a plurality of reset control lines, a plurality of light emission transfer lines and a plurality of reset transfer lines, wherein one light emission transfer line is connected to one light emission control line, one reset transfer line is connected to one reset control line, and at least one light emission transfer line is provided with a cutout, and / or at least one reset transfer line is provided with a cutout, thereby reducing the impedance of the light emission control lines and reset control lines, distributing static electricity over multiple parts of the light emission transfer lines and / or distributing static electricity over multiple parts of the reset transfer lines, thereby avoiding the accumulation of static electricity, reducing the risk of electric shock caused by tip discharge, and improving the yield of the display panel.

[0008] Other features and advantages of this application will be described in detail in the following sections on specific embodiments. [Brief explanation of the drawing]

[0009] To more clearly illustrate the technical concept in the embodiments of this application, the accompanying drawings used to describe the embodiments are briefly introduced below. Clearly, the drawings described below represent only a few embodiments of this application. Those skilled in the art can obtain other drawings based on these without any creative effort.

[0010] The following explanation will be given with reference to the drawings in order to better understand the present invention and its beneficial effects. In the following explanation, the same reference symbols indicate the same part.

[0011] [Figure 1] This is a cross-sectional view of a comparative display device according to an embodiment of the present application. [Figure 2] This is a plan view of a display panel according to an embodiment of the present application. [Figure 3] This is a first cross-sectional view of a display device according to an embodiment of the present application. [Figure 4] This is a second cross-sectional view of a display device according to an embodiment of the present application. [Figure 5] This is a circuit diagram of the pixel driving circuit of a display panel according to an embodiment of the present application. [Figure 6] This is a stacking diagram of each film layer of the pixel unit of a display panel according to an embodiment of the present application. [Figure 7] Figure 6 is an exploded view of the active layer of the display panel. [Figure 8] Figure 6 is an exploded view of the first gate layer of the display panel. [Figure 9] Figure 6 is an exploded view of the second gate layer of the display panel. [Figure 10] Figure 6 is an exploded view of the first source-drain layer of the display panel. [Figure 11] Figure 6 is an exploded view of the second source-drain layer of the display panel. [Figure 12] Figure 6 is an exploded view of the pixel electrode layer of the display panel. [Figure 13] Figure 6 shows the stacking diagram of the active layer and the first gate layer of the display panel. [Figure 14] Figure 6 shows the stacking diagram of the active layer, first gate layer, and second gate layer of the display panel. [Figure 15] Figure 6 shows a stacked view of the active layer, first gate layer, second gate layer, and first source-drain layer of the display panel. [Figure 16]Figure 6 shows the stacked layers of the display panel: the active layer, the first gate layer, the second gate layer, the first source-drain layer, and the second source-drain layer. [Figure 17] This is a cross-sectional view of the display panel at line A1-A2 in Figure 6. [Modes for carrying out the invention]

[0012] The technical proposals in the embodiments of the present application are described below with reference to the drawings of the embodiments of the present disclosure. It goes without saying that the embodiments described are only a portion of the embodiments of the present application, and not all embodiments. All other embodiments that can be obtained by those skilled in the art without creative effort based on the embodiments of the present application are included within the scope of the present application.

[0013] To explain the technical problems of the embodiments of the present application, the embodiments of the present application provide a comparative display device, which is understood not to be prior art of the embodiments of the present application. Specifically, the comparative display device includes a plurality of subpixel units. Each subpixel unit includes one pixel driver circuit and one light-emitting device. The pixel driver circuit includes light-emitting control wiring and reset control wiring. The light-emitting control wiring is connected to a light-emitting control transistor, and the reset control wiring is connected to a reset transistor. To reduce the impedance of the light-emitting control wiring and reset control wiring, the light-emitting control wiring and reset control wiring are configured in a double layer.

[0014] As shown in FIG. 1, the comparison display device includes a substrate 111, a semiconductor film layer 112, a first insulating film layer 113, a first gate film layer 114, a second insulating film layer 115, and a first source-drain film layer 116. The light emission control wiring includes a first light emission control wiring provided on the first gate film layer 114 and a second light emission control wiring located in the first source-drain film layer 116, and the reset control wiring includes a first reset control wiring provided on the first gate film layer 114 and a second reset control wiring located in the first source-drain film layer 116. The light emission control wiring is a double-layer wiring, both the first light emission control wiring and the second light emission control wiring are long wirings, and static electricity 117 is likely to accumulate in the light emission control wiring. Furthermore, since the second light emission control wiring and the first light emission control wiring are offset in position, the capacitance between the second light emission control wiring and the semiconductor film layer 112 becomes large, and the capacitance between the light emission control wiring and the semiconductor film layer 112 further increases. The first light emission control wiring and the semiconductor film layer 112 are relatively close, the edge of the first light emission control wiring is relatively thin, and tip discharge is likely to occur between the first light emission control wiring and the semiconductor film layer 112, causing explosion damage due to static electricity, the light emission control wiring and the active pattern of the light emission transistor are conductive, and moreover, since the light emission control wiring controls the light emission transistor, the light emission transistor remains on, the sub-pixel unit remains on, bright spots occur, and display defects are caused. Similarly, the first reset control wiring and the second reset control wiring are long wirings, static electricity is likely to accumulate in the reset control wiring, and the first reset control wiring and the semiconductor film layer 112 are relatively close, the edge of the first reset control wiring is relatively thin, and tip discharge is likely to occur between the first reset control wiring and the semiconductor film layer 112, so due to explosion damage caused by static electricity, the reset control wiring and the active pattern of the reset transistor are conductive, and moreover, since the reset control wiring controls the reset transistor, the reset transistor turns on, and the display of the sub-pixel unit becomes abnormal. Therefore, the conventional display device has a technical problem that tip discharge occurs between the edge of the signal line and the active layer, causing display abnormalities.

[0015] Embodiments of the present application provide a display panel and a display device for solving the above technical problems with respect to the above technical problems.

[0016] FIG. 2 is a plan view of a display panel according to an embodiment of the present application. FIG. 3 is a first cross-sectional view of a display device according to an embodiment of the present application. FIG. 4 is a second cross-sectional view of a display device according to an embodiment of the present application. FIG. 5 is a circuit diagram of a pixel driving circuit of a display panel according to an embodiment of the present application. FIG. 6 is a stacked view of each film layer of a pixel unit of a display panel according to an embodiment of the present application. FIG. 7 is an exploded view of an active layer of a display panel in FIG. 6. FIG. 8 is an exploded view of a first gate layer of a display panel in FIG. 6. FIG. 9 is an exploded view of a second gate layer of a display panel in FIG. 6. FIG. 10 is an exploded view of a first source-drain layer of a display panel in FIG. 6. FIG. 11 is an exploded view of a second source-drain layer of a display panel in FIG. 6. FIG. 12 is an exploded view of a pixel electrode layer of a display panel in FIG. 6. FIG. 13 is a stacked view of an active layer and a first gate layer of a display panel in FIG. 6. FIG. 14 is a stacked view of an active layer, a first gate layer, and a second gate layer of a display panel in FIG. 6. FIG. 15 is a stacked view of an active layer, a first gate layer, a second gate layer, and a first source-drain layer of a display panel in FIG. 6. FIG. 16 is a stacked view of an active layer, a first gate layer, a second gate layer, a first source-drain layer, and a second source-drain layer of a display panel in FIG. 6. FIG. 17 is a cross-sectional view of A1-A2 of a display panel in FIG. 6.

[0017] As shown in FIGS. 2 to 17, embodiments of the present application provide a display panel. The display panel 2 includes a substrate 21 and a driving circuit layer 22. The driving circuit layer 22 is provided on one side of the substrate 21 and includes a plurality of emission control lines EM, a plurality of reset control lines Reset-A, a plurality of emission transfer lines SL4, and a plurality of reset transfer lines SL3. One of the emission transfer lines SL4 is connected to one of the emission control lines EM, and one of the reset transfer lines SL3 is connected to one of the reset control lines Reset-A.

[0018] Of these, at least one of the light emission transfer lines is provided with a cutout, and / or at least one of the reset transfer lines is provided with a cutout.

[0019] Embodiments of the present invention provide a display panel and a display device, the display panel having a drive circuit layer comprising a plurality of light emission control lines, a plurality of reset control lines, a plurality of light emission transfer lines and a plurality of reset transfer lines, wherein one light emission transfer line is connected to one light emission control line, one reset transfer line is connected to one reset control line, and at least one light emission transfer line is provided with a cutout, and / or at least one reset transfer line is provided with a cutout, thereby reducing the impedance of the light emission control lines and reset control lines, distributing static electricity over multiple parts of the light emission transfer lines and / or distributing static electricity over multiple parts of the reset transfer lines, thereby avoiding the accumulation of static electricity, reducing the risk of electric shock caused by tip discharge, and improving the yield of the display panel.

[0020] Specifically, it is located on a different layer from the light emission control line EM and the light emission transfer line SL4, and on a different layer from the reset transfer line SL3 and the reset control line Reset-A.

[0021] In some embodiments, as shown in Figures 2 to 17, the display panel 2 includes a plurality of pixel units 240, each of which includes a plurality of sub-pixel units (e.g., a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c), and the light emission transfer line SL4 includes a plurality of light emission connection lines EM-L, with the cutout 311 between two adjacent light emission connection lines EM-L, and each light emission connection line EM-L is installed corresponding to one of the sub-pixel units. By installing each light emission connection line corresponding to one sub-pixel unit, each light emission connection line can drive each transistor to enable each sub-pixel unit to operate normally. At the same time, dividing the light emission transfer line into multiple light emission transfer lines further disperses static electricity, avoids the accumulation of static electricity, reduces the risk of blast injuries caused by static electricity due to tip discharge, and improves the yield of the display panel.

[0022] In some embodiments, as shown in Figures 2 to 17, the display panel 2 includes a plurality of pixel units 240, each of which includes a plurality of sub-pixel units (e.g., a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c), and the reset transfer line SL4 includes a plurality of reset connection lines RL, with the cut-off between two adjacent reset connection lines RL, and each reset connection line RL is installed corresponding to one of the sub-pixel units. By installing each reset connection line corresponding to one sub-pixel unit, each reset connection line can drive a transistor to enable each sub-pixel unit to operate normally. At the same time, dividing the reset wiring into multiple reset wirings further disperses static electricity, avoids the accumulation of static electricity, reduces the risk of blast injuries caused by static electricity due to tip discharge, and improves the yield of the display panel.

[0023] In the above embodiment, the cut-off opening was described as being provided between two sub-pixel units, but the embodiments of the present application are not limited thereto. The cut-off opening may be provided within a single sub-pixel unit as long as it avoids the active patterns of each transistor, that is, as long as the cut-off opening does not overlap with the orthographic projection of the active patterns of each transistor onto the substrate.

[0024] In some embodiments, as shown in Figures 2 to 17, the display panel 2 includes a plurality of pixel units 240, each of which includes a plurality of sub-pixel units (e.g., a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c), the light emission transfer wiring SL4 includes a plurality of light emission connection lines EM-L, with the cutout 311 between two adjacent light emission connection lines EM-L, and each light emission connection line EM-L is installed corresponding to one of the sub-pixel units. The reset transfer wiring SL4 includes a plurality of reset connection lines RL, with the cutout 311 between two adjacent reset connection lines RL, and each reset connection line RL is installed corresponding to one of the sub-pixel units. By having each light emission connection line installed corresponding to one sub-pixel unit and each reset connection line installed corresponding to one sub-pixel unit, each light emission connection line drives each transistor, and each reset connection line drives the transistor, allowing each sub-pixel unit to operate normally. At the same time, the light transfer line is divided into multiple light connection lines, and the reset transfer line is divided into multiple reset connection lines to further disperse static electricity, avoid static electricity buildup, reduce the risk of electric shock caused by tip discharge, and improve the yield of display panels. Specifically, each light connection line is connected to a light control line, and each reset connection line is connected to a reset control line.

[0025] In some embodiments, as shown in Figures 2 to 17, the drive circuit layer 22 includes a first gate layer 224 and a first source-drain layer 228. The first gate layer 224 is provided between the substrate 21 and the first source-drain layer 228. The first gate layer 224 includes the light emission connection line EM-L and the reset connection line RL, and the first source-drain layer 228 includes the light emission control line EM and the reset control line Reset-A. By providing the light emission connection line and the reset connection line in the first gate layer, and the light emission control line and the reset control line in the first source-drain layer, and by connecting the light emission connection line to the light emission control line and the reset connection line to the reset control line, the impedance of the light emission control line and the reset control line can be reduced, and by installing multiple light emission connection lines connected to the same light emission control line in a disconnected manner, and multiple reset connection lines connected to the same reset control line in a disconnected manner, the accumulation of static electricity can be avoided, the risk of electric shock caused by tip discharge can be reduced, and the yield of the display panel can be improved.

[0026] As shown in Figures 2 to 17, embodiments of the present invention provide a display panel. The display panel 2 includes a plurality of pixel units 240, each of which includes a plurality of sub-pixel units (for example, a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c). The display panel 2 includes a substrate 21 and a drive circuit layer 22. The drive circuit layer 22 is provided on one side of the substrate 21. The drive circuit layer 22 includes a first gate layer 224 and a first source-drain layer 228. The first gate layer 224 is provided between the substrate 21 and the first source-drain layer 228. The first gate layer 224 includes a plurality of light emission connection lines EM-L and a plurality of reset connection lines RL, and the first source-drain layer 228 includes a light emission control line EM and a reset control line Reset-A. The light emission connection line EM-L is connected to the light emission control line EM, and the reset connection line RL is connected to the reset control line Reset-A.

[0027] Here, within two adjacent subpixel units (for example, the first subpixel unit 240a and the second subpixel unit 240b), two adjacent light emission connection lines EM-L are cut and arranged, and / or two adjacent reset connection lines RL are cut and arranged.

[0028] Embodiments of the present invention provide a display panel. The display panel includes a first gate layer 224 which includes a plurality of light emission connection lines EM-L and a plurality of reset connection lines RL, and a first source-drain layer 228 which includes a light emission control line EM and a reset control line Reset-A, with the light emission connection line EM-L connected to the light emission control line EM and the reset connection line RL connected to the reset control line Reset-A, and in two adjacent subpixel units, two adjacent light emission connection lines EM-L are disconnected and / or two adjacent reset connection lines RL are disconnected and / or the impedance of the light emission control lines and reset control lines is reduced, static electricity is distributed to the plurality of light emission connection lines and / or static electricity is distributed to the plurality of reset connection lines, static electricity accumulation is avoided, the risk of electric shock caused by terminal discharge is reduced, and the yield of the display panel is improved.

[0029] Specifically, the edges of the light emission connection wire and the reset connection wire have a slope.

[0030] Specifically, in the first direction, within two adjacent subpixel units, two adjacent light emission connection lines are disconnected and / or two adjacent reset connection lines are disconnected.

[0031] Specifically, to make it easier to understand, each transistor in a pixel driving circuit has a gate, a first electrode, and a second electrode. However, in the actual manufacturing process, in order to reduce the space occupied by the transistors, the electrodes and signal lines of each transistor are directly connected instead of individually installing the electrodes of several transistors. For example, in a pixel driving circuit, the first electrode of the driving transistor T1 and the second electrode of the switching transistor T2 are connected to the first node A. When manufacturing the driving transistor and the switching transistor, there is no need to individually install the first electrode of the driving transistor and the second electrode of the switching transistor. The active pattern of the driving transistor and the active pattern of the switching transistor are directly connected, and the connection point between the active patterns of the driving transistor and the switching transistor can be considered as the first node A. This reduces the number of transistor electrodes and thus the space occupied by the transistors. In another example, the first electrode of the compensation transistor is connected to the second electrode of the initialization transistor. However, in actual design, it is not necessary to install the first electrode of the compensation transistor and the second electrode of the initialization transistor separately. By directly connecting the active pattern of the compensation transistor and the active pattern of the initialization transistor, the connection point between the active patterns of the compensation transistor and the initialization transistor can be considered as a point location connected to the stationary point (point Q), or can be considered as point Q itself. This reduces the number of electrode patterns of the transistor and decreases the space occupied by the transistor. Similarly, for other structures not shown in the film layer diagram, the above design can be adopted and the above explanation can be referred to; therefore, the explanation is omitted in the following embodiments.

[0032] Specifically, in the actual manufacturing process, another method to reduce the space occupied by transistors is to share electrodes among multiple transistors or to have the electrodes and signal lines of a transistor share the same structure. For example, by connecting the gate of a driving transistor to one plate of a storage capacitor, it is not necessary to provide the gate of the driving transistor and one plate of the storage capacitor separately, and a certain structure can be used as both the gate of the driving transistor and one plate of the storage capacitor. Similarly, in other cases where the same structure is used for the electrodes and / or signal lines of multiple transistors, refer to the above description and therefore the description will be omitted in the following embodiments.

[0033] Specifically, the display panel includes a plurality of repeating units, one of which may include one pixel unit, for example, the pixel unit shown in Figure 6 in the embodiment of this application, or a pixel unit in which a reset connection line is electrically connected to the first electrode of an initialization transistor. One repeating unit may include two pixel units. The distinction between the two pixel units is that in one pixel unit, a reset connection line is electrically connected to the first electrode of an initialization transistor, and the first electrode of the initialization transistor is connected to the initialization signal line, thereby reducing the voltage drop on the initialization signal line, while in the other pixel unit, a reset connection line is electrically connected to the reset signal line, thereby reducing the voltage drop on the reset signal line. In other respects, the two image units may be the same. In the following embodiments, the case in which one repeating unit includes one pixel unit will be described as an example.

[0034] Specifically, the display panel may include a plurality of pixel units 240, each pixel unit 240 may include a plurality of sub-pixel units, and the plurality of sub-pixel units may include a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c. The first sub-pixel unit 240a, the second sub-pixel unit 240b, and the third sub-pixel unit 240c each include a pixel driving circuit 220 and a light-emitting device LED. The designs of the light-emitting devices of the first sub-pixel unit 240a, the second sub-pixel unit 240b, and the third sub-pixel unit 240c may differ, specifically, the light-emitting color of the light-emitting devices of the first sub-pixel unit 240a, the second sub-pixel unit 240b, and the third sub-pixel unit 240c may be different, and / or the area of ​​the light-emitting devices may be different, and / or the thickness of the light-emitting devices may be different.

[0035] Specifically, the emission colors of the first subpixel unit 240a, the second subpixel unit 240b, and the third subpixel unit 240c may be red, green, and blue, respectively. However, the embodiments of the present application are not limited thereto. For example, the emission colors of the first subpixel unit 240a, the second subpixel unit 240b, and the third subpixel unit 240c may be red, blue, and green, respectively, or the emission colors of the first subpixel unit 240a, the second subpixel unit 240b, and the third subpixel unit 240c may be blue, green, and red, respectively.

[0036] Specifically, for the design of all pixel units other than those explicitly described in the embodiments of this application, one can refer to the design of the pixel units according to the embodiments of this application for the design of all pixel drive circuits. Similarly, for the design of all pixel drive circuits, one can refer to the design of the pixel drive circuits in the embodiments of this application. For example, if the difference between two pixel drive circuits is that the high-potential power lines of one pixel drive circuit are different from those of the other pixel drive circuit, and the other designs of the two pixel drive circuits are the same, then when describing the design of the pixel drive circuits, the other designs of the two pixel drive circuits are the same except for the difference in the high-potential power lines. Similarly, one can determine the distinction and the same design of pixel units, but this is not repeated in the following embodiments.

[0037] Specifically, as shown in Figure 2, the display panel 2 includes a display area AA and a non-display area NA, and the pixel units are provided within the display area AA.

[0038] Specifically, as shown in Figures 3 and 4, the display panel 2 includes a substrate 21, a drive circuit layer 22, a light-emitting functional layer 24, and a package layer 25.

[0039] Specifically, the drive circuit layer 22 includes a buffer layer 221, an active layer 222, a first gate insulating layer 223, a first gate layer 224, a second gate insulating layer 225, a second gate layer 226, an interlayer insulating layer 227, a first source-drain layer 228, a passivation layer 229, a first planarization layer 231, a second source-drain layer 232, a second planarization layer 233, and a third planarization layer 234. The buffer layer 221 is provided on one side of the substrate 21, the active layer 222 is provided on the side of the buffer layer 221 away from the substrate 21, the first gate insulating layer 223 is provided on the side of the active layer 222 away from the buffer layer 231, the first gate layer 224 is provided on the side of the first gate insulating layer 223 away from the active layer 222, the second gate insulating layer 225 is provided on the side of the first gate insulating layer 224 away from the first gate insulating layer 223, the second gate layer 226 is provided on the side of the second gate insulating layer 225 away from the first gate layer 224, and the interlayer insulating layer 227 is provided on the second gate of the second gate layer 226 The first source-drain layer 228 is provided on the side away from the insulating layer 225, the passivation layer 229 is provided on the side away from the interlayer insulating layer 227 of the first source-drain layer 228, the first planarization layer 231 is provided on the side away from the first source-drain layer 228 of the passivation layer 229, the second planarization layer 233 is provided on the side away from the first planarization layer 231 of the second source-drain layer 232, and the third planarization layer 234 is provided on the side away from the second source-drain layer 232 of the second planarization layer 233.

[0040] Specifically, the light-emitting functional layer 24 includes a pixel electrode layer 241, a pixel definition layer 242, a light-emitting material layer 243, and a common electrode layer 244. The pixel definition layer 242 is provided on the side of the pixel electrode layer 241 away from the drive circuit layer 22, the light-emitting material layer 243 is provided on the side of the pixel definition layer 242 away from the pixel electrode layer 241, and the common electrode layer 244 is provided on the side of the light-emitting material layer 243 away from the pixel definition layer 242.

[0041] Specifically, the pixel definition layer 242 may include a first pixel definition layer 242a and a second pixel definition layer 242b, but the embodiments of this application are not limited thereto, and a single-layer pixel definition layer design is also possible.

[0042] Specifically, the sealing layer 25 includes a first inorganic layer, an organic layer, and a second inorganic layer.

[0043] Specifically, the light-emitting functional layer 24 includes a light-emitting device LED, and the pixel electrode layer 241 in the light-emitting functional layer 24 includes the anode ANO of the light-emitting device LED.

[0044] Specifically, the embodiments of this application describe the display panel from the perspective of the display panel's circuitry, film layer structure, and the design of each film layer. Therefore, the fact that some structures belong to one structure and others to another is intended to limit them from different angles. For example, the fact that a pixel driving circuit belongs to the driving circuit layer means that, from the perspective of the film layer structure, the pixel driving circuit is formed by the structure in the driving circuit layer. Also, the fact that a pixel unit includes a pixel driving circuit means that, from the perspective of the design of the pixel unit, each pixel unit needs to be driven by a corresponding pixel driving circuit. It is understood that the pixel driving circuits belonging to the two structures, the driving circuit layer and the pixel unit, are the same pixel driving circuit. Similarly, other similar limitations are described above and will not be repeated in the following embodiments.

[0045] In some embodiments, within any two subpixel units, two adjacent light-emitting connection wires are installed in a disconnected manner. By installing two adjacent light-emitting connection wires in any two subpixel units in a disconnected manner, static electricity can be distributed among multiple light-emitting connection wires, reducing the risk of tip discharge between the light-emitting connection wires and the active layer, and improving the yield of the display panel.

[0046] Specifically, in a comparative display device, the first light emission control wiring is a long wiring, static electricity accumulates on the first light emission control wiring, and there is a slope on the edge of the first light emission control wiring, and the thickness of the edge is relatively small, making it easy for tip discharge to occur between the sloped portion of the first light emission control wiring and the semiconductor film layer. In this embodiment, however, by cutting and installing two adjacent light emission connection wires, static electricity can be distributed and discharged to multiple light emission connection wires, thereby avoiding the problem of electrostatic discharge between the light emission connection wires and the active pattern due to the accumulation of static electricity, reducing the risk of tip discharge occurring between the light emission connection wires and the active layer, and improving the yield of the display panel.

[0047] In some embodiments, within any two subpixel units, two adjacent reset connection lines are installed in a disconnected manner. By installing two adjacent reset connection lines in any two subpixel units in a disconnected manner, static electricity can be distributed among multiple reset connection lines, reducing the risk of tip discharge between the reset connection lines and the active layer, and improving the yield of the display panel.

[0048] Specifically, in a comparative display device, the first reset control wiring is a long wiring, static electricity accumulates on the first reset control wiring, and there is a slope on the edge of the first reset control wiring, and the thickness of the edge is relatively small, making it easy for tip discharge to occur between the sloped portion of the first reset control wiring and the semiconductor film layer. In this embodiment, however, by cutting and installing two adjacent reset connection wires, static electricity can be distributed and discharged to multiple reset connection wires, thereby avoiding the problem of electrostatic discharge between the reset connection wire and the active pattern due to the accumulation of static electricity, reducing the risk of tip discharge occurring between the reset connection wire and the active layer, and improving the yield of the display panel.

[0049] In some embodiments, as shown in Figures 6 to 15, within any two subpixel units, two adjacent light emission connection lines EM-L are cut and installed, and two adjacent reset connection lines RL are cut and installed. By cutting and installing two adjacent light emission connection lines and two adjacent reset connection lines within any two subpixel units, static electricity can be distributed to multiple light emission connection lines and multiple reset connection lines, thereby reducing the risk of tip discharge between the light emission connection lines and the active layer, and reducing the risk of tip discharge between the reset connection lines and the active layer, thereby improving the yield of the display panel.

[0050] Specifically, in a comparative display device, the first light emission control wiring is a long wiring, and the first reset control wiring is also a long wiring, causing static electricity to accumulate in the first light emission control wiring and the first reset control wiring. Furthermore, the edges of the first light emission control wiring and the first reset control wiring are sloped, and the thickness of the edges is relatively small, making it easy for tip discharge to occur between the sloped portions of the first light emission control wiring and the first reset control wiring and the semiconductor film layer. In this embodiment, however, by cutting and installing two adjacent light emission connection wires and two adjacent reset connection wires, static electricity can be distributed and released to multiple light emission connection wires and multiple reset connection wires, thereby avoiding the problem of electrostatic discharge occurring between the light emission connection wires and the active pattern due to the accumulation of static electricity, avoiding the problem of electrostatic discharge occurring between the reset connection wires and the active pattern due to the accumulation of static electricity, reducing the risk of tip discharge occurring between the light emission connection wires and reset connection wires and the active layer, and improving the yield of the display panel.

[0051] In some embodiments, as shown in Figures 6 to 16, the light emission control line EM and the light emission connection line EM-L are provided along a first direction X, the orthographic projection of the light emission connection line EM-L onto the substrate 21 and the orthographic projection of the light emission control line EM onto the substrate 21 overlap, and the width H1 of the light emission connection line EM-L in a second direction Y is greater than or equal to the width H2 of the light emission control line EM in the second direction Y. In the overlapping region of the light emission connection line EM-L and the light emission control line EM, the orthographic projection of the light emission control line EM onto the substrate 21 is located within the orthographic projection of the light emission connection line EM-L onto the substrate, and the angle between the first direction X and the second direction Y is greater than 0 degrees and 90 degrees or less. As the orthographic projection of the light-emitting connection line EM-L on the substrate 21 and the orthographic projection of the light-emitting control line EM on the substrate 21 overlap, the width of the light-emitting connection line EM-L in the second direction Y is greater than or equal to the width of the light-emitting control line EM in the second direction Y. Within the region where the two overlap, the orthographic projection of the light-emitting control line EM on the substrate is located within the orthographic projection of the light-emitting connection line EM-L on the substrate. This allows the light-emitting connection line EM-L to shield the light-emitting control line, avoiding the formation of capacitance between the light-emitting control line EM-L and the active pattern, reducing the capacitance between the light-emitting control line and the active pattern, lowering the risk of tip discharge occurring between the light-emitting connection line and the active layer, and improving the yield of the display panel.

[0052] Specifically, in a comparative display device, the first and second light emission control wirings are offset from each other, and the first and second light emission control wirings each form a coupling capacitance with the active pattern, making it easier for tip discharge to occur between the first light emission control wiring and the active pattern, which can cause electrostatic discharge injuries. In contrast, the embodiment of this application makes the width of the light emission connection wire in the second direction greater than or equal to the width of the light emission control wire in the second direction, so that in the region where they overlap, the orthographic projection of the light emission control wire onto the substrate is located within the orthographic projection of the light emission connection wire onto the substrate, thereby allowing the light emission connection wire to cover the light emission control wire, reducing and ultimately eliminating the coupling capacitance between the light emission control wire and the active pattern, reducing the risk of tip discharge occurring between the light emission connection wire and the active pattern, and improving the yield of the display panel.

[0053] Specifically, in the installation area corresponding to the active pattern, the orthographic projection of the light emission control line onto the substrate lies within the orthographic projection of the light emission connection line onto the substrate.

[0054] In some embodiments, as shown in Figures 6 to 16, the reset control line Reset-Q and the reset connection line RL are provided along a first direction X, the orthographic projection of the reset connection line RL onto the substrate 21 and the orthographic projection of the reset control line Reset-Q onto the substrate 21 overlap, and the width H3 of the reset connection line RL in the second direction Y is greater than or equal to the width H4 of the reset control line Reset-Q in the second direction Y. Here, in the overlapping region of the reset connection line RL and the reset control line Reset-Q, the orthographic projection of the reset control line Reset-Q onto the substrate 21 is located within the orthographic projection of the reset connection line RL onto the substrate 21, and the angle between the first direction and the second direction is greater than 0 degrees and less than or equal to 90 degrees. Because the orthographic projection of the reset connection line RL on the substrate 21 and the orthographic projection of the reset control line Reset-Q on the substrate 21 overlap, the width of the reset connection line RL in the second direction Y is greater than or equal to the width of the reset control line Reset-Q in the second direction Y. Within the region where the two overlap, the orthographic projection of the reset control line Reset-Q on the substrate 21 is located within the orthographic projection of the reset connection line RL on the substrate 21. As a result, the reset connection line RL can shield the reset control line Reset-Q, avoiding the formation of capacitance between the reset control line Reset-Q and the active pattern, reducing the capacitance between the light emission control line and the active pattern, reducing the risk of tip discharge occurring between the light emission connection line and the active layer, and improving the yield of the display panel.

[0055] Specifically, in a comparative display device, the first reset control wiring and the second reset control wiring are offset from each other, and the first and second reset control wirings each form a coupling capacitance with the active pattern, making it easier for tip discharge to occur between the first reset control wiring and the active pattern, which can cause electrostatic discharge injuries. In contrast, the embodiment of the present invention makes the width of the reset connection wire in the second direction greater than or equal to the width of the reset control wire in the second direction, so that in the region where they overlap, the reset connection wire can cover the reset control wire such that the orthographic projection of the reset control wire Reset-Q onto the substrate 21 is located within the orthographic projection of the reset connection wire RL onto the substrate 21. This reduces, and ultimately eliminates, the coupling capacitance between the reset control wire and the active pattern, reducing the risk of tip discharge occurring between the reset connection wire and the active pattern, and improving the yield of the display panel.

[0056] Specifically, the orthographic projection of the reset control line onto the substrate, corresponding to the installation area of ​​the active pattern, lies within the orthographic projection of the reset connection line onto the substrate.

[0057] Specifically, as shown in Figures 1 and 17, the embodiment of the present invention reduces and ultimately eliminates the coupling capacitance between the light emission control line and the active pattern by having the light emission control line cover the light emission control line in the overlapping region of the light emission connection line and the light emission control line, and by having the reset connection line cover the reset control line in the overlapping region of the reset connection line and the reset control line.

[0058] In some embodiments, as shown in Figures 6 to 16, the drive circuit layer 22 includes a first via hole 301, the light emission control line EM is connected to the light emission connection line EM-L through the first via hole 301, and the light emission control line EM is installed symmetrically with respect to the first via hole 301. By connecting the light emission control line to the light emission connection line through the first via hole and symmetrically arranging the light emission control line with respect to the first via hole, the shielding effect of the light emission control line by the light emission connection line is enhanced, preventing the formation of coupling capacitance due to the direct opposition between the light emission control line and the active pattern, reducing the coupling capacitance between the light emission control line and the active pattern, lowering the risk of tip discharge between the light emission connection line and the active pattern, and improving the yield of the display panel.

[0059] Specifically, the light-emitting connection wires are installed symmetrically with respect to the first via hole.

[0060] Specifically, in a comparative display device, compared to providing the connection point between the first light emission control wiring and the second light emission control wiring on the lower side closer to the first light emission control wiring, the embodiment of the present invention reduces the risk of tip discharge occurring between the light emission connection wire and the active pattern by providing the light emission control wire symmetrically with respect to the first via hole, thereby improving the yield of the display panel.

[0061] Specifically, the first via hole 301 penetrates the interlayer insulating layer 227 and the second gate insulating layer 225.

[0062] In some embodiments, as shown in Figures 6 to 16, the drive circuit layer 22 further includes a pixel drive circuit 220, an active layer 222, a first source-drain layer 228, and a second via hole 302, wherein the pixel drive circuit 220 includes an active pattern T7A of the active layer 222 including a reset transistor T7, and the first source-drain layer 228 further includes a reset signal line VI-A.

[0063] Here, the second via hole 302 is installed in correspondence with the reset signal line VI-A, and the second via hole 302 is installed in correspondence with the activation pattern T7A of the reset transistor T7, and the reset signal line VI-A passes through the second via hole 302 and is connected to the activation pattern T7A of the reset transistor T7. By providing the reset signal line in the first source-drain layer and providing the second via hole in correspondence with the activation pattern of the reset transistor and the reset signal line, the portion of the reset signal line located in the active layer can be removed, avoiding the space that occupies the active layer and improving the aperture ratio.

[0064] Specifically, compared to forming two portions of the reset signal line using a semiconductor film layer and a first source-drain film layer in a comparative display device, the embodiment of the present invention avoids occupying space in the active layer by adopting a single-layer design for the reset signal line, taking into consideration the small influence of the semiconductor film layer on the impedance of the reset signal line, thereby avoiding process complexity and reduced yield. By positioning the second via hole in correspondence with the active pattern of the reset transistor and the reset signal line, the reset signal line can be made to pass directly through the second via hole and connect to the active pattern of the reset transistor, eliminating the need for additional transfer lines and reducing process steps and space occupancy.

[0065] Specifically, the second via hole 302 penetrates the interlayer insulating layer 227, the second gate insulating layer 225, and the first gate insulating layer 223.

[0066] In some embodiments, as shown in Figures 6 to 16, the drive circuit layer 22 further includes a pixel drive circuit 220, an active layer 222, a first source-drain layer 228, and a third via hole 303. The pixel drive circuit 220 includes an initialization transistor T4, the active layer 222 includes an activation pattern T4A of the initialization transistor T4, and the first source-drain layer 228 further includes initialization signal lines VI-Q.

[0067] Here, the third via hole 303 is provided in correspondence with the initialization signal lines VI-Q, and the third via hole 303 is provided in correspondence with the activation pattern T4A of the initialization transistor T4, and the initialization signal lines VI-Q are connected to the activation pattern T4A of the initialization transistor T4 by passing through the third via hole 303. By providing the initialization signal lines in the first source-drain layer and the third via hole in correspondence with the activation pattern and initialization signal lines of the initialization transistor, the impedance can be reduced, the occupancy of space in the active layer can be avoided, and the aperture ratio can be improved by changing the location of the initialization signal lines from the active layer and the second gate layer to the first source-drain layer.

[0068] Specifically, compared to forming the two parts of the initialization signal line using a semiconductor film layer and a second gate film layer respectively in a comparative display device, the embodiment of the present invention, taking into consideration the relatively high impedance of the semiconductor film layer and the second gate film layer, forms the initialization signal line using a first source-drain layer, thereby reducing the impedance of the initialization signal line, avoiding the use of a single-layer design for the initialization signal line and occupying space in the active layer, thus avoiding process complexity and reduced yield. By positioning the third via hole in correspondence with the active pattern and initialization signal line of the initialization transistor, the initialization signal line can pass through the third via hole and be directly connected to the active pattern of the initialization transistor, eliminating the need for additional transfer lines and reducing process steps and space occupancy.

[0069] Specifically, the third via hole 303 penetrates the interlayer insulating layer 227, the second gate insulating layer 225, and the first gate insulating layer 223.

[0070] Specifically, the impedance of the first source-drain layer is smaller than the impedance of the second gate layer and smaller than the impedance of the active layer.

[0071] In some embodiments, as shown in Figures 6 to 16, the drive circuit layer 22 further includes data lines Data, and a gap exists between the orthographic projection of the light-emitting connection line EM-L onto the substrate 21 and the orthographic projection of at least some of the data lines Data onto the substrate 21. By having a gap between the orthographic projection of the light-emitting connection line EM-L onto the substrate 21 and the orthographic projection of at least some of the data lines Data onto the substrate 21, each light-emitting connection line EM-L can reduce the coupling capacitance between each light-emitting control line EM and the data line Data, and the total capacitance of at least some of the data lines can be reduced, which prevents insufficient pixel charging time and, consequently, crosstalk due to erroneous charging, improves display uniformity, and enhances the display effect.

[0072] Specifically, in a comparative display device, both the first and second light emission control wirings overlap with the respective data lines. In contrast, in the embodiment of the present invention, multiple light emission connection lines are cut, and a portion of the gates of the first and second light emission control transistors in the light emission connection lines remains. This reduces the coupling capacitance between the light emission control lines and at least some of the data lines by ensuring that the orthographic projection of the light emission connection lines onto the substrate does not overlap with at least some of the data lines.

[0073] In some embodiments, as shown in Figures 6 to 16, the drive circuit layer 22 further includes data lines Data, and a gap exists between the orthographic projection of the reset connection line RL onto the substrate 21 and the orthographic projection of the data line Data onto the substrate 21. By having a gap between the orthographic projection of the reset connection line RL onto the substrate 21 and the orthographic projection of the data line Data onto the substrate 21, each reset connection line RL can reduce the coupling capacitance between each reset control line Reset-A and the data line Data, thereby reducing the total capacitance of the data lines, preventing insufficient pixel charging time and consequently crosstalk due to mischarging, improving display uniformity, and enhancing the display effect.

[0074] Specifically, in a comparative display device, both the first and second reset control wiring overlap with the data lines. In contrast, in the embodiment of the present invention, multiple reset connection lines are cut, a portion of the reset transistor gates in the reset connection lines remains, there is no overlap between the orthographic projection of the reset connection lines on the substrate and the data lines, and the coupling capacitance between the reset control lines and at least some of the data lines is reduced.

[0075] In some embodiments, as shown in Figures 3 to 16, the drive circuit layer 22 further includes a first gate layer 224, a first source-drain layer 228, and a second source-drain layer 232, wherein the second source-drain layer 232 is located on the side of the first source-drain layer 228 away from the first gate layer 224, and the second source-drain layer 232 includes a high-potential power line VDD.

[0076] Here, the first gate layer 224 further includes an initialization connection line SL2. The first source-drain layer further includes an initialization control line Reset-Q. The initialization connection line SL2 includes a first connection part SL2a and a second connection part SL2b, and the first connection part SL2a is connected to the initialization control line Reset-Q and the second connection part SL2b. There is a gap between the orthographic projection of one end of the first connection part SL2a onto the substrate 21 and the orthographic projection of one end of the high-potential power line VDD onto the substrate 21. By having a gap between the orthographic projection of one end of the first connection part onto the substrate and the orthographic projection of one end of the high-potential power line onto the substrate, the coupling capacitance between the high-potential power line and the initialization control line can be reduced, improving the uniformity of the display and enhancing the display effect.

[0077] Specifically, it can be seen that the initialization control line passes through a via hole and is connected to one end of the first connection part SL2a, and that there is a gap between the orthographic projection of the other end of the first connection part SL2a onto the substrate and the orthographic projection of one end of the high-potential power line VDD onto the substrate.

[0078] In some embodiments, as shown in Figures 3 to 16, the drive circuit layer 22 further includes a first gate layer 224, a second gate layer 226, a first source-drain layer 228, and a second source-drain layer 232. The second gate layer 226 is provided between the first gate layer 224 and the first source-drain layer 228, and the second source-drain layer 232 is provided on the side of the first source-drain layer 228 away from the second gate layer 226. The second gate layer 226 includes a first high-potential power supply connection line VDD-L1, the first source-drain layer 228 includes a second high-potential power supply connection line VDD-L2, and the second source-drain layer 232 includes a high-potential power supply line VDD.

[0079] The second high-potential power supply connection line VDD-L2 is connected to the first high-potential power supply connection line VDD-L1 and the high-potential power supply line VDD. The drive circuit layer 22 further includes a fourth via hole 304. The second high-potential power supply connection line VDD-L2 passes through the fourth via hole 304 and is connected to the first high-potential power supply connection line VDD-L1. The lower end of the fourth via hole 304 is collinear with the lower end of the second high-potential power supply connection line VDD-L2. By positioning the lower end of the fourth via hole and the lower end of the second high-potential power supply connection line collinear, the distance between the fourth via hole and the active pattern of the drive transistor can be increased, thereby preventing the fourth via hole from affecting the electrical characteristics of the active pattern of the drive transistor and improving the electrical stability of the drive transistor.

[0080] Specifically, as shown in Figure 5, the pixel driving circuit 220 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3, and an initialization transistor T4. The gate of the switching transistor T2 is connected to the switching control line Scan(n), the first electrode of the switching transistor T2 is connected to the data line Data, and the second electrode of the switching transistor T2 and the first electrode of the driving transistor T1 are connected to the first node A. The gate of the compensation transistor T3 is connected to the switching control line Scan(n), the first electrode of the compensation transistor T3 and the gate of the driving transistor T1 are connected to the second node Q, and the second electrode of the compensation transistor T3 and the second electrode of the driving transistor T1 are connected to the third node B. The gate of the initialization transistor T4 is connected to the initialization control line Reset-Q, the first electrode of the initialization transistor T4 is connected to the initialization signal line VI-Q, and the second electrode of the initialization transistor T4 and the gate of the driving transistor T1 are connected to the second node Q.

[0081] Specifically, as shown in Figure 5, the pixel driving circuit 220 further includes a first light emission control transistor T5, a second light emission control transistor T6, a reset transistor T7, and a storage capacitor Cst.

[0082] The gate of the first light emission control transistor T5 is connected to the light emission control line EM, the first electrode of the first light emission control transistor T5 is connected to the high-potential power supply line VDD, and the second electrode of the first light emission control transistor T5 is connected to the first electrode of the drive transistor T1 and connected to the first node A.

[0083] The gate of the second light emission control transistor T6 is connected to the light emission control line EM, and the first electrode of the second light emission control transistor T6 and the second electrode of the drive transistor T1 are connected to the third node B.

[0084] The gate of the reset transistor T7 is connected to the reset control line Reset-A, the first electrode of the reset transistor T7 is connected to the reset signal line VI-A, the second electrode of the reset transistor T7 and the second electrode of the second light emission control transistor T6 are connected to the fourth node C, and the second electrode of the reset transistor T7 and the anode of the light emission device LED are connected to the fourth node C.

[0085] One plate of the storage capacitor Cst is connected to the high-potential power line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the drive transistor T1 and to the second node Q.

[0086] Specifically, as shown in Figure 5, the cathode of the light-emitting device LED is connected to the low-potential power line VSS.

[0087] Specifically, the display panel includes multiple switching control lines, each capable of driving one row of pixel units. The switching control line Scan(n) is the nth switching control line among the multiple switching control lines, where n is 1 or greater and is a positive integer. The switching control line Scan(n) is connected to a gate drive circuit, which may input a signal, or a drive chip may directly input a signal. Similarly, the display panel may include multiple initialization control lines, multiple reset control lines, and multiple light emission control lines. Each initialization control line, each light emission control line, and each reset control line drives one row of pixel units. The initialization control lines, light emission control lines, and reset control lines may be connected to a gate drive circuit, or a drive chip may input a signal. The gate drive circuits connected to the initialization control lines, light emission control lines, and reset control lines may be the same as, or different from, the gate drive circuits connected to the switching control lines.

[0088] Specifically, since structures are filled into each vial and each membrane layer is stacked and installed, the location of each vial is not visible, but the location of each vial may be determined based on the location of each structure.

[0089] In some embodiments, as shown in Figures 3 to 16, the display panel 2 includes a plurality of pixel units 240 arranged in an array. The pixel unit 240 includes a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c. The first sub-pixel unit 240a includes a first light-emitting device 341, the second sub-pixel unit 240b includes a second light-emitting device 342, and the third sub-pixel unit 240c includes a third light-emitting device 343. The areas of the anode ANO1 of the first light-emitting device 341, the anode ANO2 of the second light-emitting device 342, and the anode ANO3 of the third light-emitting device 343 are different from each other. Because the luminous efficiencies of the different light-emitting devices are different, by making the areas of the anodes of the first light-emitting device, the second light-emitting device, and the third light-emitting device different from each other, the volume of the light-emitting devices can be set according to the luminous efficiency of each light-emitting device, and the luminous brightness of each light-emitting device can be made uniform to improve the display effect.

[0090] Specifically, the light-emitting device LED includes a first light-emitting device, a second light-emitting device, and a third light-emitting device, and the anode of the light-emitting device includes the anode of the first light-emitting device, the anode of the second light-emitting device, and the anode of the third light-emitting device.

[0091] Specifically, as shown in Figures 3 and 4, the light-emitting material layer 243 includes a first light-emitting material layer 243a, a second light-emitting material layer 243b, and a third light-emitting material layer 243c, and the light-emitting colors of the first light-emitting material layer 243a, the second light-emitting material layer 243b, and the third light-emitting material layer 243c are different from each other. Specifically, the pixel electrode layer forms the anode of the light-emitting device, the light-emitting material layer forms the light-emitting material layer of the light-emitting device, and the common electrode forms the cathode of the light-emitting device.

[0092] Specifically, taking as an example that the emission colors of the first light-emitting material layer 243a, the second light-emitting material layer 243b, and the third light-emitting material layer 243c are red, green, and blue, respectively, the luminous efficiency of each light-emitting material is different. Specifically, the luminous efficiency of the blue light-emitting material is the lowest and the luminous efficiency of the red light-emitting material is the highest. Therefore, the anode area of ​​the first light-emitting device can be made smaller than the anode area of ​​the second light-emitting device, and the anode area of ​​the second light-emitting device can be made smaller than the anode area of ​​the third light-emitting device.

[0093] In some embodiments, as shown in Figures 2 to 16, in the first direction X, the width of the anode ANO1 of the first light-emitting device 341 is smaller than the width of the anode ANO2 of the second light-emitting device 342, and the width of the anode ANO2 of the second light-emitting device 342 is smaller than the width of the anode ANO3 of the third light-emitting device 343, and the first direction X is the same as the direction in which the light emission control line extends. By making the width of the anode of the first light-emitting device smaller than the width of the anode of the second light-emitting device, and making the width of the anode of the second light-emitting device smaller than the width of the anode of the third light-emitting device, the volume of the light-emitting devices can be set based on the luminous efficiency of each light-emitting device, and the luminous brightness of each light-emitting device can be matched to improve the display effect.

[0094] In some embodiments, as shown in Figures 3 to 6 and 7, the drive circuit layer 22 further includes an active layer 222. The display panel 2 includes a plurality of pixel units 240 arranged in an array, each of which includes three pixel drive circuits 220. In each of the pixel driving circuits 220, the active layer 222 includes the active pattern T1A of the driving transistor T1, the active pattern T2A of the switching transistor T2, the first electrode T2S of the switching transistor T2, the active pattern T3A of the compensating transistor T3, the first electrode T3S of the compensating transistor T3, the active pattern T4A of the initializing transistor T4, the first electrode T4S of the initializing transistor, the second electrode T4D of the initializing transistor, the active pattern T5A of the first light emission control transistor T5, the first electrode T5S of the first light emission control transistor T5, the active pattern T6A of the second light emission control transistor T6, the second electrode T6D of the second light emission control transistor T6, the active pattern T7A of the reset transistor T7, the first electrode T7S of the reset transistor T7, the second electrode T7D of the reset transistor T7, the first node A, and the third node B. The activation pattern T1A of the drive transistor T1 is provided along the first direction X, while the activation patterns T2A of the switching transistor T2, T4A of the first initialization transistor T4, T5A of the first light emission control transistor T5, T6A of the second light emission control transistor T6, and T7A of the reset transistor T7 are provided along the second direction Y. The activation pattern T3A of the compensation transistor T3 includes a portion provided along the first direction X and a portion provided along the second direction Y. The activation pattern T1A of the drive transistor T1 is connected to the activation pattern T2A of the switching transistor T2, the activation pattern T3A of the compensation transistor T3, the activation pattern T5A of the first light emission control transistor T5, and the activation pattern T6A of the second light emission control transistor T6, and the activation pattern T3A of the compensation transistor T3 is connected to the activation pattern T4A of the first initialization transistor T4.The active pattern T6A of the second light-emitting control transistor T6 is connected to the active pattern T7A of the reset transistor T7, and the angle between the first direction X and the second direction Y is greater than 0 degrees and less than or equal to 90 degrees.

[0095] Specifically, Figures 6 to 16 show excerpts of a portion of a two-row pixel unit, revealing that the reset transistor is located below the second light-emitting control transistor.

[0096] In some embodiments, as shown in Figures 3 to 6 and 8, the drive circuit layer 22 further includes a first gate layer 224. In each pixel drive circuit 220, the first gate layer 224 is provided with the gate T1G of the drive transistor T1, the gate T2G of the switching transistor T2, the gate T3G of the compensation transistor T3, the gate T4G of the initialization transistor T4, the gate T5G of the first light emission control transistor T5, the gate T6G of the second light emission control transistor T6, the gate T7G of the reset transistor T7, the first electrode plate CsT1 of the storage capacitor Cst, the light emission connection line EM-L, the switching connection line SL1, the initialization connection line SL2 and the reset connection line RL, the initialization connection line SL2, the switching connection line SL1, the gate T1G of the drive transistor T1, the light emission connection line EM-L and the reset connection line RL, all spaced apart in sequence along the second direction Y.

[0097] Specifically, as shown in Figures 6 and 8, the light emission connection line EM-L and the reset connection line RL are disconnected and installed in a row of pixel units.

[0098] Specifically, as shown in Figure 8, the gate T2G of the switching transistor T2 is connected to the gate T3G of the compensation transistor T3.

[0099] Specifically, as shown in Figure 8, some structures are identified using multiple codes because the electrodes and signal lines share this structure, and the signals transmitted through this structure are the same (without considering the voltage drop issue). For example, the gate T5G of the first light-emitting control transistor T5 and the light-emitting connection line EM-L are marked as the same structure because the corresponding portion of the light-emitting connection line EM-L and the active pattern of the first light-emitting control transistor T5 is the gate T5G of the first light-emitting control transistor T5. Similarly, the meaning of other structures that are marked using multiple codes can also be determined.

[0100] Specifically, as shown in Figures 6 to 8, the gates of each transistor are positioned to correspond to the activation patterns of each transistor. For example, the gate T3G of the compensation transistor is positioned to correspond to the activation pattern T3A of the compensation transistor T3.

[0101] In some embodiments, as shown in Figures 5 to 8, the gate T3G of the compensation transistor T3 includes a first gate T3Ga and a second gate T3Gb. The first gate T3Ga is connected to the second gate T3Gb. By using a dual-gate design for the gate of the compensation transistor, the gate control capability of the display panel can be improved and leakage current can be reduced.

[0102] In some embodiments, as shown in Figures 5 to 8, the gate T4G of the initialization transistor T4 includes a third gate T4Ga and a fourth gate T4Gb, where the third gate T4Ga is connected to the fourth gate T4Gb. By using a dual-gate design for the gate of the initialization transistor, the gate control capability of the display panel can be improved and leakage current can be reduced.

[0103] In some embodiments, as shown in Figures 3 to 6 and 9, the drive circuit layer 22 further includes a second gate layer 226. In each of the pixel drive circuits 220, the second gate layer 226 includes a first high-potential power supply connection line VDD-L1 and a second electrode plate CsT2 of storage capacitance Cst, the first high-potential power supply connection line VDD-L1 being connected to the second electrode plate CsT2 of storage capacitance Cst.

[0104] Specifically, as shown in Figures 6 and 9, the first high-potential power supply connection line VDD-L1 is connected to the second electrode plate CsT2 of the storage capacitor Cst, a via hole is provided in the second electrode plate CsT2 of the storage capacitor Cst, the second electrode plate CsT2 of the storage capacitor Cst is provided corresponding to the first electrode plate CsT1 of the storage capacitor Cst, and the first electrode of the compensation transistor is connected to the gate of the drive transistor by passing through the via hole.

[0105] Specifically, the second gate layer may include a repair line. By installing a repair line on the pixel unit, if an abnormality occurs in a sub-pixel unit or pixel unit, the connection between the anode of the light-emitting device corresponding to the sub-pixel unit and the pixel driving circuit can be disconnected. By directly connecting the repair line to the anode of the sub-pixel unit, the sub-pixel unit can be driven directly, thus avoiding the occurrence of dark spots. If no abnormality occurs in the sub-pixel unit or pixel unit, the repair line may be made floating.

[0106] In some embodiments, as shown in Figures 3 to 6 and 10, the drive circuit layer 22 further includes a first source-drain layer 228. In each of the pixel drive circuits 220, the first source-drain layer 228 includes an initialization signal line VI-Q, an initialization control line Reset-Q, a switching control line Scan(n), a second high-potential power supply connection line VDD-L2, an emission control line EM, a reset control line Reset-A, a reset signal line VI-A, a first transfer line KL1, a second transfer line KL2, a third transfer line KL3, and a fourth transfer line KL4. The initialization signal line VI-Q, the initialization control line Reset-Q, the switching control line Scan(n), the first transfer line KL1, the second high-potential power supply connection line VDD-L2, the emission control line EM, the third transfer line KL3, the reset control line Reset-A, and the reset signal line VI-A are arranged sequentially at intervals along the second direction Y.

[0107] Specifically, as shown in Figures 6 to 10, the initialization signal lines VI-Q in a row of pixel units are continuously connected to the first electrode T4S of the initialization transistor T4.

[0108] Specifically, as shown in Figures 6 to 10, in a single row of pixel units, the initialization control line Reset-Q is continuous, and the initialization control line Reset-Q is connected to the initialization connection line SL2, thereby reducing the impedance of the initialization control line.

[0109] Specifically, as shown in Figures 6 to 10, in one row of pixel units, the switching control line Scan(n) is connected, and the switching control line Scan(n) is connected to the switching control line Scan(n).

[0110] Specifically, as shown in Figures 6 to 10, in a single row of pixel units, the second high-potential power supply connection line VDD-L2 is continuous, and the second high-potential power supply connection line VDD-L2 is connected to the second electrode plate CsT2 of the storage capacitor Cst, thereby connecting the second high-potential power supply connection line VDD-L2 to the first high-potential power supply connection line VDD-L1, and reducing the impedance of the high-potential power supply line.

[0111] Specifically, as shown in Figures 6 to 10, in a single row of pixel units, the light emission control lines EM are continuous, and the light emission control lines EM are connected to the light emission connection lines EM-L, reducing the impedance of the light emission control lines.

[0112] Specifically, as shown in Figures 6 to 10, in a single row of pixel units, the reset control line Reset-A is continuous, and the reset control line Reset-A is connected to the reset connection line RL, thereby reducing the impedance of the reset control line Reset-A.

[0113] Specifically, as shown in Figures 6 to 10, in a single row of pixel units, reset signal lines VI-A are continuous, and reset signal lines VI-A are connected to the first electrode T7S of the reset transistor T7.

[0114] Specifically, as shown in Figures 6 to 10, the first transfer line KL1 is connected to the first electrode T2S of the switching transistor T2, one end of the second transfer line KL2 is connected to the first electrode T3S of the compensating transistor T3, the other end of the second transfer line KL2 is connected to the gate T1G of the driving transistor T1, the third transfer line KL3 is connected to the first electrode T5S of the first light emission control transistor T5, and the fourth transfer line KL4 is connected to the second electrode T6D of the second light emission control transistor T6.

[0115] In some embodiments, as shown in Figures 3 to 6 and 11, the drive circuit layer 22 further includes a second source-drain layer 232. Within each pixel unit 240, the second source-drain layer 232 includes three data lines Data, three high-potential power lines VDD, one low-potential power line VSS, one reset connection line VI-L, and three anode connection lines ANO-L. The three data lines Data and the three high-potential power lines VDD are arranged alternately along the first direction X. The low-potential power line VSS is located on the side of the high-potential power line VDD away from the data line Data, the reset connection line VI-L is located between one data line Data and one high-potential power line VDD, each anode connection line ANO-L is located between one high-potential power line VDD and one data line Data, and the three high-potential power lines VDD are connected to one second high-potential power connection line VDD-L2.

[0116] Specifically, as shown in Figures 6 and 11, the data line Data, the high-potential power line VDD, the low-potential power line VSS, the reset connection line VI-L, and the anode connection line ANO-L are all provided along the second direction Y.

[0117] Specifically, as shown in Figures 6 to 11, the data line Data is connected to the first transfer line KL1, the high-potential power line VDD is connected to the second high-potential power connection line VDD-L2, and the high-potential power line VDD is connected to the third transfer line KL3. This enables gridding and signal transmission of the high-potential power line VDD, and reduces the impedance of the high-potential power line. As can be understood, the signals in the first and second high-potential power connection lines are the signals of the high-potential power line, and the first and second high-potential power connection lines can be considered as part of the high-potential power line.

[0118] Specifically, as shown in Figures 6 to 11, the anode connection line ANO-L may be connected to the fourth transfer line KL4.

[0119] In some embodiments, as shown in Figures 3 to 6 and Figures 11 to 12, the light-emitting functional layer 24 includes a pixel electrode layer 241. Within each pixel unit 240, the pixel electrode layer 241 includes three anodes ANO of the light-emitting device LEDs, each anode ANO of the light-emitting device LED is connected to the anode connection line ANO-L, and one of the anode connection lines ANO-L is connected to a fourth connection line.

[0120] Specifically, the orthographic projection of the anode of the light-emitting device on the substrate and the orthographic projection of the high-potential power line on the substrate overlap.

[0121] Specifically, as shown in Figure 12, the anode ANO of the light-emitting device LED is installed along the second direction Y, the anodes ANO of multiple light-emitting device LEDs are installed at intervals along the first direction X, the anode ANO of each light-emitting device LED is connected to the anode connection line ANO-L, the anode connection line ANO-L is connected to the fourth transfer line KL4, and the fourth transfer line KL4 is connected to the second electrode T6D of the second light-emitting control transistor T6, thereby realizing the connection between the light-emitting device and the second light-emitting control transistor.

[0122] In some embodiments, as shown in Figures 3 to 12, the display panel 2 includes a plurality of pixel units 240 arranged in an array. The pixel unit 240 includes a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c. The first sub-pixel unit 240a includes a first light-emitting device 341, the second sub-pixel unit 240b includes a second light-emitting device 342, and the third sub-pixel unit 240c includes a third light-emitting device 343. The pixel driving circuit 220 includes a first pixel driving circuit 220a, a second pixel driving circuit 220b, and a third pixel driving circuit 220c, which are electrically connected to the anode of the first light-emitting device 341, the anode of the second light-emitting device 342, and the anode of the third light-emitting device 343, respectively. The data line Data includes a first data line Data-R, a second data line Data-G, and a third data line Data-B, which are electrically connected to the first pixel drive circuit 220a, the second pixel drive circuit 220b, and the third pixel drive circuit 220c, respectively. The high-potential power line VDD includes a first high-potential power line VDD1, a second high-potential power line VDD2, and a third high-potential power line VDD3, which are electrically connected to the first pixel drive circuit 220a, the second pixel drive circuit 220b, and the third pixel drive circuit 220c, respectively.

[0123] Specifically, the first data line Data-R, the second data line Data-G, and the third data line Data-B may correspond to the first subpixel unit, the second subpixel unit, and the third subpixel unit, respectively. As can be seen, when displayed on a display panel, the brightness of different subpixel units may be the same or different, and therefore, different drive voltages may be used to drive different subpixel units. Thus, by inputting different voltages to the first data line Data-R, the second data line Data-G, and the third data line Data-B, the brightness corresponding to each subpixel unit can be displayed.

[0124] Specifically, the first high-potential power line VDD1, the second high-potential power line VDD2, and the third high-potential power line VDD3 may correspond to the first subpixel unit, the second subpixel unit, and the third subpixel unit, respectively, and may be the same or different from the first high-potential power line VDD1, the second high-potential power line VDD2, and the third high-potential power line VDD3.

[0125] Furthermore, to explain the relative positions of each film layer, Figures 6, 13 to 16 are provided and explained. The relative positions of each structure in the first gate layer 224 and each structure in the active layer 222 can be seen from Figure 13. The relative positions of each structure in the active layer 222, the first gate layer 224, and the second gate layer 226 can be seen from Figure 14. The relative positions of each structure in the active layer 222, the first gate layer 224, the second gate layer 226, and the first source-drain layer 228 can be seen from Figure 15. The relative positions of each structure in the active layer 222, the first gate layer 224, the second gate layer 226, the first source-drain layer 228, and the second source-drain layer 232 can be seen from Figure 16.

[0126] Specifically, in the above embodiment, the first electrode of the transistor is the source and the second electrode is the drain, or in the above embodiment, the first electrode of the transistor is the drain and the second electrode is the source.

[0127] Specifically, the active layer material may include a silicon semiconductor material, more specifically low-temperature polysilicon, or the active layer material may include an oxide semiconductor material, more specifically a metal oxide semiconductor material, and more specifically indium gallium zinc oxide.

[0128] Specifically, the drive transistor, switch transistor, compensation transistor, initialization transistor, first light emission control transistor, second light emission control transistor, and reset transistor may be P-type transistors or N-type transistors.

[0129] Specifically, as can be understood, when disassembling each film layer with reference to Figure 6, there may be some structural deficiencies in some film layers due to differences in the cut sections. As can be understood, the relative position and dimensions of each film layer in the display panel can be determined by referring to Figure 6 and combining it with other figures. For example, in Figure 11, there may be some structural deficiencies in the first data line Data-R in the second source-drain layer 232, and the low-potential power line VSS is not shown, but it can be understood that the position and dimensions of the first data line Data-R and the low-potential power line VSS can be determined by referring to Figure 6 and other drawings.

[0130] Specifically, the above embodiments have described the display panel in detail from the perspectives of the circuit of the display panel, the film layer structure, the specific design of each film layer, and the connection and relative relationships between each film layer. However, if there are no conflicts between the embodiments, they can be combined. For example, the light emission control line and the light emission connection line are installed along a first direction, the orthographic projection of the light emission connection line onto the substrate and the orthographic projection of the light emission control line onto the substrate overlap, the width of the light emission connection line in a second direction is greater than or equal to the width of the light emission control line in the second direction, and in the overlapping region of the light emission control line and the light emission connection line, the orthographic projection of the light emission connection line onto the substrate is located within the orthographic projection of the light emission connection line onto the substrate. The reset control line and the reset connection line are installed along a first direction, the orthographic projection of the reset connection line onto the substrate and the orthographic projection of the reset control line onto the substrate overlap, the width of the reset connection line in a second direction is greater than or equal to the width of the reset control line in a second direction, and in the overlapping region of the reset connection line and the reset control line, the orthographic projection of the reset control line onto the substrate is located within the orthographic projection of the reset connection line onto the substrate, and the angle between the first direction and the second direction is greater than 0 degrees and less than or equal to 90 degrees.

[0131] Furthermore, embodiments of the present invention provide a display device including a display panel described in any of the above embodiments.

[0132] Specifically, the display panel includes an organic light-emitting diode display panel.

[0133] In the description of this application, the terms “first” and “second” are used for descriptive purposes only and should not be understood as indicating or implying relative importance, or implicitly specifying the number of technical features. Therefore, defining “first” and “second” features may, explicitly or implicitly, include at least one of those features. In the description of this application, unless otherwise specified, “plural” means two or more.

[0134] In the embodiments described above, each description of an embodiment has its own emphasis, and parts not described in detail in one embodiment can be referenced to the relevant descriptions of other embodiments.

[0135] The expressions between embodiments, embodiments, and related technical features of this application may be combined and substituted for each other, as long as they do not contradict each other.

[0136] The above are merely preferred embodiments of the present invention and do not limit the present invention in any way. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical substance of the present invention, without departing from the content of the technical solution of the present invention, all fall within the scope of the technical solution of the present invention.

Claims

1. It is a display panel, circuit board and The substrate includes a drive circuit layer installed on one side of the substrate, The drive circuit layer includes a plurality of light emission control lines, a plurality of reset control lines, a plurality of light emission transfer lines, and a plurality of reset transfer lines, wherein one of the light emission transfer lines is connected to one of the light emission control lines, and one of the reset transfer lines is connected to one of the reset control lines. A display panel characterized in that at least one of the light emission transfer lines is provided with a cutout, and / or at least one of the reset transfer lines is provided with a cutout.

2. The display panel includes a plurality of pixel units, each of which includes a plurality of sub-pixel units, and the light emission transfer line includes a plurality of light emission connection lines, with the cutout located between two adjacent light emission connection lines, and each light emission connection line is installed corresponding to one of the sub-pixel units. The display panel according to claim 1, characterized in that the reset transfer line includes a plurality of reset connection lines, the disconnection is between two adjacent reset connection lines, and each reset connection line is installed corresponding to one of the subpixel units.

3. The light emission control line and the light emission connection line are installed along a first direction, the orthographic projection of the light emission connection line onto the substrate and the orthographic projection of the light emission control line onto the substrate overlap, and the width of the light emission connection line in a second direction is greater than or equal to the width of the light emission control line in a second direction. The display panel according to claim 2, characterized in that, in the region where the light-emitting connection line and the light-emitting control line overlap, the orthographic projection of the light-emitting control line onto the substrate is located within the orthographic projection of the light-emitting connection line onto the substrate, and the angle between the first direction and the second direction is greater than 0 degrees and less than or equal to 90 degrees.

4. The reset control line and the reset connection line are installed along a first direction, the orthographic projection of the reset connection line onto the substrate and the orthographic projection of the reset control line onto the substrate overlap, and the width of the reset connection line in a second direction is greater than or equal to the width of the reset control line in a second direction. The display panel according to claim 2, characterized in that, in the region where the reset connection line and the reset control line overlap, the orthographic projection of the reset control line onto the substrate lies within the orthographic projection of the reset connection line onto the substrate, and the angle between the first direction and the second direction is greater than 0 degrees and 90 degrees or less.

5. The display panel according to any one of claims 2 to 4, wherein the drive circuit layer includes a first gate layer and a first source-drain layer, the first gate layer is installed between the substrate and the first source-drain layer, the first gate layer includes the light-emitting connection line and the reset connection line, and the first source-drain layer includes the light-emitting control line and the reset control line.

6. The display panel according to any one of claims 2 to 4, characterized in that the drive circuit layer includes a first via hole, the light emission control line is connected to the light emission connection line through the first via hole, and the light emission control line is installed symmetrically with respect to the first via hole.

7. The drive circuit layer further includes a pixel drive circuit, an active layer, a first source-drain layer, and a second via hole, the pixel drive circuit includes a reset transistor, the active layer includes an active pattern for the reset transistor, and the first source-drain layer further includes a reset signal line. The display panel according to any one of claims 2 to 4, characterized in that the second via hole is installed corresponding to the reset signal line and corresponding to the activation pattern of the reset transistor, and the reset signal line passes through the second via hole and is connected to the activation pattern of the reset transistor.

8. The drive circuit layer further includes a pixel drive circuit, an active layer, a first source-drain layer, and a third via hole, the pixel drive circuit includes an initialization transistor, the active layer includes an activation pattern for the initialization transistor, and the first source-drain layer further includes an initialization signal line. The display panel according to any one of claims 2 to 4, characterized in that the third via hole is installed corresponding to the initialization signal line and corresponding to the activation pattern of the initialization transistor, and the initialization signal line passes through the third via hole and is connected to the activation pattern of the initialization transistor.

9. The drive circuit layer further includes a first gate layer, a first source-drain layer, and a second source-drain layer, wherein the second source-drain layer is located on the side of the first source-drain layer away from the first gate layer, and the second source-drain layer includes a high-potential power line. The display panel according to any one of claims 2 to 4, wherein the first gate layer further includes an initialization connection line, the first source-drain layer further includes an initialization control line, the initialization connection line includes a first connection portion and a second connection portion, the first connection portion is connected to the initialization control line and the second connection portion, and there is a gap between the orthographic projection of one end of the first connection portion onto the substrate and the orthographic projection of one end of the high-potential power line onto the substrate.

10. The drive circuit layer further includes a first gate layer, a second gate layer, a first source-drain layer, and a second source-drain layer, wherein the second gate layer is installed between the first gate layer and the first source-drain layer, the second source-drain layer is installed on the side of the first source-drain layer away from the second gate layer, the second gate layer includes a first high-potential power supply connection line, the first source-drain layer includes a second high-potential power supply connection line, and the second source-drain layer includes a high-potential power supply line. The display panel according to any one of claims 2 to 4, characterized in that the second high-potential power supply connection line is connected to the first high-potential power supply connection line and the high-potential power supply line, the drive circuit layer further includes a fourth via hole, the second high-potential power supply connection line passes through the fourth via hole and is connected to the first high-potential power supply connection line, and the lower end of the fourth via hole and the lower end of the second high-potential power supply connection line are located on the same straight line.

11. A display device characterized by including a display panel according to any one of claims 1 to 4.

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