Memory device including bitline

Abstract

To provide a memory device with excellent operating characteristics and improved integration density. [Solution] The memory device of the present invention comprises a peripheral circuit region, a first cell region located at a different vertical level from the peripheral circuit region and including a plurality of lower bit lines and a plurality of bypass bit lines, and a second cell region including a plurality of upper bit lines electrically connected to the plurality of bypass bit lines, wherein the plurality of lower bit lines include a first lower bit line including a first segment and a second segment located spaced apart from each other with a line cut region in between, and a second lower bit line located spaced apart from the first lower bit line in a first horizontal direction and extending in a second horizontal direction, and the plurality of bypass bit lines include a first cell region located spaced apart in a second horizontal direction within the line cut region, and the first cell region is located between the peripheral circuit region and the second cell region.

Description

Technical Field

[0001] The present invention relates to a memory device, and more particularly to a memory device having memory strings arranged in a vertical direction.

Background Art

[0002] In an electronic system that requires data storage, a memory device capable of storing a large amount of data is required. As one method for increasing the data storage capacity of a memory device, a memory device including three-dimensionally arranged memory cells has been proposed instead of two-dimensionally arranged memory cells. In addition, a memory device has been proposed in which a part of the memory device is formed on a first substrate, another part of the memory device is formed on a second substrate, and the first substrate and the second substrate are bonded.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a memory device having excellent operating characteristics and improved integration density.

Means for Solving the Problems

[0004] A memory device according to one aspect of the present invention made to achieve the above objectives comprises a peripheral circuit region, a first cell region arranged at a different vertical level from the peripheral circuit region and including a plurality of lower bit lines and a plurality of bypass bit lines, and a second cell region including a plurality of upper bit lines electrically connected to the plurality of bypass bit lines, wherein the plurality of lower bit lines include a first lower bit line including a first segment and a second segment arranged spaced apart from each other with a line cut region in between, and a second lower bit line spaced apart from the first lower bit line in a first horizontal direction and extending in a second horizontal direction, the plurality of bypass bit lines include a first cell region arranged spaced apart in the second horizontal direction within the line cut region, and the first cell region is arranged between the peripheral circuit region and the second cell region.

[0005] A memory device according to another aspect of the present invention made to achieve the above objectives comprises a peripheral circuit region, a first cell region disposed on the peripheral circuit region and including a plurality of lower bit lines and a plurality of bypass bit lines, and a second cell region disposed on the first cell region and including a plurality of upper bit lines electrically connected to the plurality of bypass bit lines, wherein the plurality of lower bit lines include cut lower bit lines including a first segment and a second segment disposed spaced apart from each other with a line cut region in between, and one or more normal bit lines that are spaced apart in a first horizontal direction from the cut lower bit lines and extend in a second horizontal direction, and the plurality of bypass bit lines include a first cell region disposed spaced apart in the second horizontal direction within the line cut region.

[0006] A memory device according to yet another aspect of the present invention made to achieve the above objectives comprises a peripheral circuit region, a first cell region disposed on the peripheral circuit region including a plurality of lower bit lines, a plurality of bypass bit lines, and lower connecting lines, and a second cell region disposed on the first cell region and including a plurality of upper bit lines electrically connected to the plurality of bypass bit lines, wherein the plurality of lower bit lines include cut lower bit lines including a first segment and a second segment disposed spaced apart from each other with a line cut region in between, and one or more normal bit lines that are spaced apart from the cut lower bit lines in a first horizontal direction and extend in a second horizontal direction, the plurality of bypass bit lines are disposed spaced apart in the second horizontal direction within the line cut region, and the lower connecting lines include a first cell region that is disposed spaced apart from the first segment and the second segment in a first horizontal direction and includes a portion that electrically connects the first segment and the second segment. [Effects of the Invention]

[0007] According to the present invention, by arranging n bypass bit lines in a row within a single line cut region, the first length of the first lower connecting line is relatively small, thereby reducing the area overhead of the bonding pad region and enabling efficient design of the bonding pad region area. Furthermore, since the lower bit line of the first cell region and the upper bit line of the second cell region can be connected to the peripheral circuit via the lower through-via in the bonding pad region, the access speed deviation between the first memory cell array of the first cell region and the second memory cell array of the second cell region can be reduced and / or prevented. Furthermore, since multiple bypass bit lines are sequentially spaced apart between the first and second segments of the first lower bit line, the length of the first lower connecting line is relatively short, thereby enabling efficient design of the bonding pad area. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram of a memory device according to one embodiment. [Figure 2] This is a circuit diagram showing a memory block according to one embodiment. [Figure 3] This figure schematically shows the structure of a memory device according to one embodiment. [Figure 4] This figure illustrates a memory device according to one embodiment. [Figure 5] This figure shows a memory device of a first example according to one embodiment. [Figure 6] Figure 5 is a schematic cross-sectional view showing the memory device. [Figure 7] Figure 5 is a schematic diagram showing the bit line concatenation structure of the memory device. [Figure 8] This is a planar layout diagram showing the arrangement of the lower bit lines in Figure 7. [Figure 9] This is a planar layout diagram showing the arrangement of the upper bit lines in Figure 7. [Figure 10] This figure shows a second example of a memory device according to one embodiment. [Figure 11] Figure 10 is a schematic diagram showing the bit line concatenation structure of the memory device. [Figure 12] This is a planar layout diagram showing the arrangement of the lower bit lines in Figure 11. [Figure 13] This is a planar layout diagram showing the arrangement of the upper bit lines in Figure 11. [Figure 14] This figure shows a memory device of a third example according to one embodiment. [Figure 15] Figure 14 is a schematic diagram showing the bit line concatenation structure of the memory device. [Figure 16] This is a planar layout diagram showing the arrangement of the lower bit lines in Figure 14. [Figure 17] This is a planar layout diagram showing the arrangement of the upper bit lines in Figure 14. [Figure 18] This figure shows a memory device of the fourth example according to one embodiment. [Figure 19]It is a schematic diagram showing the bit line connection structure of the memory device in FIG. 18. [Figure 20] It is a diagram showing a memory device of a fifth example according to an embodiment. [Figure 21] It is a schematic diagram showing the bit line connection structure of the memory device in FIG. 20.

Mode for Carrying Out the Invention

[0009] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail while referring to the drawings.

[0010] FIG. 1 is a block diagram of a memory device 10 according to an embodiment.

[0011] Referring to FIG. 1, the memory device 10 includes a memory cell array 11 and a peripheral circuit PRCT. The peripheral circuit PRCT includes a page buffer circuit 12, a control logic circuit 13, a voltage generator 14, and a row decoder 15. Although not shown in FIG. 1, the peripheral circuit PRCT may further include a data input / output circuit or an input / output interface, etc. Also, the peripheral circuit PRCT may further include a temperature sensor, a command decoder, an address decoder, etc. In this specification, the memory device 10 refers to a "non-volatile memory device".

[0012] The memory cell array 11 includes a plurality of memory blocks (BLK1 to BLKz), where z is a positive integer, and each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of memory cells. The memory cell array 11 is connected to the page buffer circuit 12 via the bit line BL, connected to the voltage generator 14 via the common source line CSL, and connected to the row decoder 15 via the word line WL, the string selection line SSL, and the ground selection line GSL. For example, the memory cell is a flash memory cell. Hereinafter, embodiments of the present invention will be described in detail by taking the case where the memory cell is a NAND flash memory cell as an example. However, the present invention is not limited thereto, and in some embodiments, the memory cell may be a memory cell such as ReRAM (resistive RAM), PRAM (phase change RAM), MRAM (magnetic RAM).

[0013] In the present embodiment, the memory cell array 11 includes a three-dimensional memory cell array, the three-dimensional memory cell array includes a plurality of NAND strings, and each NAND string includes memory cells respectively connected to word lines vertically stacked on a substrate, which will be described in detail with reference to FIG. 2. However, the present invention is not limited thereto, and in some embodiments, the memory cell array 11 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along the row and column directions.

[0014] The page buffer circuit 12 includes multiple page buffers PB. Each of the multiple page buffers PB is connected to a memory cell of the memory cell array 11 via a corresponding bit line BL. The page buffer circuit 12 selects at least one bit line BL from among the bit lines BL in response to the control logic circuit 13. For example, the page buffer circuit 12 selects several bit lines from among the bit lines BL in response to the column address Y_ADDR received from the control logic circuit 13 and the control voltage VY output from the voltage generator 14. Each of the multiple page buffers PB acts as a write driver or sense amplifier. For example, in a program operation, each of the multiple page buffers PB applies a voltage to the bit line BL corresponding to the data Y_DATA, which has been internally processed via the control logic circuit 13, to store the data DATA in the memory cell. For example, in a program verification operation or a read operation, each of the multiple page buffers PB senses a current or voltage via the bit line BL and senses the programmed data DATA by internally processing the sensed data Y_DATA via the control logic circuit 13.

[0015] The control logic circuit 13 outputs various control signals, such as the voltage control signal CTRL_vol, row address X_ADDR, and column address Y_ADDR, for programming data into the memory cell array 11, reading data from the memory cell array 11, or erasing data stored in the memory cell array 11, based on the command CMD, address ADDR, data DATA, and control signal CTRL. In this way, the control logic circuit 13 controls the various operations within the memory device 10 as a whole. For example, the control logic circuit 13 receives the command CMD, address ADDR, data DATA, and control signal CTRL from the memory controller.

[0016] The voltage generator 14 generates various types of voltages for performing program, read, and erase operations on the memory cell array 11 based on the voltage control signal CTRL_vol. Specifically, the voltage generator 14 generates word line voltages VWL, such as program voltage, read voltage, pass voltage, erase verification voltage, and program verification voltage, and also generates control voltages VY for the page buffer circuit 12, such as transistor gate voltage for supplying BL voltage. Furthermore, the voltage generator 14 also generates string selection line SSL voltage, ground selection line GSL voltage, and common source line CSL voltage based on the voltage control signal CTRL_vol.

[0017] The row decoder 15 selects one of several memory blocks (BLK1 to BLKz) in response to the row address X_ADDR received from the control logic circuit 13, selects one of the word lines WL of the selected memory block, and selects one of the string selection lines SSL. For example, during program operation, the row decoder 15 applies a program voltage and a program verification voltage to the selected word line WL, and during read operation, the row decoder 15 applies a read voltage to the selected word line WL.

[0018] According to this embodiment, the memory cell array 11 is arranged in a first cell region CE1 (see Figure 3) and a second cell region CE2 (see Figure 3), and the peripheral circuit PRCT is arranged in the peripheral circuit region PERI (see Figure 3). Here, at least a portion of the peripheral circuit PRCT overlaps the memory cell array 11 in a perpendicular direction.

[0019] Figure 2 is a circuit diagram showing a memory block BLK according to one embodiment.

[0020] Referring to Figure 2, memory block BLK corresponds to one of the multiple memory blocks (BLK1 to BLKz) in Figure 1. Memory block BLK contains NAND strings (NS11 to NS33), and each NAND string (e.g., NS11) contains a series-connected string selection transistor SST, multiple memory cells MCs, and a ground selection transistor GST. The transistors (SST, GST) and memory cells MCs contained in each NAND string form a structure stacked vertically along the substrate.

[0021] The bit lines (BL1 to BL3) extend along a first direction (for example, the Y direction in Figure 3), and the word lines (WL1 to WL8) extend along a second direction (for example, the X direction in Figure 3). In this embodiment, the first direction is referred to as the first horizontal direction, and the second direction is referred to as the second horizontal direction. NAND strings (NS11, NS21, NS31) are located between the first bit line BL1 and the common source line CSL, NAND strings (NS12, NS22, NS32) are located between the second bit line BL2 and the common source line CSL, and NAND strings (NS13, NS23, NS33) are located between the third bit line BL3 and the common source line CSL.

[0022] The string selection transistor SST is connected to the corresponding string selection line (SSL1~SSL3). Multiple memory cells MCs are each connected to their corresponding word lines (WL1~WL8). The ground selection transistor GST is connected to the corresponding ground selection line (GSL1~GSL3). The string selection transistor SST is connected to the corresponding bit line, and the ground selection transistor GST is connected to the common source line CSL. Here, the number of NAND strings, word lines, bit lines, ground selection lines, and string selection lines can be varied depending on the embodiment.

[0023] Figure 3 is a schematic diagram showing the structure of a memory device 100 according to one embodiment.

[0024] Referring to Figure 3, the memory device 100 includes a peripheral circuit region PERI, a first cell region CE1, and a second cell region CE2, all arranged in the vertical direction Z. For example, the peripheral circuit region PERI includes first to fourth peripheral circuit mats (PRCT1, PRCT2, PRCT3, PRCT4) arranged in a matrix. Each of the first to fourth peripheral circuit mats (PRCT1, PRCT2, PRCT3, PRCT4) includes a peripheral circuit PRCT, as described with reference to Figure 1. The peripheral circuit region PERI includes a pad region PA on a portion of the peripheral circuit region PERI (for example, at the edge of the peripheral circuit region PERI), and a pad PAD is located in the pad region PA. The pad PAD is an input / output terminal configured to receive power or signals from an external device and supply them to the first to fourth peripheral circuit mats (PRCT1, PRCT2, PRCT3, PRCT4) within the peripheral circuit region PERI.

[0025] The first cell region CE1 includes first to fourth lower memory mats (MCA1A, MCA2A, MCA3A, MCA4A) arranged in a matrix. The first to fourth lower memory mats (MCA1A, MCA2A, MCA3A, MCA4A) are positioned to overlap perpendicularly with the first to fourth peripheral circuit mats (PRCT1, PRCT2, PRCT3, PRCT4). Each of the first to fourth lower memory mats (MCA1A, MCA2A, MCA3A, MCA4A) contains a memory cell array 11 as described with reference to Figure 1.

[0026] The second cell region CE2 includes first to fourth upper memory mats (MCA1B, MCA2B, MCA3B, MCA4B) arranged in a matrix. Each of the first to fourth upper memory mats (MCA1B, MCA2B, MCA3B, MCA4B) is positioned to overlap perpendicularly with the first to fourth lower memory mats (MCA1A, MCA2A, MCA3A, MCA4A) and also perpendicularly with the first to fourth peripheral circuit mats (PRCT1, PRCT2, PRCT3, PRCT4). Each of the first to fourth upper memory mats (MCA1B, MCA2B, MCA3B, MCA4B) includes a memory cell array 11, as described with reference to Figure 1.

[0027] Here, the terms "lower" and "upper" are used to indicate the relative positions of the first and second components with respect to the peripheral circuit area PERI. For example, the first lower memory mat MCA1A, included in the first cell area CE1, is located closer to the peripheral circuit area PERI, while the first upper memory mat MCA1B, included in the second cell area CE2, is located further away from the peripheral circuit area PERI. Therefore, when the memory device 100 is installed and used in an external device, the "lower" components are located at a higher vertical level than the "upper" components, or conversely, at a lower vertical level.

[0028] Figure 3 illustrates an example in which the pad PAD is located on the pad region PA within the peripheral circuit region PERI, but in other embodiments, the pad PAD may be located on the second cell region CE2.

[0029] Figure 4 is a diagram illustrating an exemplary memory device 100 according to one embodiment.

[0030] Figure 4 schematically shows the layout of a part of the memory device 100 in Figure 3, for example, the first peripheral circuit mat PRCT1, the first lower memory mat MCA1A, and the first upper memory mat MCA1B, which are arranged in the vertical direction Z.

[0031] Referring to Figure 4, the first lower memory mat MCA1A includes a cell area CR and connecting areas (SR1, SR2) located on both sides of the cell area CR. The first upper memory mat MCA1B also includes a cell area CR and connecting areas (SR1, SR2) located on both sides of the cell area CR. The cell area CR of the first upper memory mat MCA1B is positioned in a location corresponding to the cell area CR of the first lower memory mat MCA1A, or in a position that overlaps perpendicularly with the cell area CR of the first lower memory mat MCA1A.

[0032] In some embodiments, the connecting regions (SR1, SR2) may be located on one side of the cell region CR, or they may be located in the center.

[0033] The first peripheral circuit mat PRCT1 includes a page buffer circuit area PGBUF, a page buffer driver PBD, a control logic circuit area CL, and a row decoder area (XD1, XD2). For example, the page buffer circuit area PGBUF is the area where the page buffer circuit 12, as described with reference to Figure 1, is located. The control logic circuit area CL is the area where the control logic circuit 13, as described with reference to Figure 1, is located. The row decoder areas (XD1, XD2) are the areas where the row decoder 15, as described with reference to Figure 1, is located. The row decoder areas (XD1, XD2) are located in positions corresponding to (or vertically overlapping) the connecting areas (SR1, SR2) of the first lower memory mat MCA1A and the connecting areas (SR1, SR2) of the first upper memory mat MCA1B.

[0034] The first lower memory mat MCA1A is electrically connected to the first peripheral circuit mat PRCT1 by the bit line pad BLBP, the word line pad WLBP, and the common source line pad CSLBP, and the first upper memory mat MCA1B is electrically connected to the first lower memory mat MCA1A by the bit line pad BLBP, the word line pad WLBP, and the common source line pad CSLBP. As a result, the bit lines of the first lower memory mat MCA1A and the bit lines of the first upper memory mat MCA1B are electrically connected to the page buffer circuit area PGBUF of the first peripheral circuit mat PRCT1 via the bit line pad BLBP. In addition, the word lines of the first lower memory mat MCA1A and the word lines of the first upper memory mat MCA1B are electrically connected to the row decoder areas (XD1, XD2) of the first peripheral circuit mat PRCT1 via the word line pad WLBP. The common source line of the first lower memory mat MCA1A and the common source line of the first upper memory mat MCA1B are electrically connected to the page buffer driver PBD of the first peripheral circuit mat PRCT1 via the common source line pad CSLBP.

[0035] In some embodiments, the bit line pad BLBP may be divided into multiple regions and arranged in the first lower memory mat MCA1A and the first upper memory mat MCA1B.

[0036] Figure 5 shows a memory device 110 of a first example according to one embodiment. Figure 6 is a schematic cross-sectional view showing the memory device 110 of Figure 5.

[0037] Referring to Figures 5 and 6, the peripheral circuit region PERI, the first cell region CE1, and the second cell region CE2 are stacked in the vertical direction Z. The first memory cell array MCA is located in the first cell region CE1, and the second memory cell array MCB is located in the second cell region CE2. The control circuit CC and the page buffer circuit PBC are located in the peripheral circuit region PERI.

[0038] Each of the first cell region CE1 and the second cell region CE2 includes the main cell region CRA and the bonding pad region BLBP_R. The peripheral circuit region PERI and the first cell region CE1 are bonded to each other at the first bonding interface IF1 by lower bonding pads (BPL1, BPL2), and the first cell region CE1 and the second cell region CE2 are bonded to each other at the second bonding interface IF2 by upper bonding pads (BPU1, BPU2). The upper bonding pads (BPU1, BPU2) are located in the bonding pad region BLBP_R. In some embodiments, the bonding pad region BLBP_R in the memory device 110 may be divided into multiple regions.

[0039] The main cell region CRA of the first cell region CE1 contains a plurality of lower word lines WLA and a lower channel structure CHA that extends vertically in the Z direction through the plurality of lower word lines WLA. Here, the plurality of lower word lines WLA and the lower channel structure CHA are referred to as the first memory cell array MCA. The first memory cell array MCA is electrically connected to the lower bit line BLA.

[0040] The main cell region CRA of the second cell region CE2 contains multiple upper word lines WLB and an upper channel structure CHB that extends vertically in the Z direction through the multiple upper word lines WLB. Here, the multiple upper word lines WLB and the upper channel structure CHB are referred to as the second memory cell array MCB. The second memory cell array MCB is electrically connected to the upper bit line BLB.

[0041] The first memory cell array MCA in the first cell region CE1 is connected to the lower bit line BLA via bit line contact 122A, and the lower bit line BLA is electrically connected to the lower bonding pads (BPL1, BPL2) via the lower connecting line CLA and connecting via 124A. The second memory cell array MCB in the second cell region CE2 is connected to the upper bit line BLB via bit line contact 122B, and the upper bit line BLB is electrically connected to the upper bonding pads (BPU1, BPU2) via connecting via 124B and upper connecting line CLB.

[0042] A lower through-via IOA is located in the bonding pad region BLBP_R of the first cell region CE1. The lower through-via IOA is located vertically in the Z direction, penetrating multiple lower sacrificial layers 132A. The multiple lower sacrificial layers 132A are located at the same vertical level as each of the multiple lower word lines WLA. A lower substrate layer SUBA is located in the main cell region CRA of the first cell region CE1, and the lower substrate layer SUBA is electrically connected to the lower channel structure CHA. The lower substrate layer SUBA does not overlap the bonding pad region BLBP_R perpendicularly.

[0043] An upper through-via IOB is located in the bonding pad region BLBP_R of the second cell region CE2. The upper through-via IOB is located vertically in the Z direction, penetrating multiple upper sacrificial layers 132B. The multiple upper sacrificial layers 132B are located at the same vertical level as each of the multiple upper word lines WLB. An upper substrate layer SUBB is located in the main cell region CRA of the second cell region CE2, and the upper substrate layer SUBB is electrically connected to the upper channel structure CHB. The upper substrate layer SUBB overlaps the bonding pad region BLBP_R perpendicularly. In some embodiments, the upper through-via IOB may not be electrically connected to the upper substrate layer SUBB. In some other embodiments, the upper through-via IOB may be electrically connected to the upper substrate layer SUBB.

[0044] Within the peripheral circuit region PERI, the control circuit CC and the page buffer circuit PBC are arranged on the substrate SUB1. In this embodiment, the page buffer circuit PBC includes a first cell page buffer PB_C1 and a second cell page buffer PB_C2.

[0045] The first cell page buffer PB_C1 represents a page buffer circuit for driving the lower bit line BLA, which is electrically connected to the first memory cell array MCA. The first cell page buffer PB_C1 is electrically connected to the lower bit line BLA via the lower bonding pads (BPL1, BPL2) (and / or via the connecting via 124A and the lower bonding line CLA).

[0046] The second cell page buffer PB_C2 represents a page buffer circuit for driving the upper bit line BLB, which is electrically connected to the second memory cell array MCB. The second cell page buffer PB_C2 is electrically connected to the bypass bit line BB via the lower bonding pads (BPL1, BPL2) (and / or via connecting via 124A and lower connecting line CLA), and is electrically connected to the upper bit line BLB via the lower through-via IOA and upper bonding pads (BPU1, BPU2) (and / or via connecting via 124B and upper connecting line CLB).

[0047] In this embodiment, the distance between the lower bit line BLA in the first cell region CE1 and the peripheral circuit region PERI is shorter than the distance between the first memory cell array MCA and the peripheral circuit region PERI. Also, the distance between the upper bit line BLB in the second cell region CE2 and the peripheral circuit region PERI is shorter than the distance between the second memory cell array MCB and the peripheral circuit region PERI.

[0048] In this embodiment, the front face of the first cell region CE1 is attached to the front face of the peripheral circuit region PERI, and the front face of the second cell region CE2 is attached to the rear face of the first cell region CE1. The front face of the first cell region CE1 and the front face of the peripheral circuit region PERI are in contact with each other at the first bonding interface IF1, and the front face of the second cell region CE2 and the rear face of the first cell region CE1 are in contact with each other at the second bonding interface IF2. Here, the front face of the first cell region CE1 indicates the upper surface of the first cell region CE1 adjacent to the lower bit line BLA, and the rear surface of the first cell region CE1 indicates the bottom surface of the first cell region CE1 adjacent to the lower substrate layer SUBA. Also, the rear surface of the peripheral circuit region PERI indicates the bottom surface of the substrate SUB1, and the front face of the peripheral circuit region PERI indicates the upper surface of the peripheral circuit region PERI located on the opposite side from the substrate SUB1.

[0049] Figure 7 is a schematic diagram showing the bit line linkage structure of the memory device 110 in Figure 5. Figure 8 is a plan layout diagram showing the arrangement of the lower bit lines in Figure 7. Figure 9 is a plan layout diagram showing the arrangement of the upper bit lines in Figure 7.

[0050] Referring to Figures 7 to 9 in conjunction with Figure 6, the lower bit line BLA includes the first to fourth lower bit lines (BL1A, BL2A, BL3A, BL4A), and the upper bit line BLB includes the first to fourth upper bit lines (BL1B, BL2B, BL3B, BL4B). The first to fourth lower bit lines (BL1A, BL2A, BL3A, BL4A) extend in the second horizontal direction Y at the second vertical level LV2, and the first to fourth upper bit lines (BL1B, BL2B, BL3B, BL4B) extend in the second horizontal direction Y at the fourth vertical level LV4, which is higher than the second vertical level LV2.

[0051] In this embodiment, the first lower bit line BL1A includes a first segment SEG1 and a second segment SEG2, which are spaced apart from each other with a line cut region BLCR in between. Each of the first segment SEG1 and the second segment SEG2 extends in the second horizontal direction Y, and the second segment SEG2 is spaced apart from the first segment SEG1 along the second horizontal direction Y and is arranged in a straight line. The line cut region BLCR is located within the bonding pad region BLBP_R and is positioned to overlap the bonding pad region BLBP_R perpendicularly. The first lower bit line BL1A is separated into the first segment SEG1 and the second segment SEG2 by the line cut region BLCR and is here referred to as the "cut bit line".

[0052] In this embodiment, the second to fourth lower bit lines (BL2A, BL3A, BL4A) do not have line cut regions and extend in the second horizontal direction Y at a position that overlaps with the first lower bit line BL1A in the first horizontal direction X. In one embodiment, each of the second to fourth lower bit lines (BL2A, BL3A, BL4A) extends as a single line across the entire bonding pad area BLBP_R. The second to fourth lower bit lines (BL2A, BL3A, BL4A) do not have line cut regions and extend as a single line across the entire bonding pad area BLBP_R and are therefore referred to here as "uncut bit lines" or "normal bit lines".

[0053] In this embodiment, the first to fourth bypass bit lines (BB1, BB2, BB3, BB4) are arranged within the line cut region BLCR, separated from the first lower bit line BL1A. The first to fourth bypass bit lines (BB1, BB2, BB3, BB4) are arranged in a straight line along the second horizontal direction Y, and the first to fourth bypass bit lines (BB1, BB2, BB3, BB4) are arranged in a straight line along the second horizontal direction Y with respect to the two first lower bit lines BL1A. For example, the first to fourth bypass bit lines (BB1, BB2, BB3, BB4) are arranged side by side between the first segment SEG1 and the second segment SEG2. The first to fourth bypass bit lines (BB1, BB2, BB3, BB4) are arranged at the second vertical level LV2 and have upper surfaces that are at the same level as the upper surface of the first lower bit line BL1A.

[0054] In one embodiment, the first to fourth bypass bit lines (BB1, BB2, BB3, BB4) are electrically connected to the first to fourth upper bit lines (BL1B, BL2B, BL3B, BL4B) of the second cell region CE2, respectively. In this embodiment, the second bypass bit line BB2 is electrically connected to the second upper bit line BL2B via the second lower through via IO2A and the second upper connecting line CL2B. In this embodiment, the second upper connecting line CL2B has a first end that contacts the bottom surface of the upper connecting via 124B which extends along the first horizontal direction X at the third vertical level LV3, which is lower than the fourth vertical level LV4, and is connected to the second upper bit line BL2B, and a second end that contacts the top surface of the second lower through via IO2A. As a result, the second upper bit line BL2B and the second bypass bit line BB2, which are spaced apart from each other in the first horizontal direction X, are electrically connected to each other via the upper connecting via 124B, the second upper connecting line CL2B, and the second lower through via IO2A.

[0055] In this embodiment, the second bypass bit line BB2 is electrically connected to the second cell page buffer PB_C2 located within the peripheral circuit region PERI. In this embodiment, as shown in Figure 6, a bit line contact 122A is positioned between the second lower through via IO2A (e.g., lower through via IOA) and the second bypass bit line BB2 (e.g., bypass bit line BB). The bit line contact 122A may be formed as a single layer or may have a structure in which two or more segments are stacked vertically.

[0056] In this embodiment, similar to the second bypass bit line BB2, the third bypass bit line BB3 is electrically connected to the third upper bit line BL3B via the third lower through via IO3A and the third upper connecting line CL3B. The third upper connecting line CL3B extends from the second upper connecting line CL2B in the second horizontal direction Y and in the first horizontal direction X. The third bypass bit line BB3 is electrically connected to the second cell page buffer PB_C2 located within the peripheral circuit region PERI. In this embodiment, similar to the second bypass bit line BB2, the fourth bypass bit line BB4 is electrically connected to the fourth upper bit line BL4B via the fourth lower through via IO4A and the fourth upper connecting line CL4B. The fourth upper connecting line CL4B extends from the third upper connecting line CL3B in the second horizontal direction Y and in the first horizontal direction X. The fourth bypass bit line BB4 is electrically connected to the second cell page buffer PB_C2 located within the peripheral circuit region PERI.

[0057] In this embodiment, the first segment SEG1 and the second segment SEG2 of the first lower bit line BL1A are electrically connected via the lower connecting line CLA. In this embodiment, as shown in Figure 7, the first lower connecting line CL1A is located at the first vertical level LV1, and the first segment SEG1 and the second segment SEG2 are located at the second vertical level LV2, which is higher than the first vertical level LV1. The first lower connecting line CL1A is located spaced apart from the first segment SEG1 and the second segment SEG2 in the first horizontal direction X. The first segment SEG1 and the second segment SEG2 are electrically connected to the first lower connecting line CL1A via connecting vias 124A that contact the bottom surfaces of the first segment SEG1 and the second segment SEG2. As a result, a bypass electrical path is formed from the first segment SEG1 to the second segment SEG2, via the connecting via 124A in contact with the bottom surface of the first segment SEG1, the first lower connecting line CL1A, and the connecting via 124A in contact with the bottom surface of the second segment SEG2.

[0058] In this embodiment, as shown in Figure 8, the first lower connecting line CL1A has a first length L1 in the second horizontal direction Y, and the first length L1 is greater than the length of the line cut region BLCR in the second horizontal direction Y. The first length L1 varies depending on the number of bypass bit lines BB, the spacing between the bypass bit lines BB, and / or the length of each bypass bit line BB in the second horizontal direction Y.

[0059] For example, the memory device 110 described with reference to Figures 5 to 9 illustrates the case where four bypass bit lines BB are arranged within one line cut region BLCR. In this case, the first to fourth lower bit lines (BL1A, BL2A, BL3A, BL4A) constitute a lower bit line unit, and such lower bit line units are repeatedly arranged along the first horizontal direction X. In other words, a line cut region BLCR is formed with one lower bit line BLA corresponding to a total of four upper bit lines BLB, and the bypass bit lines BB corresponding to a total of four upper bit lines BLB are arranged within the line cut region BLCR, which is referred to as a 4:1 bypass bit line matching structure.

[0060] However, in other embodiments, the memory device 110 has an n:1 bypass bit line matching structure, where n can have any value from 2 to 50. For example, when n bypass bit lines BB are arranged within a line cut region BLCR, the first segment SEG1 and the second segment SEG2 of the first lower bit line BL1A are arranged on either side of the n bypass bit lines BB, and n-1 uncut lower bit lines BLA are arranged next to the first lower bit line BL1A, and lower bit line units consisting of the first lower bit line BL1A and n-1 uncut lower bit lines BLA can be repeatedly arranged. In this way, a line cut region BLCR is formed with one lower bit line BLA corresponding to a total of n upper bit lines BLB, and bypass bit lines BB corresponding to a total of n upper bit lines BLB can be arranged within the line cut region BLCR.

[0061] In this embodiment, by arranging n bypass bit lines BB in a row within a single line cut region BLCR, the first length L1 of the first lower connecting line CL1A is relatively small, thereby reducing the area overhead of the bonding pad region BLBP_R, or in other words, enabling efficient design of the area of ​​the bonding pad region BLBP_R.

[0062] In general, in bonding-type memory elements where cell regions and peripheral circuit regions are formed on separate wafers and then bonded together, there is a problem where the length of the routing lines for electrically connecting the bit lines of the cell region and the page buffers of the peripheral circuit region becomes relatively long, resulting in a decrease in element performance. In particular, when bonding two or more cell regions to improve integration density, even if the bit lines of one layer are connected to the peripheral circuit via through vias, the bit lines of two layers require routing lines to be designed through the edge region around the cell array, which leads to a problem of access speed differences between single-layer cells and two-layer cells.

[0063] However, according to this embodiment, the lower bit line BLA of the first cell region CE1 and the upper bit line BLB of the second cell region CE2 can be connected to the peripheral circuit via the lower through-via IOA in the bonding pad region BLBP_R, thereby reducing and / or preventing the access speed deviation between the first memory cell array MCA of the first cell region CE1 and the second memory cell array MCB of the second cell region MC2.

[0064] Furthermore, since multiple bypass bit lines BB are sequentially spaced apart between the first segment SEG1 and the second segment SEG2 of the first lower bit line BL1A, the length of the first lower connecting line CL1A is relatively short, thereby enabling efficient design of the bonding pad area BLBP_R.

[0065] Figure 10 shows a second example of a memory device 120 according to one embodiment. Figure 11 is a schematic diagram showing the bit line linkage structure of the memory device 120 in Figure 10. Figure 12 is a plan layout diagram showing the arrangement of the lower bit lines in Figure 11. Figure 13 is a plan layout diagram showing the arrangement of the upper bit lines in Figure 11.

[0066] Referring to Figures 10 to 13, the peripheral circuit region PERI, the first cell region CE1, and the second cell region CE2 are stacked in the vertical direction Z in order. In this embodiment, the rear face of the first cell region CE1 is attached to the front face of the peripheral circuit region PERI, and the rear face of the second cell region CE2 is attached to the front face of the first cell region CE1. The first memory cell array MCA is placed in the first cell region CE1, and the second memory cell array MCB is placed in the second cell region CE2.

[0067] In this embodiment, the distance between the lower bit line BLA of the first cell region CE1 and the peripheral circuit region PERI is greater than the distance between the first memory cell array MCA and the peripheral circuit region PERI. Also, the distance between the upper bit line BLB of the second cell region CE2 and the peripheral circuit region PERI is greater than the distance between the second memory cell array MCB and the peripheral circuit region PERI.

[0068] The first memory cell array MCA in the first cell region CE1 is connected to the lower bit line BLA via bit line contact 122A. The lower bit line BLA is located at the first vertical level LV1 and is electrically connected to the lower bonding pads (BPL1, BPL2) via lower through via IOA. The lower bit line BLA is electrically connected to the lower bonding line CLA, which is located at the second vertical level LV2, higher than the first vertical level LV1.

[0069] The second memory cell array MCB in the second cell region CE2 is connected to the upper bit line BLB via bit line contact 122B. The upper bit line BLB is located at the third vertical level LV3 and is electrically connected to the upper bonding pads (BPU1, BPU2) via upper through via IOB.

[0070] The first cell page buffer PB_C1 is electrically connected to the lower bit line BLA via the lower bonding pads (BPL1, BPL2) (and / or via the lower through via IOA and lower connecting line CLA). The second cell page buffer PB_C2 is electrically connected to the lower bypass bit line BBA via the lower bonding pads (BPL1, BPL2) (and / or via the lower through via IOA and lower connecting line CLA), and is electrically connected to the upper bit line BLB via the upper bonding pads (BPU1, BPU2) (and / or via the upper through via IOB and upper connecting line CLB). A portion of the upper bit line BLB is electrically connected to the upper through via IOB via the upper bypass bit line BBB and upper connecting line CLB.

[0071] In this embodiment, the lower bit line BLA includes the first to fourth lower bit lines (BL1A, BL2A, BL3A, BL4A), and the upper bit line BLB includes the first to fourth upper bit lines (BL1B, BL2B, BL3B, BL4B). The first to fourth lower bit lines (BL1A, BL2A, BL3A, BL4A) extend in the second horizontal direction Y at the first vertical level LV1, and the first to fourth upper bit lines (BL1B, BL2B, BL3B, BL4B) extend in the second horizontal direction Y at the third vertical level LV3, which is higher than the first vertical level LV1.

[0072] In one embodiment, the first lower bit line BL1A includes a first segment SEG1 and a second segment SEG2, which are spaced apart from each other with a line cut region BLCR in between. Each of the first segment SEG1 and the second segment SEG2 extends in a second horizontal direction Y, and the second segment SEG2 is spaced apart from the first segment SEG1 along the second horizontal direction Y and is arranged in a straight line.

[0073] In one embodiment, no line cut regions are provided in the second to fourth lower bit lines (BL2A, BL3A, BL4A), and each of the second to fourth lower bit lines (BL2A, BL3A, BL4A) extends as a single line across the entire bonding pad region BLBP_R.

[0074] In this embodiment, the first to fourth lower bypass bit lines (BB1A, BB2A, BB3A, BB4A) are arranged within the line cut region BLCR, separated from the first lower bit line BL1A. The first to fourth lower bypass bit lines (BB1A, BB2A, BB3A, BB4A) are arranged in a straight line along the second horizontal direction Y. The first to fourth lower bypass bit lines (BB1A, BB2A, BB3A, BB4A) are arranged at the first vertical level LV1 and have upper surfaces that are at the same level as the upper surface of the first lower bit line BL1A.

[0075] In this embodiment, the first segment SEG1 and the second segment SEG2 of the first lower bit line BL1A are electrically connected via the lower connecting line CLA. In this embodiment, as shown in Figure 11, the first lower connecting line CL1A is positioned at a second vertical level LV2 which is higher than the first vertical level LV1 of the first segment SEG1 and the second segment SEG2.

[0076] In this embodiment, the first upper bit line BL1B includes a first segment SEG1 and a second segment SEG2, which are spaced apart from each other with a line cut region BLCR in between. Each of the first segment SEG1 and the second segment SEG2 of the first upper bit line BL1B extends in the second horizontal direction Y, and the second segment SEG2 is spaced apart from the first segment SEG1 along the second horizontal direction Y and is arranged in a straight line.

[0077] In this embodiment, the second to fourth upper bypass bit lines (BB2B, BB3B, BB4B) are arranged within the line cut region BLCR, separated from the first upper bit line BL1B. The second to fourth upper bypass bit lines (BB2B, BB3B, BB4B) are arranged in a straight line along the second horizontal direction Y. The second to fourth upper bypass bit lines (BB2B, BB3B, BB4B) are located at the third vertical level LV3 and have upper surfaces that are at the same level as the upper surface of the first upper bit line BL1B.

[0078] In this embodiment, the second upper bit line BL2B is electrically connected to the second upper bypass bit line BB2B via the second upper connecting line CL2B, the third upper bit line BL3B is electrically connected to the third upper bypass bit line BB3B via the third upper connecting line CL3B, and the fourth upper bit line BL4B is electrically connected to the fourth upper bypass bit line BB4B via the fourth upper connecting line CL4B. The first segment SEG1 and the second segment SEG2 of the first upper bit line BL1B are electrically connected via the first upper connecting line CL1B. In this embodiment, as shown in Figure 11, the first to fourth upper connecting lines (CL1B, CL2B, CL3B, CL4B) are positioned at a fourth vertical level LV4, which is higher than the third vertical level LV3 of the first segment SEG1 and the second segment SEG2.

[0079] In this embodiment, the second to fourth upper bypass bit lines (BB2B, BB3B, BB4B) are positioned to overlap perpendicularly with each of the second to fourth lower bypass bit lines (BB2A, BB3A, BB4A), perpendicularly with each of the second to fourth lower through vias (IO2A, IO3A, IO4A), and perpendicularly with each of the second to fourth upper through vias (IO2B, IO3B, IO4B).

[0080] In this embodiment, the second upper bit line BL2B is electrically connected to the second cell page buffer PB_C2 located within the peripheral circuit region PERI via the second upper bypass bit line BB2B, the second upper through via IO2B, the second lower bypass bit line BB2A, and the second lower through via IO2A. This provides a relatively short electrical path from the second upper bit line BL2B to the second cell page buffer PB_C2.

[0081] Furthermore, similar to the second upper bit line BL2B, the third upper bit line BL3B is electrically connected to the second cell page buffer PB_C2 located in the peripheral circuit region PER via the third upper bypass bit line BB3B, the third upper through via IO3B, the third lower bypass bit line BB3A, and the third lower through via IO3A. Similarly, the fourth upper bit line BL4B is electrically connected to the second cell page buffer PB_C2 located in the peripheral circuit region PEI via the fourth upper bypass bit line BB4B, the fourth upper through via IO4B, the fourth lower bypass bit line BB4A, and the fourth lower through via IO4A.

[0082] Figure 14 shows a third example of a memory device 130 according to one embodiment. Figure 15 is a schematic diagram showing the bit line linkage structure of the memory device 130 in Figure 14. Figure 16 is a plan layout diagram showing the arrangement of the lower bit lines in Figure 14. Figure 17 is a plan layout diagram showing the arrangement of the upper bit lines in Figure 14.

[0083] Referring to Figures 14 to 17, the peripheral circuit region PERI, the first cell region CE1, and the second cell region CE2 are stacked in order in the vertical direction Z. In this embodiment, the back of the first cell region CE1 is attached to the front of the peripheral circuit region PERI, and the back of the second cell region CE2 is attached to the front of the first cell region CE1. The first memory cell array MCA is placed in the first cell region CE1, and the second memory cell array MCB is placed in the second cell region CE2.

[0084] The first memory cell array MCA within the first cell region CE1 is connected to the lower bit line BLA via bit line contact 122A. The lower bit line BLA is located at the second vertical level LV2 and is electrically connected to the lower bonding pads (BPL1, BPL2) via lower through via IOA. The lower bit line BLA is electrically connected to the lower bonding line CLA located at the first vertical level LV1, which is lower than the second vertical level LV2.

[0085] The second memory cell array MCB in the second cell region CE2 is connected to the upper bit line BLB via bit line contact 122B. The upper bit line BLB is located at the fourth vertical level LV4 and is electrically connected to the upper bonding line CLB located at the third vertical level LV3, which is lower than the fourth vertical level LV4. The upper bonding line CLB is electrically connected to the bypass bit line BB of the first cell region CE1 via upper through-via IOB. In this embodiment, the upper bit line BLB is electrically connected to the second cell page buffer PB_C2 located in the peripheral circuit region PER2 via the upper bonding line CLB, upper through-via IOB, upper bonding pads (BPU1, BPU2), bypass bit line BB, lower through-via IOA, and lower bonding pads (BPL1, BPL2).

[0086] Figures 14 and 15 exemplify a configuration in which the upper connecting line CLB is positioned at a higher vertical level than the upper through-via IOB and is located on the upper surface of the upper through-via IOB. In other embodiments, the upper connecting line CLB may be positioned at a lower vertical level than the upper through-via IOB, for example, the upper connecting line CLB may be connected to the bottom surface of the upper through-via IOB. In this case, the upper bit line BLB may be electrically connected to a second cell page buffer PB_C2 located in the peripheral circuit region PERI via the upper through-via IOB, the upper connecting line CLB, upper bonding pads (BPU1, BPU2), bypass bit line BB, lower through-via IOA, and lower bonding pads (BPL1, BPL2).

[0087] Figure 18 shows a fourth example of a memory device 140 according to one embodiment. Figure 19 is a schematic diagram showing the bit line concatenation structure of the memory device 140 in Figure 18.

[0088] Referring to Figures 18 and 19, the second cell region CE2, the first cell region CE1, and the peripheral circuit region PERI are stacked in order in the vertical direction Z. In this embodiment, the back of the first cell region CE1 is mounted on the front of the second cell region CE2, and the front of the peripheral circuit region PERI is mounted on the front of the first cell region CE1. The first memory cell array MCA is placed in the first cell region CE1, and the second memory cell array MCB is placed in the second cell region CE2.

[0089] In this embodiment, the second cell region CE2 includes the upper bit line BLB, and the first cell region CE1 includes the lower bit line BLA. The lower bit line BLA is positioned at a higher vertical level than the upper bit line BLB, and the vertical distance between the lower bit line BLA and the peripheral circuit region PERI is shorter than the vertical distance between the upper bit line BLB and the peripheral circuit region PERI.

[0090] Except for the fact that the stacking order of the second cell area CE2, the first cell area CE1, and the peripheral circuit area PERI in the memory device 140 described with reference to Figures 18 and 19 is the opposite of the stacking order of the second cell area CE2, the first cell area CE1, and the peripheral circuit area PERI in the memory device 110 described with reference to Figures 5 to 9, the memory device 140 has the same technical characteristics as the memory device 110 described with reference to Figures 5 to 9, so a detailed explanation is omitted here.

[0091] Figure 20 shows a fifth example of a memory device 150 according to one embodiment. Figure 21 is a schematic diagram showing the bit line linking structure of the memory device 150 in Figure 20.

[0092] Referring to Figures 20 and 21, the second cell region CE2, the first cell region CE1, and the peripheral circuit region PERI are stacked in order in the vertical direction Z. In this embodiment, the front of the first cell region CE1 is mounted on the back of the second cell region CE2, and the front of the peripheral circuit region PERI is mounted on the back of the first cell region CE1. The first memory cell array MCA is placed in the first cell region CE1, and the second memory cell array MCB is placed in the second cell region CE2.

[0093] Except for the fact that the stacking order of the second cell area CE2, the first cell area CE1, and the peripheral circuit area PERI in the memory device 150, as described with reference to Figures 20 and 21, is the opposite of the stacking order of the second cell area CE2, the first cell area CE1, and the peripheral circuit area PERI in the memory device 120, as described with reference to Figures 10 to 13, the memory device 150 has the same technical characteristics as the memory device 120, as described with reference to Figures 10 to 13, so a detailed explanation is omitted here.

[0094] According to the embodiment described above, the bit lines of the first cell region and the bit lines of the second cell region can be connected to peripheral circuits via through vias in the bonding pad region, thereby reducing and / or preventing access speed deviations between the first memory cell array of the first cell region and the second memory cell array of the second cell region. Furthermore, the length of the connecting lines that link the segments of the lower bit lines is relatively short, which enables efficient design of the bonding pad region area.

[0095] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of Symbols]

[0096] 10, 100, 110, 120, 130, 140, 150 memory devices 11 memory cell array 12 Page Buffer Circuit 13 Control Logic Circuits 14 Voltage Generator 15 Raw Decoder 122A, 122B bit line contacts 124A, 124B connecting vias 132A, 132B Lower and Upper Sacrificial Layers ADDR address BB Bypass Bit Line BB1-BB4 1st-4th Bypass Bit Lines BB1A~BB4A 1st~4th Lower Bypass Bit Lines BB2B~BB4B 2nd~4th Upper Bypass Bit Line BBA, BBB lower, upper bypass bit lines BL Bitline BL1~BL3 1st~3rd bit lines BL1A~BL4A 1st~4th lower bit lines BL1B~BL4B 1st~4th Upper Bit Lines BLA, BLB lower and upper bit lines BLBP Bit Line Pad BLBP_R Bonding Pad Area BLCR line cut area BLK1~BLKz memory blocks BPL1, BPL2 Lower Bonding Pads BPU1, BPU2 Upper Bonding Pad CC control circuit CE1, CE2: First and second cell regions CHA, CHB lower and upper channel structures CL Control Logic Circuit Area CL1A First Lower Connecting Line CL1B~CL4B 1st~4th Upper Connecting Line CLA, CLB lower and upper connecting lines CMD command CR cell area CRA Main Cell Area CSL Common Sourceline CSLBP Common Source Line Pad CTRL control signal CTRL_vol Voltage control signal DATA GSL, GSL1-GSL3 Ground Selection Line GST Ground Select Transistor IF1, IF2: First and second bonding interfaces IOA, IOB lower, upper through vias IO1A~IO4A: 1st to 4th lower through vias IO1B~IO4B: 1st to 4th upper through vias LV1~LV4 1st~4th Vertical Levels MCA, MCB 1st and 2nd memory cell arrays MCA1A~MCA4A 1st~4th Lower Memory Mat MCA1B~MCA4B 1st~4th Upper Memory Mat MCs memory cells MTC1A, MTC1B 1st lower and upper memory mats MTP1 First Peripheral Circuit Mat NS11~NS13, NS21~NS23, NS31~NS33 NAND strings PA pad area PAD PB Page Buffer PB_C1, PB_C2: First and second cell page buffers PBC (Page Buffer Circuit) PBD Page Buffer Driver PERI Peripheral Circuit Region PGBUF Page Buffer Circuit Area PRCT Peripheral Circuits PRCT1~PRCTT4 1st~4th Peripheral Circuit Mat SEG1, SEG2: First and second segments SR1, SR2 consolidated area SSL, SSL1~SSL3 String Selection Line SUB1 board SUBA, SUBB lower and upper substrate layers VWL Word Line Voltage VY control voltage WL Wardline WLA, WLB lower and upper wardlines WLBP Wordline Pad X_ADDR row address XD1, XD2 Low Decoder Area Y_ADDR column address Y_DATA Internally processed data

Claims

1. Peripheral circuit region and A first cell region, which includes multiple lower bit lines and multiple bypass bit lines and is located at a different vertical level from the peripheral circuit region, A second cell region including a plurality of upper bit lines electrically connected to the plurality of bypass bit lines, The aforementioned multiple lower bit lines are, A first lower bit line including a first segment and a second segment arranged spaced apart from each other with a line cut region in between, The first lower bit line includes a second lower bit line that is spaced apart from the first lower bit line in a first horizontal direction and extends in a second horizontal direction, The plurality of bypass bit lines include a first cell region that is spaced apart in the second horizontal direction within the line cut region, A memory device characterized in that the first cell region is arranged between the peripheral circuit region and the second cell region.

2. The memory device according to claim 1, characterized in that the plurality of bypass bit lines are arranged between the first segment and the second segment of the first lower bit line.

3. The memory device according to claim 1, characterized in that the plurality of bypass bit lines are arranged in a straight line with the first segment of the first lower bit line.

4. The memory device according to claim 1, wherein the first cell region is arranged to be separated from the first segment and the second segment in a first horizontal direction and further includes a lower connecting line which includes a portion that electrically connects the first segment and the second segment.

5. The lower connecting line has a first length in the second horizontal direction, The memory device according to claim 4, characterized in that the first length is greater than the second horizontal length of the line cut region.

6. The aforementioned first cell region is, Multiple word lines arranged vertically apart within the main cell area, Within the main cell region, there are a plurality of channel structures that extend vertically and penetrate the plurality of word lines, Multiple sacrificial layers arranged vertically apart within the bonding pad region, The bonding pad region includes a plurality of through vias extending vertically and penetrating the plurality of sacrificial layers, The memory device according to claim 1, characterized in that the plurality of through vias are electrically connected to each of the plurality of bypass bit lines.

7. The aforementioned peripheral circuit region is circuit board and A first cell page buffer disposed on the substrate, The substrate includes a second cell page buffer disposed on the substrate, The memory device according to claim 6, characterized in that the plurality of upper bit lines are electrically connected to the second cell page buffer via the plurality of bypass bit lines and the plurality of through vias.

8. The second cell region further includes a plurality of upper connecting lines that are electrically connected to the plurality of upper bit lines and extend in the first horizontal direction, The memory device according to claim 6, characterized in that the plurality of upper connecting lines are arranged at a different vertical level from the plurality of upper bit lines.

9. The number of bypass bit lines arranged in the line cut region is n. The number of the aforementioned upper bit lines is n. The memory device according to claim 1, characterized in that n is a natural number of 2 or more.

10. The memory device according to claim 9, characterized in that n is a natural number in the range of 2 to 50.

11. The lower bit line unit includes the first lower bit line and one or more second lower bit lines. The upper bit line unit includes the plurality of upper bit lines, The memory device according to claim 9, characterized in that the lower bit line unit and the upper bit line are repeatedly arranged along the first horizontal direction.

12. Peripheral circuit region and A first cell region is arranged on the peripheral circuit region and includes a plurality of lower bit lines and a plurality of bypass bit lines, A second cell region is provided on the first cell region and includes a plurality of upper bit lines that are electrically connected to the plurality of bypass bit lines, The aforementioned multiple lower bit lines are, A cut lower bit line including a first segment and a second segment arranged spaced apart from each other with a line cut region in between, It includes one or more normal bit lines that are separated in a first horizontal direction from the cut lower bit line and extend in a second horizontal direction, The memory device is characterized in that the plurality of bypass bit lines include a first cell region that is spaced apart in the second horizontal direction within the line cut region.

13. The number of bypass bit lines arranged within the line cut region is n. The number of the aforementioned upper bit lines is n. The memory device according to claim 12, characterized in that n is a natural number of 2 or more.

14. The memory device according to claim 13, characterized in that n is a natural number in the range of 2 to 50.

15. The aforementioned first cell region is, Multiple word lines arranged vertically apart within the main cell area, Within the main cell region, there are a plurality of channel structures that extend vertically and penetrate the plurality of word lines, Multiple sacrificial layers arranged vertically apart within the bonding pad region, The bonding pad region includes a plurality of through vias extending vertically and penetrating the plurality of sacrificial layers, The memory device according to claim 12, characterized in that the plurality of through vias are electrically connected to each of the plurality of bypass bit lines.

16. The memory device according to claim 15, characterized in that the line cut region is arranged to overlap perpendicularly with the bonding pad region.

17. The aforementioned peripheral circuit region is circuit board and A first cell page buffer disposed on the substrate, The substrate includes a second cell page buffer disposed on the substrate, The memory device according to claim 15, characterized in that the plurality of upper bit lines are electrically connected to the second cell page buffer via the plurality of bypass bit lines and the plurality of through vias.

18. The first cell region is positioned at a first horizontal distance from the first segment and the second segment, and further comprises a lower connecting line that electrically connects the first segment and the second segment. The second cell region further includes a plurality of upper connecting lines that are electrically connected to the plurality of upper bit lines and extend in the first horizontal direction, The plurality of lower connecting lines are arranged at a different vertical level from the plurality of lower bit lines. The memory device according to claim 15, characterized in that the plurality of upper connecting lines are arranged at a different vertical level from the plurality of upper bit lines.

19. Peripheral circuit region and A first cell region is arranged on the peripheral circuit region and includes multiple lower bit lines, multiple bypass bit lines, and lower connecting lines, A second cell region is provided on the first cell region and includes a plurality of upper bit lines that are electrically connected to the plurality of bypass bit lines, The aforementioned multiple lower bit lines are, A cut lower bit line including a first segment and a second segment arranged spaced apart from each other with a line cut region in between, It includes one or more normal bit lines that are separated in a first horizontal direction from the cut lower bit line and extend in a second horizontal direction, The plurality of bypass bit lines are arranged within the line cut region, separated by the second horizontal direction. The memory device is characterized in that the lower connecting line is arranged to be separated from the first segment and the second segment in the first horizontal direction and includes a first cell region which includes a part that electrically connects the first segment and the second segment.

20. The peripheral circuit region includes a first cell page buffer and a second cell page buffer, The plurality of lower bit lines are electrically connected to the first cell page buffer, The memory device according to claim 19, characterized in that the plurality of upper bit lines are electrically connected to the second cell page buffer via the plurality of bypass bit lines.

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