Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can improve the warping of an insulating substrate. [Solution] The semiconductor device of the present disclosure comprises an insulating substrate having an insulating layer having a first main surface and a second main surface which is the surface opposite to the first main surface, a first metal layer bonded to the first main surface, and a second metal layer bonded to the second main surface, and a chip bonded to the surface of the second metal layer opposite to the surface bonded to the insulating substrate, wherein the first metal layer has a region in which the size of the grain boundary on the surface opposite to the surface bonded to the insulating substrate in the first metal layer is smaller than the size of the grain boundary on the surface opposite to the surface bonded to the insulating substrate in the second metal layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In a substrate having metal layers on both sides of an insulating substrate, such as an ALN (Aluminum Nitride) or Si3N4 (Silicon Nitride) ceramic used for a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazed) substrate with copper plate patterns arranged on the upper and lower surfaces, in a semiconductor device using such a substrate, when wiring is performed with other metals such as Al (aluminum) or Cu (copper) for chip mounting, pattern etching is performed on the metal layer to achieve the circuit function. Due to the area difference and volume difference between the back and front metal layers, warping occurs in the substrate. Also, due to die bonding, warping occurs in the substrate due to the difference in the linear expansion coefficients of the ceramic and the metal layer. Due to these warping problems of the substrate, there are issues such as unstable mounting on the base plate for mounting the substrate, and when the substrate is sealed by transfer molding or the like, the resin for sealing creeps in due to the influence of warping, resulting in resin burrs on the back surface, and problems such as burr removal and additional operations have occurred. Therefore, a structure that does not intentionally use an insulating substrate has sometimes been adopted. (Patent Document 1) [[ID=】

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Conventional techniques involve etching the metal layer to form circuit patterns on an insulating substrate. Etching the metal layer results in differences in area, volume, and pattern between the upper and lower metal layers, causing an imbalance in thermal stress between the upper and lower parts of the substrate. This imbalance in thermal stress can cause warping of the insulating substrate during the die-bonding process of semiconductor device assembly. This warping of the insulating substrate during assembly can lead to problems such as the formation of resin burrs on the back of the substrate during the molding process.

[0005] Therefore, the present disclosure aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve the warping of an insulating substrate. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure comprises an insulating substrate having an insulating layer having a first main surface and a second main surface which is the surface opposite to the first main surface, a first metal layer bonded to the first main surface, and a second metal layer bonded to the second main surface, and a chip bonded to the opposite side of the substrate bonding surface of the second metal layer opposite to the substrate bonding surface which is bonded to the insulating substrate, wherein the first metal layer has a region in which the size of the grain boundary on the opposite side of the substrate bonding surface opposite to the substrate bonding surface which is bonded to the insulating substrate is smaller than the size of the grain boundary on the opposite side of the substrate bonding surface of the second metal layer.

[0007] The semiconductor device of the present disclosure comprises an insulating substrate having an insulating layer having a first main surface and a second main surface which is the surface opposite to the first main surface, a first metal layer bonded to the first main surface, and a second metal layer bonded to the second main surface, and a chip bonded to the substrate bonding opposite surface of the second metal layer opposite to the substrate bonding surface which is bonded to the insulating substrate, wherein the first metal layer has a region in which the size of the grain boundary on the substrate bonding opposite surface of the first metal layer opposite to the substrate bonding surface which is bonded to the insulating substrate is smaller than the size of the grain boundary on the substrate bonding surface of the first metal layer.

[0008] The present disclosure's method for manufacturing a semiconductor device comprises a preparation step of preparing an insulating substrate having an insulating layer having a first main surface and a second main surface which is the surface opposite to the first main surface, a first metal layer bonded to the first main surface, and a second metal layer bonded to the second main surface, and a chip; a die bonding step of die bonding the chip to the opposite side of the substrate bonding surface on the second metal layer that is bonded to the insulating substrate; and a peening step of performing peening on a portion of the first metal layer that includes at least the opposite side of the substrate bonding surface on the surface opposite to the substrate bonding surface that is bonded to the insulating substrate. [Effects of the Invention]

[0009] The semiconductor device of this disclosure has a region with smaller grain boundaries on the opposite side of the substrate bonding of the first metal layer to the substrate than the opposite side of the substrate bonding of the second metal layer to which the chip is bonded. As a result, the opposite side of the substrate bonding of the first metal layer is stretched more than the opposite side of the substrate bonding of the second metal layer, and the concave warping of the first metal layer of the insulating substrate can be reduced.

[0010] The semiconductor device of this disclosure has a region in which the grain boundary on the opposite side of the substrate bonding is smaller than the grain boundary on the substrate bonding surface of the first metal layer. As a result, the opposite side of the substrate bonding of the first metal layer is stretched more than the substrate bonding surface of the first metal layer, and the concave warping of the first metal layer of the insulating substrate can be reduced.

[0011] The semiconductor device manufacturing method of this disclosure can reduce grain boundaries on the substrate-opposite side of the first metal layer by performing a peening treatment on the substrate-opposite side of the first metal layer, thereby stretching the substrate-opposite side of the first metal layer. By performing a peening treatment on the substrate-opposite side of the first metal layer after die bonding, when the warpage is at its maximum, the convex warpage on the second metal layer side of the insulating substrate can be reduced. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic cross-sectional view of a semiconductor device with exaggerated curvature in a comparative example of Embodiment 1. [Figure 2] This is a cross-sectional view of a schematic semiconductor device after the die bonding process, with exaggerated warping, in a comparative example of Embodiment 1. [Figure 3] This is a schematic oblique view of a semiconductor device after the die bonding process, with warping exaggerated, in a comparative example of Embodiment 1. [Figure 4] This is a rear view of the semiconductor device in a comparative example of Embodiment 1. [Figure 5] This is a cross-sectional view of the semiconductor device in Embodiment 1 after the peening process. [Figure 6] This is a cross-sectional view of the semiconductor device in Embodiment 1. [Figure 7] This is a cross-sectional view showing the peening process of the manufacturing method in Embodiment 1. [Figure 8] This is a process flow diagram of the manufacturing method in Embodiment 1. [Figure 9] This is a process flow diagram of the manufacturing method in Embodiment 2. [Modes for carrying out the invention]

[0013] 1. Embodiment 1 A semiconductor device according to Embodiment 1 will be described with reference to the drawings. Figure 1 is a schematic cross-sectional view of a comparative example of Embodiment 1 with exaggerated warping. Figure 2 is a cross-sectional view of a schematic semiconductor device according to a comparative example of Embodiment 1 with exaggerated warping after the die bonding process. Figure 3 is an oblique view of a schematic semiconductor device according to a comparative example of Embodiment 1 with exaggerated warping after the die bonding process. Figure 4 is a back view of the semiconductor device according to a comparative example of Embodiment 1. Figure 5 is a cross-sectional view of the semiconductor device according to Embodiment 1 after the peening process. Figure 6 is a cross-sectional view of the semiconductor device according to Embodiment 1. Figure 7 is a cross-sectional view showing the peening process of the manufacturing method of the semiconductor device according to Embodiment 1.

[0014] 1-1. Configuration of Semiconductor Devices The semiconductor device of this embodiment includes an insulating layer 3 having a first main surface and a second main surface opposite to the first main surface, a first metal layer 21 joined to the first main surface, and a second metal layer 22 joined to the second main surface. It further includes an insulating substrate 1 having these components, and a chip 4 joined to the opposite side of the substrate joining surface of the second metal layer 22 that is joined to the insulating substrate 1. In this embodiment, the first metal layer 21 has a region where the size of the grain boundary 10 on the opposite side of the substrate joining surface of the first metal layer 21 that is joined to the insulating substrate 1 is smaller than the size of the grain boundary 10 on the opposite side of the substrate joining surface of the second metal layer 22 that is joined to the insulating substrate 1.

[0015] <Insulating substrate 1> In the insulating substrate 1 of this embodiment, a semiconductor chip 4 is joined to one side surface, and the material is composed of ceramic, resin, etc. For the joining of the insulating substrate 1 and the semiconductor chip 4, a joining material b11 such as a brazing material or solder is used. A circuit pattern is formed on the second metal layer 22. For example, the circuit pattern is created by etching a material such as copper which is the material of the second metal layer 22.

[0016] In this embodiment, the insulating substrate 1 is composed of a metal layer and an insulating layer 3. The insulating substrate 1 is laminated in the order of the first metal layer 21, the insulating layer 3, and the second metal layer 22, with the insulating layer 3 sandwiched between the two metal layers. As described above, the metal layer is mainly formed of copper as the material and constitutes a circuit pattern. The insulating layer 3 is formed of an insulating ceramic material such as alumina. By sandwiching an insulator between the two types of metal layers, the respective electric circuits formed by the two types of circuit boards do not interfere with each other, and short circuits and electrical problems can be prevented.

[0017] As described above, the joining material b11 is provided on both surfaces of the insulating layer 3 (the substrate joining surface of the first metal layer 21 and the substrate joining surface of the second metal layer 22). The joining material b11 mainly uses a brazing material, but a sintered material using a metal paste such as solder or silver paste may also be used.

[0018] In this embodiment, the second metal layer 22 is provided with a chip 4 bonded to the opposite side of the substrate bonding surface from the substrate bonding surface that is bonded to the insulating substrate 1. That is, the semiconductor chip 4 or capacitor chip 4, etc., is attached to the substrate bonding surface of the second metal layer 22 via a bonding material a5. In the semiconductor device, a heat sink is attached to the opposite side from where the semiconductor chip 4, etc., is attached.

[0019] <Tip 4> In this embodiment, chip 4 is bonded to the substrate opposite the second metal layer 22 having a circuit pattern. The semiconductor chip 4 can be an IGBT (Insulated Gate Bipolar Transistor) or the like. IGBTs are used for high-voltage, high-current switching and are utilized in motor control and inverter circuits. The type of semiconductor chip 4 may be not limited to IGBTs, but may also be a diode, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or other types.

[0020] The semiconductor chip 4 is connected to the electrode terminals 6 using bonding wires 7. For example, copper or aluminum can be used for the bonding wires 7.

[0021] The semiconductor chip 4 is bonded to the substrate opposite side of the second metal layer 22. In this embodiment, the semiconductor chip 4 is attached to the substrate opposite side of the second metal layer 22 via a bonding material a5.

[0022] One end of a bonding wire 7 is bonded to the side of the semiconductor chip 4 opposite to the second metal layer 22. The other end of the bonding wire 7 is bonded to an external terminal. The semiconductor chip 4 is electrically connected to the outside world by the bonding wire 7 being bonded to the external terminal.

[0023] <Other components of the semiconductor device> As described above, one end of a bonding wire 7 is attached to a portion of the substrate-opposite side of the second metal layer 22 to which the semiconductor chip 4 is bonded. The other end of the bonding wire 7 is connected to one end of the electrode 6. The semiconductor chip 4 is connected to the electrode 6, which is an external terminal, via the bonding wire 7. The external terminal extends outside the encapsulating material 8, and the other end of the external terminal is exposed to the outside from the encapsulating material 8. The external terminal, which is exposed to the outside, can come into contact with other components, thereby enabling connection to external components.

[0024] In this embodiment, the semiconductor device is filled with a sealing material 8 so as to cover the entire chip 4, insulating substrate 1, and bonding wire 7 in order to protect the chip 4, insulating substrate 1, etc.

[0025] <First metal layer 21> As described above, in the insulating substrate 1 used in semiconductor devices and the like, metal layers such as copper or aluminum are bonded to both sides of an insulating layer 3, such as ceramic, by a bonding material b11 such as brazing material.

[0026] As shown in Figures 1 to 3, the first metal layer 21 described in the comparative example of this embodiment is bonded to the other side of the insulating layer 3. The first metal layer 21 has a curve on the side opposite to the substrate bond. The first metal layer 21 is mainly made of copper or aluminum. In the comparative example of this embodiment, the curve of the first metal layer 21 is a concave curve in which the protrusion height decreases as it approaches the center.

[0027] <Second metal layer 22> As described above, a circuit pattern is formed on the second metal layer 22 to which the chip 4 or wiring is bonded by etching or other means. Therefore, the balance of the area or volume of the metal layer changes between the front and back of the insulating substrate 1, which generally causes the substrate to warp. The side of the second metal layer 22 that has been partially removed by etching or other means extends, causing the side of the insulating substrate 1 with the second metal layer 22 to warp convexly, with the protrusion height increasing as it approaches the center, while the side of the insulating substrate 1 with the first metal layer 21 to warp concavely, with the protrusion height decreasing as it approaches the center.

[0028] Furthermore, in addition to simple warping, depending on the etching pattern, the insulating substrate 1 may deform in a twisted manner. This phenomenon is thought to be caused by two factors: the layering of materials with different coefficients of thermal expansion, and the disruption of the balance between the volume and area of ​​the metal layer of the insulating substrate 1 due to etching and other processes.

[0029] In this embodiment, a circuit pattern is formed on the second metal layer 22 to which the chip 4 is bonded, but not on the first metal layer 21. Therefore, etching or other processes performed only on the second metal layer 22 disrupt the balance of volume and area of ​​the metal layers on both sides of the insulating substrate 1. This disrupts the balance of thermal stress, causing warping or twisting of the insulating substrate 1.

[0030] Furthermore, in this embodiment, materials with different coefficients of linear expansion, such as copper for the metal layer and ceramic for the insulating layer 3, are laminated. When materials with different coefficients of linear expansion are joined at high temperatures and then cooled, thermal stress is generated as a physical phenomenon. If the metal layers of the insulating substrate 1 on both sides are balanced in terms of area and volume, the thermal stress is balanced and warping does not occur.

[0031] For example, the coefficient of thermal expansion of Si3N4 (silicon idride) used in insulating layer 3 is approximately 2.8 × 10⁻⁶. ‐6 The temperature is / ℃, and copper plates used in metal layers are approximately 16.5 × 10 ‐6 The temperature is / °C. Because there is a difference of more than 5 times in the coefficient of linear expansion between the insulating layer 3 and the metal layer, warping occurs in the comparative example of Embodiment 1, as shown in Figures 1 to 3.

[0032] Furthermore, after the die bonding process, the chip 4 is bonded to the insulating substrate 1. The coefficient of thermal expansion of the chip 4 is approximately 2.6 × 10⁻⁶. -6 Because the temperature is around / ℃, the semiconductor device of this disclosure will have a convex warp in the second metal layer 22 to which the chip 4 is bonded, and the amount of warping will increase even further.

[0033] When a semiconductor device is assembled while it is warped, stress is generated in the bonding material a5, which is the die bond material, due to the warping of the insulating substrate 1.

[0034] Figure 4 shows the occurrence of resin burrs 9 on the second metal layer 22 side of the insulating substrate 1 during the transfer molding process in which the sealing material 8 is filled into the semiconductor device. As described above, if the semiconductor device is assembled while warped, defects such as resin burrs 9 may occur, raising concerns about a decline in quality. This disclosure proposes solutions to address these issues of warping and improve quality.

[0035] <Grain boundary in the metal layer 10> In this embodiment, the first metal layer 21 has a region in which the size of the grain boundary 10 on the opposite side of the substrate bonding surface in the first metal layer 21 that is bonded to the insulating substrate 1 is smaller than the size of the grain boundary 10 on the opposite side of the substrate bonding surface in the second metal layer 22 that is bonded to the insulating substrate 1.

[0036] This configuration allows the grain boundary region on the opposite side of the substrate bond of the first metal layer 21 to the substrate to be smaller than the opposite side of the substrate bond of the second metal layer 22 to which the chip 4 is bonded. As a result, the opposite side of the substrate bond of the first metal layer 21 is stretched more than the opposite side of the substrate bond of the second metal layer 22, thereby reducing the convex warping of the insulating substrate 1 on the second metal layer 22 side.

[0037] In this embodiment, as will be described later, by performing a peening treatment on the surface of the first metal layer 21 opposite to the substrate bonding surface, the grain boundaries on the surface of the first metal layer 21 opposite to the substrate bonding surface become smaller, and the surface of the first metal layer 21 opposite to the substrate bonding surface is compressed and stretched. In addition, plastic deformation occurs on the surface of the first metal layer 21 opposite to the substrate bonding surface, and compressive stress is generated on the surface of the substrate bonding surface. At the same time, the hardness of the first metal layer 21 also increases, so the fatigue strength can be increased.

[0038] In this embodiment, the size of the grain boundary 10 on the substrate bonding surface of the second metal layer 22 is the same as the size of the grain boundary 10 on the substrate bonding surface of the second metal layer 22.

[0039] In this configuration, the grain boundary 10 is the same size on the substrate bonding surface of the second metal layer 22 and the substrate bonding surface, so the substrate bonding surface of the second metal layer 22 is not stretched and the warping does not increase. In other words, peening treatment is not performed on the substrate bonding surface of the second metal layer 22. In addition, since it is not necessary to apply peening treatment to the entire first metal layer 21, the processing steps can be shortened.

[0040] In this embodiment, the first metal layer 21 and the second metal layer 22 are made of the same material. This configuration makes it possible to maintain uniform thermal expansion in the first and second metal layers 22 at both ends of the insulating substrate 1, thereby reducing warping in response to temperature changes.

[0041] Addition of the feature part of claim 4 and the effect of paragraph 0010

[0042] As shown in Figure 5, by applying a peening treatment to the surface of the first metal layer 21 opposite to the substrate bonding surface, the grain boundaries 10 in the second metal layer 22 gradually decrease from the substrate bonding surface toward the opposite surface. Therefore, the stretching effect is continuously increased from the substrate bonding surface toward the opposite surface, and the uneven distribution of internal stress in the first metal layer 21 is reduced.

[0043] 1-2. Manufacturing method Figure 8 shows a flowchart illustrating the manufacturing method of a semiconductor device. <Preparation Steps> First, in preparation step S11, an insulating substrate 1 and a chip 4 are prepared, each having an insulating layer 3 with a first main surface and a second main surface opposite to the first main surface, a first metal layer 21 bonded to the first main surface, and a second metal layer 22 bonded to the second main surface. The configuration of each prepared component is as described above, so a further explanation is omitted.

[0044] <Die Bonding Process> In the die bonding process S12, the chip 4 is die-bonded to the opposite side of the substrate bonding surface of the second metal layer 22 that is bonded to the insulating substrate 1. That is, the chip 4 is bonded to the insulating substrate 1 using the bonding material a5, which is the die bonding material.

[0045] In this configuration, the chip 4 is bonded to the insulating substrate 1, while the coefficient of linear expansion of the chip 4 is approximately 2.6 × 10⁻⁶. -6 Because the temperature is around / ℃, the semiconductor device of this disclosure will have a convex warp on the side of the second metal layer 22 to which the chip 4 is bonded, and the amount of warping will be even greater.

[0046] When a semiconductor device is assembled while it is warped, stress is generated in the bonding material a5, which is the die bond material, due to the warping of the insulating substrate 1.

[0047] <Peening Process> In the peening process S13, peening is performed on at least the portion of the first metal layer 21 that includes the opposite side of the substrate bonding surface to the substrate bonding surface that is bonded to the insulating substrate 1.

[0048] With this configuration, by performing a peening treatment on the surface of the first metal layer 21 opposite to the substrate bond, the grain boundaries on the surface opposite to the substrate bond can be reduced, and the surface of the first metal layer 21 opposite to the substrate bond can be stretched. By performing a peening treatment on the surface of the first metal layer 21 opposite to the substrate bond after die bonding, when the warpage is at its maximum, the convex warpage on the second metal layer 22 side of the insulating substrate 1 can be reduced.

[0049] Figure 7 shows the peening process of the semiconductor device in this embodiment. In this embodiment, the peening process is performed using shot peening, in which a nozzle 12 emits fine particles 13 toward the second metal layer 22. In shot peening, tiny particles are impacted onto the surface at high speed, causing compression and stretching. At this time, the grain boundaries become smaller due to plastic deformation. Work hardening also occurs due to plastic deformation.

[0050] In the peening process, laser peening may be performed. In laser peening, compressive residual stress is generated by applying a laser to the surface, causing it to stretch. At this time, the grain boundaries become smaller.

[0051] By performing the above steps, the semiconductor device of this embodiment, as shown in Figures 5 to 7, is completed.

[0052] According to the above manufacturing method, by applying a peening treatment to the surface of the first metal layer 21 opposite to the substrate bonding surface, the surface of the first metal layer 21 opposite to the substrate bonding surface is stretched, and the concave warping of the 11th metal layer 21 of the insulating substrate 1 can be reduced.

[0053] 2. Embodiment 2 Figure 9 is a process flow diagram of the manufacturing method in Embodiment 2.

[0054] Unlike Embodiment 1, this embodiment further includes a warpage measurement step S23 between the die bonding step and the peening step for measuring the warpage of the insulating substrate 1. Since the rest of the embodiment is the same as Embodiment 1, the explanation will be omitted.

[0055] As shown in Figure 9, the die bonding process S22 and the peening process S24 are further interposed by a warpage measurement process S23 for measuring the warpage of the insulating substrate 1. In the peening process S24, the amount and area of ​​peening are determined based on the warpage measured in the warpage measurement process S23.

[0056] With this configuration, by determining the amount and area of ​​peening according to the warp measured in the warp measurement process S23, the warp can be appropriately corrected even if the degree of warp and the tendency of warp change.

[0057] In this embodiment, in the peening process S22, the amount of peeling is increased in the region where the surface of the first metal layer 21 opposite the substrate bonding, as measured in the warpage measurement process S23, has a concave warpage. With this configuration, even if the degree of concave warpage changes at various points on the surface of the first metal layer 21 opposite the substrate bonding, the concave warpage can be appropriately corrected by increasing the amount of peeling in the region with a concave warpage.

[0058] For example, in the warpage measurement process S23, the degree of concavity and warpage at each location on the substrate-opposite side of the first metal layer 21 is measured. Then, in the peening process S22, the amount of peening at each location is calculated based on the degree of concavity and warpage at each location, and the peening process is performed at each location based on the amount of peening at each location. As the amount of concavity and warpage at each location increases, the amount of peeling at each location increases. For example, the amount of peening at each location is adjusted by the peening process time at each location, the intensity of the peening process at each location (for example, the amount or intensity of particle ejection, or the intensity of the laser). Peening is not performed at locations without warpage.

[0059] Further warping occurs during the die bonding process S22. However, when the chip 4 is large, or when multiple chips 4 are die-bonded, localized thermal stress occurs, making the warping tendency more complex. Therefore, to correct the warping with greater precision, it is possible to measure the amount of warping linearly or planarly after the die bonding process S22, and then correct the complex warping by changing the amount of peening at each location.

[0060] While this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but are applicable individually or in various combinations to the embodiments. Accordingly, countless variations not illustrated are envisioned within the scope of the art disclosed in this disclosure. For example, these include modifying, adding or omitting at least one component, or even extracting at least one component and combining it with a component from another embodiment. [Explanation of symbols]

[0061] 1 Insulating substrate, 3 Insulating layer, 4 Chip, 5 Bonding material a, 6 Electrode, 7 Bonding wire, 8 Encapsulating material, 9 Resin burr, 10 Grain boundary, 11 Bonding material b, 12 Nozzle, 13 Fine particles, 21 First metal layer, 22 Second metal layer

Claims

1. An insulating substrate having an insulating layer having a first main surface and a second main surface which is the surface opposite to the first main surface, a first metal layer bonded to the first main surface, and a second metal layer bonded to the second main surface, The second metal layer comprises a chip bonded to the opposite side of the substrate bonding surface, which is opposite to the substrate bonding surface that is bonded to the insulating substrate, The semiconductor device is characterized in that the first metal layer has a region in which the size of the grain boundary on the substrate bonding surface opposite to the substrate bonding surface in the first metal layer is smaller than the size of the grain boundary on the substrate bonding surface opposite to the substrate bonding surface of the second metal layer.

2. The semiconductor device according to claim 1, wherein the first metal layer has a region in which the size of the grain boundary on the substrate bonding surface of the first metal layer is smaller than the size of the grain boundary on the substrate bonding surface of the first metal layer.

3. The semiconductor device according to claim 1, wherein the first metal layer and the second metal layer are made of the same material.

4. An insulating substrate having an insulating layer having a first main surface and a second main surface which is the surface opposite to the first main surface, a first metal layer bonded to the first main surface, and a second metal layer bonded to the second main surface, The second metal layer comprises a chip bonded to the opposite side of the substrate bonding surface, which is opposite to the substrate bonding surface that is bonded to the insulating substrate, The semiconductor device has a region in which the first metal layer has a grain boundary on the substrate bonding surface opposite to the substrate bonding surface in the first metal layer that is bonded to the insulating substrate, and the size of the grain boundary on the substrate bonding surface of the first metal layer is smaller than the size of the grain boundary on the substrate bonding surface of the first metal layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the size of the grain boundary on the substrate bonding surface of the second metal layer is the same as the size of the grain boundary on the substrate bonding surface of the second metal layer.

6. The semiconductor device according to any one of claims 1 to 4, wherein a circuit pattern is formed on the second metal layer and no circuit pattern is formed on the first metal layer.

7. Preparation steps for preparing an insulating substrate having an insulating layer having a first main surface and a second main surface which is the surface opposite to the first main surface, a first metal layer bonded to the first main surface, and a second metal layer bonded to the second main surface, and a chip. A die bonding step of die bonding the chip to the substrate bonding surface opposite to the substrate bonding surface in the second metal layer that is bonded to the insulating substrate, A peening step is performed on the portion of the first metal layer that includes at least the substrate bonding surface opposite to the substrate bonding surface that is bonded to the insulating substrate, A method for manufacturing a semiconductor device comprising the same equipment.

8. The process further includes a warpage measurement step for measuring the warpage of the insulating substrate between the die bonding step and the peening step, The method for manufacturing a semiconductor device according to claim 7, wherein in the peening step, the amount and portion of the peening are determined based on the warpage measured in the warpage measurement step.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the amount of peeling performed in the peening step is increased in the region where the substrate-opposite surface of the first metal layer, as measured in the warpage measurement step, has a concave warpage.

10. The method for manufacturing a semiconductor device according to any one of claims 7 to 9, wherein the peening step is performed by shot peening or laser peening.

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