Motherboard for display devices

Abstract

To enable efficient and highly accurate inspection during the manufacturing of display devices. [Solution] According to the embodiment, the mother board for the display device comprises a plurality of panel parts including a display area and a peripheral area surrounding the display area, a margin area around the plurality of panel parts, a lower electrode disposed in the display area, a rib layer disposed in the plurality of panel parts and the margin area, a first partition disposed in the display area, a plurality of second partitions disposed in the margin area, a first laminated film disposed in the plurality of panel parts and the margin area and containing an organic layer of a first color, and a first sealing layer covering the first laminated film. The plurality of second partitions are arranged in a layout corresponding to the shape of a process control mark or the shape of an alignment mark. The process control mark and the alignment mark are composed of a first laminated film disposed on the plurality of second partitions, and a first sealing layer covering the first laminated film and the plurality of second partitions.

Description

Technical Field

[0001] Embodiments of the present invention relate to a mother substrate for a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In manufacturing such display devices, inspections are carried out to check whether the elements on the substrate are formed as designed. Technologies for efficiently or highly accurately performing such inspections are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a mother substrate for a display device capable of efficiently or highly accurately performing inspections during the manufacture of the display device.

[0005] ​ Generally, according to the embodiment, the mother board for a display device comprises a plurality of panel portions, each including a display area and a peripheral area surrounding the display area; a margin area surrounding the plurality of panel portions; a lower electrode disposed in the display area; a rib layer disposed in the plurality of panel portions and the margin area; a first partition disposed in the display area; a plurality of second partitions disposed in the margin area; a first laminated film disposed in the plurality of panel portions and the margin area, including an organic layer of a first color; and a first sealing layer covering the first laminated film. The plurality of second partitions are arranged in a layout corresponding to the shape of a process control mark or the shape of an alignment mark. The process control mark and the alignment mark are composed of a first laminated film disposed on the plurality of second partitions, and a first sealing layer covering the first laminated film and the plurality of second partitions.

[0006] Furthermore, according to the embodiment, the mother board for the display device includes a plurality of panel portions, each including a display area and a peripheral area surrounding the display area; a margin area surrounding the plurality of panel portions; a lower electrode disposed in the display area; a rib layer disposed in the plurality of panel portions and the margin area; a first partition disposed in the display area; a second partition disposed in the margin area; a first laminated film disposed in the plurality of panel portions and the margin area, containing an organic layer of a first color; and a first sealing layer covering the first laminated film. The second partition has an outer shape corresponding to the shape of a process control mark or an alignment mark, and has a plurality of partition openings. The process control mark and the alignment mark are composed of a first laminated film disposed in each of the plurality of partition openings, and a first sealing layer disposed to cover the plurality of partition openings.

[0007] Furthermore, according to the embodiment, the mother board for the display device includes a plurality of panel portions, each including a display area and a peripheral area surrounding the display area; a margin area surrounding the plurality of panel portions; a lower electrode disposed in the display area; a rib layer disposed in the plurality of panel portions and the margin area; a first partition wall disposed in the display area; a second partition wall disposed in the margin area; a first laminated film disposed in the plurality of panel portions and the margin area, including an organic layer of a first color; a first sealing layer covering the first laminated film; and a first resin layer covering the first sealing layer. The second partition wall has a plurality of partition openings, and the width of each of the plurality of partition openings is 40 μm or longer. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device according to one embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display panel along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view of a motherboard according to one embodiment. [Figure 5] Figure 5 is a schematic plan view of a part of a motherboard according to one embodiment. [Figure 6] Figure 6 is a flowchart showing an example of a method for manufacturing a display device according to one embodiment. [Figure 7A] Figure 7A is a schematic cross-sectional view showing the process of forming a panel portion on a motherboard according to one embodiment. [Figure 7B] Figure 7B is a schematic cross-sectional view showing the process following Figure 7A. [Figure 7C] Figure 7C is a schematic cross-sectional view showing the process that follows Figure 7B. [Figure 7D] Figure 7D is a schematic cross-sectional view showing the process following Figure 7C. [Figure 7E] Figure 7E is a schematic cross-sectional view showing the process following Figure 7D. [Figure 7F] Figure 7F is a schematic cross-sectional view showing the process following Figure 7E. [Figure 7G] Figure 7G is a schematic cross-sectional view showing the process following Figure 7F. [Figure 7H] Figure 7H is a schematic cross-sectional view showing the process following Figure 7G. [Figure 7I] Figure 7I is a schematic cross-sectional view showing the process following Figure 7H. [Figure 7J] Figure 7J is a schematic cross-sectional view showing the process following Figure 7I. [Figure 8] Figure 8 is a schematic plan view showing an example of a configuration applicable to a test pattern according to an embodiment. [Figure 9] Figure 9 is a schematic cross-sectional view of the mother substrate along line IX-IX in Figure 8. [Figure 10] Figure 10 is a schematic plan view showing an example of a configuration applicable to a test pattern according to an embodiment. [Figure 11] Figure 11 is a schematic plan view showing the configuration of a test pattern in a state where process management marks and alignment marks are formed in the configurations shown in Figures 8 and 9. [Figure 12] Figure 12 is a schematic plan view showing an enlarged view of the region surrounded by line XII in Figure 11. [Figure 13A] Figure 13A is a schematic cross-sectional view showing the process of forming elements constituting a display element in the test pattern of the configuration shown in Figures 8 and 9. [Figure 13B] Figure 13B is a schematic cross-sectional view showing the process following Figure 13A. [Figure 13C] Figure 13C is a schematic cross-sectional view showing the process following Figure 13B. [Figure 13D] Figure 13D is a schematic cross-sectional view showing the process following Figure 13C. [Figure 14] Figure 14 is a schematic plan view showing an example of a configuration applicable to a test pattern according to an embodiment. [Figure 15]Figure 15 is a schematic cross-sectional view of the motherboard along the line XV-XV in Figure 14. [Figure 16] Figure 16 is a schematic plan view showing the configuration of a test pattern with process control marks and alignment marks formed on the same surface as shown in Figures 14 and 15. [Figure 17] Figure 17 is a schematic plan view showing an enlarged view of the area enclosed by line XVII in Figure 16. [Figure 18A] Figure 18A is a schematic cross-sectional view showing the process of forming the elements constituting the display element in the test pattern of the configuration shown in Figures 14 and 15. [Figure 18B] Figure 18B is a schematic cross-sectional view showing the process following Figure 18A. [Figure 18C] Figure 18C is a schematic cross-sectional view showing the process following Figure 18B. [Figure 18D] Figure 18D is a schematic cross-sectional view showing the process following Figure 18C. [Figure 19] Figure 19 is a schematic plan view showing an example of a configuration applicable to a test pattern according to one embodiment. [Figure 20A] Figure 20A is a schematic cross-sectional view showing an example of the configuration of a test pattern related to a comparative example. [Figure 20B] Figure 20B is a schematic cross-sectional view showing an example of the configuration of a test pattern according to one embodiment. [Modes for carrying out the invention]

[0009] Several embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0010] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis as the Y direction, and the direction along the Z axis as the Z direction. The Z direction is the normal direction of the plane containing the X and Y directions. Viewing various elements parallel to the Z direction is called a plan view.

[0011] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0012] Figure 1 shows an example configuration of a display device DSP according to one embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, circle, or ellipse.

[0014] The display area DA comprises multiple pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes multiple sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The display area DA is arranged with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply video signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. In the example in Figure 1, the scan lines GL and power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0017] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE.

[0018] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0019] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, is connected to the terminal section T. Signals and voltages for driving the pixel circuit 1 are input to the display device DSP via this flexible circuit board and the terminal section T.

[0020] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP2 and SP3 are aligned with sub-pixel SP1 in the X direction. Furthermore, sub-pixels SP2 and SP3 are aligned in the Y direction.

[0021] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple sub-pixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0022] A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio.

[0023] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0024] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0025] A conductive partition wall 6 (first partition wall) is positioned above the rib layer 5. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6 overlaps with the rib layer 5 overall and has a similar planar shape to the rib layer 5.

[0026] Specifically, partition wall 6 has partition wall opening 601 at sub-pixel SP1, partition wall opening 602 at sub-pixel SP2, and partition wall opening 603 at sub-pixel SP3. Partition wall openings 601, 602, and 603 are larger than pixel openings AP1, AP2, and AP3, respectively. Partition wall openings 601, 602, and 603 overlap with the entirety of display elements DE1, DE2, and DE3, respectively. In other words, partition wall 6 surrounds display elements DE1, DE2, and DE3.

[0027] Figure 3 is a schematic cross-sectional view of the display panel PNL along the line III-III in Figure 2. A circuit layer 11 is placed on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0028] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The rib layer 5 is positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of Figure 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0029] The partition wall 6 includes a conductive lower section 61 positioned on the rib layer 5 and an upper section 62 positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of partition wall 6 is called an overhang.

[0030] In the example shown in Figure 3, the lower section 61 comprises a bottom layer 63 positioned on top of the rib layer 5 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the axial layer 64. Also, in the example shown in Figure 3, both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0031] Furthermore, in the example shown in Figure 3, the upper section 62 comprises a first top layer 65 and a second top layer 66 positioned on top of the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, it is not limited to this, and the first top layer 65 and the second top layer 66 may have equivalent widths.

[0032] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0033] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers to improve the light extraction efficiency of the organic layers OR1, OR2, and OR3, respectively.

[0034] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0035] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13, respectively. Sealing layer SE11 continuously covers the laminated film FL1 and the partition wall 6 surrounding sub-pixel SP1. Sealing layer SE12 continuously covers the laminated film FL2 and the partition wall 6 surrounding sub-pixel SP2. Sealing layer SE13 continuously covers the laminated film FL3 and the partition wall 6 surrounding sub-pixel SP3.

[0036] In the example shown in Figure 3, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the same partition 6. Similarly, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the same partition 6. As another example, the ends of sealing layer SE11 and sealing layer SE12 may overlap on the partition 6. Likewise, the ends of sealing layer SE11 and sealing layer SE13 may overlap on the partition 6.

[0037] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0038] A cover component, such as a polarizing plate, touch panel, protective film, or cover glass, may be further placed on top of the resin layer RS2. Such a cover component may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive).

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0040] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0041] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0042] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked sequentially in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The bottom layer 63 and axial layer 64 of the lower part 64 of the partition wall 6 are formed of, for example, a metallic material. For example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used as the metallic material for the axial layer 64. The axial layer 64 may also be formed of an insulating material. Furthermore, the lower part 64 may be formed as a single layer.

[0045] The first top layer 65 of the partition wall 6 is formed of, for example, a metallic material. The second top layer 66 of the partition wall 6 is formed of, for example, a conductive oxide. As the metallic material forming the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the second top layer 66, for example, ITO or IZO can be used. The upper part 62 may consist of three or more layers, or it may be formed of a single layer. Furthermore, the upper part 62 may include a layer formed of an insulating material.

[0046] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line SL through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0049] During the manufacturing of a display device (DSP), a large motherboard is created in which multiple areas (panel sections) corresponding to the display panel PNL are formed. The following describes the configurations that can be applied to this motherboard.

[0050] Figure 4 is a schematic plan view of the motherboard MB (display device motherboard) according to this embodiment. The motherboard MB is rectangular, as shown in the figure, but it may have other shapes such as a circle.

[0051] The motherboard MB has multiple panel sections PP arranged in a matrix, and a marginal area BA surrounding these panel sections PP. In the example in Figure 4, the panel sections PP are arranged in the X and Y directions with the marginal area BA in between. However, at least two of the multiple panel sections PP of the motherboard MB may be adjacent to each other without being separated by the marginal area BA.

[0052] The motherboard MB further includes at least one test pattern TEG. In the example in Figure 4, multiple test patterns TEG are arranged in the blank area BA. The placement and number of these test patterns TEG are not particularly limited, but in one example, it is preferable that the test patterns TEG are distributed in various places such as near the edges and in the center of the motherboard MB.

[0053] Figure 5 is a schematic plan view of a portion of the motherboard MB. This figure focuses on one panel section PP. The outline of the panel section PP corresponds to the cut line CL1 used to cut the panel section PP from the motherboard MB.

[0054] Each panel section PP has the aforementioned display area DA and peripheral area SA. Furthermore, the peripheral area SA includes an inspection area TA. The inspection area TA is equipped with inspection pads and the like for checking the operation of the display panel PNL.

[0055] Each panel section PP has a cut line CL2 formed on it. This cut line CL2 divides the panel section PP into a portion including the display area DA and a portion including the inspection area TA.

[0056] During the manufacturing of the DSP display device, the panel portion PP is first cut out from the motherboard MB along the cut line CL1. Furthermore, the cut-out panel portion PP is inspected using the inspection pads described above. After this inspection, the inspection area TA is separated from the panel portion PP along the cut line CL2.

[0057] The test pattern TEG shown in Figure 4 may be placed not only in the margin area BA, but also in the surrounding area SA. For example, the test pattern TEG can be placed in the inspection area TA. In this case, the test pattern TEG will not remain on the panel portion PP after the inspection area TA has been separated along the cut line CL2. Even when the test pattern TEG is placed in the margin area BA as shown in Figure 4, the test pattern TEG will not remain on the panel portion PP after the inspection area TA has been separated along the cut line CL2.

[0058] As another example, the test pattern TEG may be placed in the peripheral area SA excluding the inspection area TA. In this case, the test pattern TEG remains in the panel section PP after the inspection area TA has been separated along the cut line CL2.

[0059] Next, an example of a method for manufacturing a display device DSP will be described. Figure 6 is a flowchart of an example of a method for manufacturing a display device DSP. Figures 7A to 7J are schematic cross-sectional views showing the process of forming the panel portion PP on the mother board MB. In Figures 7A to 7J, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0060] In forming the panel portion PP, first a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10 of the mother board MB (step PR1 in Figure 6). Next, as shown in Figure 7A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR2 in Figure 6).

[0061] Next, as shown in Figure 7B, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire motherboard MB (step PR3 in Figure 6). At this point, the pixel apertures AP1, AP2, and AP3 are not provided on the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0062] After the formation of the rib layer 5, a process for forming the partition wall 6 is carried out (processes PR4 and PR5 in Figure 6). In process PR4, as shown in Figure 7C, a first layer L1 for processing into the bottom layer 63, a second layer L2 for processing into the axial layer 64, a third layer L3 for processing into the first top layer 65, and a fourth layer L4 for processing into the second top layer 66 are sequentially formed over the entire motherboard MB. Furthermore, a resist R1 is placed on top of the fourth layer L4. The resist R1 is patterned to the shape of the partition wall 6. The first layer L1, second layer L2, third layer L3, and fourth layer L4 can be formed, for example, by sputtering.

[0063] In the subsequent process PR5, the first layer L1, second layer L2, third layer L3, and fourth layer L4 are patterned using the resist R1 as a mask. In one example, the first layer L1 is formed from titanium nitride, the second layer L2 from aluminum, the third layer L3 from titanium, and the fourth layer L4 from ITO. In this case, process PR5 may include wet etching to remove the portion of the fourth layer L4 exposed from the resist R1, dry etching to remove the portions of the first layer L1, second layer L2, and third layer L3 exposed from the resist R1, and wet etching to reduce the width of the second layer L2. The etching performed in process PR5 is appropriately selected according to the structure and material of the partition wall 6.

[0064] After step PR5, a partition wall 6 is formed in the display area DA, as shown in Figure 7D. After the formation of the partition wall 6, the resist R1 is removed (peeled off). In the wet etching process described above, which reduces the width of the second layer L2, the second top layer 66 (fourth layer L4) may also be slightly eroded. If this erosion occurs, the width of the second top layer 66 becomes smaller than the width of the first top layer 65.

[0065] Next, a process is carried out to create pixel apertures AP1, AP2, and AP3 (process PR6 in Figure 6). In this process PR6, a resist R2 is formed to cover the partition wall 6, as shown in Figure 7E. Furthermore, dry etching is performed on the rib layer 5 using the resist R2 as a mask. As a result, pixel apertures AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed on the rib layer 5, as shown in Figure 7F. After the dry etching, the resist R2 is removed (peeled off).

[0066] After step PR6, a step is performed to remove the rib layer 5 at the terminal portion T shown in Figure 1 (step PR7 in Figure 6).

[0067] After step PR7, a process for forming the display element DE1 is carried out (step PR8 in Figure 6). In forming the display element DE1, first, as shown in Figure 7G, a multilayer film FL1 and a sealing layer SE11 are formed. As shown in Figure 3, the multilayer film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can be formed, for example, by CVD.

[0068] The laminated film FL1 and the sealing layer SE11 are formed on the entire motherboard MB, including not only the display area DA of each panel section PP, but also the peripheral area SA and the margin area BA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0069] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 7G, a resist R3 is placed on top of the sealing layer SE11. The resist R3 covers the subpixel SP1 and a portion of the surrounding partition wall 6.

[0070] Subsequently, an etching process is performed using resist R3 as a mask. As a result, as shown in Figure 7H, the portions of the multilayer film FL1 and the sealing layer SE11 that are exposed from resist R3 are removed. In other words, the portions of the multilayer film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 on the sub-pixel SP1. For example, in the peripheral region SA and the margin region BA, the multilayer film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, resist R3 is removed (peeled off).

[0071] After step PR8, a process for forming the display element DE2 is carried out (step PR9 in Figure 6). The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0072] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can be formed, for example, by CVD. The multilayer film FL2 is divided into multiple parts by overhanging partitions 6. The sealing layer SE12 continuously covers each divided part of the multilayer film FL2 and the partitions 6. By patterning the multilayer film FL2 and the sealing layer SE2, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 7I. For example, in the peripheral region SA and the blank region BA, the multilayer film FL2 and the sealing layer SE12 are removed by etching during the patterning process.

[0073] After process PR9, a process for forming the display element DE3 is carried out (process PR10 in Figure 6). The display element DE3 can be formed using the same procedure as the display elements DE1 and DE2. That is, in forming the display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0074] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. The multilayer film FL3 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE13 continuously covers each divided part of the multilayer film FL3 and the partition walls 6. By patterning the multilayer film FL3 and the sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 7J. For example, in the peripheral region SA and the blank region BA, the multilayer film FL3 and the sealing layer SE13 are removed by etching during the patterning process.

[0075] Note that, while this example assumes that the display elements DE1, DE2, and DE3 are formed in this order, they may be formed in any other order.

[0076] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, sealing layer SE2, and resin layer RS2 shown in Figure 3 are formed in sequence (step PR11 in Figure 6). Furthermore, each panel portion PP is cut out from the motherboard MB along the cut line CL1 (step PR12 in Figure 6).

[0077] Subsequently, each panel section PP is inspected (step PR13 in Figure 6). This inspection includes lighting tests of each display element DE1, DE2, and DE3 using inspection pads placed in the inspection area TA. After the inspection, the inspection area TA is cut along the cut line CL2 (step PR14 in Figure 6). This completes the display panel PNL.

[0078] Figure 8 is a schematic plan view showing an example of a configuration applicable to the test pattern TEG. Figure 9 is a schematic cross-sectional view of the motherboard MB including the test pattern TEG along the IX-IX line in Figure 8. In Figure 9, elements below the organic insulating layer 12 are omitted.

[0079] The configurations shown in Figures 8 and 9 are applicable to a test pattern TEG on which at least one of the following is formed: a vernier for confirming the position of the exposure mask, identification characters for confirming whether the elements constituting the display element are properly formed, and alignment marks used for positioning the various elements. The vernier and identification characters may also be called process control marks, as they are marks used to control whether the various processes for manufacturing the display panel PNL are being carried out correctly.

[0080] As shown in Figure 8, the test pattern TEG is composed of a rib layer 5 and multiple partition walls 7 (second partition wall, protrusions). The rib layer 5 is arranged across the panel section PP and the margin area BA shown in Figure 4.

[0081] Multiple partition walls 7 are arranged on the rib layer 5 in layouts corresponding to the shapes of the process control marks and alignment marks. As will be described in detail later, in the example in Figure 8, multiple partition walls 7 are arranged on the rib layer 5 in layouts corresponding to the shapes of the elongated rod-shaped vernier in the Y direction, the identification characters "+30", the identification characters "ER", and the L-shaped alignment marks.

[0082] In the example in Figure 8, a configuration is shown in which a total of five partition walls 7 are arranged in the X and Y directions to correspond to the "+" portion of the identification character "+30" (see the area enclosed by the dashed line in the figure). However, as shown in Figure 10, for example, a single cross-shaped partition wall 7 may be arranged to correspond to the "+" portion. However, if the size of the partition wall 7 is large, there is a possibility that electrostatic discharge (ESD) may occur or that the process control mark may not be formed properly (for example, the laminated film that constitutes the process control mark may peel off). Therefore, when comparing the configuration in Figure 8 and the configuration in Figure 10 regarding the layout of the partition wall 7 corresponding to the "+" portion, the configuration in Figure 8 is preferable.

[0083] Furthermore, although the example in Figure 8 shows a configuration in which the partition wall 7 is square in plan view, the shape of the partition wall 7 may be other shapes, such as a rectangle in plan view.

[0084] As shown in Figure 9, partition wall 7, like partition wall 6, includes a lower section 71 (bottom layer 73 and axial layer 74) and an upper section 72 (first top layer 75 and second top layer 76). Also, like partition wall 6, both ends of the bottom layer 73 of partition wall 7 protrude from the sides of the axial layer 74.

[0085] The lower part 71 of partition wall 7 is made of the same material as the lower part 61 of partition wall 6. Specifically, the bottom layer 73 and the axial layer 74 are made of the same material as the bottom layer 63 and axial layer 64 of partition wall 6, respectively. The thickness of the bottom layer 73 is equivalent to the thickness of the bottom layer 63 of partition wall 6. Also, the thickness of the axial layer 74 is equivalent to the thickness of the axial layer 64 of partition wall 6.

[0086] The upper part 72 of partition wall 7 is made of the same material as the upper part 62 of partition wall 6. Specifically, the first top layer 75 and the second top layer 76 are made of the same material as the first top layer 65 and the second top layer 66 of partition wall 6, respectively. The thickness of the first top layer 75 is equivalent to the thickness of the first top layer 65 of partition wall 6. Also, the thickness of the second top layer 76 is equivalent to the thickness of the second top layer 66 of partition wall 6.

[0087] Furthermore, the partition wall 7 is formed by processes PR4 and PR5 in Figure 6, just like the partition wall 6. Specifically, in processes PR4 and PR5, the bottom layer 73 is formed on top of the rib layer 5, the axial layer 74 is formed on top of the bottom layer 73, the first top layer 75 is formed on top of the axial layer 74, and the second top layer 76 is formed on top of the first top layer 75.

[0088] Figure 11 is a schematic plan view showing the configuration of the test pattern TEG with process control marks and alignment marks formed on the configuration shown in Figures 8 and 9. In the example in Figure 11, the configuration of the test pattern TEG includes the process control marks and alignment marks formed during the process of forming the display element DE1 in the display area DA (i.e., process PR8 in Figure 6). Figure 12 is a schematic plan view showing an enlarged view of the area enclosed by line XII in Figure 11.

[0089] In the example shown in Figure 11, the test pattern TEG has multiple vernier VEs and multiple identification character IDs as process control marks. In addition to the process control marks mentioned above, the test pattern TEG also has multiple alignment marks AL.

[0090] Figure 12 shows a magnified view of only a portion of the identification character ID enclosed by line XII in Figure 11. The vernier VE, identification character ID, and alignment mark AL all have similar structures and are composed of a laminated film FL1 and a sealing layer SE11. The laminated film FL1, which constitutes the vernier VE, identification character ID, and alignment mark AL, is positioned on the upper part 72 of the partition wall 7, which is located on the rib layer 5, and is not positioned anywhere else. The sealing layer SE11, which constitutes the vernier VE, identification character ID, and alignment mark AL, is positioned to cover the partition wall 7, which is located on the rib layer 5, and the laminated film FL1, which is located on the upper part 72 of the partition wall 7.

[0091] In the example shown in Figure 11, the multiple vernier VEs include vernier VE1 to VE8. Vernier VE1 to VE8 extend in the Y direction and are formed in a long rectangular shape in the Y direction.

[0092] In the example shown in Figure 11, the widths of the verniers VE1 to VE8 in the X direction are all the same. Note that while this example shows eight verniers, the number of verniers may be seven or fewer, or nine or more.

[0093] The verniers VE1 to VE8 are arranged at equal pitches in the X direction. Specifically, the pitch P of each vernier VE1 to VE8 is equal.

[0094] In the example in Figure 11, the lengths of verniers VE1, VE3, VE5, and VE7 in the Y direction are all equal, and the lengths of verniers VE2, VE4, VE6, and VE8 in the Y direction are all equal. If we define the length of verniers VE1, VE3, VE5, and VE7 in the Y direction as length L1, and the length of verniers VE2, VE4, VE6, and VE8 in the Y direction as length L2, then length L1 is greater than length L2 (L1 > L2). Note that the relationship of the lengths of verniers VE1 to VE8 in the Y direction is not limited to this example. For example, the lengths of verniers VE1 to VE8 in the Y direction may all be the same. That is, length L1 may be equal to length L2 (L1 = L2).

[0095] In the example in Figure 11, the multiple identification character IDs include identification character ID1 and ID2. Identification character ID1 has a shape corresponding to the number "+30". Identification character ID2 has a shape corresponding to the alphabet "ER". Identification characters ID1 and ID2 are arranged in the X direction with a predetermined spacing between them.

[0096] Identifier characters ID1 and ID2 have equivalent lengths in the Y direction. In the example in Figure 11, the Y-direction lengths of both identifier characters ID1 and ID2 are length L3, and length L3 is equal to the length L1 of verniers VE1, VE3, VE5, and VE7. However, the Y-direction lengths of identifier characters ID1 and ID2 do not necessarily have to be the same; they only need to be equivalent (similar in length). Also, the Y-direction lengths of the identifier characters ID and the Y-direction lengths of the verniers VE do not necessarily have to be the same; they may be different lengths.

[0097] In the example in Figure 11, the multiple alignment marks AL include alignment marks AL1 to AL4. Alignment mark AL1 has an L-shape, alignment mark AL2 has a shape obtained by rotating alignment mark AL1 90° to the right (clockwise), alignment mark AL3 has a shape obtained by rotating alignment mark AL2 90° to the right (clockwise), and alignment mark AL4 has a shape obtained by rotating alignment mark AL3 90° to the right (clockwise).

[0098] In the example in Figure 11, the lengths of alignment marks AL1 to AL4 in the X direction are equal. Also, the lengths of alignment marks AL1 to AL4 in the Y direction are equal. In the example in Figure 11, the lengths of alignment marks AL1 to AL4 in the X direction and the Y direction are both L4, showing the case where the lengths in the X and Y directions are equal. However, the lengths of alignment marks AL1 to AL4 in the X direction and the Y direction do not necessarily have to be the same; they may be different lengths.

[0099] Figures 11 and 12 show a test pattern TEG formed at a predetermined location in the blank area BA, including process control marks and alignment marks formed in process PR8. However, at another location in the blank area BA, a test pattern TEG is formed in the process of forming the display element DE2 in the display area DA (i.e., process PR9 in Figure 6), and includes process control marks and alignment marks consisting of the laminated film FL2 and the sealing layer SE12, similar to the test pattern TEG shown in Figures 11 and 12. Furthermore, at yet another location in the blank area BA, a test pattern TEG is formed in the process of forming the display element DE3 in the display area DA (i.e., process PR10 in Figure 6), and includes process control marks and alignment marks consisting of the laminated film FL3 and the sealing layer SE13, similar to the test pattern TEG shown in Figures 11 and 12.

[0100] Figures 13A to 13D are schematic cross-sectional views when step PR8 for forming the display element DE1 is performed on the test pattern TEG with the configuration shown in Figures 8 and 9. The cross-sections shown in Figures 13A to 13D are of the same location as in Figure 9, with the elements below the organic insulating layer 12 omitted.

[0101] In step PR8, a laminated film FL1 and a sealing layer SE11 are formed on the rib layer 5 and the partition wall 7, as shown in Figure 13A. A resist R corresponding to the resist R3 shown in Figure 7H is formed on the laminated film FL1 and the sealing layer SE11. Furthermore, the resist R is exposed using a mask MK, as indicated by multiple arrows. The mask MK has a shape corresponding to the process control marks and alignment marks formed on the test pattern TEG. In other words, the mask MK is open in positions other than where the process control marks and alignment marks are formed. The resist R is, for example, a positive type. Therefore, as shown in Figure 13B, the exposed portion of the resist R is removed in the development process.

[0102] Subsequently, an etching process is performed using the resist R as a mask. As a result, as shown in Figure 13C, the portions of the multilayer film FL1 and the sealing layer SE11 that are exposed from the resist R are removed. The multilayer film FL1 and the sealing layer SE11 that constitute the process control marks and alignment marks are covered with resist R and are therefore not removed by this etching process. The sealing layer SE11 positioned around the partition wall 7 adheres strongly to the partition wall 7 (its side surface) and is not peeled off together with the resist R when the resist R is removed (peeled) after this process. Therefore, as shown in Figure 13D, the sealing layer SE11 positioned around the partition wall 7 and the multilayer film FL1 positioned on top of the partition wall 7 remain in the test pattern TEG after the resist R has been removed, and these sealing layer SE11 and multilayer film FL1 function as process control marks and alignment marks. However, the multilayer film FL1 positioned near the side surface of the partition wall 7 is removed by interfacial erosion of the peeling solution used to peel off the resist R and by subsequent etching processes.

[0103] Here, we have described the case where process PR8 for forming the display element DE1 is performed on the test pattern TEG with the configuration shown in Figures 8 and 9. Similarly, when process PR9 for forming the display element DE2 is performed on the test pattern TEG with the configuration shown in Figures 8 and 9, the sealing layer SE12 arranged around the partition wall 7 and the laminated film FL2 arranged on top of the partition wall 7 remain, and these sealing layer SE12 and laminated film FL2 function as process control marks and alignment marks. Similarly, when process PR10 for forming the display element DE3 is performed on the test pattern TEG with the configuration shown in Figures 8 and 9, the sealing layer SE13 arranged around the partition wall 7 and the laminated film FL3 arranged on top of the partition wall 7 remain, and these sealing layer SE13 and laminated film FL3 function as process control marks and alignment marks.

[0104] As described above, by arranging multiple partitions 7 in the margin area BA in a layout corresponding to the process control marks and alignments to be formed as the test pattern TEG, a test pattern TEG including process control marks and alignment marks composed of the laminated films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 can be formed in the margin area BA.

[0105] By forming a test pattern TEG including process control marks and alignment marks in the margin area BA, it is possible to verify, for example, whether the exposure mask was positioned correctly during the manufacturing process of the display panel PNL by using a vernier, one of the process control marks. Furthermore, by forming a test pattern TEG including process control marks and alignment marks in the margin area BA, it is possible to verify, for example, whether the elements constituting the display element are formed correctly by using an identification character, one of the process control marks. In addition, by forming a test pattern TEG including process control marks and alignment marks in the margin area BA, it is possible to align various elements using the alignment marks, for example.

[0106] Figure 14 is a schematic plan view showing another example of a configuration applicable to the test pattern TEG. Figure 15 is a schematic cross-sectional view of the motherboard MB including the test pattern TEG along the XV-XV line in Figure 14. In Figure 15, elements below the organic insulating layer 12 are omitted. The configurations shown in Figures 14 and 15 are applicable to the test pattern TEG on which process control marks and alignment marks are formed, similar to the configurations shown in Figures 8 and 9.

[0107] As shown in Figure 14, the test pattern TEG consists of a rib layer 5 and multiple partition walls 8 (second partition walls). The rib layer 5 is arranged across the panel section PP and the margin area BA shown in Figure 4.

[0108] The external shapes of the multiple bulkheads 8 correspond to the shapes of the process control marks and alignment marks, respectively. In the example in Figure 14, bulkhead 8 with an external shape corresponding to a long, rod-shaped vernier in the Y direction, bulkhead 8 with an external shape corresponding to the identification characters "+30", bulkhead 8 with an external shape corresponding to the identification characters "ER", and bulkhead 8 with an external shape corresponding to an L-shaped alignment mark are arranged on the rib layer 5.

[0109] Each partition wall 8 has multiple partition wall openings 801 (recesses). The number of partition wall openings 801 formed in each partition wall 8, as well as the shape and size of the partition wall openings 801, can be arbitrary. However, from the viewpoint of properly forming process control marks and alignment marks, it is desirable to form a large number of small partition wall openings 801. This is because the formation of a large number of small partition wall openings 801 increases the contact area between the partition wall 8 and the sealing layers SE11, SE12, and SE13.

[0110] As shown in Figure 15, partition wall 8, like partition wall 6, includes a lower section 81 (bottom layer 83 and axial layer 84) and an upper section 82 (first top layer 85 and second top layer 86). Also, like partition wall 6, both ends of the bottom layer 83 of partition wall 8 protrude from the sides of the axial layer 84.

[0111] The lower part 81 of partition wall 8 is made of the same material as the lower part 61 of partition wall 6. Specifically, the bottom layer 83 and the axial layer 84 are made of the same material as the bottom layer 63 and axial layer 64 of partition wall 6, respectively. The thickness of the bottom layer 83 is equivalent to the thickness of the bottom layer 63 of partition wall 6. Also, the thickness of the axial layer 84 is equivalent to the thickness of the axial layer 64 of partition wall 6.

[0112] The upper part 82 of partition wall 8 is made of the same material as the upper part 62 of partition wall 6. Specifically, the first top layer 85 and the second top layer 86 are made of the same material as the first top layer 65 and the second top layer 66 of partition wall 6, respectively. The thickness of the first top layer 85 is equivalent to the thickness of the first top layer 65 of partition wall 6. Also, the thickness of the second top layer 86 is equivalent to the thickness of the second top layer 66 of partition wall 6.

[0113] The partition wall 8 is formed in the same way as the partition wall 6, by processes PR4 and PR5 in Figure 6. Specifically, in processes PR4 and PR5, the bottom layer 83 is formed on the rib layer 5, the axial layer 84 is formed on the bottom layer 83, the first top layer 85 is formed on the axial layer 84, and the second top layer 86 is formed on the first top layer 85. Subsequently, a plurality of partition wall openings 801 are formed, including the three partition wall openings 801 shown in Figure 15.

[0114] Figure 16 is a schematic plan view showing the configuration of the test pattern TEG with process control marks and alignment marks formed on the configuration shown in Figures 14 and 15. In the example in Figure 15, the configuration of the test pattern TEG includes the process control marks and alignment marks formed during the process of forming the display element DE1 in the display area DA (i.e., process PR8 in Figure 6). Figure 17 is a schematic plan view showing an enlarged view of the area enclosed by line XVII in Figure 16.

[0115] In the example shown in Figure 16, the test pattern TEG has multiple vernier VE1 to VE8 and multiple identification characters ID1 and ID2 as process control marks. In addition to the process control marks mentioned above, the test pattern TEG also has multiple alignment marks AL1 to AL4.

[0116] Figure 17 shows a magnified view of only a portion of the identification character ID1 enclosed by line XVII in Figure 16. However, the verniers VE1-VE8, identification characters ID1 and ID2, and alignment marks AL1-AL4 all have a similar structure and are composed of a laminated film FL1 and a sealing layer SE11. The laminated film FL1 that constitutes the verniers VE1-VE8, identification characters ID1 and ID2, and alignment marks AL1-AL4 is positioned on the rib layer 5 in the partition opening 801 and is not positioned anywhere else. The sealing layer SE11 that constitutes the verniers VE1-VE8, identification characters ID1 and ID2, and alignment marks AL1-AL4 covers the partition opening 801. More specifically, the sealing layer SE11 that constitutes the verniers VE1-VE8, identification characters ID1 and ID2, and alignment marks AL1-AL4 continuously covers the laminated film FL1 positioned in the partition opening 801 and a portion of the upper part 82 of the partition 8.

[0117] Note that the shapes and sizes (lengths) of the verniers VE1-VE8, identification characters ID1 and ID2, and alignment marks AL1-AL4 are the same as in the example in Figure 11, so a detailed explanation is omitted here.

[0118] Figures 16 and 17 show a test pattern TEG formed at a predetermined location in the blank area BA, including process control marks and alignment marks formed in process PR8. However, at another location in the blank area BA, a test pattern TEG is formed in the process of forming the display element DE2 in the display area DA (i.e., process PR9 in Figure 6), and includes process control marks and alignment marks consisting of the laminated film FL2 and the sealing layer SE12, similar to the test pattern TEG shown in Figures 16 and 17. Furthermore, at yet another location in the blank area BA, a test pattern TEG is formed in the process of forming the display element DE3 in the display area DA (i.e., process PR10 in Figure 6), and includes process control marks and alignment marks consisting of the laminated film FL3 and the sealing layer SE13, similar to the test pattern TEG shown in Figures 16 and 17.

[0119] Figures 18A to 18D are schematic cross-sectional views when step PR8 for forming the display element DE1 is performed on the test pattern TEG with the configuration shown in Figures 14 and 15. The cross-sections shown in Figures 18A to 18D are of the same location as in Figure 15, with the elements below the organic insulating layer 12 omitted.

[0120] In step PR8, a laminated film FL1 and a sealing layer SE11 are formed on the rib layer 5 and the partition wall 8, as shown in Figure 18A. A resist R corresponding to the resist R3 shown in Figure 7H is formed on the laminated film FL1 and the sealing layer SE11. Furthermore, the resist R is exposed using a mask MK, as indicated by multiple arrows. The mask MK has a shape corresponding to the process control marks and alignment marks formed on the test pattern TEG. In other words, the mask MK is open in positions other than where the process control marks and alignment marks are formed. The resist R is, for example, a positive type. Therefore, as shown in Figure 18B, the exposed portion of the resist R is removed in the development process.

[0121] Subsequently, an etching process is performed using the resist R as a mask. As a result, as shown in Figure 18C, the portions of the multilayer film FL1 and the sealing layer SE11 that are exposed from the resist R are removed. The multilayer film FL1 and the sealing layer SE11 that constitute the process control marks and alignment marks are covered with the resist R and are therefore not removed by this etching process. The partition opening 801 and the sealing layer SE11 positioned around the partition opening 801 are strongly adhered to the partition 8 (its side surface) and are not peeled off together with the resist R when the resist R is removed (peeled) after this process. Therefore, as shown in Figure 18D, the test pattern TEG after the resist R has been removed contains the multilayer film FL1 positioned at the partition opening 801 and the sealing layer SE11 positioned on the upper part 82 around the partition opening 801, and these multilayer film FL1 and sealing layer SE11 function as process control marks and alignment marks. However, the laminated film FL1 positioned on the upper part 82 of the partition wall 8 is removed by interfacial erosion of the stripping solution used to remove the resist R, or by subsequent etching steps.

[0122] Here, we have described the case where process PR8 for forming the display element DE1 is performed on the test pattern TEG with the configuration shown in Figures 14 and 15. Similarly, when process PR9 for forming the display element DE2 is performed on the test pattern TEG with the configuration shown in Figures 14 and 15, the laminated film FL2 placed on the partition opening 801 and the sealing layer SE12 placed on the partition opening 801 and the upper part 82 surrounding the partition opening 801 remain, and these laminated film FL2 and sealing layer SE12 function as process control marks and alignment marks. Similarly, when process PR10 for forming the display element DE3 is performed on the test pattern TEG with the configuration shown in Figures 14 and 15, the laminated film FL3 placed on the partition opening 801 and the sealing layer SE13 placed on the partition opening 801 and the upper part 82 surrounding the partition opening 801 remain, and these laminated film FL3 and sealing layer SE13 function as process control marks and alignment marks.

[0123] As described above, by placing a partition wall 8 having an outer shape corresponding to the process control marks and alignments to be formed as a test pattern TEG in the margin area BA, a test pattern TEG including process control marks and alignment marks composed of the laminated films FL1, FL2, FL3 and sealing layers SE11, SE12, SE13 can be formed in the margin area BA.

[0124] By forming a test pattern TEG including process control marks and alignment marks in the margin area BA, it is possible to verify, for example, whether the exposure mask was positioned correctly during the manufacturing process of the display panel PNL by using a vernier, one of the process control marks. Furthermore, by forming a test pattern TEG including process control marks and alignment marks in the margin area BA, it is possible to verify, for example, whether the elements constituting the display element are formed correctly by using an identification character, one of the process control marks. In addition, by forming a test pattern TEG including process control marks and alignment marks in the margin area BA, it is possible to align various elements using the alignment marks, for example.

[0125] Unlike Figures 8 and 9, and Figures 14 and 15, Figure 19 is a schematic plan view showing an example of a configuration applicable, for example, to a test pattern TEG for measuring cathode resistance (see the area enclosed by the dashed line in the figure).

[0126] As shown in Figure 19, the test pattern TEG consists of a rib layer 5 and a partition wall 9 (second partition wall). The rib layer 5 is arranged across the panel section PP and the margin area BA shown in Figure 4.

[0127] The partition wall 9 has multiple partition wall openings 901 (recesses). If the length of each partition wall opening 901 in the X direction is defined as L5 and the length in the Y direction is defined as L6, it is desirable that both lengths L5 and L6 have a length of 40 μm to 50 μm or more.

[0128] Unlike the test pattern TEG on which process control marks and alignment marks are formed, the test pattern TEG for measuring cathode resistance shown in Figure 19 includes not only the laminated films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13, but also a resin layer RS1 placed on top of the sealing layers SE11, SE12, SE13. In this test pattern TEG on which the resin layer RS1 is placed, if the size of the partition opening 901 is small, as shown in Figure 20A, when air bubbles accumulated under the overhang of the partition wall 9 escape, the resin layer RS1 will be divided, resulting in coating defects. For this reason, in the test pattern TEG on which the resin layer RS1 is placed, as shown in Figure 19, it is desirable to form a partition opening 901 that is of a predetermined size or larger, more specifically, a partition opening 901 with lengths L5 and L6 both of 40 μm to 50 μm or longer. According to this, as shown in Figure 20B, when air bubbles accumulated under the overhang of the partition wall 9 escape, it is possible to suppress the fragmentation of the resin layer RS1 and prevent the occurrence of coating defects, thereby enabling the normal formation of the test pattern TEG for measuring the cathode resistance.

[0129] Furthermore, by placing the partition wall 9 having the partition wall opening 901 in the margin area BA, the partition wall opening 901 and the sealing layers SE11, SE12, SE13 placed around the partition wall opening 901 are strongly bonded to the partition wall 9 (its side surface), leaving the laminated films FL1, FL2, FL3 placed in the partition wall opening 901 and the sealing layers SE11, SE12, SE13 placed on the partition wall 9 surrounding the partition wall opening 901, and forming a test pattern TEG in the margin area BA, similar to the test pattern TEG on which process control marks and alignment marks are formed.

[0130] As described above, this embodiment makes it possible to perform inspections during the manufacturing of a display device DSP efficiently and with high accuracy. In addition to what has been described here, various other desirable effects can be obtained from this embodiment.

[0131] All display devices, motherboards, and manufacturing methods that a person skilled in the art can implement by appropriately modifying the design based on the display devices, motherboards, and manufacturing methods disclosed in the above embodiments also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0132] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0133] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0134] MB…Motherboard, DSP…Display device, DA…Display area, SA…Peripheral area, BA…Margin area, PX…Pixel, SP1,SP2,SP3…Sub-pixel, LE1,LE2,LE3…Lower electrode, OR1,OR2,OR3…Organic layer, UE1,UE2,UE3…Upper electrode, FL1,FL2,FL3…Laminated film, SE11,SE12,SE13,SE2…Sealing layer, RS1,RS2…Resin layer, TEG…Test pattern VE, VE1~VE8... Vernier, ID, ID1, ID2... Identification characters, AL, AL1~AL4... Alignment marks, 5... Rib layer, 6~9... Bulkhead, 61, 71, 81... Lower part, 62, 72, 82... Upper part, 63, 73, 83... Bottom layer, 64, 74, 84... Axial layer, 65, 75, 85... First top layer, 66, 76, 86... Second top layer, 801, 901... Bulkhead opening, 12... Organic insulation layer.

Claims

1. Multiple panel sections, each including a display area and a peripheral area surrounding the display area, The marginal area around the plurality of panel sections, The lower electrode located in the display area, The plurality of panel sections and the rib layer arranged in the margin area, A first partition wall arranged in the display area, Multiple second partitions arranged in the margin area, The plurality of panel portions and the margin region are arranged, and the first laminated film includes an organic layer of the first color, A first sealing layer covering the first laminated film, Equipped with, The plurality of second partitions are arranged in a layout corresponding to the shape of the process control mark or the shape of the alignment mark. The process control marks and alignment marks are composed of a first laminated film placed on each of the plurality of second partitions, and a first sealing layer covering the first laminated film and the plurality of second partitions. Motherboard for display devices.

2. The first sealing layer constituting the process control mark and the alignment mark is adhered to the side surfaces of the plurality of second partitions. Mother board for display device according to claim 1.

3. The first partition and the plurality of second partitions each include a lower part and an upper part having an end protruding from the side surface of the lower part, The first laminated film constituting the process control mark and the alignment mark is positioned on the upper part included in each of the plurality of second partitions, and is not positioned near the sides of the plurality of second partitions. Motherboard for display device according to claim 2.

4. In each of the first partition and the plurality of second partitions, the lower part is positioned on the rib layer. The lower portion included in each of the first partition and the plurality of second partitions is formed of the same material. The upper portion included in each of the first partition and the plurality of second partitions is formed of the same material. Motherboard for display device according to claim 3.

5. The process control mark includes at least one of a vernier and an identification character for managing the manufacturing process of the plurality of panel parts. Mother board for display device according to any one of claims 1 to 4.

6. Multiple panel sections, each including a display area and a peripheral area surrounding the display area, The marginal area surrounding the plurality of panel sections, The lower electrode located in the display area, The plurality of panel sections and the rib layer arranged in the margin area, A first partition wall arranged in the display area, A second partition wall is positioned in the aforementioned margin area, The plurality of panel portions and the margin region are arranged, and the first laminated film includes an organic layer of the first color, A first sealing layer covering the first laminated film, Equipped with, The second partition wall has an outer shape corresponding to the shape of the process control mark or the shape of the alignment mark, and has a plurality of partition wall openings. The process control marks and alignment marks are composed of a first laminated film arranged in each of the plurality of partition openings and a first sealing layer arranged to cover the plurality of partition openings. Motherboard for display devices.

7. The first sealing layer constituting the process control mark and the alignment mark is adhered to the side surface of the second partition at each of the plurality of partition openings. Mother board for display device according to claim 6.

8. The first partition and the second partition each include a lower part and an upper part having an end protruding from the side surface of the lower part, The first laminated film constituting the process control mark and the alignment mark is positioned on the rib layer in each of the plurality of partition wall openings, and is not positioned on the upper part of the second partition wall. Mother board for display device according to claim 7.

9. In each of the first and second partitions, the lower part is positioned on the rib layer. The lower portion included in each of the first and second partitions is formed of the same material. The upper portion included in each of the first and second partitions is formed of the same material. Mother board for display device according to claim 8.

10. The process control mark includes at least one of a vernier and an identification character for managing the manufacturing process of the plurality of panel parts. Motherboard for display device according to any one of claims 6 to 9.

11. Multiple panel sections, each including a display area and a peripheral area surrounding the display area, The marginal area surrounding the plurality of panel sections, The lower electrode located in the display area, The plurality of panel sections and the rib layer arranged in the margin area, A first partition wall arranged in the display area, A second partition wall is positioned in the aforementioned margin area, The plurality of panel portions and the margin region are arranged, and the first laminated film includes an organic layer of the first color, A first sealing layer covering the first laminated film, A first resin layer covering the first sealing layer, Equipped with, The second partition wall has a plurality of partition wall openings, Each of the aforementioned partition openings has a width of 40 μm or more. Motherboard for display devices.

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