Display board, display device, and method for manufacturing a display board

Abstract

This suppresses light reflection at the aperture edge of the first aperture. [Solution] The display substrate 21 comprises a light-transmitting substrate 21GS having light-transmitting properties, a first insulating film 33 disposed on the light-transmitting substrate 21GS, a second insulating film 34 disposed on the first insulating film 33 and having a different refractive index from the first insulating film 33, and a pixel electrode 25. The first insulating film 33 and the second insulating film 34 are provided with a first opening 36 that overlaps with at least a portion of the pixel electrode 25, and the opening edge of the first opening 36 is configured to be along the normal to the main surface of the light-transmitting substrate 21GS.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a display substrate, a display device, and a method for manufacturing a display substrate in which light reflection at the opening edge of a first opening is suppressed.

Background Art

[0002] Conventionally, as an example of a display device and a substrate (display substrate) provided in the display device, the one described in Patent Document 1 below is known. The display device described in Patent Document 1 has pixels arranged in a matrix on a transparent substrate 1. Each pixel has an opening region in which an electro-optical element that emits light through the substrate is formed, and a non-opening region in which a thin film transistor TFT that drives the electro-optical element is formed. The non-opening region has a first film configuration that includes the thin film transistor TFT. The opening region has a second film configuration that extends from the first film configuration and is interposed between the electro-optical element and the substrate. The second film configuration is different from the first film configuration in order to adjust the light passing through the opening region.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the display device described in Patent Document 1 mentioned above, the first film structure on the non-aperture region side includes a silicon nitride film with a refractive index different from that of the substrate glass, whereas the second film structure on the aperture region side does not include a silicon nitride film. In other words, an aperture is provided in the aperture region that communicates with the gate insulating film and the interlayer insulating film. However, the aperture edges of the apertures in the gate insulating film and the interlayer insulating film are tapered with respect to the normal to the substrate. As a result, the aperture edges of the apertures in the gate insulating film and the interlayer insulating film are exposed in the aperture region. Because light from the backlight is reflected at the interface of the aperture edges exposed in the aperture region, a problem arises in which the amount of transmitted light in the aperture region decreases. In addition, because ambient light is reflected by the tapered end face of the aperture edges exposed in the aperture region, a problem arises in which the display quality decreases.

[0005] The technology described herein was developed based on the circumstances described above and aims to suppress light reflection at the aperture edge of the first aperture. [Means for solving the problem]

[0006] (1) A display substrate relating to the technology described herein comprises a light-transmitting substrate, a first insulating film disposed on the light-transmitting substrate, a second insulating film disposed on the first insulating film and having a refractive index different from that of the first insulating film, and a pixel electrode, wherein the first insulating film and the second insulating film are provided with a first opening that overlaps with at least a portion of the pixel electrode, and the opening edge of the first opening is configured to be along the normal to the main surface of the light-transmitting substrate.

[0007] (2) In addition to (1) above, the display substrate may also include a third insulating film disposed beneath the first insulating film on the light-transmitting substrate, wherein the first opening may be continuously provided in the third insulating film.

[0008] (3) In addition to (1) or (2) above, the display substrate may also include a first light-shielding portion that covers the opening edge of the first opening in the first insulating film and the second insulating film and blocks light.

[0009] (4) In addition to (3) above, the display substrate may also include an electrode made of a part of a metal film disposed on the second insulating film, and the first light-shielding portion may be made of a part of the metal film.

[0010] (5) A display device relating to the technology described herein comprises a display substrate as described in any of (1) to (4) above, and a counter substrate disposed opposite to the display substrate.

[0011] (6) In addition to (5) above, the display device may also have a second light-shielding portion on the opposing substrate that blocks light, and the second light-shielding portion may have a second aperture that overlaps with at least a portion of the pixel electrode and the first aperture.

[0012] (7) A method for manufacturing a display substrate relating to the technology described herein includes: forming a first insulating film on a light-transmitting substrate; forming a second insulating film on the first insulating film; forming a mask film made of a semiconductor material or a transparent electrode material on the second insulating film; selectively etching the mask film to provide a third opening; etching the first insulating film and the second insulating film through the third opening of the mask film; providing a first opening in the first insulating film and the second insulating film that overlaps with the third opening of the mask film; and providing a pixel electrode in which at least a portion overlaps with the first opening.

[0013] (8) In addition to (7) above, the method for manufacturing the display substrate may also involve: forming a semiconductor film on the translucent substrate before forming the first insulating film; selectively etching the semiconductor film to provide a semiconductor portion; selectively etching the mask film to provide a fourth opening that overlaps with a part of the semiconductor portion together with the third opening; etching the first insulating film and the second insulating film through the third and fourth openings of the mask film; providing a fifth opening in the first insulating film and the second insulating film that overlaps with the fourth opening of the mask film together with the first opening; and after etching the first insulating film and the second insulating film, supplying a cleaning agent containing hydrofluoric acid onto the mask film to clean the portion of the semiconductor portion facing the fifth opening through the fifth opening and to remove the mask film.

[0014] (9) In addition to the above (7) or (8), the method for manufacturing the display substrate may also involve wet etching the mask film to provide the third opening, and then dry etching the first insulating film and the second insulating film through the third opening in the mask film to provide the first opening.

[0015] (10) In addition to any of (7) to (9) above, the method for manufacturing the display substrate may also involve forming a third insulating film on the light-transmitting substrate before forming the first insulating film, etching the third insulating film in addition to the first insulating film and the second insulating film through the third opening of the mask film, so that the first opening is continuous across the first insulating film, the second insulating film and the third insulating film.

[0016] (11) In addition to any of (7) to (10) above, the method for manufacturing the display substrate may also involve forming the first opening in the first insulating film and the second insulating film, then forming a metal film on the second insulating film, and selectively etching the metal film to provide a first light-shielding portion that covers the opening edge of the first opening.

[0017] (12) Further, in addition to the above (11), the method for manufacturing the display substrate may include selectively etching the metal film to provide an electrode together with the first light-shielding portion.

Advantages of the Invention

[0018] According to the technology described in this specification, it is possible to suppress the reflection of light at the opening edge of the opening.

Brief Description of the Drawings

[0019] [Figure 1] Plan view of the liquid crystal panel, driver, and flexible substrate constituting the liquid crystal display device according to Embodiment 1 [Figure 2] Cross-sectional view of the liquid crystal panel, driver, and flexible substrate according to Embodiment 1 [Figure 3] Circuit diagram showing the electrical configuration of the array substrate constituting the liquid crystal panel according to Embodiment 1 [Figure 4] Plan view showing the pixel arrangement of the array substrate according to Embodiment 1 [Figure 5] Cross-sectional view taken along line v-v of FIG. 4 in the liquid crystal panel according to Embodiment 1 [Figure 6] Cross-sectional view taken along line vi-vi of FIG. 4 in the liquid crystal panel according to Embodiment 1 [Figure 7] Cross-sectional view taken along line vii-vii of FIG. 4 in the liquid crystal panel according to Embodiment 1 [Figure 8] Cross-sectional view similar to FIG. 5 showing the state where the first interlayer insulating film, the second interlayer insulating film, the mask film, and the first photoresist film are formed in the fifth step after passing through the first to fourth steps included in the array substrate manufacturing process according to Embodiment 1 [Figure 9] Cross-sectional view similar to FIG. 5 showing the state where the first photoresist film is exposed and developed in the fifth step included in the array substrate manufacturing process according to Embodiment 1 [Figure 10] Cross-sectional view similar to FIG. 5 showing the state where the mask film is wet-etched in the fifth step included in the array substrate manufacturing process according to Embodiment 1 [Figure 11]A cross-sectional view similar to Figure 5, showing the state in which the first interlayer insulating film and the second interlayer insulating film have been dry-etched in the fifth step included in the array substrate manufacturing process according to Embodiment 1. [Figure 12] A cross-sectional view similar to Figure 5, showing the state after the mask film has been removed by supplying cleaning solution in the sixth step included in the array substrate manufacturing process according to Embodiment 1. [Figure 13] A cross-sectional view similar to Figure 5, showing the state after the second metal film and the second photoresist film have been formed in the seventh step of the array substrate manufacturing process according to Embodiment 1, and after the second photoresist film has been exposed and developed. [Figure 14] A cross-sectional view similar to Figure 5, showing the state after the second metal film has been etched in the seventh step included in the array substrate manufacturing process according to Embodiment 1. [Figure 15] A cross-sectional view similar to Figure 5 of the liquid crystal panel according to Embodiment 2. [Figure 16] A cross-sectional view similar to Figure 6 of the liquid crystal panel according to Embodiment 2. [Figure 17] A cross-sectional view similar to Figure 7 of the liquid crystal panel according to Embodiment 2. [Figure 18] A cross-sectional view similar to Figure 5, showing the state after the second metal film and the second photoresist film have been formed in the seventh step included in the array substrate manufacturing process according to Embodiment 2, and after the second photoresist film has been exposed and developed. [Figure 19] A cross-sectional view similar to Figure 5, showing the state after the second metal film has been etched in the seventh step included in the array substrate manufacturing process according to Embodiment 2. [Modes for carrying out the invention]

[0020] <Embodiment 1> Embodiment 1 will be explained with reference to Figures 1 to 14. In this embodiment, a liquid crystal display device 10 is illustrated. Note that parts of each figure show the X, Y, and Z axes, and each axis is drawn so that it corresponds to the direction shown in each figure. Also, the upper side of Figures 2, 5 to 14 is considered the front side, and the lower side of the same figure is considered the back side.

[0021] As shown in Figure 1, the liquid crystal display device 10 comprises at least a horizontally elongated rectangular liquid crystal panel (display device, display panel) 11 capable of displaying images, and a backlight device (illumination device) that irradiates the liquid crystal panel 11 with light for display purposes. The backlight device is positioned on the back side (rear side) of the liquid crystal panel 11 and includes a light source that emits white light (e.g., an LED) and an optical component that converts the light from the light source into planar light by applying an optical effect. The central part of the main surface of the liquid crystal panel 11 is designated as a display area AA where images are displayed. In contrast, the frame-like outer peripheral part of the main surface of the liquid crystal panel 11 surrounding the display area AA is designated as a non-display area NAA where images are not displayed.

[0022] The liquid crystal panel 11 will be described with reference to Figure 2 in addition to Figure 1. As shown in Figures 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. Of the pair of substrates 20 and 21, the front side is the opposing substrate 20, and the back side is the array substrate (display substrate) 21. Both the opposing substrate 20 and the array substrate 21 are formed by laminating various films on the inner surface of light-transmitting glass substrates (light-transmitting substrates) 20GS and 21GS. A liquid crystal layer 22 containing liquid crystal molecules, which are substances whose optical properties change when an electric field is applied, is interposed between the pair of substrates 20 and 21. A sealing portion 23 is provided between the outer edges of the pair of substrates 20 and 21 to seal the liquid crystal layer 22. The sealing portion 23 is formed in the shape of a rectangular frame surrounding the liquid crystal layer 22. Polarizing plates 14 are attached to the outer surfaces of both substrates 20 and 21.

[0023] As shown in Figures 1 and 2, the opposing substrate 20 has a shorter short side dimension than the array substrate 21. The opposing substrate 20 is bonded to the array substrate 21 such that one end in the short side direction (Y-axis direction) is aligned with it. Therefore, the other end of the array substrate 21 in the short side direction is an exposed portion 21A that protrudes laterally from the opposing substrate 20. This exposed portion 21A is entirely a non-display area (NAA), and the driver 12 and flexible substrate 13 for supplying various signals are mounted on it.

[0024] The driver 12 consists of an LSI chip with an internal drive circuit. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 using COG (Chip On Glass) mounting. The driver 12 processes various signals transmitted by the flexible substrate 13. As shown in Figures 1 and 2, the driver 12 is positioned adjacent to one side of the display area AA in the Y-axis direction, sandwiched between the flexible substrate 13 and the display area AA. The driver 12 has a horizontally elongated rectangular shape in its planar form. The driver 12 can supply various signals to source wiring 27 and the like provided on the array substrate 21. The flexible substrate 13 is constructed by forming a large number of wiring patterns on a substrate made of a synthetic resin material (e.g., polyimide resin) that has insulating and flexible properties. One end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit board (control board, etc.).

[0025] Next, the configuration of the display area AA on the array substrate 21 will be explained using Figure 3. As shown in Figure 3, at least TFTs (transistors, switching elements) 24 and pixel electrodes 25 are provided on the inner surface of the display area AA on the array substrate 21. Multiple TFTs 24 and pixel electrodes 25 are arranged in a matrix (arrangement) with spacing along the X-axis and Y-axis directions. Around these TFTs 24 and pixel electrodes 25, gate wiring (scanning wiring) 26 and source wiring (image wiring, signal wiring) 27 are arranged orthogonally (intersecting) with each other. Multiple gate wirings 26 extend along the X-axis direction and are arranged with spacing along the Y-axis direction. Multiple source wirings 27 extend along the Y-axis direction and are arranged with spacing along the X-axis direction. The TFT24 includes a gate electrode 24A connected to the gate wiring 26, a source electrode (electrode) 24B connected to the source wiring 27, a drain electrode (electrode) 24C connected to the pixel electrode 25, and a semiconductor portion 24D connected to the source electrode 24B and the drain electrode 24C. The TFT24 is driven based on a scanning signal supplied to the gate electrode 24A by the gate wiring 26. This scanning signal contains a potential higher than the threshold voltage of the TFT24. As a result, the potential related to the image signal supplied to the source electrode 24B by the source wiring 27 is supplied to the drain electrode 24C via the semiconductor portion 24D. Consequently, the pixel electrode 25 is charged to the potential related to the image signal.

[0026] As shown in Figure 4, the TFT 24 is positioned near the intersection of the gate wiring 26 and the source wiring 27. The pixel electrode 25 is positioned in the area surrounded by the gate wiring 26 and the source wiring 27, and its planar shape is, for example, a vertically elongated, roughly rectangular shape. More specifically, the pixel electrode 25 has a planar shape that is like a vertically elongated rectangle with one corner slightly cut out. As a result, the pixel electrode 25 does not overlap with most of the TFT 24 (including the gate electrode 24A and source electrode 24B), but it overlaps with a part of the TFT 24 (including the drain electrode 24C). Of the pixel electrode 25, the part that does not overlap with the TFT 24 is mainly the main body part 25A that contributes to the display. Of the pixel electrode 25, the part that overlaps with the TFT 24 is the connection part 25B that is connected to the drain electrode 24C.

[0027] The configuration of the display area AA on the opposing substrate 20 constituting the liquid crystal panel 11 will be explained with reference to Figure 5. As shown in Figure 5, the display area AA of the opposing substrate 20 is provided with a number of color filters 28 at positions that overlap with each pixel electrode 25 on the array substrate 21. The color filters 28 are arranged in an alternating pattern along the X-axis, with three colors exhibiting red (R), green (G), and blue (B). Each of the three color filters 28 extends along the Y-axis, so that the whole is arranged in a roughly striped pattern. The overlapping color filters 28 and pixel electrodes 25 constitute a pixel PX, which is a display unit. In this liquid crystal panel 11, the three color filters 28 arranged along the X-axis and the three pixel electrodes 25 facing each color filter 28 constitute three color pixels PX (red pixels, green pixels, and blue pixels), respectively. In this liquid crystal panel 11, three adjacent color pixels PX along the X-axis constitute a display pixel capable of displaying a predetermined gradation of color.

[0028] As shown in Figure 5, the display area AA of the opposing substrate 20 is provided with a black matrix (second light-shielding area) 29 that separates the spaces (boundaries) between adjacent pixels PX in the X-axis and Y-axis directions, respectively. The black matrix 29 is provided not only in the display area AA but also in the non-display area NAA. In the display area AA, the black matrix 29 has a grid-like structure that overlaps with the TFT 24, gate wiring 26, and source wiring 27, but in the non-display area NAA, it is generally solid. In the display area AA, the black matrix 29 has pixel apertures (second apertures) 29A at positions that overlap with the pixels PX (pixel electrodes 25). The number and spacing of the pixel apertures 29A match the number and spacing of the pixels PX. Specifically, the pixel apertures 29A do not overlap with the connection portion 25B of the pixel electrodes 25 provided on the array substrate 21, but are arranged to overlap with the main body portion 25A, and are slightly smaller in size than the main body portion 25A when viewed in plan. The pixel aperture 29A is sized to overlap most of the main body portion 25A, excluding the outer edge, and not overlap with the outer edge portion of the main body portion 25A.

[0029] As shown in Figure 5, an overcoat film 30 is provided on the upper side of the color filter 28 and the black matrix 29. The overcoat film 30 is provided in a solid form over almost the entire surface of the opposing substrate 20. The overcoat film 30 is made of an organic material such as acrylic resin (e.g., PMMA) and functions to flatten any steps that occur on the layer below it. Of both substrates 20 and 21, an alignment film (not shown) is formed on the innermost surface (uppermost layer) in contact with the liquid crystal layer 22 to align the liquid crystal molecules contained in the liquid crystal layer 22.

[0030] Furthermore, either the opposing substrate 20 or the array substrate 21 is provided with a common electrode (not shown) made of the same transparent electrode material as the pixel electrodes 25, which is superimposed on the pixel electrodes 25 at a distance from them. The common electrode extends over at least almost the entire display area AA and is arranged to superimpose on all pixel electrodes 25 at a distance from them. The liquid crystal panel 11 applies a predetermined electric field to the liquid crystal layer 22 based on the potential difference generated between this common electrode and each pixel electrode 25, thereby enabling each pixel PX to display a predetermined grayscale.

[0031] Here, the various films laminated on the inner surface of the array substrate 21 will be explained with reference to Figure 5. As shown in Figure 5, the glass substrate 21GS of the array substrate 21 has at least the following layers laminated in order from the bottom layer side (glass substrate 21GS side): base coat film (third insulating film) 31, semiconductor film, gate insulating film (third insulating film) 32, first metal film, first interlayer insulating film (first insulating film) 33, second interlayer insulating film (second insulating film) 34, second metal film (metal film) MF2, planarization film (fourth insulating film) 35, first transparent electrode film, and alignment film. Of these, the second metal film MF2 is shown in Figure 13.

[0032] The first metal film and the second metal film MF2 are both conductive, being single-layer films made of one type of metal material or multilayer films or alloys made of different types of metal materials. The first metal film constitutes the gate wiring 26, the gate electrode 24A of the TFT 24, etc. The second metal film MF2 constitutes the source wiring 27, the source electrode 24B and drain electrode 24C of the TFT 24, etc.

[0033] The semiconductor film consists of a crystalline polysilicon semiconductor material (semiconductor material) prepared by known methods such as laser crystallization. The polysilicon semiconductor material of the semiconductor film has higher electron mobility compared to amorphous silicon semiconductor materials and oxide semiconductor materials. The semiconductor film constitutes the semiconductor portion 24D of the TFT 24, etc. The first transparent electrode film consists of a transparent electrode material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The first transparent electrode film constitutes the pixel electrode 25, etc.

[0034] The base coat film 31, gate insulating film 32, first interlayer insulating film 33, and second interlayer insulating film 34 are all single-layer or multilayer films made of inorganic materials (inorganic resin materials). Of these, the gate insulating film 32 and the first interlayer insulating film 33 are both single-layer films made of SiO2 (silicon oxide, silicon oxide), which is a type of inorganic material, and their refractive index is approximately 1.4 to 1.55. Therefore, there is almost no difference in refractive index between the gate insulating film 32 and the first interlayer insulating film 33. The second interlayer insulating film 34 is made of SiN, which is a type of inorganic material. x The second interlayer insulating film 34 is a single layer film made of silicon nitride, and its refractive index is approximately 2. Therefore, the refractive index of the second interlayer insulating film 34 is greater than that of the gate insulating film 32 and the first interlayer insulating film 33. The planarization film 35 is made of an organic material such as PMMA (acrylic resin). The thickness of the planarization film 35 is much greater than the thickness of the base coat film 31, the gate insulating film 32, the first interlayer insulating film 33, and the second interlayer insulating film 34. This planarization film 35 planarizes the inner surface of the array substrate 21 (the surface on the liquid crystal layer 22 side). The base coat film 31 is located on the lower layer side of the semiconductor film. The gate insulating film 32 is interposed between the semiconductor film and the first metal film. The first interlayer insulating film 33 and the second interlayer insulating film 34 are interposed between the first metal film and the second metal film MF2. The planarization film 35 is interposed between the second metal film MF2 and the first transparent electrode film.

[0035] The detailed configuration of the TFT24 will now be explained. As shown in Figure 5, the gate electrode 24A, which is made up of a part of the first metal film, is superimposed on the upper layer side of the semiconductor portion 24D, which is made up of a part of the semiconductor film, via a gate insulating film 32. In other words, the TFT24 can be said to be a top-gate type transistor. As shown in Figures 4 and 5, the semiconductor portion 24D has a horizontally elongated rectangular shape that extends along the X-axis. The gate electrode 24A is superimposed on the central portion of the semiconductor portion 24D in the length direction (X-axis direction). The source electrode 24B and drain electrode 24C, each made up of a part of the second metal film MF2, are positioned at intervals from each other in the X-axis direction, with the gate electrode 24A in between, and are superimposed on the end portions of the semiconductor portion 24D in the length direction, respectively.

[0036] As shown in Figure 5, the gate insulating film 32, first interlayer insulating film 33, and second interlayer insulating film 34 interposed between the source electrode 24B and drain electrode 24C and the semiconductor portion 24D have first pixel contact holes (fifth openings) CH1 in communication at positions overlapping with both the source electrode 24B and the semiconductor portion 24D, and at positions overlapping with both the drain electrode 24C and the semiconductor portion 24D. The source electrode 24B and the semiconductor portion 24D are connected through one of the first pixel contact holes CH1. The drain electrode 24C and the semiconductor portion 24D are connected through the other first pixel contact hole CH1. The connection portion 25B of the pixel electrode 25, which is part of the first transparent electrode film, is arranged to overlap with the drain electrode 24C. The planarization film 35 interposed between the connection portion 25B and the drain electrode 24C has a second pixel contact hole CH2 at a position overlapping with both the connection portion 25B and the drain electrode 24C. The connection portion 25B and the drain electrode 24C are connected through the second pixel contact hole CH2. In this embodiment, the second pixel contact hole CH2 is arranged superimposed on the other first pixel contact hole CH1.

[0037] The array substrate 21 according to this embodiment has a structure in which a first interlayer insulating film 33 and a second interlayer insulating film 34 having a higher refractive index than the first interlayer insulating film 33 are laminated together. As a result, not all of the light irradiated onto the liquid crystal panel 11 from the backlight device passes through the first interlayer insulating film 33 and the second interlayer insulating film 34, and some is reflected at the interface between the first interlayer insulating film 33 and the second interlayer insulating film 34. Therefore, there is a concern that the amount of light transmitted through the main body 25A and the pixel aperture 29A of the pixel electrode 25, that is, the amount of light transmitted to the pixel PX, will be insufficient.

[0038] In this embodiment, as shown in Figures 5 to 7, the first interlayer insulating film 33 and the second interlayer insulating film 34 are provided with a first aperture 36 at a position that overlaps with at least a portion of the pixel electrode 25. In this way, the light irradiated from the backlight device onto the liquid crystal panel 11 that is directed toward the pixel electrode 25 is less likely to pass through the first aperture 36 and be reflected at the interface between the first interlayer insulating film 33 and the second interlayer insulating film 34. This ensures that the amount of transmitted light to the pixel PX is sufficient. The first aperture 36 is formed over a range that overlaps with the main body portion 25A (pixel aperture 29A) of the pixel electrode 25, and is arranged not to overlap with the connecting portion 25B of the pixel electrode 25. This ensures that the amount of transmitted light to the main body portion 25A of the pixel electrode 25 that contributes to display is sufficient.

[0039] Furthermore, in this embodiment, as shown in Figures 5 to 7, the first interlayer insulating film 33 and the second interlayer insulating film 34 are configured such that the opening edge of the first opening 36 aligns with the normal to the main surface of the glass substrate 21GS and is parallel to the Z-axis direction. The expression "the opening edge of the first opening 36 is configured to align with the normal to the main surface of the glass substrate 21GS" includes not only the case where the opening edge of the first opening 36 is a straight line parallel to the Z-axis direction (perpendicular to the main surface of the glass substrate 21GS), but also cases where the opening edge of the first opening 36 is inclined by, for example, ±5° with respect to the Z-axis direction. In this way, compared to the conventional case where the opening edges of the gate insulating film and interlayer insulating film are tapered and inclined with respect to the normal to the substrate, the overlap range between the opening edge of the first opening 36 and the pixel electrode 25 is narrowed, or the opening edge of the first opening 36 and the pixel electrode 25 are not in an overlapping relationship. Furthermore, compared to the conventional design, the area in which the aperture edge of the first aperture 36 is exposed to the pixel aperture 29A of the black matrix 29 is narrowed or not exposed at all. As a result, light directed toward the pixel electrode 25 is less likely to be reflected at the interface of the portion of the first interlayer insulating film 33 and the second interlayer insulating film 34 that constitutes the aperture edge of the first aperture 36, and external light is less likely to be reflected by the end face of the aperture edge of the first aperture 36. Consequently, a larger amount of transmitted light can be secured in the pixel aperture 29A (pixel PX), and unwanted external light reflection is suppressed, thereby maintaining good display quality.

[0040] In this embodiment, the base coat film 31 and gate insulating film 32, which are located beneath the first interlayer insulating film 33 on the glass substrate 21GS, have a continuous first opening 36, as shown in Figures 5 to 7. That is, the first opening 36 penetrates all the insulating films 31 to 34 located below the planarization film 35 on the array substrate 21. The opening edge of the first opening 36 is configured to follow the normal to the main surface of the glass substrate 21GS across the base coat film 31, gate insulating film 32, first interlayer insulating film 33, and second interlayer insulating film 34. If the first opening 36 were not formed in the base coat film 31 and the gate insulating film 32, there is a risk that the portion of the base coat film 31 and the gate insulating film 32 that overlaps with the first opening 36 would be removed by etching when forming the first opening 36 in the first interlayer insulating film 33 and the second interlayer insulating film 34. This would result in variations in the film thickness of the portion of the base coat film 31 and the gate insulating film 32 that overlaps with the first opening 36, potentially causing unevenness in the amount of transmitted light or color unevenness. In this embodiment, however, by providing the first opening 36 across the first interlayer insulating film 33, the second interlayer insulating film 34, the base coat film 31, and the gate insulating film 32, the occurrence of such unevenness in the amount of transmitted light and color unevenness can be avoided. Furthermore, by configuring the aperture edge of the first aperture 36 to align with the normal to the main surface of the glass substrate 21GS, light directed toward the pixel electrode 25 is less likely to be reflected at the interface of the portion of the first interlayer insulating film 33, the second interlayer insulating film 34, the base coat film 31, and the gate insulating film 32 that constitutes the aperture edge of the first aperture 36, and external light is less likely to be reflected by the end face at the aperture edge of the first aperture 36.

[0041] This embodiment has the structure described above, and next, the manufacturing method of the liquid crystal panel 11 will be explained. The manufacturing method of the liquid crystal panel 11 includes a counter substrate manufacturing process for manufacturing the counter substrate 20, an array substrate manufacturing process for manufacturing the array substrate 21, and a bonding process for bonding the manufactured counter substrate 20 and the array substrate 21 together. Below, the array substrate manufacturing process (manufacturing method of the array substrate 21) will be explained.

[0042] The array substrate manufacturing process includes at least the following steps: a first step of forming a base coat film 31; a second step of forming and patterning a semiconductor film; a third step of forming a gate insulating film 32; a fourth step of forming and patterning a first metal film; a fifth step of forming and patterning a first interlayer insulating film 33 and a second interlayer insulating film 34, etc.; a sixth step of cleaning the semiconductor portion 24D; a seventh step of forming and patterning a second metal film MF2; an eighth step of forming and patterning a planarization film 35; and a ninth step of forming and patterning a first transparent electrode film.

[0043] The term "patterning" used above refers to the processing of a film based on a general photolithography method. Specifically, a photoresist film is deposited on the film to be processed, the photoresist film is exposed using an exposure device through a photomask having a predetermined aperture pattern, the photoresist film is developed, and etching is performed through the developed photoresist film to process the film, i.e., pattern the film.

[0044] In the first step, a base coat film 31 is deposited on the glass substrate 21GS (see Figures 5 to 7). In the second step, a semiconductor film is deposited on the base coat film 31 and the semiconductor film is selectively etched by photolithography. This forms the semiconductor portion 24D of the TFT 24 (see Figure 5). In the third step, a gate insulating film 32 is deposited on the base coat film 31 and the semiconductor film (see Figures 5 to 7). In the fourth step, a first metal film is deposited on the gate insulating film 32 and the first metal film is selectively etched by photolithography. This forms the gate electrode 24A and gate wiring 26 of the TFT 24 (see Figures 4 and 5).

[0045] In the fifth step, a first interlayer insulating film 33 is deposited on the gate insulating film 32 and the first metal film, and then a second interlayer insulating film 34 is deposited on the first interlayer insulating film 33. Then, as shown in Figure 8, a mask film MF1 is deposited on the second interlayer insulating film 34, and then a first photoresist film PR1 is deposited on the mask film MF1. The first photoresist film PR1 may be either positive or negative. Here, the mask film MF1 functions as a mask when patterning the first interlayer insulating film 33 and the second interlayer insulating film 34, as will be described in detail later. The mask film MF1 has a smaller film thickness than the first photoresist film PR1. Specifically, while the film thickness of the first photoresist film PR1 is about a few micrometers, the film thickness of the mask film MF1 is about a few tens of nanometers. In this embodiment, the mask film MF1 is made of an oxide semiconductor material, which is a type of semiconductor material. The oxide semiconductor material constituting the mask film MF1 may contain at least one metal element from among In, Ga, and Zn, for example, an In-Ga-Zn-O semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not particularly limited, and include, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. The In-Ga-Zn-O semiconductor used for the semiconductor film may be amorphous or crystalline. The oxide semiconductor material constituting the mask film MF1 may contain other oxide semiconductors instead of the In-Ga-Zn-O semiconductor. For example, it may contain an In-Sn-Zn-O semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). In-Sn-Zn-O semiconductors are ternary oxides of indium (In), tin (Sn), and zinc (Zn).Alternatively, the oxide semiconductor layer may contain W (tungsten)-containing In-W-Zn-O semiconductors, In-W-Sn-Zn-O semiconductors, In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, etc.

[0046] In the fifth step, as shown in Figure 8, after sequentially depositing the first interlayer insulating film 33, the second interlayer insulating film 34, the mask film MF1, and the first photoresist film PR1 as described above, the first photoresist film PR1 is exposed using an exposure apparatus and a photomask (not shown along with the exposure apparatus) having a predetermined aperture pattern, and then developed. As a result, the first photoresist film PR1 remains on the mask film MF1 with the aperture pattern of the photomask transferred onto it. Specifically, if the first photoresist film PR1 is positive type, an unexposed portion that does not overlap with the aperture of the photomask remains, and if the first photoresist film PR1 is negative type, an exposed portion that overlaps with the aperture of the photomask remains. As shown in Figure 9, the remaining first photoresist film PR1 has a first resist aperture PR1A that overlaps with the planned formation position of the first aperture 36, and a second resist aperture PR1B that overlaps with the planned formation position of the first pixel contact hole CH1. The opening edges of the first resist opening PR1A and the second resist opening PR1B in the first photoresist film PR1 are tapered (inclined) with respect to the normal to the main surface of the glass substrate 21GS.

[0047] The mask film MF1 is wet-etched using the first photoresist film PR1 having the above configuration as a mask. As shown in Figure 10, the portion of the mask film MF1 that overlaps with the first photoresist film PR1 remains, while the portions exposed to the first resist opening PR1A and the second resist opening PR1B are selectively dissolved and removed by the etching solution. This wet etching provides the mask film MF1 with a first mask opening (third opening) MF1A that overlaps with the first resist opening PR1A, and a second mask opening (fourth opening) MF1B that overlaps with the second resist opening PR1B. Here, since the thickness of the mask film MF1 is sufficiently smaller than the thickness of the first photoresist film PR1, the edges of the first mask opening MF1A and the second mask opening MF1B are parallel (approximately parallel) to the normal to the main surface of the glass substrate 21GS.

[0048] In the fifth step, the mask film MF1 patterned as described above is used as a mask to sequentially dry etch the first interlayer insulating film 33, the second interlayer insulating film 34, the gate insulating film 32, and the base coat film 31 from the top layer. As a result, as shown in Figure 11, the portions of the first interlayer insulating film 33, the second interlayer insulating film 34, the gate insulating film 32, and the base coat film 31 that overlap with the first mask opening MF1A are removed, and the portions of the first interlayer insulating film 33, the second interlayer insulating film 34, and the gate insulating film 32 that overlap with the second mask opening MF1B are removed. The portions of the first interlayer insulating film 33, the second interlayer insulating film 34, and the gate insulating film 32 that overlap with the first photoresist film PR1 remain. The portions of the base coat film 31 that overlap with the first photoresist film PR1 and the second mask opening MF1B remain.

[0049] When the first interlayer insulating film 33, the second interlayer insulating film 34, the gate insulating film 32, and the base coat film 31 are selectively dry-etched through the first mask opening MF1A of the mask layer MF1, a first opening 36 is formed in communication with the first mask opening MF1A, as shown in Figure 11. Here, as described above, the opening edge of the first mask opening MF1A in the mask film MF1 made of semiconductor material is parallel to the normal to the main surface of the glass substrate 21GS. By using a mask film MF1 with such a configuration as a mask and dry-etching the first interlayer insulating film 33, the second interlayer insulating film 34, the gate insulating film 32, and the base coat film 31, it becomes easy to configure the opening edge of the first opening 36 to be aligned with the normal to the main surface of the glass substrate 21GS. Consequently, the portion of the glass substrate 21GS that overlaps with the first opening 36 becomes exposed. Similarly, when the first interlayer insulating film 33, the second interlayer insulating film 34, and the gate insulating film 32 are selectively dry-etched through the second mask opening MF1B of the mask layer MF1, a first pixel contact hole CH1, which overlaps with the second mask opening MF1B, is formed in communication with the first interlayer insulating film 33, the second interlayer insulating film 34, and the gate insulating film 32. Consequently, the portion of the semiconductor portion 24D that overlaps with the first pixel contact hole CH1 becomes exposed. After the dry etching of the first interlayer insulating film 33, the second interlayer insulating film 34, the gate insulating film 32, and the base coat film 31 is completed in this manner, the first photoresist film PR1 is removed with a stripping solution. It is also possible to remove the first photoresist film PR1 prior to dry etching.

[0050] In the sixth step, as shown in Figure 12, a cleaning agent containing, for example, hydrofluoric acid is supplied onto the mask film MF1. This cleans the surface of the semiconductor portion 24D exposed through the first pixel contact hole CH1, thereby removing the oxide film that had formed on the surface of the semiconductor portion 24D. At this time, the mask film MF1 is removed mainly by being dissolved by hydrofluoric acid. In this way, since the mask film MF1 can be removed in the sixth step of cleaning the semiconductor portion 24D, the cycle time can be shortened compared to a case where a dedicated step for removing the mask film MF1 was required.

[0051] In the seventh step, a second metal film MF2 is deposited on the second interlayer insulating film 34, and then a second photoresist film PR2 is deposited on the second metal film MF2. After that, the second photoresist film PR2 is exposed using an exposure apparatus and a photomask having a predetermined aperture pattern (neither the exposure apparatus nor the photomask is shown), and then developed. As a result, the second photoresist film PR2 remains on the second metal film MF2 with the aperture pattern of the photomask transferred onto it. Specifically, if the second photoresist film PR2 is positive type, an unexposed portion that does not overlap with the aperture of the photomask remains, and if the second photoresist film PR2 is negative type, an exposed portion that overlaps with the aperture of the photomask remains. As shown in Figure 13, the second photoresist film PR2 remains at the planned formation positions of the source electrode 24B, the drain electrode 24C, and the source wiring 27.

[0052] The second metal film MF2 is wet-etched or dry-etched using the second photoresist film PR2 with this pattern as a mask. As a result, as shown in Figure 14, the portion of the second metal film MF2 that overlaps with the second photoresist film PR2 is selectively retained, and the portion that does not overlap with the second photoresist film PR2 is selectively removed. This forms the source electrode 24B, drain electrode 24C, and source wiring 27 of the TFT 24 (see Figures 4 and 5). The source electrode 24B is connected to the semiconductor portion 24D through one of the first pixel contact holes CH1. The drain electrode 24C is connected to the semiconductor portion 24D through the other first pixel contact hole CH1.

[0053] In the eighth step, a planarization film 35 is deposited on the second interlayer insulating film 34 and the second metal film MF2, and the planarization film 35 is selectively etched by photolithography. As a result, a second pixel contact hole CH2 is formed on the planarization film 35 at a position overlapping with the drain electrode 24C (see Figure 5). In the ninth step, a first transparent electrode film is deposited on the planarization film 35, and the first transparent electrode film is selectively etched by photolithography. As a result, the pixel electrode 25 is formed (see Figure 5). The connection portion 25B of the pixel electrode 25 is connected to the drain electrode 24C through the second pixel contact hole CH2.

[0054] In this embodiment, as shown in Figure 11, in the fifth step, the first interlayer insulating film 33, the second interlayer insulating film 34, the gate insulating film 32, and the base coat film 31 are etched using a mask film MF1 made of semiconductor material as a mask to form the first opening 36. This makes it easy to configure the opening edge of the first opening 36 to align with the normal to the main surface of the glass substrate 21GS. In this way, the opening edge of the first opening 36 and the main body portion 25A of the pixel electrode 25 are not superimposed. Compared to the conventional case where the opening edge of the opening in the gate insulating film and interlayer insulating film is tapered and inclined with respect to the normal to the substrate, light directed toward the pixel electrode 25 is less likely to be reflected at the interface of the portion of the first interlayer insulating film 33 and the second interlayer insulating film 34 that constitutes the opening edge of the first opening 36, and external light is less likely to be reflected by the end face of the opening edge of the first opening 36. Furthermore, in this embodiment, since the first opening 36 is provided across the first interlayer insulating film 33, the second interlayer insulating film 34, the base coat film 31, and the gate insulating film 32, compared to the case where the first opening is not formed in the base coat film 31 and the gate insulating film 32, situations such as unevenness in the amount of light transmitted through the main body portion 25A of the pixel electrode 25 or color unevenness are avoided.

[0055] As described above, the array substrate (display substrate) 21 of this embodiment comprises a light-transmitting glass substrate (light-transmitting substrate) 21GS, a first interlayer insulating film (first insulating film) 33 disposed on the glass substrate 21GS, a second interlayer insulating film (second insulating film) 34 disposed on the first interlayer insulating film 33 and having a different refractive index from the first interlayer insulating film 33, and a pixel electrode 25. The first interlayer insulating film 33 and the second interlayer insulating film 34 are provided with a first opening 36 that overlaps with at least a part of the pixel electrode 25, and the opening edge of the first opening 36 is configured to be along the normal (Z-axis direction) to the main surface of the glass substrate 21GS.

[0056] Light reflection can occur at the interface between the first interlayer insulating film 33 and the second interlayer insulating film 34, which have different refractive indices. Since the first interlayer insulating film 33 and the second interlayer insulating film 34 are provided with a first aperture 36 that overlaps with at least a portion of the pixel electrode 25, it is less likely that light directed toward the pixel electrode 25 will be reflected at the interface between the first interlayer insulating film 33 and the second interlayer insulating film 34. Furthermore, since the aperture edge of the first aperture 36 is configured to align with the normal to the main surface of the glass substrate 21GS, compared to the case where the aperture edge of the aperture in the conventional gate insulating film and interlayer insulating film is tapered with respect to the normal to the substrate, the overlapping range between the aperture edge of the first aperture 36 and the pixel electrode 25 is narrowed, or the aperture edge of the first aperture 36 and the pixel electrode 25 do not overlap. As a result, light directed towards the pixel electrode 25 is less likely to be reflected at the interface of the portion of the first interlayer insulating film 33 and the second interlayer insulating film 34 that constitutes the aperture edge of the first aperture 36, and external light is less likely to be reflected by the end face at the aperture edge of the first aperture 36.

[0057] Furthermore, the glass substrate 21GS includes a base coat film (third insulating film) 31 and a gate insulating film (third insulating film) 32 disposed beneath the first interlayer insulating film 33, and a first opening 36 is continuously provided in the base coat film 31 and the gate insulating film 32. The first opening 36 is continuously provided not only in the first interlayer insulating film 33 and the second interlayer insulating film 34, but also in the base coat film 31 and the gate insulating film 32 disposed beneath the first interlayer insulating film 33 on the glass substrate 21GS. If the first opening 36 is not formed in the base coat film 31 and the gate insulating film 32, there is a risk that the portion of the base coat film 31 and the gate insulating film 32 that overlaps with the first opening 36 will be removed by etching when forming the first opening 36 in the first interlayer insulating film 33 and the second interlayer insulating film 34. If this happens, variations in the film thickness of the portion of the base coat film 31 and the gate insulating film 32 that overlaps with the first opening 36 may occur, resulting in uneven light transmission or color unevenness. In this regard, by providing the first aperture 36 across the first interlayer insulating film 33, the second interlayer insulating film 34, the base coat film 31, and the gate insulating film 32, the occurrence of unevenness in transmitted light and color unevenness as described above can be avoided. Moreover, by configuring the aperture edge of the first aperture 36 to align with the normal to the main surface of the glass substrate 21GS, light directed toward the pixel electrode 25 is less likely to be reflected at the interface of the portion of the first interlayer insulating film 33, the second interlayer insulating film 34, the base coat film 31, and the gate insulating film 32 that constitutes the aperture edge of the first aperture 36, and external light is less likely to be reflected by the end face at the aperture edge of the first aperture 36.

[0058] The liquid crystal panel (display device) 11 of this embodiment comprises the array substrate 21 described above and a counter substrate 20 arranged opposite the array substrate 21. With a liquid crystal panel 11 having such a configuration, light reflection at the aperture edge of the first aperture 36 is suppressed, so that good display quality can be maintained.

[0059] Furthermore, the opposing substrate 20 is equipped with a black matrix (second light-shielding portion) 29 that blocks light, and the black matrix 29 has a pixel aperture (second aperture) 29A that overlaps with at least a portion of the pixel electrode 25 and the first aperture 36. An image can be displayed using light that has passed through the first aperture 36 and the pixel electrode 25 and through the pixel aperture 29A of the black matrix 29.

[0060] The manufacturing method for the array substrate 21 of this embodiment involves forming a first interlayer insulating film 33 on a glass substrate 21GS, forming a second interlayer insulating film 34 on the first interlayer insulating film 33, forming a mask film MF1 made of a semiconductor material or a transparent electrode material on the second interlayer insulating film 34, selectively etching the mask film MF1 to provide a first mask opening (third opening) MF1A, etching the first interlayer insulating film 33 and the second interlayer insulating film 34 through the first mask opening MF1A of the mask film MF1 to provide a first opening 36 in the first interlayer insulating film 33 and the second interlayer insulating film 34 that overlaps with the first mask opening MF1A of the mask film MF1, and providing a pixel electrode 25 in which at least a portion overlaps with the first opening 36.

[0061] After sequentially depositing a first interlayer insulating film 33, a second interlayer insulating film 34, and a mask film MF1 on a glass substrate 21GS, a first mask opening MF1A is formed in the mask film MF1 by selective etching. Subsequently, the first interlayer insulating film 33 and the second interlayer insulating film 34 are etched through the first mask opening MF1A of the mask film MF1, thereby forming a first opening 36 in the first interlayer insulating film 33 and the second interlayer insulating film 34 that overlaps with the first mask opening MF1A of the mask film MF1. After that, a pixel electrode 25 is formed, at least a portion of which overlaps with the first opening 36. In this way, since the first interlayer insulating film 33 and the second interlayer insulating film 34 are etched using a mask film MF1 made of a semiconductor material or a transparent electrode material as a mask, it becomes easy to configure the opening edge of the first opening 36 to follow the normal to the main surface of the glass substrate 21GS. In this way, compared to the case where the aperture edge of the gate insulating film and interlayer insulating film is tapered with respect to the normal to the substrate, the overlapping range between the aperture edge of the first aperture 36 and the pixel electrode 25 is narrowed, or the aperture edge of the first aperture 36 and the pixel electrode 25 become non-overlapping. As a result, light directed toward the pixel electrode 25 is less likely to be reflected at the interface of the portion of the first interlayer insulating film 33 and the second interlayer insulating film 34 that constitutes the aperture edge of the first aperture 36, and external light is less likely to be reflected by the end face of the aperture edge of the first aperture 36.

[0062] Furthermore, before forming the first interlayer insulating film 33, a semiconductor film is formed on the glass substrate 21GS, the semiconductor film is selectively etched to form a semiconductor portion 24D, the mask film MF1 is selectively etched to form a second mask opening (fourth opening) MF1B that overlaps with a part of the semiconductor portion 24D together with the first mask opening MF1A, the first interlayer insulating film 33 and the second interlayer insulating film 34 are etched through the first mask opening MF1A and the second mask opening MF1B of the mask film MF1 to form a first pixel contact hole (fifth opening) CH1 that overlaps with the second mask opening MF1B of the mask film MF1 together with the first opening 36 in the first interlayer insulating film 33 and the second interlayer insulating film 34, and after etching the first interlayer insulating film 33 and the second interlayer insulating film 34, a cleaning agent containing hydrofluoric acid is supplied onto the mask film MF1 to clean the portion of the semiconductor portion 24D facing the first pixel contact hole CH1 through the first pixel contact hole CH1 and remove the mask film MF1. A semiconductor portion 24D is formed by selectively etching a semiconductor film deposited on a glass substrate 21GS. By selectively etching the mask film MF1, a second mask opening MF1B is formed on the mask film MF1 along with a first mask opening MF1A. Subsequently, when the first interlayer insulating film 33 and the second interlayer insulating film 34 are etched through the first mask opening MF1A and the second mask opening MF1B of the mask film MF1, a first pixel contact hole CH1 is formed in the first interlayer insulating film 33 and the second interlayer insulating film 34, which overlaps with the second mask opening MF1B of the mask film MF1 along with the first opening 36. The semiconductor portion 24D is partially exposed through the first pixel contact hole CH1 of the first interlayer insulating film 33 and the second interlayer insulating film 34. When a cleaning agent containing hydrofluoric acid is supplied onto the mask film MF1 in this state, the portion of the semiconductor portion 24D facing the first pixel contact hole CH1 is cleaned through the first pixel contact hole CH1. At this time, the mask film MF1, which is made of semiconductor material or transparent electrode material, is dissolved by the cleaning agent, and as a result the mask film MF1 is removed. In this way, since the mask film MF1 can be removed in the process of cleaning the semiconductor part 24D, the cycle time can be shortened compared to when a dedicated process for removing the mask film MF1 is required.

[0063] Furthermore, a first mask opening MF1A is provided by wet etching the mask film MF1, and a first interlayer insulating film 33 and a second interlayer insulating film 34 are dry-etched through the first mask opening MF1A of the mask film MF1 to provide a first opening 36. By wet-etching the mask film MF1, which is made of a semiconductor material or a transparent electrode material, a first mask opening MF1A is provided in the mask film MF1. By dry-etching the first interlayer insulating film 33 and a second interlayer insulating film 34 through the first mask opening MF1A of the mask film MF1, a first opening 36 can be easily provided, configured such that the opening edge is aligned with the normal to the main surface of the glass substrate 21GS.

[0064] Furthermore, before depositing the first interlayer insulating film 33 on the glass substrate 21GS, a base coat film 31 and a gate insulating film 32 are deposited. The base coat film 31 and gate insulating film 32 are etched through the first mask opening MF1A of the mask film MF1, in addition to the first interlayer insulating film 33 and the second interlayer insulating film 34, so that a first opening 36 is provided that is continuous across the first interlayer insulating film 33, the second interlayer insulating film 34, the base coat film 31, and the gate insulating film 32. If the first opening 36 is not formed in the base coat film 31 and the gate insulating film 32, there is a risk that the portion of the base coat film 31 and the gate insulating film 32 that overlaps with the first opening 36 will be removed by etching when forming the first opening 36 in the first interlayer insulating film 33 and the second interlayer insulating film 34. If this happens, variations in the film thickness of the portion of the base coat film 31 and the gate insulating film 32 that overlaps with the first opening 36 may occur, resulting in uneven light transmission or color unevenness. In this respect, by forming the first opening 36 across the first interlayer insulating film 33, the second interlayer insulating film 34, the base coat film 31, and the gate insulating film 32, the occurrence of uneven light transmission and color unevenness as described above can be avoided. Furthermore, by configuring the aperture edge of the first aperture 36 to align with the normal to the main surface of the glass substrate 21GS, light directed toward the pixel electrode 25 is less likely to be reflected at the interface of the portion of the first interlayer insulating film 33, the second interlayer insulating film 34, the base coat film 31, and the gate insulating film 32 that constitutes the aperture edge of the first aperture 36, and external light is less likely to be reflected by the end face at the aperture edge of the first aperture 36.

[0065] <Embodiment 2> Embodiment 2 will be described with reference to Figures 15 to 19. This Embodiment 2 shows the case in which a first light-shielding portion 37 covering the opening edge of the first opening 136 is added. Note that redundant explanations of the structure, operation, and effects, which are the same as those of Embodiment 1 described above, will be omitted.

[0066] As shown in Figures 15 to 17, the array substrate 121 according to this embodiment is provided with a first light-shielding portion 37 that covers the opening edge of the first opening 136 in the first interlayer insulating film 133, the second interlayer insulating film 134, the gate insulating film 132, and the base coat film 131. The first light-shielding portion 37 is made of a light-shielding material that blocks light, and is made of, for example, a part of the second metal film MF102. Therefore, the first light-shielding portion 37 has at least a portion that is located on the upper side of the second interlayer insulating film 134. When viewed in plan, the first light-shielding portion 37 has an annular shape that extends around the entire circumference of the first opening 136. The first light-shielding portion 37 is arranged across the end face of the opening edge of the first opening 136, extending from the inner side to the outer side. Accordingly, the first light-shielding portion 37 covers the entire end face of the opening edge of the first opening 136, covers the entire circumference of the second interlayer insulating film 134 at the opening edge of the first opening 136, and further covers the entire circumference of the surface of the glass substrate 121GS adjacent to the first opening 136.

[0067] With this configuration, the light directed toward the opening edge of the first opening 136 in the first interlayer insulating film 133, the second interlayer insulating film 134, the gate insulating film 132, and the base coat film 131 can be blocked by the first light-shielding portion 37. This further suppresses the generation of reflected light at the interface of the portions of the first interlayer insulating film 133, the second interlayer insulating film 134, the gate insulating film 132, and the base coat film 131 that constitute the opening edge of the first opening 136, as well as reflected light at the end face of the opening edge of the first opening 136. Moreover, since the first light-shielding portion 37 is made up of a part of the same second metal film MF102 as the source electrode 124B and the drain electrode 124C, it is possible to reduce manufacturing costs compared to the case where a dedicated light-shielding film is provided to provide the first light-shielding portion 37.

[0068] This embodiment has the structure described above, and next, the array substrate manufacturing process included in the manufacturing method of the liquid crystal panel 111 will be mainly described. Below, the seventh step will be described in detail. Steps 1 to 6, 8 and 9 are as described in Embodiment 1.

[0069] In step 7, when the second photoresist film PR102 deposited on the second metal film MF102 is exposed and developed, the second photoresist film PR102 remains with a pattern as shown in Figure 18. The second photoresist film PR102 remains at the planned formation locations of the source electrode 124B, the drain electrode 124C, and the source wiring 127, as well as at the planned formation location of the first light-shielding portion 37 (see Figure 15). The second metal film MF102 is wet-etched or dry-etched using the second photoresist film PR102 with this configuration as a mask. As a result, as shown in Figure 19, the portion of the second metal film MF102 that overlaps with the second photoresist film PR102 is selectively retained, and the portion that does not overlap with the second photoresist film PR102 is selectively removed. This allows for the formation of the source electrode 124B, drain electrode 124C, and source wiring 127 of the TFT 124, as well as the formation of the first light-shielding portion 37. The first light-shielding portion 37 covers the opening edge of the first opening 136 in the first interlayer insulating film 133, the second interlayer insulating film 134, the gate insulating film 132, and the base coat film 131.

[0070] Furthermore, in the bonding process included in the manufacturing method of the liquid crystal panel 111, when bonding the opposing substrate 120 and the array substrate 121, there is a slight misalignment of the opposing substrate 120 with respect to the array substrate 121 in the direction along the main surface (horizontal direction). In that case, there is a risk that the first opening 136 on the array substrate 121 side and the pixel opening 129A on the opposing substrate 120 side will be misaligned. Even in such cases, as shown in Figures 15 to 17, since the opening edge of the first opening 136 is covered by the first light-shielding portion 37, the generation of reflected light at the interface of the portion of the first interlayer insulating film 133, the second interlayer insulating film 134, the gate insulating film 132, and the base coat film 131 that constitutes the opening edge of the first opening 136, and the generation of reflected light at the end face of the opening edge of the first opening 136 are suppressed. As a result, even if the first aperture 136 and the pixel aperture 129A are misaligned, unwanted reflected light is less likely to pass through the pixel aperture 129A, increasing the certainty that good display quality will be maintained.

[0071] As described above, the array substrate 121 according to this embodiment includes a first light-shielding portion 37 that covers the opening edge of the first opening 136 in the first interlayer insulating film 133 and the second interlayer insulating film 134 and blocks light. The first light-shielding portion 37 can block light directed toward the opening edge of the first opening 136 in the first interlayer insulating film 133 and the second interlayer insulating film 134. This makes it possible to further suppress the generation of reflected light at the interface of the portion of the first interlayer insulating film 133 and the second interlayer insulating film 134 that constitutes the opening edge of the first opening 136, and reflected light at the end face of the opening edge of the first opening 136.

[0072] Furthermore, the device includes a source electrode (electrode) 124B and a drain electrode (electrode) 124C, which are made from a part of the second metal film (metal film) MF102 disposed on the second interlayer insulating film 134, and the first light-shielding portion 37 is made from a part of the second metal film MF102. Since the source electrode 124B, the drain electrode 124C, and the first light-shielding portion 37 are each made from a part of the second metal film MF102, manufacturing costs can be reduced compared to a case where a dedicated light-shielding film is provided to provide the first light-shielding portion 37.

[0073] The liquid crystal panel 111 of this embodiment comprises the array substrate 121 described above and a counter substrate 120 arranged opposite the array substrate 121. The counter substrate 120 includes a light-blocking black matrix 129, and the black matrix 129 has pixel apertures 129A that overlap with at least a portion of the pixel electrodes 125 and the first aperture 136. An image can be displayed using light that has passed through the first aperture 136 and the pixel electrodes 125 and through the pixel apertures 129A of the black matrix 129. When the array substrate 121 is equipped with a first light-shielding portion 37, even if a misalignment occurs between the array substrate 121 and the opposing substrate 120, resulting in an inconsistent arrangement of the first aperture 136 and the pixel aperture 129A, the first light-shielding portion 37 covers the aperture edge of the first aperture 136, thereby suppressing the generation of reflected light at the interface of the portion of the first interlayer insulating film 133 and the second interlayer insulating film 134 that constitutes the aperture edge of the first aperture 136, as well as reflected light at the end face of the aperture edge of the first aperture 136. This increases the certainty that good display quality is maintained.

[0074] As described above, the manufacturing method of the array substrate 121 according to this embodiment involves first providing a first opening 136 in the first interlayer insulating film 133 and the second interlayer insulating film 134, then depositing a second metal film (metal film) MF102 on the second interlayer insulating film 134, and selectively etching the second metal film MF102 to provide a first light-shielding portion 37 that covers the opening edge of the first opening 136. By selectively etching the second metal film MF102 deposited on the second interlayer insulating film 134, a first light-shielding portion 37 that covers the opening edge of the first opening 136 is provided. The first light-shielding portion 37 can block light directed toward the opening edge of the first opening 136 in the first interlayer insulating film 133 and the second interlayer insulating film 134. This makes it possible to further suppress the generation of reflected light at the interface of the portion of the first interlayer insulating film 133 and the second interlayer insulating film 134 that constitutes the opening edge of the first opening 136, as well as reflected light at the end face of the opening edge of the first opening 136.

[0075] Furthermore, the second metal film MF102 is selectively etched to provide the source electrode (electrode) 124B and the drain electrode (electrode) 124C together with the first light-shielding portion 37. By selectively etching the second metal film MF102, the source electrode 124B, the drain electrode 124C, and the first light-shielding portion 37 are provided. In this way, since the source electrode 124B, the drain electrode 124C, and the first light-shielding portion 37 are each made up of a part of the second metal film MF102, it is possible to reduce manufacturing costs and the like compared to the case where a dedicated light-shielding film is provided to provide the first light-shielding portion 37.

[0076] <Other Embodiments> The technology disclosed herein is not limited to the embodiments described above in the description and drawings, but also includes, for example, the following embodiments.

[0077] (1) The material of the mask film MF1 may be an amorphous silicon material in addition to an oxide semiconductor material.

[0078] (2) The material of the mask film MF1 may be a transparent electrode material (ITO, IZO, etc.) in addition to a semiconductor material.

[0079] (3) The first openings 36, 136 may be formed in the gate insulating film 32, 132, the first interlayer insulating film 33, 133, and the second interlayer insulating film 34, 134, but may not be formed in the base coat film 31, 131.

[0080] (4) An insulating film made of an inorganic material may be additionally provided on the array substrates 21 and 121, below the planarization film 35 and above the second metal films MF2 and MF102.

[0081] (5) In (4) above, a metal film or transparent electrode film may be added to the array substrates 21 and 121 on the upper side of the added insulating film and on the lower side of the planarization film 35. In this case, the added metal film or transparent electrode film may be patterned to provide an intermediate electrode that overlaps with both the drain electrodes 24C and 124C and the connection portion 25B, and contact holes may be provided in the added insulating film and the planarization film, respectively, that overlap with the intermediate electrode, and the intermediate electrode may be connected to the drain electrodes 24C and 124C and the connection portion 25B through each contact hole.

[0082] (6) The planarization film 35 may not be formed on the array substrates 21 and 121. In that case, an insulating film made of an inorganic material may be provided instead of the planarization film 35.

[0083] (7) The specific materials used for the first interlayer insulating film 33, 133 and the second interlayer insulating film 34, 134 can be changed as appropriate in addition to those mentioned above.

[0084] (8) The pixel electrodes 25, 125 may be arranged on the array substrate 21, 121 below the first interlayer insulating film 33, 133. In this case, for example, a part of the semiconductor film may be made less resistive (conductive), and the less resistive portion may be used as the pixel electrodes 25, 125.

[0085] (9) The drain electrodes 24C and 124C may be arranged such that the portion overlapping with the semiconductor portion 24D and the portion overlapping with the connection portion 25B do not overlap. In this case, the second pixel contact hole CH2 connecting the drain electrodes 24C and 124C to the connection portion 25B is arranged not to overlap with the other first pixel contact hole CH1 connecting the drain electrodes 24C and 124C to the semiconductor portion 24D.

[0086] (10) TFTs 24 and 124 may be of the double-gate type or other types in addition to the top-gate type. In that case, for example, a metal film may be formed on the lower side of the base coat films 31 and 131, and a bottom gate electrode superimposed on the semiconductor part 24D may be provided using that metal film.

[0087] (11) The semiconductor film material may be an oxide semiconductor material or an amorphous silicon semiconductor material. In that case, the array substrates 21, 121 are configured such that a first metal film, gate insulating film 32, 132, semiconductor film, first interlayer insulating film 33, 133, second interlayer insulating film 34, 134, second metal films MF2, MF102, planarization film 35, and first transparent electrode film are laminated on glass substrates 21GS, 121GS in that order, and the base coat films 31, 131 are omitted. In such a configuration, the first openings 36, 136 may be provided in such a way that they penetrate the gate insulating films 32, 132, the first interlayer insulating films 33, 133 and the second interlayer insulating films 34, 134, but they may not be formed in the gate insulating films 32, 132.

[0088] (12) In (11) above, TFT24,124 may be bottom gate type or double gate type.

[0089] (13) In the non-display area NAA of the array substrates 21 and 121, gate drive circuits (GDM (Gate Driver Monolithic) circuits) for supplying scanning signals to gate wiring 26 and switch circuits (SSD (Source Shared Driving) circuits) for distributing image signals supplied from the driver 12 to multiple source wiring 27 may be monolithically provided using the respective films on the glass substrates 21GS and 121GS.

[0090] (14) In (13) above, the array substrates 21 and 121 may be provided with a first semiconductor film made of a polysilicon semiconductor material and a second semiconductor film made of an oxide semiconductor material or an amorphous silicon semiconductor material. In that case, the first semiconductor film can constitute the semiconductor portion of the transistors that make up the gate drive circuit and switch circuit arranged in the non-display region NAA, and the second semiconductor film can constitute the semiconductor portion 24D of the TFTs 24 and 124 arranged in the display region AA.

[0091] (15) The black matrices 29, 129 may be provided on the array substrates 21, 121.

[0092] (16) The array substrates 21 and 121 may have resin substrates made of synthetic resin in addition to glass substrates 21GS and 121GS as light-transmitting substrates.

[0093] (17) The driver 12 may also be mounted on the flexible substrate 13 which is mounted on the array substrates 21 and 121 using the FOG (Film On Glass) method, or it may be mounted using the COF (Chip On Film) method.

[0094] (18) The planar shape of the liquid crystal panel 11,111 may be a vertically elongated rectangle, square, circle, semicircle, vertically elongated oval, ellipse, trapezoid, etc.

[0095] (19) The display mode of the LCD panel 11,111 may be any of the following: FFS (Fringe Field Switching) mode, TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, etc.

[0096] (20) The display device may be other than the liquid crystal panel 11,111 (such as an organic EL (Electro Luminescence) display panel) or an EPD (microcapsule electrophoretic display panel). [Explanation of symbols]

[0097] 11,111…Liquid crystal panel (display device), 20,120…Opposite substrate, 21,121…Array substrate (display substrate), 21GS,121GS…Glass substrate (translucent substrate), 24B,124B…Source electrode (electrode), 24C,124C…Drain electrode (electrode), 24D…Semiconductor part, 25,125…Pixel electrode, 29,129…Black matrix (second light-shielding part), 29A,129A…Pixel aperture (second aperture), 31,131…Base code Gate film (third insulating film), 32,132... Gate insulating film (third insulating film), 33,133... First interlayer insulating film (first insulating film), 34,134... Second interlayer insulating film (second insulating film), 36,136... First aperture, 37... First light-shielding portion, CH1... First pixel contact hole (fifth aperture), MF1... Mask film, MF1A... First mask aperture (third aperture), MF1B... Second mask aperture (fourth aperture), MF2,MF102... Second metal film (metal film)

Claims

1. A light-transmitting substrate having light-transmitting properties, A first insulating film disposed on the light-transmitting substrate, A second insulating film is disposed on the first insulating film and has a refractive index different from that of the first insulating film, It comprises a pixel electrode and, A display substrate is provided in which the first insulating film and the second insulating film are provided with a first aperture that overlaps with at least a portion of the pixel electrode, and the aperture edge of the first aperture is configured to be along the normal to the main surface of the light-transmitting substrate.

2. The light-transmitting substrate comprises a third insulating film disposed beneath the first insulating film, The display substrate according to claim 1, wherein the first opening is continuously provided in the third insulating film.

3. The display substrate according to claim 1 or claim 2, further comprising a first light-shielding portion that covers the opening edge of the first opening in the first insulating film and the second insulating film and blocks light.

4. The electrode comprises a part of a metal film disposed on the second insulating film, The display substrate according to claim 3, wherein the first light-shielding portion is a part of the metal film.

5. A display board according to claim 1 or claim 2, A display device comprising: a counter board arranged opposite to the display board;

6. The opposing substrate is provided with a second light-shielding portion that blocks light, The display device according to claim 5, wherein the second light-shielding portion has a second opening that overlaps with at least a portion of the pixel electrode and the first opening.

7. A first insulating film is formed on a light-transmitting substrate. A second insulating film is formed on the first insulating film, A mask film made of a semiconductor material or a transparent electrode material is formed on the second insulating film. The mask film is selectively etched to provide a third opening. The first insulating film and the second insulating film are etched through the third opening of the mask film, and a first opening is provided in the first insulating film and the second insulating film that overlaps with the third opening of the mask film. A method for manufacturing a display substrate, comprising a pixel electrode in which at least a portion overlaps with the first aperture.

8. Before forming the first insulating film, a semiconductor film is formed on the light-transmitting substrate. The semiconductor film is selectively etched to provide a semiconductor portion. The mask film is selectively etched to provide a fourth opening that overlaps with a part of the semiconductor portion together with the third opening. The first insulating film and the second insulating film are etched through the third and fourth openings of the mask film, and a fifth opening is provided in the first insulating film and the second insulating film that overlaps with the fourth opening of the mask film together with the first opening. A method for manufacturing a display substrate according to claim 7, wherein, after etching the first insulating film and the second insulating film, a cleaning agent containing hydrofluoric acid is supplied onto the mask film to clean the portion of the semiconductor portion facing the fifth opening through the fifth opening, and the mask film is removed.

9. The mask film is wet-etched to provide the third opening, A method for manufacturing a display substrate according to claim 7 or claim 8, wherein the first insulating film and the second insulating film are dry-etched through the third opening of the mask film to provide the first opening.

10. Before forming the first insulating film on the light-transmitting substrate, a third insulating film is formed. A method for manufacturing a display substrate according to claim 7 or claim 8, wherein the third insulating film is etched through the third opening of the mask film in addition to the first insulating film and the second insulating film, so that the first opening is continuous across the first insulating film, the second insulating film and the third insulating film.

11. After providing the first opening in the first insulating film and the second insulating film, a metal film is formed on the second insulating film. A method for manufacturing a display substrate according to claim 7 or claim 8, wherein the metal film is selectively etched to provide a first light-shielding portion that covers the opening edge of the first opening.

12. The method for manufacturing a display substrate according to claim 11, wherein the metal film is selectively etched to provide electrodes together with the first light-shielding portion.

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