Compressor and memory system
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2025-01-22
- Publication Date
- 2026-08-03
Smart Images
Figure 2026125254000001_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to a compression device and a memory system.
Background Art
[0002] Generally, in a compression device having a dictionary compression circuit, data input in the past is buffered in a dictionary buffer, data that matches the input data is searched from the past data on the dictionary buffer, and when the matching data is stored in the dictionary buffer, it is replaced with a match distance that is the address of the dictionary buffer and a match length that indicates the length of the matching data, and compression is performed by outputting it as a dictionary compression result.
[0003] One method of improving the compression ratio of a dictionary compression circuit is to increase the size of the dictionary buffer (dictionary buffer size). This is because the larger the dictionary buffer size, the wider the search range of past data can be. However, increasing the dictionary buffer size increases the circuit scale of the dictionary compression circuit.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Patent Document 2
Patent Document 3
Summary of the Invention
Problems to be Solved by the Invention
[0005] The problem that this invention aims to solve is to provide a compression device and a memory system that can improve the compression ratio of a dictionary-type compression circuit while suppressing an increase in the circuit size of the dictionary-type compression circuit. [Means for solving the problem]
[0006] A compression device according to one embodiment compresses input first data. The compression device includes a dictionary buffer, a match candidate search circuit, and a match selection circuit, and comprises a dictionary-style compression circuit that performs dictionary-style coding multiple times on the first data, and an input control circuit that outputs input data based on the first data to the dictionary-style compression circuit. The input control circuit outputs the first data as first input data from a specified starting position to the match candidate search circuit, and outputs the first data as second input data of the same length as the first input data from the beginning position to the dictionary buffer. The dictionary buffer stores as dictionary data data equal to the size of the dictionary buffer from the second input data sequentially input from the input control circuit. The match candidate search circuit acquires the dictionary data that matches at least a portion of the first input data sequentially input from the input control circuit, and generates compressed data by the current dictionary-style coding. The match selection circuit, if there is compressed data corresponding to the first data previously generated by the match candidate search circuit, compares the size of the compressed data generated by the current lexicographic coding with the size of the compressed data corresponding to the specified starting position that was previously generated, and outputs the smaller compressed data. If there is no compressed data corresponding to the first data previously generated by the match candidate search circuit, it outputs the compressed data generated by the current lexicographic coding. [Brief explanation of the drawing]
[0007] [Figure 1] A diagram showing an example of the configuration of an information processing system including a compression device according to the first embodiment. [Figure 2] A figure showing an example of dictionary-type compression in a compression device according to the first embodiment. [Figure 3] A block diagram showing an example of the configuration of a compression device according to the first embodiment. [Figure 4] A diagram showing an example of compression processing by a compression device according to the first embodiment. [Figure 5] A flowchart showing an example of the procedure for compression processing by the compression device according to the first embodiment. [Figure 6] A flowchart showing an example of the procedure for compression processing by the compression device according to the first embodiment. [Figure 7] A block diagram showing an example of the configuration of a compression device according to the second embodiment. [Figure 8] A block diagram showing an example of the configuration of a compression device according to the third embodiment. [Figure 9] A block diagram showing an example of the configuration of a compression device according to the third embodiment. [Figure 10] A block diagram showing an example of the configuration of a compression device according to the third embodiment. [Modes for carrying out the invention]
[0008] The embodiments will be described below with reference to the drawings.
[0009] (First Embodiment) Figure 1 shows an example of the configuration of an information processing system including a compression device according to the first embodiment. The information processing system 1 includes a host device 2 and a memory system 3.
[0010] Host device 2 is an information processing device that stores data in memory system 3. Host device 2 is, for example, a storage server or personal computer that stores large amounts of diverse data in memory system 3. Hereinafter, host device 2 will be referred to as host 2.
[0011] The memory system 3 is a semiconductor storage device configured to write data to and read data from a non-volatile memory. The non-volatile memory is, for example, a NAND-type flash memory 4. The memory system 3 is realized, for example, as a solid state drive (SSD). Hereinafter, the case where the memory system 3 is realized as an SSD will be exemplified, but the memory system 3 may be realized as a hard disk drive (HDD).
[0012] The memory system 3 can be used as storage for the host 2. The memory system 3 may be built into the host 2 or may be connected to the host 2 via a cable or a network.
[0013] The interface for connecting the host 2 and the memory system 3 complies with standards such as SCSI, Serial Attached SCSI (SAS), ATA (AT Attachment), Serial ATA (SATA), PCI Express (PCIe) (registered trademark), Ethernet (registered trademark), Fibre channel, NVM Express (NVMe) (registered trademark), etc.
[0014] The memory system 3 includes, for example, a NAND-type flash memory 4, a dynamic random access memory (DRAM) 5, and a controller 6.
[0015] The NAND-type flash memory 4 includes one or more memory chips. Each memory chip includes a plurality of blocks. One block functions as the minimum unit of a data erasure operation. A block may also be referred to as an "erasure block" or a "physical block". Each of the plurality of blocks includes a plurality of pages. Each of the plurality of pages includes a plurality of memory cells connected to a single word line. One page functions as the unit of a data write operation and a data read operation. Note that the word line may function as the unit of a data write operation and a data read operation.
[0016] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, which is referred to as the maximum P / E cycle number. One P / E cycle of a certain block includes an erase operation to put all memory cells in this block into an erased state and a write operation to write data to each page of this block.
[0017] DRAM5 is a volatile memory. The storage area of DRAM5 is allocated, for example, as a storage area for firmware (FW), a cache area for a logical-physical address translation table, and a buffer area for user data.
[0018] Controller 6 is a memory controller that controls NAND flash memory 4 and DRAM5. Controller 6 is realized, for example, by a circuit such as a System-on-a-chip (SoC). Controller 6 may incorporate a static random access memory (SRAM) or DRAM. In this case, external DRAM5 of controller 6 may not be provided.
[0019] Controller 6 functions, for example, as a flash translation layer (FTL) configured to execute data management and block management of NAND flash memory 4. The data management executed by this FTL includes (1) management of mapping information indicating the correspondence between each logical address and each physical address of NAND flash memory 4, and (2) processing for hiding the difference between data read / write operations in page units and data erase operations in block units. Block management includes management of bad blocks, wear leveling, and garbage collection.
[0020] The logical address is used by host 2 to address the storage area of memory system 3. The logical address is, for example, a logical block address (LBA).
[0021] The management of the mapping between each logical address and each physical address is performed, for example, using a logical-physical address translation table. The controller 6 uses the logical-physical address translation table to manage the mapping between each logical address and each physical address in specific management size units. The physical address corresponding to a given logical address indicates the physical storage location in the NAND flash memory 4 where the user data for that logical address is written. The logical-physical address translation table may be loaded from the NAND flash memory 4 to the DRAM 5 when the memory system 3 is started.
[0022] Data can only be written to a single page once per P / E cycle. Therefore, the controller 6 writes the updated user data corresponding to a certain logical address to a different physical memory location, rather than to the physical memory location where the previous user data corresponding to that logical address is stored. The controller 6 then invalidates the previous user data by updating the logical-physical address translation table to associate this logical address with this different physical memory location.
[0023] The controller 6 includes, for example, a CPU 11, a NAND interface (NAND I / F) 12, a DRAM interface (DRAM I / F) 13, a host interface (Host I / F) 14, and a compressor 15. These components, the CPU 11, NAND I / F 12, DRAM I / F 13, Host I / F 14, and compressor 15, are connected, for example, via a bus 10.
[0024] The CPU 11 is a processor configured to control the NAND I / F 12, DRAM I / F 13, host I / F 14, and the compressor 15. The CPU 11 performs various processes by executing firmware (FW) loaded from the NAND flash memory 4 into the DRAM 5. FW is a control program containing a set of instructions that causes the CPU 11 to perform various processes. In addition to the FTL processing described above, the CPU 11 also performs command processing to handle various commands from the host 2. The operation of the CPU 11 is controlled by the FW executed by the CPU 11. Note that some or all of the FTL processing and command processing may be performed by dedicated hardware within the controller 6.
[0025] The NAND I / F12 electrically connects the controller 6 and the NAND flash memory 4. The NAND I / F12 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).
[0026] The NAND I / F 12 functions as a NAND control circuit configured to control the NAND flash memory 4. The NAND I / F 12 may be connected to multiple memory chips within the NAND flash memory 4 via multiple channels (Ch). By driving multiple memory chips in parallel, the access to the entire NAND flash memory 4 can be widened.
[0027] The DRAM I / F13 functions as a DRAM control circuit configured to control access to DRAM5.
[0028] The host interface 14 is a circuit that functions as an interface for communication between the memory system 3 and the host 2. The host interface 14 includes circuits that receive various commands from the host 2, such as input / output (I / O) commands and various control commands. I / O commands may include write commands and read commands. Control commands may include unmap commands (trim commands) and format commands. The host interface 11 includes circuits that send responses and data corresponding to commands to the host 2.
[0029] The compression device 15 is an encoding unit that compresses data by encoding the data to be written to the NAND flash memory 4. The CPU 11, for example, inputs the received write data as plaintext data to the compression device 15 in response to receiving a write command from the host 2. The compression device 15 encodes the plaintext data input from the CPU 11. The compression device 15 includes, for example, a dictionary-type compression circuit 22 to compress the data.
[0030] The dictionary-style compression circuit 22 is a data compression circuit that performs dictionary-style encoding on the input data.
[0031] Dictionary coding is an encoding method that uses a dictionary buffer, which holds previously input data, to convert data to be compressed into a match distance and a match length. Dictionary coding is also called dictionary compression. In dictionary compression, the dictionary buffer is searched to retrieve past data that matches the data to be compressed in at least part, and the match distance and match length are obtained. The match distance is the distance in the dictionary buffer from the location where the data to be compressed is stored to the location where the retrieved past data is stored. The match length is the length of the portion that matches the retrieved past data and the data to be compressed. By converting the data to be compressed into a match distance and a match length, the data can be compressed. If no past data that matches the data to be compressed in at least part is stored in the dictionary buffer, the dictionary compression circuit 22 outputs the data to be compressed as is.
[0032] Figure 2 shows an example of dictionary-style compression. In the example shown in Figure 2, the previously entered data sequence "...cacabc" is stored in the dictionary buffer. The current input data sequence is "caba".
[0033] In this case, the current input data sequence "caba" matches the first two characters of the data sequence "ca" stored in the dictionary buffer six positions prior to where the current input data sequence "caba" is stored. Additionally, the current input data sequence "caba" matches the first three characters of the data sequence "cab" stored in the dictionary buffer four positions prior to where the current input data sequence "caba" is stored.
[0034] In dictionary compression, the current input data sequence "caba" is converted into a match distance and match length that refer to the data sequence in the dictionary buffer that has the longest matching length.
[0035] Therefore, the current input data sequence "caba" is converted into a match distance "4" and a match length "3" that relatively reference the data sequence "cab" in the dictionary buffer. The match distance "4" indicates the relative distance in the dictionary buffer from the location where the current input data sequence "caba" is stored to the location where the data sequence "cab" is stored. The match length "3" indicates the length of the portion that matches between the current input data sequence "caba" and the data sequence "cab". Thus, when the dictionary compression circuit 22 performs dictionary compression on the current input data sequence "caba", it outputs, for example, (4,3) which shows the match distance and match length.
[0036] Figure 3 is a block diagram showing an example configuration of the compression device 15. The compression device 15 comprises a control module 21, a dictionary-based compression circuit 22, and an input control circuit 23. The dictionary-based compression circuit 22 also includes a dictionary buffer 31, a match candidate search circuit 32, and a match selection circuit 33. In this embodiment, it is assumed that the write data received in response to a write command from the host 2 is temporarily stored in the DRAM 5 as data to be compressed, but the write data may also be stored in the SRAM or DRAM built into the controller 6.
[0037] The control module 21 controls the operation of the dictionary-style compression circuit 22 and the input control circuit 23. The dictionary-style compression circuit 22 performs dictionary-style compression multiple times on the data to be compressed.
[0038] The input control circuit 23 obtains two sets of input data, input data 51 for the dictionary buffer and input data 52 for match candidate search, from, for example, the DRAM 5. The input data 51 for the dictionary buffer corresponds to the past input data in this dictionary-style compression. The input data 52 for match candidate search corresponds to the data to be compressed in this dictionary-style compression.
[0039] The input control circuit 23 retrieves the data to be compressed, stored in DRAM 5, from a specified starting position as input data 52 for searching for match candidates. More specifically, the input control circuit 23 retrieves the data to be compressed, stored in DRAM 5, from a starting position shifted according to the number of data compressions (number of lexicographical compressions) as input data 52 for searching for match candidates.
[0040] Furthermore, the input control circuit 23 obtains data with the same data length as the input data 52 for match candidate search as input data 51 for the dictionary buffer, from the beginning position of the data to be compressed stored in the DRAM 5.
[0041] The input control circuit 23 outputs the acquired input data 51 for the dictionary buffer to the dictionary buffer 31, and outputs the acquired input data 52 for match candidate search to the match candidate search circuit 32.
[0042] The dictionary buffer 31 is implemented, for example, as a shift register. The dictionary buffer 31 buffers data equal to the size of the dictionary buffer from the input data 51 for the dictionary buffer that is sequentially input from the input control circuit 23 as past input data (dictionary data).
[0043] The match candidate search circuit 32 takes the input data 52 for match candidate search, which is sequentially input from the input control circuit 23, as the data to be compressed in this dictionary-based compression, searches the dictionary buffer 31 for past input data equal to the size of the dictionary buffer, and obtains past input data that matches at least a portion of the data to be compressed, thereby obtaining the match distance and match length.
[0044] If the match candidate search circuit 32 obtains the match distance and match length, it converts the data to be compressed in this dictionary-style compression into a match symbol consisting of the match distance and match length, and then compresses the data to be compressed.
[0045] The data compressed by the match candidate search circuit 32 (compressed data) is output to the match selection circuit 33. If the match candidate search circuit 32 is unable to obtain the matching distance and matching length, that is, if no past data that matches at least part of the data to be compressed in this dictionary-style compression is stored in the dictionary buffer 31, it outputs the data to be compressed as is to the match selection circuit 33.
[0046] The match selection circuit 33 writes the result of the first dictionary-style compression output from the match candidate search circuit 32 to, for example, the DRAM 5. More specifically, the match selection circuit 33 writes the compressed data from the first dictionary-style compression output from the match candidate search circuit 32 to the DRAM 5, or writes the data to be compressed in the first dictionary-style compression output from the match candidate search circuit 32 to the DRAM 5.
[0047] In subsequent dictionary-based compressions, the match selection circuit 33 compares the size of the compressed data output from the match candidate search circuit 32 with the size of the compressed data obtained from previous dictionary-based compressions in DRAM 5, and writes the compressed data with the smaller data size to DRAM 5 as the compressed data with a better compression ratio.
[0048] If the data to be compressed is write data received in response to a write command from host 2, once the series of compression processes by the compression device 15 are completed, the controller 6 reads the compressed data written to DRAM 5 and executes the process of writing the compressed data to NAND flash memory 4. When the compressed data is stored in NAND flash memory 4, predetermined processes such as error correction and randomization may be performed. In this case, the CPU 11 writes the data on which the predetermined processes have been performed to the compressed data to NAND flash memory 4 via NAND I / F 12. That is, the CPU 11 writes data based on the compressed data to NAND flash memory 4. Also in this case, when the CPU 11 reads the compressed data from NAND flash memory 3, it reads data based on a read command from host 2 from NAND flash memory 4 via NAND I / F 12. After predetermined processes such as error correction and randomization de-processing are performed on the data read from NAND flash memory 4, the CPU 11 stores it in DRAM 5 as compressed data. The compressed data stored in the DRAM 5 is input by the CPU 11 to a decoding circuit (not shown). The decoding circuit, for example, is built into the controller 6 and decompresses the input compressed data to generate decompressed data (decoded data). In other words, the decoding circuit decompresses the compressed data based on the data read from the NAND flash memory 4 to generate decompressed data (decoded data).
[0049] The components within the compression device 15 are implemented by, for example, at least one of the following: registers, memory, adders, multipliers, selectors, and other arithmetic units. Registers are implemented by, for example, sequential circuits such as flip-flops. Memory is implemented by, for example, memory elements such as SRAM or DRAM. Adders, multipliers, selectors, and other arithmetic units are implemented by, for example, combinational logic circuits.
[0050] Here, with reference to Figure 4, the compression process performed in the compression device 15 according to this embodiment will be specifically described. In the graph shown in Figure 4, the vertical axis represents the time since the input of various data began, and the horizontal axis represents the position of the various data. In Figure 4, it is assumed that the data length of the data to be compressed is 32 KiB, and the dictionary buffer size of the dictionary buffer 31 is 2 KiB. Furthermore, the compression process described below is performed by the control module 21 of the compression device 15 controlling the operation of the dictionary-type compression circuit 22 and the input control circuit 23.
[0051] In this case, during the first dictionary-style compression (initial dictionary-style compression), the input control circuit 23 obtains the data to be compressed, which has a data length of 32 KiB and is stored in the DRAM 5, from the beginning position, as input data 51a for the dictionary buffer and input data 52a for searching for match candidates.
[0052] The acquired input data 51a for the dictionary buffer and input data 52a for match candidate search are output to the dictionary buffer 31 and match candidate search circuit 32 at the same time by the input control circuit 23.
[0053] The dictionary buffer 31 buffers 2 KiB of input data (the size of the dictionary buffer) from the input data 51a that is sequentially input from the input control circuit 23 as past input data. For example, if the input data 51a for the dictionary buffer has a data length of 32 KiB, and data up to the position corresponding to 2 KiB has been input to the dictionary buffer 31, the dictionary buffer 31 buffers the data corresponding to the range from 0 KiB to 2 KiB as past input data. Similarly, if the input data 51a for the dictionary buffer has a data length of 32 KiB, and data up to the position corresponding to 3 KiB has been input to the dictionary buffer 31, the dictionary buffer 31 buffers the data corresponding to the range from 1 KiB to 3 KiB as past input data. In this way, the dictionary buffer 31 buffers 2 KiB (the size of the dictionary buffer) of data from the input data 51a that is sequentially input from the input control circuit 23, starting from the data corresponding to the most recent input position.
[0054] The match candidate search circuit 32 takes the input data 52a for match candidate search, which is sequentially input from the input control circuit 23, as the data to be compressed in the first dictionary-style compression, and searches the dictionary buffer 31 for 2 KiB of past input data.
[0055] In the first dictionary-style compression, the match search range r is the range of data 52a that is sequentially input from the input control circuit 23, starting from the data corresponding to the most recent input position and going back 2 KiB. m As the input data 52a is sequentially input, this match search range r m The slides. For example, as shown in Figure 4, if the match candidate search circuit 32 receives data up to the position 4KiB from the input data 52a for match candidate search which has a data length of 32KiB, the match candidate search circuit 32 searches for past input data in the dictionary buffer 31 at this point that corresponds to the range of 2KiB to 4KiB, as past input data that matches at least a part of the data corresponding to the position 4KiB.
[0056] In the first dictionary-style compression, since there is no previously compressed data stored in DRAM5, the match selection circuit 33 writes the result of the first dictionary-style compression (compressed data) output from the match candidate search circuit 32 to DRAM5.
[0057] In the second dictionary-style compression (first recompression), the input control circuit 23 acquires the data to be compressed, which has a data length of 32KiB, as input data 52b for searching for match candidates, starting from a position shifted by 2KiB (the dictionary buffer size). In other words, the input control circuit 23 acquires data with a data length of 30KiB, starting from the 2KiB position, as input data 52b for searching for match candidates in the second dictionary-style compression.
[0058] Furthermore, the input control circuit 23 obtains data with the same data length as the input data 52b for match candidate search (i.e., data with a data length of 30KiB) as input data 51b for the dictionary buffer in the second dictionary-style compression, starting from the beginning of the data to be compressed which has a data length of 32KiB. In other words, the input control circuit 23 obtains data with a data length of 30KiB, starting from position 0KiB, as input data 51b for the dictionary buffer in the second dictionary-style compression.
[0059] The acquired input data 51b for the dictionary buffer and input data 52b for match candidate search are output to the dictionary buffer 31 and the match candidate search circuit 32 at the same time by the input control circuit 23.
[0060] Similar to the first dictionary compression, the dictionary buffer 31 buffers 2 KiB of input data from the input data 51b for the dictionary buffer that is sequentially input from the input control circuit 23 as past input data.
[0061] Similar to the first dictionary-style compression, the match candidate search circuit 32 uses the input data 52b for match candidate search, which is sequentially input from the input control circuit 23, as the data to be compressed in the second dictionary-style compression, and searches the dictionary buffer 31 for 2 KiB of past input data. For example, as shown in Figure 4, if the input data 52b for match candidate search, which has a data length of 30 KiB, is input to the match candidate search circuit 32 up to the data corresponding to the 4 KiB position, the match candidate search circuit 32 searches the dictionary buffer 31 for past input data corresponding to the range from 0 KiB to 2 KiB at this point, which matches at least a portion of the data corresponding to the 4 KiB position.
[0062] According to this, the match candidate search circuit 32 can search for past input data corresponding to the 4KiB position of the data to be compressed, which has a data length of 32KiB, in the first lexicographical compression, and search for past input data corresponding to the 0KiB to 2KiB range in the second lexicographical compression. In other words, in the first lexicographical compression, the match candidate search circuit 32 can compress the data corresponding to the 4KiB position based on past input data corresponding to the 2KiB to 4KiB range, and in the second lexicographical compression, it can compress the data corresponding to the 4KiB position based on past input data corresponding to the 0KiB to 2KiB range.
[0063] The match selection circuit 33 retrieves compressed data from the DRAM 5 that corresponds to the starting position of the data to be compressed in the second dictionary-style compression (input data 52b for match candidate search), which is the compressed data from the first dictionary-style compression. It then compares the size of the retrieved compressed data from the first dictionary-style compression with the size of the compressed data from the second dictionary-style compression and writes the compressed data with the smaller data size to the DRAM 5 as the compressed data with a better compression ratio. For example, if the size of the compressed data from the second dictionary-style compression is smaller than the size of the compressed data from the first dictionary-style compression, the match selection circuit 33 overwrites the compressed data from the first dictionary-style compression stored in the DRAM 5, starting from the starting position of the data to be compressed in the second dictionary-style compression, with the compressed data from the second dictionary-style compression. Note that in Figure 4, for the sake of explanation, the starting positions of the input data 52b for match candidate search and the previous (first) compressed data are shown to be shifted, but in reality, the starting positions of the input data 52b for match candidate search and the first compressed data are the same.
[0064] As described above, the compression device 15 according to this embodiment allows for comparison of data corresponding to a 4KiB position with past input data corresponding to a range from 0KiB to 4KiB by performing dictionary-style compression twice, thereby achieving a search equivalent to a match search using a dictionary buffer size that is logically twice the size (i.e., a dictionary buffer size of 4KiB).
[0065] Furthermore, while the data length of the input data 51a for the dictionary buffer and the input data 52a for match candidate search in the first dictionary-style compression is 32 KiB, the data length of the input data 51b for the dictionary buffer and the input data 52b for match candidate search in the second dictionary-style compression is 30 KiB, which is shorter by the dictionary buffer size (i.e., 2 KiB). Therefore, the total processing time required for the two dictionary-style compressions is shorter than simply doubling the time required for the first dictionary-style compression. In other words, the compression device 15 according to this embodiment makes it possible to double the logical dictionary buffer size while shortening the total processing time required for compression compared to simply performing two dictionary-style compressions.
[0066] Generally, dictionary-style compression circuits that perform dictionary-style compression tend to increase in size as the dictionary buffer size increases. However, the compression device 15 having the dictionary-style compression circuit 22 according to this embodiment can improve the compression ratio while suppressing an increase in circuit size by logically expanding the dictionary buffer size. Furthermore, as described above, the total processing time required for compression can also be made shorter than the time required for the first dictionary-style compression (normal dictionary-style compression) simply multiplied by the number of times.
[0067] Note that recompression is performed a predetermined number of times. Figure 4 assumes, for example, that seven recompressions (i.e., eight lexicographical compressions) are performed.
[0068] The input control circuit 23, in the same way as in the second dictionary compression, acquires the input data 52 for match search candidates in the third to eighth dictionary compressions from a starting position shifted by 2 KiB (the dictionary buffer size) each time it is recompressed, starting from the data to be compressed, which has a data length of 32 KiB. For example, in the eighth dictionary compression, the input control circuit 23 acquires data with a starting position shifted by "number of dictionary compression iterations × dictionary buffer size," specifically data with a data length of 18 KiB starting at a position of 14 (= 7 × 2) KiB, as the input data 52c for match candidate search.
[0069] Furthermore, the input control circuit 23 obtains data with the same data length as the input data 52c for match candidate search (i.e., data with a data length of 18KiB) as input data 51c for the dictionary buffer in the eighth dictionary-style compression, starting from the beginning of the data to be compressed, which has a data length of 32KiB. In other words, the input control circuit 23 obtains data with a data length of 18KiB, starting from position 0KiB, as input data 51c for the dictionary buffer in the eighth dictionary-style compression.
[0070] The acquired input data 51c for the dictionary buffer and input data 52c for match candidate search are output to the dictionary buffer 31 and the match candidate search circuit 32 at the same time by the input control circuit 23.
[0071] Similar to the first and second dictionary compressions, the dictionary buffer 31 buffers 2 KiB of input data from the input data 51c for the dictionary buffer that is sequentially input from the input control circuit 23 as past input data.
[0072] Similar to the first and second dictionary-style compressions, the match candidate search circuit 32 uses the input data 52c for match candidate search, which is sequentially input from the input control circuit 23, as the data to be compressed in the eighth dictionary-style compression, and searches the dictionary buffer 31 for 2 KiB of past input data. For example, as shown in Figure 4, if the input data 52c for match candidate search, which has a data length of 18 KiB, is input to the match candidate search circuit 32 up to the data corresponding to the 16 KiB position, the match candidate search circuit 32 searches the dictionary buffer 31 for past input data corresponding to the range from 0 KiB to 2 KiB at this point, which matches at least a portion of the data corresponding to the 16 KiB position.
[0073] According to this, the match candidate search circuit 32 can search for past input data corresponding to the 16KiB position of the data to be compressed, which has a data length of 32KiB, in the first to eighth lexicographical compressions, which correspond to the range from 0KiB to 16KiB.
[0074] The match selection circuit 33 retrieves compressed data from DRAM 5 that corresponds to the starting position of the data to be compressed in the 8th dictionary-style compression (input data 52c for match candidate search), which is the compressed data from the 7th dictionary-style compression. It then compares the size of the retrieved compressed data from the 7th dictionary-style compression with the size of the compressed data from the 8th dictionary-style compression and writes the compressed data with the smaller data size to DRAM 5 as the compressed data with a better compression ratio. Note that in Figure 4, for the sake of explanation, the starting positions of the input data 52c for match candidate search and the compressed data from the previous (7th) compression are shown to be shifted, but in reality, the starting positions of the input data 52c for match candidate search and the compressed data from the 7th are the same.
[0075] As described above, the compression device 15 according to this embodiment can compare data corresponding to a 16KiB position with past input data corresponding to a range from 0KiB to 16KiB by performing dictionary-style compression, for example, eight times, thereby achieving a search equivalent to a match search using a dictionary buffer size eight times larger (i.e., a dictionary buffer size of 16KiB).
[0076] The data length of the input data 52 for match candidate search is 32 KiB in the first lexicographical compression, 30 KiB in the second, 28 KiB in the third, 26 KiB in the fourth, 24 KiB in the fifth, 22 KiB in the sixth, 20 KiB in the seventh, and 18 KiB in the eighth. In other words, the total data length of the input data 52 for match candidate search that was compressed over the eight lexicographical compressions is 200 (= 32 + 30 + ... + 20 + 18) KiB, which is 6.25 (= 200 ÷ 32) times the data length of the input data 52a for match candidate search in the first lexicographical compression (normal lexicographical compression), and the total processing time required for the eight lexicographical compressions is also 6.25 times longer. However, as mentioned above, the total processing time required for eight dictionary-style compressions would be eight times the processing time required for one dictionary-style compression if simply eight dictionary-style compressions were performed. However, with the compression device 15 according to this embodiment, it is possible to perform the compression in 6.25 times the processing time, which is shorter than usual.
[0077] Figure 5 is a flowchart showing an example of the compression process performed by the compression device 15 according to this embodiment. The series of compression processes shown in Figure 5 are performed by the control module 21 of the compression device 15 controlling the operation of each circuit 31, 32, 33 included in the dictionary-style compression circuit 22 and the input control circuit 23. In Figure 5, "N" indicates the number of repetitions of dictionary-style compression performed by the compression device 15 (number of recompressions). For example, in the case of the first dictionary-style compression, N is 0, and in the case of the second dictionary-style compression, N is 1. Also, in Figure 5, "L" indicates the upper limit of the number of repetitions of dictionary-style compression, and "S" indicates the dictionary buffer size of the dictionary buffer 31.
[0078] The control module 21 of the compression device 15 controls the input control circuit 23 to acquire the data to be compressed stored in the DRAM 5 as input data 52 for match candidate search, starting from the starting position specified by "N × S". The control module 21 of the compression device 15 also controls the input control circuit 23 to acquire the data to be compressed as input data 51 for the dictionary buffer, starting from "0 (starting position)" for the same length as the input data 52 for match candidate search in this dictionary-style compression. Furthermore, the control module 21 of the compression device 15 controls the match selection circuit 33 to acquire compressed data corresponding to the starting position specified by "N × S" as compressed data for comparison, which will be described later (step S1).
[0079] For example, in the case of the first dictionary-style compression, the control module 21 of the compression device 15 controls the input control circuit 23 to acquire the data to be compressed as input data 52 for match candidate search, starting from the starting position (i.e., the beginning position) specified by "0 × S". The control module 21 of the compression device 15 also controls the input control circuit 23 to acquire the data to be compressed as input data 51 for the dictionary buffer, starting from "0 (beginning position)" for the same length as the input data 52 for match candidate search in the first dictionary-style compression. Note that in the first dictionary-style compression, since there is no compressed data for comparison yet, the process of acquiring compressed data in step S1 is omitted.
[0080] Furthermore, in the case of the second dictionary-style compression, the control module 21 of the compression device 15 controls the input control circuit 23 to acquire the data to be compressed as input data 52 for match candidate search, starting from the starting position specified by "1 × S" (i.e., a position shifted by the dictionary buffer size S from the beginning position). The control module 21 of the compression device 15 also controls the input control circuit 23 to acquire the data to be compressed as input data 51 for the dictionary buffer, starting from "0 (beginning position)" for the same length as the input data 52 for match candidate search in the first dictionary-style compression. In addition, the control module 21 of the compression device 15 controls the match selection circuit 33 to acquire compressed data corresponding to the starting position specified by "1 × S" as compressed data for comparison.
[0081] The compression device 15 compresses the data to be compressed in this dictionary-style compression (the input data for match candidate search 52) based on the input data 52 for match candidate search and the input data 51 for the dictionary buffer obtained by the processing in step S1, and generates compressed data. The generated compressed data is compared in data size with the compressed data obtained by the processing in step S1, and the compressed data with a better compression ratio is stored in the DRAM 5. The process of generating and comparing compressed data and writing the compressed data with a better compression ratio to the DRAM 5 is performed by the control module 21 of the compression device 15, which controls the circuits 31, 32, and 33 included in the dictionary-style compression circuit 22.
[0082] After this dictionary-style compression, the control module 21 of the compression device 15 adds 1 to the number of dictionary-style compression iterations N (step S2) and determines whether the number of dictionary-style compression iterations N is less than the upper limit L (i.e., whether the number of dictionary-style compression iterations N has reached the upper limit L) (step S3).
[0083] In step S3, if it is determined that the number of repetitions N of dictionary compression is less than the upper limit L and has not yet reached the upper limit L (Yes in step S3), the control module 21 of the compression device 15 executes the process of step S1 again. On the other hand, in step S3, if it is determined that the number of repetitions N of dictionary compression is greater than or equal to the upper limit L and has reached the upper limit L (No in step S3), the control module 21 of the compression device 15 terminates the series of compression processes.
[0084] In Figure 5, a compression process is illustrated where dictionary-style compression is repeated a predetermined number of times up to a certain upper limit L. However, the compression device 15 according to this embodiment may, for example, perform the compression process shown in Figure 6.
[0085] The following describes another example of the compression process performed by the compression device 15 according to this embodiment, with reference to the flowchart in Figure 6. The series of compression processes shown in Figure 6 are performed by the control module 21 of the compression device 15 controlling the operation of each circuit 31, 32, 33 included in the dictionary-style compression circuit 22 and the input control circuit 23, similar to the compression process shown in Figure 5. In Figure 6, "N" indicates the number of repetitions (number of recompressions) of dictionary-style compression performed by the compression device 15, similar to the case in Figure 5. Furthermore, "L" in Figure 6 indicates the upper limit of the number of repetitions of dictionary-style compression, similar to the case in Figure 5, and "S" in Figure 6 also indicates the dictionary buffer size of the dictionary buffer 31, similar to the case in Figure 5.
[0086] First, the control module 21 of the compression device 15 controls the input control circuit 23 to acquire the data to be compressed stored in the DRAM 5 as input data 52 for match candidate search, starting from the starting position specified by "N × S", similar to the process in step S1 of Figure 5. The control module 21 of the compression device 15 also controls the input control circuit 23 to acquire the data to be compressed as input data 51 for the dictionary buffer, starting from "0 (starting position)" for the same length as the input data 52 for match candidate search in this dictionary-style compression. Furthermore, the control module 21 of the compression device 15 controls the match selection circuit 33 to acquire the compressed data corresponding to the starting position specified by "N × S" as compressed data for comparison (step S11).
[0087] The compression device 15 compresses the data to be compressed in this dictionary-style compression (the input data for match candidate search 52) based on the input data 52 for match candidate search and the input data 51 for the dictionary buffer obtained by the processing in step S11, and generates compressed data. The generated compressed data is compared in data size with the compressed data obtained by the processing in step S11, and the compressed data with a better compression ratio is stored in the DRAM 5. The process of generating and comparing compressed data and writing the compressed data with a better compression ratio to the DRAM 5 is performed by the control module 21 of the compression device 15 controlling the circuits 31, 32, and 33 included in the dictionary-style compression circuit 22.
[0088] Here, the control module 21 of the compression device 15 determines whether the data reduction rate in the current dictionary-style compression is less than or equal to a predetermined value (step S12). The data reduction rate is a value calculated based on the size of the compressed data in the current dictionary-style compression and the size of the compressed data in past dictionary-style compressions, and is defined, for example, by "1 - {(size of the compressed data in the current dictionary-style compression) / (size of the compressed data in the previous dictionary-style compression)}".
[0089] In the process of step S12, if it is determined that the data reduction rate is less than or equal to a default value (Yes in step S12), the control module 21 of the compression device 15 terminates the series of compression processes before the number of repetitions N of dictionary compression reaches the upper limit L.
[0090] On the other hand, in the process of step S12, if it is determined that the data reduction rate is not less than or equal to a default value, that is, is greater than the default value (No. in step S12), the control module 21 of the compression device 15 adds 1 to the number of repetitions N of dictionary compression (step S13), similar to the processes of steps S2 and S3 in Figure 5, and determines whether the number of repetitions N of dictionary compression is less than the upper limit L (that is, whether the number of repetitions N of dictionary compression has reached the upper limit L) (step S14).
[0091] In step S14, if it is determined that the number of repetitions N of dictionary-style compression is less than the upper limit L and has not yet reached the upper limit L (Yes in step S14), the control module 21 of the compression device 15 executes the process in step S11 again. On the other hand, in step S14, if it is determined that the number of repetitions N of dictionary-style compression is greater than or equal to the upper limit L and has reached the upper limit L (No in step S14), the control module 21 of the compression device 15 terminates the series of compression processes.
[0092] In general, it is known that in dictionary-based compression, the further the match search range is from the location of the data to be compressed, the smaller the compression effect becomes. According to the process in step S12 described above, it is possible to determine whether or not the compression effect is small, and if it is determined that the compression effect is small, the subsequent processing can be omitted, thereby reducing the total processing time and enabling the generation of compressed data more efficiently.
[0093] Furthermore, the data reduction rate may be defined not by "1 - {(size of compressed data in the current dictionary-style compression) / (size of compressed data in the previous dictionary-style compression)}", but by, for example, "1 - {(size of compressed data in the current dictionary-style compression) / (size of compressed data in the dictionary-style compression two steps prior)}". In this case, the compression device 15 needs to store in the DRAM 5 information indicating the size of the compressed data in the dictionary-style compression two steps prior, in addition to the compressed data in the previous dictionary-style compression. However, by performing dictionary-style compression once that happened not to reduce the data, the possibility that subsequent dictionary-style compressions that could have reduced the data will not be performed can be reduced.
[0094] The compression device 15 according to the first embodiment described above includes a dictionary buffer 31, a match candidate search circuit 32, and a match selection circuit 33, and comprises a dictionary-style compression circuit 22 that performs dictionary-style coding multiple times on the data to be compressed, and an input control circuit 23 that outputs input data based on the data to be compressed to the dictionary-style compression circuit 22.
[0095] The input control circuit 23 outputs the data to be compressed to the match candidate search circuit 32 as input data 52 for match candidate search, starting from the specified starting position, and outputs the data to be compressed to the dictionary buffer 31 as input data 51 for the dictionary buffer, which is the same length as the input data 52 for match candidate search, starting from the beginning position. The dictionary buffer 31 stores the data equal to the size of the dictionary buffer as dictionary data from the input data 51 for the dictionary buffer that is sequentially input from the input control circuit 23. The match candidate search circuit 32 acquires dictionary data that matches at least a portion of the input data 52 for match candidate search that is sequentially input from the input control circuit 23, and generates compressed data using the current dictionary encoding. If there is compressed data that has been previously generated by the match candidate search circuit 32, the match selection circuit 33 compares the size of the compressed data generated by the current dictionary encoding with the size of the compressed data that has been previously generated and corresponds to the specified starting position, and outputs the compressed data with the smaller size. If there is no compressed data that has been previously generated by the match candidate search circuit 32, the match selection circuit 33 outputs the compressed data generated by the current dictionary encoding.
[0096] According to this, it is possible to logically expand the dictionary buffer size and improve the compression ratio while suppressing an increase in circuit size.
[0097] In this embodiment, the case where the shift amount of the starting position of the input data 52 for match candidate search is the dictionary buffer size has been described, but the shift amount of the starting position of the input data 52 for match candidate search does not have to be the dictionary buffer size. For example, if the positions of data to be compressed that have a high probability of containing similar data are known in advance, the total processing time required for the compression process can be expected to be shortened by shifting the starting position of the input data 52 for match candidate search to those positions all at once.
[0098] (Second Embodiment) A second embodiment will now be described. The configuration according to the second embodiment differs from the configuration according to the first embodiment in that the input control circuit 23 has a delay buffer 23a, as shown in Figure 7. In the following, only the differences from the first embodiment will be described, and the explanation of the points that are the same as the first embodiment will be omitted.
[0099] The delay buffer 23a is implemented as, for example, SRAM. The delay buffer 23a delays the data to be compressed, which is sequentially acquired from the DRAM 5, by the delay amount set in the delay buffer 23a, and outputs the delayed data to the dictionary buffer 31 as input data 51 for the dictionary buffer.
[0100] The delay amount set in the delay buffer 23a is changed each time dictionary-based compression is performed in the dictionary-based compression circuit 22.
[0101] For example, when the compression device 15 performs the series of compression processes shown in Figure 5, in the first dictionary-style compression, the input control circuit 23 acquires the data to be compressed from the same starting position as input data 51 for the dictionary buffer and input data 52 for match candidate search, so the delay amount of the delay buffer 23a is set to 0 (zero). In the second dictionary-style compression, the input control circuit 23 acquires the data to be compressed from the starting position specified by "1 × S" as input data 52 for match candidate search, so the delay amount of the delay buffer 23a is set to the dictionary buffer size. Furthermore, in the third dictionary-style compression, the input control circuit 23 acquires the data to be compressed from the starting position specified by "2 × S" as input data 52 for match search, so the delay amount of the delay buffer 23a is set to twice the dictionary buffer size. In this way, the delay amount set in the delay buffer 23a is set according to the amount of shift of the input data 52 for match candidate search.
[0102] In the configuration according to the first embodiment, the input control circuit 23 needs to acquire two sets of data from the DRAM 5 for subsequent dictionary-style compression (recompression): input data 51 for the dictionary buffer and input data 52 for searching for match candidates, each with different starting positions. This consumes twice the DRAM bandwidth compared to normal dictionary-style compression.
[0103] On the other hand, according to the configuration of the second embodiment, the input control circuit 23 can delay the input data 51 for the dictionary buffer by the delay amount set in the delay buffer 23a. Therefore, by acquiring only one set of data from the DRAM 5, it is possible to output the input data 51 for the dictionary buffer and the input data 52 for match candidate search, which have different starting positions, to the dictionary compression circuit 22, thereby reducing the consumption of DRAM bandwidth to half that of the configuration of the first embodiment (i.e., equivalent to normal dictionary compression).
[0104] However, the configuration according to the second embodiment is applicable only when the logical dictionary buffer size of the dictionary compression circuit 22 (in other words, the match search range in multiple dictionary compressions), which changes according to the upper limit of the number of repetitions of dictionary compression, is set to be less than or equal to "delay buffer size + dictionary buffer size".
[0105] (Third embodiment) A third embodiment will now be described. The configuration according to the third embodiment differs from the configuration according to the first embodiment in that the compression device 15 further includes a dictionary-type decompression circuit 24, as shown in Figure 8. In the following, only the differences from the first embodiment will be described, and the explanation of points that are the same as the first embodiment will be omitted.
[0106] For example, if the compression device 15 needs to compress other data before it can recompress a predetermined data set, the DRAM 5 must store both the predetermined data set and the compressed data (hereinafter referred to as "data in the process of compression") that has been compressed at least once. Storing data that is not immediately used in the DRAM 5 in this way puts a strain on the DRAM 5's capacity (memory usage) and is inefficient.
[0107] Therefore, the compression device 15 according to this embodiment further includes a dictionary-type decompression circuit 24. If it is necessary to compress other data before compressing a predetermined data to be compressed and then recompressing it, only the data being compressed in the process described above is stored in the DRAM 5, the predetermined data to be compressed is discarded (deleted) from the DRAM 5, and the DRAM 5 is made available for compressing the other data to be compressed.
[0108] Furthermore, if only the data being compressed is stored in DRAM5 and the data to be compressed is discarded from DRAM5, the compression device 15 needs to store information in DRAM5 that allows it to determine how much the starting position of the input data 52 for match candidate search should be shifted during recompression. This information that allows it to determine how much the starting position of the input data 52 for match candidate search should be shifted during recompression is, for example, information indicating the size of the logical dictionary buffer in this dictionary-based compression. According to this, the compression device 15 can determine that during recompression, it should shift the starting position of the input data 52 for match candidate search by the size of the logical dictionary buffer indicated by the above information.
[0109] Furthermore, the information described above is sufficiently small in size compared to the data to be compressed, and this information will not strain the capacity of DRAM 5. In addition, information that can determine how much the starting position of the input data 52 for match candidate search should be shifted during recompression may be included as a header in the data during compression.
[0110] The dictionary-style decompression circuit 24 is controlled by the control module 21. The dictionary-style decompression circuit 24 decompresses the input compressed data and returns the compressed data to its original form (i.e., the data to be compressed). The data decompressed by the dictionary-style decompression circuit 24 is temporarily stored in the DRAM 5 as data that can be acquired by the input control circuit 23. As a result, even if the predetermined data to be compressed is discarded from the DRAM 5 between the time the input control circuit 23 compresses the data and then recompresses it, the input control circuit 23 can acquire the predetermined data to be compressed that has been decompressed by the dictionary-style decompression circuit 24 at the time of recompression, and the compression device 15 can recompress the predetermined data to be compressed.
[0111] The configuration according to the third embodiment is not limited to the configuration shown in Figure 8, but may also be the configuration shown in Figure 9, for example. The configuration shown in Figure 9 differs from the configuration shown in Figure 8 in that the compression device 15 further includes an entropy coding circuit 25 and an entropy decoding circuit 26.
[0112] The entropy coding circuit 25 and the entropy decoding circuit 26 are controlled by the control module 21.
[0113] The entropy coding circuit 25 performs entropy coding on the result of dictionary-style compression output from the match selection circuit 33 (i.e., the compressed data generated by this dictionary-style compression) to generate compressed data.
[0114] Entropy coding is a variable-length coding scheme that dynamically generates a code table using the frequency of occurrence of the symbols to be coded. Entropy coding is defined, for example, in deflate or gzip. The code table contains information indicating n types of symbols and n codewords associated with each of the n types of symbols. In entropy coding, short codewords are assigned to symbols with high frequency of occurrence, and long codewords are assigned to symbols with low frequency of occurrence. The entropy coding circuit 25 converts the input symbols into codewords according to this assignment. In other words, the codewords obtained by the conversion are variable-length codes.
[0115] Symbols are, for example, fixed-length data. Compressed data generated by entropy coding contains codewords obtained by transforming each of the multiple match symbols included in the result of lexicographic compression. Compressed data generated by entropy coding may further include the code table data used for entropy coding as a header. The code table data is used to reconstruct the code table (decode table) when decompressing the compressed data generated by entropy coding.
[0116] In this case, it is assumed that it is necessary to compress other data before compressing the predetermined data to be compressed again. Therefore, the compressed data generated by performing dictionary compression (dictionary coding) and entropy coding on the predetermined data to be compressed is stored in DRAM5 as data in the process of compression, and the original data to be compressed is discarded from DRAM5.
[0117] The entropy decoding circuit 26 reconstructs a restoration table from the code table data included as a header in the compressed data generated by entropy coding, and decodes the result of dictionary-style compression (i.e., the compressed data generated by dictionary-style compression) from the compressed data based on the restoration table. The compressed data decoded by the entropy decoding circuit 26 (data in the process of being compressed) is output to the dictionary-style decompression circuit 24 and is also temporarily stored in the DRAM 5 as data that can be acquired by the match selection circuit 33.
[0118] The process performed by the dictionary-style decompression circuit 24 using the partially compressed data output from the entropy decoding circuit 26 is the same as in the configuration shown in Figure 8, so a detailed explanation is omitted here.
[0119] The configuration shown in Figure 9 allows for a further reduction in memory usage compared to the configuration shown in Figure 8.
[0120] Furthermore, the configuration according to the third embodiment is not limited to the configurations shown in Figures 8 and 9, but may also be the configuration shown in Figure 10, for example. The configuration shown in Figure 10 differs from the configuration shown in Figure 9 in that the compression device 15 further includes a header generation circuit 27 and a header analysis circuit 28.
[0121] The header generation circuit 27 and the header analysis circuit 28 are controlled by the control module 21.
[0122] The header generation circuit 27 embeds (includes) information into the header of the data being compressed that allows it to determine how much the starting position of the input data 52 for match candidate search should be shifted during recompression. The header analysis circuit 28 analyzes the information embedded in the header of the data being compressed and outputs a value indicating the amount of shift in the starting position of the input data 52 for match candidate search to the input control circuit 23. The processes performed by the other circuits have been described above, so a detailed explanation is omitted here.
[0123] The configuration shown in Figure 10 makes it easier to integrate into a system compared to a configuration in which information that can determine how much the starting position of the input data 52 for searching for match candidates should be shifted during recompression is stored in DRAM5.
[0124] The header generation circuit 27 may, instead of embedding information in the header of the data being compressed that would allow it to determine how much the starting position of the input data 52 for match candidate search should be shifted during recompression, embed, for example, a flag (recompression flag) indicating that recompression is necessary. In this case, the header analysis circuit 28 analyzes the header of the data being compressed and, upon confirming that recompression is necessary for the data being compressed and that the header does not contain information that would allow it to determine how much the starting position of the input data 52 for match candidate search should be shifted, outputs a default value to the input control circuit 23 as the amount to shift the starting position of the input data 52 for match candidate search.
[0125] Alternatively, the header generation circuit 27 may choose not to embed information in the header of the data being compressed that would allow it to determine how much the starting position of the input data 52 for searching for match candidates should be shifted during recompression. Instead, it may embed, for example, a flag (termination flag) indicating that recompression is not necessary. In this case, the header analysis circuit 28 analyzes the header of the data being compressed, and if it confirms that recompression is not necessary for the data being compressed, it terminates the compression process for that data.
[0126] Furthermore, the header generation circuit 27 may further embed information indicating the data reduction rate calculated by the match selection circuit 33 during the current dictionary compression (i.e., dictionary compression performed on the data in the process of compression) into the header of the data in the process of compression. Alternatively, the header generation circuit 27 may further embed information indicating the size of the compressed data in a dictionary compression performed before the current dictionary compression (for example, the dictionary compression before the previous one) into the header of the data in the process of compression. In this case, the header analysis circuit 28 analyzes the information embedded in the header of the data in the process of compression and outputs a value indicating the amount of shift in the starting position of the input data 52 for match candidate search to the input control circuit 23, as well as the value of the data reduction rate calculated during the dictionary compression performed on the data in the process of compression and a value indicating the size of the compressed data in a dictionary compression performed before the current dictionary compression to the data in the process of compression. This enables the match selection circuit 33 to execute the process of step S12 shown in Figure 6, and enables the compression device 15 to execute the series of compression processes shown in Figure 6.
[0127] The controller 6, which includes the compression device 15 as shown in the first, second, and third embodiments, may, for example, execute a series of compression processes by the compression device 15 on the write data received in response to a write command from the host 2, and then write the compressed data to the NAND flash memory 4. Alternatively, the controller 6 may, for example, read the compressed data stored in the NAND flash memory 4 in response to a command from the host 2 relating to block management of the NAND flash memory 4, which is a command to move valid data in a block containing a mixture of valid and invalid data to another block (i.e., a command to instruct the execution of garbage collection), execute a series of compression processes (recompression) by the compression device 15 on the compressed data, and then write the compressed data (recompressed data) to the NAND flash memory 4.
[0128] According to at least one embodiment described above, it is possible to provide a compression device and a memory system that can improve the compression ratio of a dictionary-type compression circuit while suppressing an increase in the circuit size of the dictionary-type compression circuit.
[0129] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]
[0130] 1...Information processing system, 2...Host, 3...Memory system, 4...NAND flash memory, 5...DRAM, 6...Controller, 10...Bus, 11...CPU, 12...NAND I / F, 13...DRAM I / F, 14...Host I / F, 15...Compressor, 21...Control module, 22...Dictionary-style compression circuit, 23...Input control circuit, 23a...Delay buffer, 24...Dictionary-style decompression circuit, 25...Entropy coding circuit, 26...Entropy decoding circuit, 27...Header generation circuit, 28...Header analysis circuit, 31...Dictionary buffer, 32...Match candidate search circuit, 33...Match selection circuit, 51, 51a, 51b, 51c...Input data for dictionary buffer, 52, 52a, 52b, 52c...Input data for match candidate search, r m ...match search range.
Claims
1. A compression device that compresses the input first data, A dictionary compression circuit includes a dictionary buffer, a match candidate search circuit, and a match selection circuit, and performs dictionary encoding multiple times on the first data, An input control circuit that outputs input data based on the first data to the dictionary-type compression circuit, Equipped with, The aforementioned input control circuit is The match candidate search circuit outputs the first data from a specified starting position as the first input data. The first data is output to the dictionary buffer as a second input data of the same length as the first input data, starting from the beginning position. The dictionary buffer stores, as dictionary data, data equal to the size of the dictionary buffer from the second input data sequentially input from the input control circuit. The match candidate search circuit acquires the dictionary data that matches at least a portion of the first input data sequentially input from the input control circuit, and generates compressed data using dictionary encoding. The aforementioned match selection circuit is If there is compressed data corresponding to the first data that has been previously generated by the match candidate search circuit, the size of the compressed data generated by the current dictionary encoding is compared with the size of the compressed data that has been previously generated and corresponds to the specified starting position, and the smaller compressed data is output. If there is no compressed data corresponding to the first data previously generated by the match candidate search circuit, the compressed data generated by the current dictionary encoding is output. Compressor.
2. The input control circuit shifts the starting position of the first input data by the dictionary buffer size each time it is recompressed. The compression device according to claim 1.
3. The dictionary-based compression circuit determines whether or not to complete the dictionary-based encoding of the first data based on the size of the compressed data generated by the current dictionary-based encoding and the size of previously generated compressed data. The compression device according to claim 1.
4. The input control circuit has a delay buffer, The delay buffer outputs data obtained by delaying the first data by a predetermined delay amount to the dictionary buffer as the second input data. The compression device according to claim 1.
5. The system further includes a dictionary-style decompression circuit that decompresses compressed data corresponding to the first data and outputs the first data. The compression device according to claim 1.
6. An entropy coding circuit that generates compressed data by performing entropy coding on the compressed data generated by dictionary coding using the aforementioned dictionary-based compression circuit, An entropy decoding circuit that performs entropy decoding on compressed data generated by entropy coding, and decodes compressed data generated by dictionary coding, Furthermore, The match selection circuit acquires the compressed data decoded by the entropy decoding circuit as compressed data corresponding to the first data previously generated by the match candidate search circuit. The compression device according to claim 5.
7. The compressed data corresponding to the first data includes a header, The input control circuit, during recompression, determines the starting position of the first input data based on the header. The compression device according to claim 1.
8. The aforementioned header contains information indicating the size of the logical dictionary buffer in this lexicographical encoding. During recompression, the input control circuit determines the starting position of the first input data based on the information contained in the header. The compression device according to claim 7.
9. The header further includes a value calculated based on the size of the compressed data generated by this lexicographical encoding and the size of previously generated compressed data. The compression device according to claim 8.
10. A memory system that can connect to a host, A controller including an interface circuit for receiving instructions from the host, and a compression device for compressing first data received in response to the instructions from the host, Non-volatile memory and It is equipped with, The compression device is A dictionary compression circuit includes a dictionary buffer, a match candidate search circuit, and a match selection circuit, and performs dictionary encoding multiple times on the first data, An input control circuit that outputs input data based on the first data to the dictionary-type compression circuit, Equipped with, The aforementioned input control circuit is The match candidate search circuit outputs the first data from a specified starting position as the first input data. The first data is output to the dictionary buffer as a second input data of the same length as the first input data, starting from the beginning position. The dictionary buffer stores, as dictionary data, data equal to the size of the dictionary buffer from the second input data sequentially input from the input control circuit. The match candidate search circuit acquires the dictionary data that matches at least a portion of the first input data sequentially input from the input control circuit, and generates compressed data using dictionary encoding. The aforementioned match selection circuit is If there is compressed data corresponding to the first data that has been previously generated by the match candidate search circuit, the size of the compressed data generated by the current dictionary encoding is compared with the size of the compressed data that has been previously generated and corresponds to the specified starting position, and the smaller compressed data is output. If there is no compressed data corresponding to the first data previously generated by the match candidate search circuit, the compressed data generated by the current dictionary encoding is output. The controller writes the compressed data corresponding to the first data to the non-volatile memory. Memory system.
11. When the controller receives an instruction from the host to move the data stored in the non-volatile memory, it recompresses the compressed data corresponding to the first data stored in the non-volatile memory using the compression device. The memory system according to claim 10.