Semiconductor equipment

Abstract

To provide a semiconductor device that can ensure a relatively long lifespan while suppressing an increase in circuit area. [Solution] In the electronic device 200, the semiconductor device 100X includes a memory circuit 1x, a correction circuit 2x that reads data d1 from the memory circuit, generates an output signal S2 including corrected data d1b, and generates a reference signal S3 according to whether or not there is an error, and a write control circuit 6 that, when an error is found based on the reference signal, sets the state of the memory circuit to a write-enabled state in which the data can be written back to the correct data.

Description

Technical Field

[0001] The invention disclosed in this specification relates to a semiconductor device.

Background Art

[0002] Conventionally, there is a semiconductor device including a memory circuit and an error correction circuit. The memory circuit is a so-called OTP [One Time Programmable] memory that can write data in a one-time programmable manner. The error correction circuit outputs regular data obtained by correcting an error when there is an error in the data read from the memory circuit.

[0003] As an example of the related conventional technology, Patent Document 1 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] There was room for further consideration regarding the memory life of the semiconductor device disclosed in Patent Document 1.

[0006] The semiconductor device disclosed in this specification includes a memory circuit, a correction circuit, and a control circuit. The memory circuit includes a plurality of memory cells capable of storing 1-bit data and is configured to be able to store data determined by each 1-bit data. The correction circuit is configured to read data from the memory circuit, generate an output signal including regular data obtained by eliminating data errors, and generate a reference signal according to the presence or absence of an error. The write control circuit is configured to set the state of the memory circuit to a write permission state in which data can be rewritten to regular data when there is an error based on the reference signal.

Brief Description of the Drawings

[0007] [Figure 1] Figure 1 is a block diagram showing the configuration of an electronic device 200, which includes a semiconductor circuit 100Y and peripheral circuits 110. [Figure 2] Figure 2 is a block diagram showing the configuration of memory cell 7y. [Figure 3] Figure 3 is a cross-sectional view of the vertical structure of switch elements M1 and M2 during programmed operation of switch element M1. [Figure 4] Figure 4 is a cross-sectional view of the vertical structure of switch elements M1 and M2 during programmed operation of switch element M2. [Figure 5] Figure 5 is a block diagram showing the configuration of an electronic device 200 equipped with a semiconductor device 100X according to this disclosure. [Figure 6] Figure 6 shows the configuration of the memory cell 7x. [Figure 7] Figure 7 shows the memory cell 7x in the first write state. [Figure 8] Figure 8 shows the memory cell 7x in the second write state.

[0008] [Detailed explanation] <Regarding the comparative example semiconductor circuit 100Y> First, the semiconductor circuit 100Y will be described as a comparative example to the semiconductor device 100X of this disclosure. Next, the problems of the comparative example will be explained, and then the semiconductor device 100X of this disclosure will be described.

[0009] Figure 1 is a block diagram showing the configuration of an electronic device 200, which includes a semiconductor circuit 100Y and a peripheral circuit 110. As shown in Figure 1, the electronic device 200 comprises a semiconductor circuit 100Y and a peripheral circuit 110. The electronic device 200 is a device that performs predetermined functions based on the operation of the peripheral circuit 110. The peripheral circuit 110 is a circuit configured to read data d1 from the semiconductor circuit 100Y (more specifically, the memory circuit 1y described later) and perform predetermined operations according to the data d1.

[0010] The semiconductor circuit 100Y comprises a memory circuit 1y and a correction circuit 2y. The memory circuit 1y is a so-called OTP (One Time Programmable) memory, configured to allow data to be written in a one-time programmable manner. In other words, the memory circuit 1y can only be written (=programmed) once, and is configured so that the data cannot be overwritten with other data after the initial write. Here, the data stored in the memory circuit 1y will be referred to as data d1 as an example. Data d1 consists of multiple bits (7 bits, as shown in Figure 1).

[0011] The memory circuit 1y is composed of multiple memory cells 7y. Each memory cell 7y is configured to store 1-bit data (not shown). The data d1 consists of the value ("1" or "0") of the 1-bit data stored in each memory cell 7y.

[0012] Figure 2 is a block diagram showing the configuration of the memory cell 7y. As shown in Figure 2, the memory cell 7y includes a switch element M1, a switch element M2, a first bit line BL1, a second bit line BL2, a word line WL, a first switch SW1, and a sense amplifier 8.

[0013] Switch elements M1 and M2 are N-channel floating-gate MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Switch elements M1 and M2 are capable of programmable operation by changing the characteristics of the transistor through hot carrier injection. Programmable operation is the operation of writing 1-bit data (logical value "1") to switch elements M1 and M2. Switch elements M1 and M2 are also called OTP elements.

[0014] The control gate cg1 of switch element M1 is connected to the word line WL, along with the control gate cg2 of switch element M2. The source of switch element M1 is connected to the source of switch element M2. The drain of switch element M1 is connected to the first terminal of sense amplifier 8 via the first bit line BL1. The drain of switch element M2 is connected to the second terminal of sense amplifier 8 via the second bit line BL2.

[0015] The first terminal of the first switch SW1 is connected to the connection node N1 between switch elements M1 and M2. The second terminal of the first switch SW1 is electrically connected by switching between the ground terminal GND and the terminal to which the writing voltage V1 is applied.

[0016] In programmed operation, hot carriers are injected into switch elements M1 and M2, changing their electrical characteristics. This change causes the gate threshold voltages of switch elements M1 and M2 to rise. Further details about programmed operation will be described later.

[0017] The sense amplifier 8 generates a sense signal Se corresponding to the difference current between the first current I1 flowing through the first input terminal (=current flowing through the first bit line BL1) and the second current I2 flowing through the second input terminal (=current flowing through the second bit line BL2).

[0018] <Regarding writing 1-bit data to memory cell 7y> Figures 3 and 4 are longitudinal cross-sectional views of switch elements M1 and M2. When writing 1-bit data to memory cell 7y, the program operation for switch element M1 is performed in the state shown in Figure 3. Specifically, the operation is as follows: A relatively high voltage write voltage V1 (e.g., 5V) is applied to the word line WL. Then, the connection destination of the second terminal of the first switch SW1 is switched to the terminal to which the write voltage V1 is applied. As a result, the write voltage V1 is applied to the connection node N1 between the source of switch element M1 and the source of switch element M2.

[0019] In this state, for example, when writing a value of "1" to the memory cell 7y, the first bit line BL1 is set to the ground potential GND, and the second bit line BL2 is set to a floating state.

[0020] As a result, a write voltage V1, which is a relatively high voltage, is applied to the source and control gate cg1 of the switching element M1. Also, a ground voltage GND is applied to the drain of the switching element M1. Then, hot carriers E (electrons) flowing from the drain to the source are generated directly below the gate of the switching element M1. The hot carriers E are drawn in by the write voltage V1 (positive voltage) applied to the control gate cg1 and trapped (held) by the source-side sidewall SSw1 located on the side of the control gate cg1.

[0021] Therefore, even if a voltage is applied to the gate of the switching element M1 after the programming operation, the electric field due to the gate voltage does not reach directly below the sidewall SSw1. Then, at this time, the formation of the channel CN1 of the switching element M1 is interrupted on the source side. Accordingly, the threshold voltage of the switching element M1 increases, and the drain current of the switching element M1 becomes difficult to flow.

[0022] Also, for example, when writing a value of "0" to the memory cell 7y, the state as shown in FIG. 4 is set, and a programming operation is executed on the switching element M2. Specifically, the following operations are performed. In this case, in the above-described state (= the state in which the write voltage V1 is applied to the word line WL and 5V is applied to the connection node N1), the second bit line BL2 is set to the ground potential GND, and the first bit line BL1 is set to a floating state.

[0023] As a result, a relatively high voltage, the write voltage V1, is applied to the source and control gate cg2 of the switch element M2. Additionally, a ground voltage GND is applied to the drain of the switch element M2. This generates hot carriers (electrons) flowing from the drain to the source directly below the gate of the switch element M2. These hot carriers are attracted by the write voltage V1 applied to the control gate cg2 and trapped (held) by the source-side sidewall SSw2 located on the side of the control gate cg2 (not shown in the diagram).

[0024] Therefore, after program execution, even if a voltage is applied to the gate of the switch element M2, the electric field due to the gate voltage will no longer reach directly below the sidewall SSw2. At this point, the channel formation of the switch element M2 is interrupted on the source side. Consequently, the threshold voltage of the switch element M2 increases, and the drain current of the switch element M2 becomes less likely to flow.

[0025] Note that only when writing 1 bit of data to each memory cell 7y for the first time, the write voltage V1 is applied to the word line WL and 5V is applied to the connected node N1. After writing 1 bit of data to each memory cell 7y, the state shown in Figure 2 is returned.

[0026] <Regarding the reading of 1-bit data from memory cell 7y> When reading the value of a 1-bit data written to memory cell 7y, the following operation occurs: A read voltage V2 is applied to the word line WL. Then, the first current I1 flowing through the first bit line BL1 becomes a current value corresponding to the gate-source voltage of switch element M1. Similarly, the second current I2 flowing through the second bit line BL2 becomes a current value corresponding to the gate-source voltage of switch element M2. Note that the read voltage V2 is lower than the write voltage V1 (for example, 2.8V).

[0027] Furthermore, if a hot carrier E is trapped on the sidewall SSw1 of switch element M1, but not on the sidewall SSw2 of switch element M2, the threshold voltage of switch element M1 will be higher than the threshold voltage of switch element M2. As a result, the current value of the first current I1 will be smaller than the current value of the second current I2. In response to this, the sense amplifier 8 generates a sense signal Se that indicates that a 1-bit data of "1" is stored in the memory cell 7y.

[0028] Furthermore, if a hot carrier E is trapped on the sidewall SSw2 of switch element M2, but not on the sidewall SSw1 of switch element M1, the threshold voltage of switch element M2 will be higher than the threshold voltage of switch element M1. As a result, the current value of the second current I2 will be smaller than the current value of the first current I1. In response to this, the sense amplifier 8 generates a sense signal Se that indicates that a 1-bit data of "0" is stored in the memory cell 7y.

[0029] In this way, the sense signal Se generated by the sense amplifier 8 makes it possible to read out whether the value of the 1-bit data stored in the memory cell 7y is "1" or "0".

[0030] <Regarding error correction> Returning to Figure 1, the correction circuit 2y reads data d1 from the memory circuit 1y and generates the output signal S2. At this time, the correction circuit 2y can detect whether or not there is an error in the read data d1. Here, the data d1 that is stored in the memory circuit 1y when an error has occurred is called the erroneous data d1a. The original data d1, after the error in the erroneous data d1a has been corrected, is also called the normal data d1b.

[0031] The incorrect data d1a can be described as a case of so-called data corruption (more precisely, bit corruption). In other words, as shown in Figure 1, the incorrect data d1a has the bit values ​​at predetermined positions reversed compared to the normal data d1b, or it is in an uncertain state (i.e., a different value is output each time it is read).

[0032] When the correction circuit 2y detects that the data d1 read from the memory circuit 1y is erroneous data d1a, it generates corrected data d1b from the erroneous data d1a. The correction circuit 2y then generates an output signal S2 that includes the generated corrected data d1b. The peripheral circuit 110 receives the output signal S2 from the correction circuit 2y and performs a predetermined operation based on the corrected data d1b. The correction circuit 2y will be described in more detail below.

[0033] The correction circuit 2y comprises an encoding circuit 3, a decoding circuit 4, and an output signal generation circuit 5. The encoding circuit 3 generates an error correction code when writing data d1 to the memory circuit 1y. The encoding circuit 3 then adds the generated error correction code to the data d1. In other words, the data d1 stored in the correction circuit 2y includes the original data to be output to the peripheral circuit 110 and the error correction code described above.

[0034] When the decoding circuit 4 reads data d1 from the memory circuit 1y, it decodes the error correction code contained in data d1. Based on the information obtained by decoding the error correction code, the decoding circuit 4 detects whether or not there is an error in the original data contained in data d1 (=the original data to be output to the peripheral circuit 110). If data d1 contains an error (=data d1 is incorrect data d1a), the decoding circuit 4 detects the erroneous bit (=bit corruption) and corrects the value of this bit to its original value.

[0035] The bit corruption in each bit of data d1 is corrected by the decoding circuit 4, thereby eliminating the error in the erroneous data d1a. This generates the correct data d1b. The output signal generation circuit 5 generates an output signal S2 that includes the correct data d1b and inputs it to the peripheral circuit 110.

[0036] <Considerations on Error Correction and Memory Lifespan> Incidentally, as time passes from the time 1 bit of data is written to the memory circuit 1y, the bit corruption described above becomes more likely to occur. A more detailed explanation is as follows:

[0037] As described above, data d1 consists of 1-bit data stored in each memory cell 7y. And as described above, the value of the 1-bit data written to each memory cell 7y is determined to be either "1" or "0" depending on the state of the hot carrier E trapped in the sidewalls SSw1 and SSw2 of the switch elements M1 and M2.

[0038] Here, the hot carrier E trapped in the sidewalls SSw1 and SSw2 of the switch elements M1 and M2 is slowly released to the outside over time. For this reason, if hot carrier E is released from the sidewalls SSw1 and SSw2 of the switch elements M1 and M2 over a period of time, such as years, the differential current between the first current I1 and the second current I2 may gradually change from its initial state. If this change in differential current exceeds a predetermined amount, the detection result of the sense amplifier 8 will differ from the original result. As a result, the sense signal Se will show an incorrect value (= bit corruption) that is different from the value of the 1 bit data that was originally written.

[0039] If a predetermined amount of charge is released from the sidewalls SSw1 and SSw2 of the switch elements M1 and M2 in each memory cell 7y, bit corruption will occur in the 1-bit data. When bit corruption occurs, the output may be the original value of the 1-bit data or a value different from the original value of the 1-bit data, making the value of data d1 included in the read signal S1 uncertain.

[0040] As described above, when the correction circuit 2y detects the erroneous data d1a, it generates the correct data d1b by correcting the error in the erroneous data d1a. More specifically, it corrects the bits that have been corrupted as described above to their original values ​​to generate the correct data d1b.

[0041] Incidentally, as time passes after writing data d1 to memory circuit 1y, bit corruption is more likely to occur in each memory cell 7y, as described above. That is, the number of bit corruptions in data d1 increases. If a large number of bit corruptions occur in data d1, the correction circuit 2y will no longer be able to correct all of them. In that case, the output signal S2 will include erroneous data d1a whose errors have not been corrected. In this case, the operation of peripheral circuit 110 and, consequently, the function of electronic device 200 may be impaired. Therefore, the time when the correction circuit 2y can no longer correct all of the bit corruptions is the end of the lifespan of semiconductor circuit 100Y.

[0042] In recent years, there has been a demand for longer lifespan in such memory circuits 1y. It is thought that the lifespan of the semiconductor circuit 100Y can be extended by increasing the number of bits that can be error corrected by the correction circuit 2y. However, in this case, the number of parity bits required for error correction will increase, leading to an increase in the circuit area of ​​the correction circuit 2y.

[0043] To address these issues, the semiconductor device 100X of this disclosure is designed to ensure a relatively long lifespan while suppressing an increase in circuit area. The semiconductor device 100X according to the embodiment of this disclosure will be described in detail below. Note that the semiconductor device 100X according to the embodiment of this disclosure includes components common to the semiconductor circuit 100Y described earlier. For this reason, the same reference numerals are used for the common components and their descriptions are omitted.

[0044] <Regarding the semiconductor device 100X of the first embodiment related to this disclosure> Figure 5 is a block diagram showing the configuration of an electronic device 200 equipped with a semiconductor device 100X according to the present disclosure. As shown in Figure 5, the semiconductor device 100X includes a memory circuit 1x, a correction circuit 2x, and a write control circuit 6.

[0045] The memory circuit 1x is a so-called OTP memory, configured to allow data to be written in a one-time programmable manner. That is, the memory circuit 1x can only write data once on its initial execution. However, if data is written to a different data after the initial write, the difference current between I1 and I2 disappears, and the sense signal Se generated by the sense amplifier 8 allows the output of incorrect data, while prohibiting the rewriting of data to a different data after the initial write.

[0046] However, even after the initial write operation, the sense signal Se of the memory circuit 1x will not be incorrect if the data is the same as the data written. In other words, if the data d1 written to the memory circuit 1x has the above-mentioned error (=bit corruption), it is configured to be restored to the original data d1 (=normal data d1b) with the error corrected, by the method described later. The detailed configuration of the memory circuit 1x will be described later.

[0047] Correction circuit 2x corresponds to the previously mentioned correction circuit 2y. In other words, when correction circuit 2x detects that the data d1 read from memory circuit 1x is incorrect data d1a, it generates correct data d1b from the incorrect data d1a. Then, correction circuit 2x generates an output signal S2 that includes the generated correct data d1b.

[0048] The correction circuit 2x includes an encoding circuit 3, a decoding circuit 4, and an output signal generation circuit 5, similar to those described above. The encoding circuit 3 generates an error correction code when writing data d1 to the memory circuit 1x. The encoding circuit 3 then adds the generated error correction code to the data d1.

[0049] When the decoding circuit 4 reads data d1 from the memory circuit 1x, it decodes the error correction code contained in data d1. The decoding circuit 4 then detects whether or not there is an error in data d1. If there is an error in data d1 (i.e., data d1 is incorrect data d1a), the decoding circuit 4 detects the erroneous bit (i.e., bit corruption) and generates corrected data d1b by correcting the value of this bit to its original value.

[0050] The output signal generation circuit 5 of this disclosure inputs the output signal S2 to the peripheral circuit 110 and the memory circuit 1x (more specifically, to the external terminal T1 of the memory circuit 1x).

[0051] In addition to the configuration described above, the correction circuit 2x includes a reference signal generation circuit 10. The reference signal generation circuit 10 generates a reference signal S3 based on the read signal S1, that is, according to whether or not there is an error in the data d1 read from the memory circuit 1x.

[0052] The reference signal S3 is a digital signal with a voltage value that is either high level (= power supply voltage reference) or low level (= ground voltage GND reference). For example, if there is an error in the data d1 read from the memory circuit 1x, the reference signal generation circuit 10 raises the reference signal S3 to a high level. Conversely, if there is no error in the data d1 read from the memory circuit 1x, the reference signal generation circuit 10 lowers the reference signal S3 to a low level. The reference signal S3 is input to the write control circuit 6.

[0053] The write control circuit 6 generates a write control signal S4 based on the reference signal S3. The write control signal S4 is a digital signal having either a high level (= power supply voltage reference) or a low level (= ground voltage GND reference) voltage value. The write control signal S4 is input to the external terminal T2 of the memory circuit 1x. When the write control circuit 6 detects the rising edge of the reference signal S3, it switches the logic level of the write control signal S4 to either a high level or a low level.

[0054] The memory circuit 1x performs a write-back operation of the data d1 stored within itself based on the output signal S2 and the write control signal S4. More specifically, it is as follows:

[0055] If the correction circuit 2x reads an error in the data d1 from the memory circuit 1x, the reference signal S3 rises to a high level. When the write control circuit 6 detects the high-level pulse edge (rising edge or falling edge) of the reference signal S3, it raises the write control signal S4 to a high level at a predetermined timing. For example, when writing the data d1 from the memory circuit 1x back to the correct data d1b, the write control signal S4 is raised to a high level at an appropriate timing. The write control circuit 6 also lowers the write control signal S4 to a low level at a predetermined timing once the writing back to the correct data d1b is complete.

[0056] The memory circuit 1x is configured to either write-enabled or read-enabled based on the logic level of the write control signal S4. The write-enabled state is the state of the internal circuitry of the memory circuit 1x (details of which will be described later) in which the regular data d1b can be written back. The memory circuit 1x is also in the write-enabled state when the data d1 is written to the memory circuit 1x for the first time. On the other hand, the read-enabled state is the state of the internal circuitry of the memory circuit 1x in which the data d1 can be read and output as a read signal S1.

[0057] For example, when the write control signal S4 is at a high level, the memory circuit 1x enters a write-enabled state. Conversely, when the write control signal S4 is at a low level, the memory circuit 1x enters a read state.

[0058] When the memory circuit 1x is in a write-enabled state, it receives the write control signal S4 and can write the data d1 stored in itself back to the correct data d1b. Also, when the memory circuit 1x is in a read state, it receives a signal from the correction circuit 2x and outputs a read signal S1. Details of the internal configuration of the memory circuit 1x are as follows.

[0059] <Detailed configuration of memory circuit 1x> The memory circuit 1x is composed of multiple memory cells 7x. Each memory cell 7x is configured to store 1 bit of data.

[0060] Figure 6 shows the configuration of the memory cell 7x. Note that Figure 6 shows the memory cell 7x in the read state, which will be described later. As shown in Figure 6, the memory cell 7x is equipped with the same switch element M1, switch element M2, first bit line BL1, second bit line BL2, word line WL, and sense amplifier 8 as described above. In addition, the memory cell 7x is equipped with a first switch SW1, a second switch SW2, and a third switch SW3.

[0061] The first terminal of the first switch SW1 is connected to the connection node N1. The second terminal of the first switch SW1 is electrically connected by switching between the ground terminal GND and the terminal to which the write voltage V1 is applied.

[0062] The first terminal of the second switch SW2 is connected to the first bit line BL1. The second terminal of the second switch SW2 can be switched to either electrically connected to the ground terminal GND or disconnected. The first terminal of the third switch SW3 is connected to the second bit line BL2. The second terminal of the third switch SW3 can be switched to either electrically connected to the ground terminal GND or disconnected.

[0063] The first to third switches SW1 to SW3 are controlled to switch based on the output signal S2. The memory circuit 1x enters either the write-enabled state or the read state described above by switching the first to third switches SW1 to SW3 of each memory cell 7x. Specifically, this is as follows:

[0064] <Regarding writing permission status> When the memory circuit 1x is in a write-enabled state, the memory cell 7x switches to either a first write state or a second write state. The first write state is the state in which "1" is written to the memory cell 7x. The second write state is the state in which "0" is written to the memory cell 7x.

[0065] The first write state can be explained in more detail as follows. Figure 7 shows the memory cell 7x in the first write state. As shown in Figure 7, in the first write state, the second terminal of the first switch SW1 is connected to the terminal to which the write voltage V1 is applied, and the write voltage V1 is applied to the connection node N1. The second switch SW2 is turned on, and the first bit line BL1 is connected to the ground terminal GND. The third switch SW3 is turned off, and the second bit line BL2 is disconnected from the ground terminal GND. At this time, the second bit line BL2 is in a floating state. In this state, when the write voltage V1 is applied to the word line WL, a hot carrier E is trapped in the sidewall SSw1 of the switch element M1. However, the sidewall SSw2 of the switch element M2 is not trapped because the bit line is floating due to SW3, so no hot carrier E is generated.

[0066] On the other hand, the second write state can be explained in more detail as follows. Figure 8 shows the memory cell 7x in the second write state. As shown in Figure 8, in the second write state, the second terminal of the first switch SW1 is connected to the terminal to which the write voltage V1 is applied, and the write voltage V1 is applied to the connected node N1. Also, the second switch SW2 is turned off, and the first bit line BL1 is disconnected from the ground terminal GND. Then the third switch SW3 is turned on, and the second bit line BL2 is connected to the ground terminal GND. At this time, the first bit line BL1 is in a floating state. In this state, when the write voltage V1 is applied to the word line WL, a hot carrier E is trapped in the sidewall SSw2 of the switch element M2. However, the sidewall SSw1 of the switch element M1 is not trapped because the bit line is floating due to SW2, so no hot carrier E is generated.

[0067] Furthermore, the memory circuit 1x enters the write-enabled state described above not only when writing data d1 back to the regular data d1b, but also when writing data d1 to the memory circuit 1x for the first time. Similarly, in this case, the write control circuit 6 raises the write control signal S4 to a high level, and the memory circuit 1x enters the write-enabled state in response to the high-level write control signal S4.

[0068] <About the reading status> Returning to Figure 6, in the readout state, the second terminal of the first switch SW1 is connected to the ground terminal GND, and the ground voltage GND is applied to the connection node N1. Also, the second switch SW2 is turned off, disconnecting the first bit line BL1 from the ground terminal GND. Then the third switch SW3 is turned off, disconnecting the second bit line BL2 from the ground terminal GND.

[0069] At this time, the first bit line BL1 and the second bit line BL2 are in a non-floating state. In this state, a read voltage V2 is applied to the word line WL, and the first current I1 and the second current I2 flow. As described above, the first current I1 and the second current I2 are current values ​​corresponding to the state of the hot carrier E trapped in the sidewalls SSw1 and SSw2 of the switch elements M1 and M2, respectively. The sense amplifier 8 detects the difference current between the first current I1 and the second current I2 and generates a sense signal Se.

[0070] As described above, when the write control signal S4 is high, the memory circuit 1x enters a write-enabled state. At this time, each memory cell 7x enters either the first write state or the second write state, and can reinject (trap) hot carriers E into the sidewalls SSw1 and SSw2 of the switch elements M1 and M2. In other words, even if hot carriers E are released from the sidewalls SSw1 and SSw2 of the switch elements M1 and M2 of each memory cell 7x, causing bit corruption, the hot carriers E can be reinjected (trapped) into the sidewalls SSw1 and SSw2 based on the output signal S2 and the write control signal S4.

[0071] Therefore, even if an error occurs in the data d1 written to the memory circuit 1x, resulting in incorrect data d1a, it is possible to write back the correct data d1b from the incorrect data d1a.

[0072] As mentioned above, if a bit error occurs in data d1, the correction circuit 2x detects the bit error. Each time the correction circuit 2x detects a bit error, data d1 is written back to the correct data d1b. Therefore, data d1 is written back to the correct data d1b before a large number of bit errors occur. Thus, it is possible to prevent the correction circuit 2x from reaching a point where it is unable to correct all the errors. As a result, even if years have passed since the initial writing of data d1 to the memory circuit 1x, the output signal S2 is less likely to contain erroneous data d1a. Consequently, it becomes possible to extend the lifespan of the semiconductor device 100X without reducing the circuit area.

[0073] <Variation> Furthermore, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of this disclosure. For example, when storing the value "1" as a 1-bit data, the memory cell 7x is set to the first write state, but it may be set to the second write state instead. In this case, as described above, the hot carrier E is trapped in the source sidewall SSw2 of the switch element M2, so the current value of the second current I2 becomes smaller than the current value of the first current I1. In this case, the sense amplifier 8 detects that the current value of the second current I2 is smaller than the current value of the first current I1 and generates a sense signal Se that indicates that the value stored in the memory cell 7x is "1".

[0074] In this case, when storing "0" as the value of 1 bit data, the memory cell 7x is put into the first write state. As described above, in this case, the hot carrier E is trapped on the source sidewall SSw1 of the switch element M1, so the current value of the first current I1 becomes smaller than the current value of the second current I2. In this case, the sense amplifier 8 detects that the current value of the first current I1 is smaller than the current value of the second current I2 and generates a sense signal Se that indicates that the value stored in the memory cell 7x is "0".

[0075] <Note> The semiconductor device (100X) disclosed in the specification includes: a memory circuit (1x) configured to store data (d1) determined by each of the 1-bit data, including a plurality of memory cells (7x) capable of storing 1-bit data; a correction circuit (2x) configured to read the data (d1) from the memory circuit (1x), generate an output signal (S2) including corrected data (d1b) with errors corrected, and generate a reference signal (S3) according to whether or not there is an error; and a write control circuit (6) configured to change the state of the memory circuit (1x) to a write-enabled state in which the data (d1) can be written back to the correct data (d1b) when an error is found based on the reference signal (S3) (first configuration).

[0076] The semiconductor device (100X) according to the first configuration includes a control circuit that generates a write control signal (S4) based on a reference signal (S3), a memory circuit (1x) that includes a first terminal (T1) that receives an input of an output signal (S2) and a second terminal (T2) that receives an input of a write control signal (S4), and a correction circuit (2x) that can detect errors from data (d1) read from the memory circuit (1x). If an error is detected, the memory circuit (1x) changes its state according to the write control signal (S4) to a state in which it can write the data (d1) back to the correct data (d1b) based on the output signal (S2) (second configuration).

[0077] In the first or second configuration, the semiconductor device (100X) has a memory circuit (1x) that is capable of writing data (d1) in a one-time programmable manner (third configuration).

[0078] The semiconductor device (100X) in the third configuration includes a memory cell (7x) comprising a first switch element (M1) and a second switch element (M2) configured such that the magnitude of the current flowing between the drain and source changes according to the gate-source voltage difference, and each of the first switch element (M1) and the second switch element (M2) is configured to be programmable by trapping hot carriers (E) on its sidewalls (SSw1, SSw2), and the memory circuit (1x) is capable of writing data (d1) in a one-time programmable manner by executing a program operation on one of the first switch element (M1) and the second switch element (M2) of each memory cell (7x), and after the data (d1) has been written for the first time, the memory circuit (1x) writes the data (d1) back to normal data (d1b) by executing a program operation on one of the first switch element (M1) and the second switch element (M2) based on a write control signal (S4) (fourth configuration).

[0079] The semiconductor device (100X) according to the fourth configuration is configured such that the sources of the first switch element (M1) and the second switch element (M2) of each memory cell (7x) are electrically connected to be at the same potential, and the control gates (cg1, cg2) of the first switch element (M1) and the second switch element (M2) of each memory cell (7x) are electrically connected to be at the same potential, and each memory cell (7x) includes a sense amplifier (8) configured to generate a read signal (S1) corresponding to the difference current between the drain current of the first switch element (M1) and the drain current of the second switch element (M2), and the correction circuit (2x) reads data (d1) from the memory circuit (1x) based on the read signal (S1) generated by the sense amplifier (8) of each memory cell (7x) (fifth configuration). [Explanation of Symbols]

[0080] 1x, 1y memory circuit 2x, 2y correction circuit 3 Encoding circuit 4. Decoding circuit 5. Output signal generation circuit 6. Programming control circuit 7x memory cells 7y memory cell 8 Sense Amplifier 10 Reference signal generation circuit 100X, 100Y semiconductor device 110 Peripheral Circuits 200 Electronic equipment BL1 1st bit line BL2 2nd bit line GND grounding end I1 1st current I2 2nd current M1, M2 switching elements N1 connected node S1 Readout signal S2 output signal S3 Reference signal S4 Write control signal SW1 1st switch SW2 Second Switch SW3 3rd Switch SSw1 Sidewall SSw2 Sidewall Se sense signal T1 External terminal T2 External Terminal V1 Writing Voltage V2 Readout Voltage WL Wardline CG1 Control Gate CG2 Control Gate d1 data d1a Incorrect data d1b normalized data

Claims

1. A memory circuit comprising multiple memory cells capable of storing 1-bit data, configured to store data determined by each of the 1-bit data, A correction circuit is configured to read the data from the memory circuit, generate an output signal containing corrected data with errors removed, and generate a reference signal according to the presence or absence of the errors. A write control circuit is configured to set the state of the memory circuit to a write-enabled state in which the data can be written back to the correct data when an error occurs based on the reference signal, A semiconductor device equipped with a semiconductor device.

2. The control circuit generates a write control signal based on the reference signal, The aforementioned memory circuit is A first terminal that receives the input of the output signal, A second terminal that receives the input of the aforementioned write control signal, Equipped with, The correction circuit is capable of detecting the error from the data read from the memory circuit. The semiconductor device according to claim 1, wherein, when the aforementioned error is detected, the memory circuit changes its state in accordance with the write control signal to a state in which it can write the data back to the correct data based on the output signal.

3. The semiconductor device according to claim 1, wherein the memory circuit is capable of writing the data in a one-time programmable manner.

4. The memory cell comprises a first switch element and a second switch element configured such that the magnitude of the current flowing between the drain and source changes according to the gate-source voltage difference. Each of the first and second switch elements is configured to perform programmed operations by trapping hot carriers in its sidewall, The memory circuit can write the data in a one-time programmable manner by executing a program operation on one of the first switch element and the second switch element of each memory cell. The semiconductor device according to claim 3, wherein the memory circuit, after the data has been written for the first time, executes a program operation on one of the first switch element and the second switch element based on the write control signal, thereby writing the data back to the normal data.

5. The sources of the first and second switching elements of each memory cell are electrically connected so that they are at the same potential. The control gates of the first and second switch elements of each memory cell are electrically connected to each other so that they are at the same potential. Each memory cell includes a sense amplifier configured to generate a readout signal corresponding to the difference current between the drain current of the first switch element and the drain current of the second switch element. The semiconductor device according to claim 4, wherein the correction circuit reads the data from the memory circuit based on the read signal generated by the sense amplifier of each of the memory cells.

Images