Memory drive circuit, memory device, and electronic device

Abstract

Memory devices are required to have a reduced circuit area. [Solution] The memory drive device comprises a plurality of word lines, a word line drive circuit, and a charge share circuit. The charge share circuit is configured to equalize the potential by short-circuiting any of the plurality of word lines. When switching between a non-selected word line and a selected word line, the word line drive circuit puts the selected and non-selected word lines to be switched into a high-impedance state without supplying a control voltage. The charge share circuit, as an arbitrary choice, short-circuits the selected and non-selected word lines to be switched into a charge share state with an intermediate potential lower than the first logic level and higher than the second logic level.

Description

Technical Field

[0006] , ,

[0005]

[0001] The invention disclosed in this specification relates to a memory drive circuit, a memory device, and an electronic device.

Background Art

[0002] A memory device includes a memory array in which memory cells are arranged in a matrix, and cell peripheral circuits (row decoder circuit, column decoder circuit) arranged around the memory array.

[0003] As an example of the related prior art, Patent Document 1 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] The memory device disclosed in Patent Document 1 is desired to reduce the circuit area.

[0006] The memory drive device disclosed herein comprises a plurality of word lines, a word line drive circuit, and a charge share circuit. The plurality of word lines are each connected to a plurality of memory cells. The word line drive circuit is configured to supply a control voltage to each of the plurality of word lines. The charge share circuit is configured to short-circuit any of the plurality of word lines to equalize their potentials. The plurality of word lines are configured such that the word line connected to the memory cell to be accessed is designated as the selected word line, and the word lines connected to memory cells not to be accessed are designated as the deselected word lines. The word line drive circuit supplies a control voltage of a first logic level to the selected word line and a control voltage of a second logic level lower than the first logic level to each deselected word line. When switching between deselected and selected word lines, the word line drive circuit does not supply a control voltage to the selected and deselected word lines being switched, placing them in a high-impedance state. The charge share circuit optionally short-circuits the selected and deselected word lines being switched, resulting in a charge share state with an intermediate potential lower than the first logic level and higher than the second logic level.

[0007] The memory device disclosed herein comprises a memory drive device having the above configuration; a memory cell array in which a plurality of memory cells are arranged in a matrix along the transverse direction in which a word line extends and a vertical direction orthogonal to the transverse direction; a plurality of bit lines extending along the vertical direction and connected to each of the transversely aligned memory cells; a bit line drive circuit configured to supply a predetermined voltage to each of the plurality of bit lines; and a voltage generation circuit configured to supply a control voltage to the word line drive control and a predetermined voltage to the bit line drive circuit when accessing any of the plurality of memory cells.

[0008] The electronic devices disclosed herein include a memory device having the above configuration.

[0009] The vehicles disclosed herein are equipped with the electronic equipment having the above configuration. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a schematic layout diagram showing the configuration of memory device 1Y according to a comparative example. [Figure 2] Figure 2 is a timing chart showing the voltage states of selected and unselected word lines. [Figure 3] Figure 3 shows the configuration of the memory device 1X according to this disclosure. [Figure 4] Figure 4 shows the configuration of driver IVI. [Figure 5] Figure 5 is a timing chart showing the voltage states of word lines WL0 and WLn, and driver control signals B0 and Bn when the selected word line and the unselected word line in the memory device 1X are switched. [Figure 6] Figure 6 shows the configuration of the control signal generation circuit CCi. [Figure 7] Figure 7 is a timing chart showing the voltage states of the control signal generation circuit CCi. [Figure 8] Figure 8 shows the electronic device 500 on which the memory device 1X is mounted, and the vehicle Z equipped with the electronic device 500.

[0011] [Detailed explanation] <Regarding the comparative example memory device 1Y> First, memory device 1Y will be described as a comparative example to memory device 1X of this disclosure. Next, the problems of the comparative example will be explained, and then memory device 1X of this disclosure will be described.

[0012] Figure 1 is a schematic layout diagram showing the configuration of memory device 1Y in a comparative example. Figure 1 shows the orthogonal X-direction (vertical direction) and Y-direction (horizontal direction). Figure 1 is a plan view taken perpendicular to the X-direction and Y-direction.

[0013] The memory device 1Y shown in Figure 1 comprises a memory array 100 and a memory drive unit 10y. The memory device 1Y is integrated on a single semiconductor substrate.

[0014] The memory array 100 is a non-volatile memory. Here, the memory array 100 is configured as an EEPROM, for example. The memory array 100 includes memory cells arranged in a matrix in the X and Y directions (not shown). Each memory cell can store 1 bit of data.

[0015] The memory drive unit 10y includes a row decoder 200, word lines WL0 to WLn (where n is a natural number including 0), a column decoder 300, a voltage generation circuit 30, and a bit line (not shown).

[0016] The row decoder 200 and column decoder 300 are cell peripheral circuits located around the memory array 100.

[0017] Word lines WL0 to WLn are address selection lines. Word lines WL0 to WLn are drawn from the line decoder 200, extend in the X direction, and are connected to the memory array 100. Word lines WL0 to WLn traverse the memory array 100 in the X direction.

[0018] The bit line is drawn from the column decoder 300, extends in the Y direction, and is connected to the memory array 100 (not shown). The bit line is an address selection line. The bit line traverses the memory array 100 in the Y direction.

[0019] The row decoder 200 decodes the address data signal in the X direction and selects the word line. The column decoder 300 decodes the address data signal in the Y direction and selects the bit line. The memory cells corresponding to the selected word line and bit line become the memory cells selected for access. The address data signals in the X and Y directions are transmitted according to the pulse period of the clock signal CLK.

[0020] The voltage generation circuit 30 boosts the power supply voltage Vcc to generate control voltages Va and Vb. The voltage generation circuit 30 supplies the control voltage Va to the row decoder 200. Also, the voltage generation circuit 30 supplies the control voltage Vb to the column decoder 300. For example, the voltage generation circuit 30 can employ a charge pump circuit using a flying capacitor.

[0021] The voltage generation circuit 30 generates a relatively high voltage (e.g., 10 to 15 V) write voltage Vw as the control voltage Va during data writing described later. Also, the voltage generation circuit 30 generates a read voltage Vr that is lower than the write voltage Vw during data reading described later.

[0022] The voltage generation circuit 30 supplies the control voltage Va to the row decoder 200 via a power supply line VL and a ground line GL (not shown). More specifically, it supplies the write voltage Vw and the read voltage Vr via the power supply line VL. Also, the voltage generation circuit 30 supplies the ground voltage GND via the ground line GL. Note that when simply referred to as "control voltage Va" below, it can be interpreted as any of the write voltage Vw, the read voltage Vr, and the ground voltage GND.

[0023] During data reading, data is read from the selected memory cell using a sense amplifier (not shown). The sense amplifier is arranged in the sense amplifier area. The number of sense amplifiers provided is the same as the number of bits of the memory cell. That is, if it is 8 bits, 8 sense amplifiers are provided.

[0024] Also, during data writing, the write voltage Vw is applied to the selected memory cell. By applying the write voltage Vw, data writing (= write process) is performed to the selected memory cell. The write voltage Vw is a relatively high voltage. Note that the write voltage Vw is generated by a charge pump circuit (not shown).

[0025] The row decoder 200 has drivers IV0 to IVn. Drivers IV0 to IVn are inverters. Each of drivers IV0 to IVn is individually connected to each of the word lines WL0 to WLn. Each of drivers IV0 to IVn drives each of the word lines WL0 to WLn individually. Here, "drive" means applying a control voltage Va (more specifically, a write voltage Vw, a read voltage Vr, or a ground voltage GND) to each of the word lines WL0 to WLn. Also, each of drivers IV0 to IVn can be individually deactivated, thereby cutting off the supply of the control voltage Va to each of the word lines WL0 to WLn individually and creating a high-impedance state.

[0026] During the data reading process described above, the read voltage Vr is applied as the control voltage Va to the selected word line WL0 to WLn (hereinafter also referred to as the "selected word line"). At the same time, the ground voltage GND is applied as the control voltage Va to the unselected word line WL0 to WLn (hereinafter also referred to as the "unselected word line").

[0027] Similarly, during the data writing process described above, the write voltage Vw is applied to the selected word line as the control voltage Va. At the same time, the ground voltage GND is applied to the unselected word line as the control voltage Va.

[0028] Figure 2 is a timing chart showing the voltage states of the selected and unselected word lines. In Figure 2, at a predetermined timing t1, word line WL0 switches from a selected word line to an unselected word line, and word line WLn switches from an unselected word line to a selected word line.

[0029] As shown in Figure 2, when switching from a non-selected word line to a selected word line, the voltage applied to the word line to be switched (in this case, word line WLn) (=control voltage Va) is raised from a low level (=ground voltage GND) to a high level (=write voltage Vw or read voltage Vr) at the switching timing (timing t1 in the figure).

[0030] Conversely, when switching from a selected word line to a deselected word line, as shown in word line WL0 in Figure 2, the voltage applied to the word line being switched (in this case, word line WL0) (=control voltage Va) is lowered from a high level (write voltage Vw or read voltage Vr) to a low level (=ground voltage GND) at the switching timing.

[0031] Here, the high-level control voltage Va is the write voltage Vw during data writing and the read voltage Vr during data reading. The low-level control voltage Va is the ground voltage GND.

[0032] <Considerations regarding power consumption during selective / non-selective switching> As described above, when switching from a selected word line to a deselected word line, the applied voltage (= control voltage Va) is lowered from a high level to a low level. At this time, the deselected word line is connected to the application terminal of the ground voltage GND (hereinafter also simply referred to as the "ground terminal"). Then, charge is discharged from the memory element connected to the deselected word line to the ground terminal. On the other hand, when switching from a deselected word line to a selected word line, it is necessary to raise the applied voltage (= control voltage Va) from a low level to a high level.

[0033] Rising the voltage from ground voltage GND to read voltage Vr and write voltage Vw consumes a relatively large amount of power. In particular, as mentioned above, the write voltage Vw is a relatively high voltage and is generated by a voltage generation circuit 30 that employs a charge pump or the like. Therefore, during data writing, more power is consumed each time the memory cell being accessed switches.

[0034] However, when switching from a selected word line to a deselected word line, charge is simply released from each memory element connected to the deselected word line to the ground terminal. This released charge was not being effectively utilized.

[0035] These problems become more pronounced when the memory array 100 employs a so-called complementary memory configuration. In this case, each memory cell in the memory array 100 has two memory elements. Furthermore, as the bit width (number of bits in the X direction) of the memory array 100 increases, the number of memory cells connected to each of the word lines WL0 to WLn also increases.

[0036] To illustrate with a specific example, consider the following: For instance, if the bit width is 64 bits (i.e., 64 memory cells are connected to one word line), then 128 memory elements are connected to one word line. In this case, while the 128 memory cells that have switched from a selected word line to a deselected word line release charge, a separate control voltage Va is applied to supply charge to another 128 memory cells that have switched from a deselected word line to a selected word line.

[0037] As the bit width increases, the additional capacitance of each memory cell connected to each word line WL0 to WLn also increases. A larger additional capacitance means a larger amount of charge is released. Furthermore, a larger additional capacitance increases the driving load on drivers IV0 to IVn when raising the control voltage Va from a low level (=ground voltage GND) to a high level (=read voltage Vr or write voltage Vw).

[0038] Furthermore, the voltage generation circuit 30 that supplies the control voltage Va to the row decoder 200, which experiences such a large drive load, requires a relatively high boosting capability. Consequently, this leads to an increase in the circuit area of ​​the voltage generation circuit 30, and consequently, an increase in the circuit area of ​​the memory drive unit 10y and the memory unit 1Y.

[0039] To address these issues, the memory device 1X of this disclosure is capable of reducing power consumption and circuit area. The memory device 1X according to the embodiment of this disclosure will now be described in detail. Note that the memory device 1X according to the embodiment of this disclosure includes components common to the previously described memory device 1Y. Therefore, the same reference numerals are used for the common components, and their descriptions are omitted.

[0040] <Regarding the memory device 1X of the embodiment described herein> Figure 3 shows the configuration of the memory device 1X according to this disclosure. The memory device 1X includes a memory array 100 similar to that described above. In addition, the memory device 1X includes a memory drive unit 10x. The memory device 1X is integrated on a single semiconductor substrate.

[0041] The memory drive unit 10x includes a row decoder 200, a column decoder 300, a voltage generation circuit 30, and word lines WL0 to WLn, similar to those described above. In addition, the memory drive unit 10x includes a charge share circuit 201 and a drive controller 202.

[0042] The charge share circuit 201 is configured to allow selection of connection or disconnection for each of the word lines WL0 to WLn. More specifically, the charge share circuit 201 is configured to switch any two of the word lines WL0 to WLn between short (conductive state) or release (disconnected state). Specifically, it is as follows:

[0043] The charge share circuit 201 includes switches SW0 to SWn and a charge share line SL. Each of switches SW0 to SWn is a switch that can switch between a conductive state and a conductive state between its first and second terminals.

[0044] The first terminal of each switch SW0 to SWn is individually connected to each of the word lines WL0 to WLn. The second terminal of each switch SW0 to SWn is all connected to the charge share line SL. In other words, the charge share line SL can be individually switched between conducting and non-conducting states for each of the word lines WL0 to WLn via switches SW0 to SWn.

[0045] For example, when word line WL0 and word line WLn are short-circuited, the configuration is as shown in Figure 3. In this case, switches SW0 and SWn are turned ON, and switches SW1 to SWn-1 are turned OFF.

[0046] The drive controller 202 receives a clock signal CLK as input and generates switch control signals A0~An and driver control signals B0~Bn.

[0047] The drive controller 202 controls the on / off state of switches SW0 to SWn by inputting switch control signals A0 to An to each of switches SW0 to SWn. The drive controller 202 controls the driving of drivers IV0 to IVn by inputting driver control signals B0 to Bn0 to each of drivers IV0 to IVn. The detailed configuration of the drive controller 202 will be described later.

[0048] Each of the drivers IV0 to IVn applies either a write voltage Vw, a read voltage Vr, or a ground voltage GND to each of the word lines WL0 to WLn, depending on the driver control signals B0 to Bn input to it, or each of the drivers IV0 to IVn stops driving (=stops power supply) and puts the word line WL0 to WLn to which it is connected into a high impedance state. The specific configuration of drivers IV0 to IVn is as follows.

[0049] Figure 4 shows the configuration of driver IVi. Driver IVi is any i-th driver (0 to n) among drivers IV0 to IVn. In other words, driver IVi described here is common to all of drivers IV0 to IVn.

[0050] The driver IVi has switching elements n1, n2, p1, and p2. Switching elements n1 and n2 are n-channel type MOSFETs (metal-oxide-semiconductor field-effect transistors). Switching elements p1 and p2 are p-channel type MOSFETs.

[0051] Switch elements p1 and n1 are connected to each other to form a half-bridge output stage. Specifically, the following is the case: The drain of switch element p1 is connected to the drain of switch element n1. The connection note between the drains of switch elements p1 and n1 is connected to the word line WLi.

[0052] The gate of switch element p1 is connected to the gate of switch element n1. A gate drive signal Gi is input to the gates of switch elements p1 and n1. Depending on the logic level of the gate drive signal Gi, switch elements p1 and n1 are switched on and off complementaryly. The term "complementary" includes cases where the on / off states of switch elements p1 and n1 are completely reversed. It also includes cases where there is a simultaneous off period (dead time) for switch elements p1 and n1.

[0053] The drain of switch element p2 is connected to the source of switch element p1. The gate of switch element p2 receives an input signal which is the logic inverted driver control signal Bi. The source of switch element p2 is connected to the power line VL.

[0054] The power line VL is a wire to which the write voltage Vw or read voltage Vr is applied. The power line VL is connected to the output node of the voltage generation circuit 30. The voltage generation circuit 30 supplies either the write voltage Vw or the read voltage Vr to the power line VL during data reading and data writing.

[0055] The drain of switch element n2 is connected to the source of switch element n1. The gate of switch element n2 receives the input of the driver control signal Bi. The source of switch element n2 is connected to the terminal (ground terminal) to which the ground voltage GND is applied.

[0056] The drive controller 202 drives the driver IVi as follows. For example, when driving the driver IVi, the drive controller 202 sets the driver control signal Bi to a high level. At this time, both switch elements n2 and p2 are turned on. Then, the source of switch element p1 becomes conductive with the power line VL, and the source of switch element n1 becomes conductive with the ground terminal. That is, a write voltage Vw or read voltage Vr is applied to the source of switch element p1, and a ground voltage GND is applied to the source of switch element n1.

[0057] In this state, the switching elements n1 and p1 are turned on / off, supplying the write voltage Vw, read voltage Vr, or ground voltage GND to the word line WLi.

[0058] For example, when stopping the operation of driver IVi, the drive controller 202 sets the driver control signal Bi to a low level. At this time, both switch elements n2 and p2 are turned off. As a result, the source of switch element p1 is disconnected from the power line VL, and the source of switch element n1 is disconnected from the ground terminal. That is, the source of switch element p1 is not supplied with either the write voltage Vw or the read voltage Vr, and the source of switch element n1 is not supplied with the ground voltage GND. Consequently, the word line WLi becomes floating and enters a high-impedance state.

[0059] Figure 5 is a timing chart showing the voltage states of word lines WL0 and WLn, and driver control signals B0 and Bn when the selected word line and the deselected word line in the memory device 1X are switched. In Figure 5, the behavior of word line WLn switching from the deselected state to the selected state and word line WL0 switching from the selected state to the deselected state is shown from timing t11 to timing t14.

[0060] As shown in Figure 5, when switching from a non-selected word line to a selected word line, the voltage value of word line WLn becomes a middle level during the switching process. The same applies when switching from a selected word line to a non-selected word line, as with word line WL0. A middle-level voltage is higher than a low level (ground voltage GND level) and lower than a high level (write voltage Vw and read voltage Vr). Therefore, word lines WL0 and WLn, which are in a middle-level voltage state, do not correspond to a selected state. In other words, memory cells cannot be accessed through word lines WL0 and WLn, which are in a middle-level voltage state.

[0061] The switching between selected and deselected states will be explained in more detail with specific examples. Here, as shown in Figure 5, we will illustrate and explain the process of switching wordline WL0 from selected to deselected while switching wordline WLn from deselected to selected.

[0062] Word line WLn remains at a low voltage level until a predetermined timing t11. Word line WL0 remains at a high voltage level until timing t11. This high voltage level corresponds to the read voltage Vr during data reads and the write voltage Vw during data writes. At this time, driver control signals B0 and Bn are at a high level; that is, drivers IV0 and IVn are driven.

[0063] When timing t11 arrives, the drive controller 202 drops the switch control signals A0 and An to a low level. As a result, drivers IV0 and IVn stop driving. This puts word lines WL0 and WLn into a high-impedance state. The drive controller 202 maintains the driver control signals B0 and Bn at a low level until timing t14 arrives. In other words, drivers IV0 and IVn remain stopped driving until timing t14 arrives.

[0064] After timing t11, when timing t12 arrives, the drive controller 202 raises the switch control signals A0 and An to high levels and maintains the switch control signals A1 to An-1 to low levels. As described above, this causes a short circuit between word line WL0 and word line WLn (see Figure 3). This state is also called the charge share state.

[0065] As mentioned above, initially, word line WL0 is selected. Therefore, each memory element connected to word line WL0 has a charge accumulated in it corresponding to the write voltage Vw or read voltage Vr until timing t12 arrives. When word line WL0 and word line WLn are short-circuited in this state, charge moves from word line WL0 to word line WLn. As a result, word line WL0 and word line WLn are at the same potential (= an intermediate potential Vm located between the high level and the low level, which is the middle level potential mentioned above). That is, at this time, the voltage of word line WL0 decreases from the high level to the middle level. On the other hand, at this time, the voltage of word line WLn increases from the low level to the middle level.

[0066] Then, when timing t13 arrives, the drive controller 202 lowers the switch control signals A0 and An to a low level. This disconnects word line WL0 and word line WLn, and the charge share state is resolved. Then, when timing t14 arrives, the drive controller 202 raises the driver control signals B0 and Bn to a high level. This puts drivers IV0 and IVn into the driven state.

[0067] At this time, driver IV0 outputs the ground voltage GND, and driver IVn outputs the write voltage Vw or read voltage Vr. As a result, at timing t14, the voltage state of word line WL0 becomes low level (ground voltage GND level). At the same time, the voltage state of word line WLn becomes high level (write voltage Vw or read voltage Vr level).

[0068] <Detailed configuration of drive controller 202> The drive controller 202 is equipped with control signal generation circuits CC0 to CCn. Each of the control signal generation circuits CC0 to CCn generates switch control signals A0 to An0 and driver control signals B0 to Bn. Here, we will describe the control signal generation circuit CCi, one of the control signal generation circuits CC0 to CCn. The control signal generation circuit CCi is any i-th (0 to n) of the control signal generation circuits CC0 to CCn. In other words, the control signal generation circuit CCi described here is common to all of the control signal generation circuits CC0 to CCn.

[0069] Figure 6 shows the configuration of the control signal generation circuit CCi. The control signal generation circuit CCi comprises a delay circuit 250, an AND gate 251, and a signal control circuit 252.

[0070] The delay circuit 250 receives the clock signal CLK as input and generates a delay signal CLKD. The delay signal CLKD is pulse-driven with a predetermined time delay from the pulse timing of the clock signal CLK. More details are as follows:

[0071] The delay circuit 250 comprises inverters 253 and 254, a resistor R1, and capacitors C1 and C2. The input terminal of inverter 253 is connected to the output node of the clock signal CLK. The output terminal of inverter 253 is connected to the first terminal of resistor R1. The second terminal of resistor R1 is connected to the input terminal of inverter 253, along with the first terminals of capacitor C1 and capacitor C2.

[0072] The second terminal of capacitor C1 is connected to the power line VL. That is, the write voltage Vw or read voltage Vr is supplied to the second terminal of capacitor C1. The second terminal of capacitor C2 is connected to the ground terminal.

[0073] Inverter 253 receives a clock signal CLK as input and generates an output signal by logically inverting the clock signal CLK. Resistor R1, capacitor C1, and capacitor C2 function as an RC circuit that smooths the output signal of inverter 253. The signal smoothed by this RC circuit (hereinafter referred to as "smoothed signal Ss") is input to the input terminal of inverter 254. When the smoothed signal Ss exceeds a predetermined inversion threshold, inverter 254 inverts the logic and generates a delayed signal CLKD. The degree of smoothness changes depending on the resistance value of resistor R1 and the capacitances of capacitors C1 and C2. The delay time Td of the delayed signal CLKD relative to the clock signal CLK (see Figure 7 below) is determined by this degree of smoothness and the inversion threshold of inverter 254.

[0074] The first input terminal of ANDGATE 251 receives the logically inverted delay signal CLKD. The second input terminal of ANDGATE 251 receives the clock signal CLK. ANDGATE 251 outputs an output signal SI corresponding to the clock signal CLK and the delay signal CLKD. Specifically, when both the logically inverted signals of the clock signal CLK and the delay signal CLKD are at a high level, ANDGATE 251 sets the output signal SI to a high level. Otherwise, ANDGATE 251 sets the output signal SI to a low level.

[0075] The signal control circuit 252 includes an inverter 255, a buffer 256, and switch elements n3, n4, p3, and p4. The input terminal of the inverter 255 is connected to the output terminal of the AND gate 251. The inverter 255 receives the output signal SI as input and outputs a drive signal V1 which is the logical inversion of the output signal SI.

[0076] The input terminal of buffer 256 is connected to the output terminal of AND gate 251. Buffer 256 receives the output signal SI as input and outputs a drive signal V2, which is the output signal SI with predetermined buffer processing applied. The logic level of the drive signal V2 corresponds to the logic level of the output signal SI.

[0077] Switch elements n3 and n4 are N-channel MOSFETs. The gate of switch element n3 is connected to the output terminal of inverter 255 and receives the drive signal V1 as input. The source of switch element n3 is connected to the ground terminal. The drain of switch element n3 is connected to node A, which will be described later.

[0078] The gate of switch element n4 is connected to the output terminal of buffer 256 and receives the input drive signal V2. The source of switch element n4 is connected to the ground terminal. The drain of switch element n4 is connected to node B, which will be described later.

[0079] Switch elements p3 and p4 are P-channel MOSFETs. The gate of switch element p3 is connected to node B, along with the drain of switch element p4. The drain of switch element p3 is connected to node A, along with the gate of switch element p4. The source of switch element p3 is connected to power line VL. The source of switch element p4 is connected to power line VL.

[0080] Node A outputs a switch control signal Ai. Therefore, the voltage value at Node A becomes the voltage value of the switch control signal Ai. Similarly, Node B outputs a driver control signal Bi. Therefore, the voltage value at Node B becomes the voltage value of the driver control signal Bi.

[0081] Figure 7 is a timing chart showing the voltage states of the control signal generation circuit CCi. As shown in Figure 7, the clock signal CLK is at a low level before a predetermined timing t21. The address data signal ADDR is transmitted at the timing of the pulse edge of the clock signal CLK.

[0082] Prior to timing t21, the output signal SI is at a low level. As a result, the drive signal V1 becomes high and the drive signal V2 becomes low. Therefore, at this time, switch element n3 is on and switch element n4 is off. Because switch element n3 is on, the voltage at node A becomes low (ground voltage GND level). This causes switch element p4 to turn on. Also, because switch element p4 is on, a high voltage (power line VL level, read voltage Vr or write voltage Vw level) is applied to node B. This causes switch element p3 to turn off.

[0083] Therefore, during the period up to timing t21, the switch control signal Ai is at a low level and the driver control signal Bi is at a high level. In other words, the switch SWi is off and the driver IVi is in the driven state.

[0084] When timing t21 arrives, the clock signal CLK rises to a high level. On the other hand, the delay signal CLKD is pulse-driven with a delay compared to the pulse timing of the clock signal CLK, as described above. Therefore, at timing t21, the delay signal CLKD is at a low level. Consequently, the AND gate 251 raises the output signal SI to a high level in synchronization with the rising edge of the clock signal CLK.

[0085] Then, in sync with the rising edge of the output signal SI, the drive signal V1 falls to a low level and the drive signal V2 rises to a high level. Instantly following the falling edge of drive signal V1 and the rising edge of drive signal V2, switch element n3 turns off and switch element n4 turns on. As a result, the voltage at node B falls to a low level (ground voltage GND level). In other words, the driver control signal Bi falls to a low level.

[0086] Here, the P-channel MOSFET has a longer switching time from the off state to the on state compared to the N-channel MOSFET. Therefore, after the voltage at node B falls to a low level, the switch element p3 remains off for a predetermined period (from timing t21 to timing t22). As a result, node A temporarily enters a floating state, losing its voltage supply and becoming a high-impedance state.

[0087] At this time, the driver control signal Bi is at a low level. As a result, the driver IVi is in a stopped state. Consequently, as described above, no voltage is supplied to the word line WLi, and the word line WLi enters a high-impedance state. Also, as described above, no voltage is supplied to node A at this time. Therefore, the switch control signal Ai remains at a low level, and the switch SWi is off.

[0088] When timing t22 arrives, the switch element p3 turns on. This causes the voltage at node A to rise to a high level (power line VL level). In other words, the switch control signal Ai rises to a high level, and the switch SWi turns on. As a result, the word line WLi is connected to the charge share line SL.

[0089] When timing t23 arrives, the delay signal CLKD rises to a high level. Then, the AND gate 251 drops the output signal SI to a low level in synchronization with the rising edge of the delay signal CLKD. Then, the drive signal V1 rises to a high level in synchronization with the falling edge of the output signal SI. As a result, the drive signal V2 falls to a low level. Switch element n3 turns on and switch element n4 turns off to instantaneously follow the rising edge of drive signal V1 and the falling edge of drive signal V2. Therefore, the voltage at node A becomes low level. That is, the switch control signal Ai falls to a low level.

[0090] On the other hand, after the voltage at node A falls, the switch element p4 remains off for a predetermined period (from timing t23 to timing t24). As a result, node B becomes floating until timing t24, no voltage is supplied, and it enters a high-impedance state. In other words, the driver control signal Bi remains at a low level.

[0091] At this time, the switch control signal Ai is at a low level. Therefore, the switch SWi turns off. In other words, the word line WLi is disconnected from the charge share line SL. At this time, the driver control signal Bi remains at a low level, and the driver IVi remains in a stopped state.

[0092] When timing t24 arrives, the switch element p4 turns on. This causes the voltage at node B to fall to a high level (power line VL level). At this time, the driver control signal Bi rises to a high level, and the driver IVi enters the driven state. That is, one of the following voltages is supplied to the word line WLi: write voltage Vw, read voltage Vr, or ground voltage GND.

[0093] Therefore, the word lines WL0 to WLn that switch from a selected word line to a deselected word line, and those that switch from a deselected word line to a selected word line, are connected to the charge share line SL after being brought into a high impedance state as described above by the control signal generation circuits CC0 to CCn. As a result, the word lines that switch from a selected word line to a deselected word line, and those that switch from a deselected word line to a selected word line, are at an intermediate potential Vm (middle level).

[0094] In this state, the system switches from an unselected word line to a selected word line, resulting in relatively low power consumption (=power load) during data read and write operations. Specifically, the system rises from a low level (ground voltage GND level) to a middle level before rising to a high level (power line VL level, which corresponds to the write voltage Vw or read voltage Vr level). Therefore, the power load is reduced by the amount of the rise from the low level to the middle level.

[0095] Furthermore, the rise from the low level to the middle level utilizes the charge emitted from the switching between selected and unselected word lines. Therefore, the voltage can be increased from the low level to the middle level without placing a load on the voltage generation circuit 30.

[0096] This makes it possible to generate relatively high read voltage Vr and write voltage Vw while keeping the circuit area of ​​the voltage generation circuit 30 relatively small. As a result, the circuit area of ​​the memory drive unit 10x and, consequently, the memory unit 1X can be reduced.

[0097] Furthermore, the voltage generation circuit 30 employing a charge pump as described above generates a relatively high write voltage Vw. In a memory drive device 10x equipped with such a voltage generation circuit 30, the power load of the voltage generation circuit 30 can be more effectively reduced by performing the charge sharing described above.

[0098] Furthermore, as mentioned above, in the case of a memory array 100 with a relatively large bit width, the number of memory cells connected to each of the word lines WL0 to WLn increases, resulting in a larger additional capacity. In such cases, performing the charge sharing described above can more effectively reduce the power load on the voltage generation circuit 30.

[0099] As mentioned above, the switch control signals A0-An and driver control signals B0-Bn are timing-controlled by the clock signal CLK. The clock signal CLK also defines the transmission timing of the address data signal ADDR. In other words, the drive control of drivers IV0-IVn and the on / off control of switches SW0-SWn can be synchronized with the timing of access to the memory cell. Therefore, the timing of access to the memory cell and the timing of the drive control of drivers IV0-IVn and the on / off control of switches SW0-SWn can be easily adjusted to a suitable timing. Consequently, the circuit area for timing control can be reduced, and the increase in the circuit area of ​​the memory device 1X can be suppressed.

[0100] <Variation> Furthermore, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of this disclosure. For example, the voltage generation circuit 30 described above is not limited to a charge pump, and various boost circuits may be employed. Also, although the memory device 1X is described as being integrated on a single semiconductor substrate, it is not limited to this.

[0101] Furthermore, the memory device 1X described above can be mounted on an electronic device 500. The electronic device 500 is, for example, an in-vehicle device mounted on a vehicle Z (see Figure 8), or an audio player, etc.

[0102] <Note> The memory drive device (10x) described in the specification comprises a plurality of word lines (WL0~WLn) each connected to a plurality of memory cells, a word line drive circuit (200) configured to supply a control voltage (Va) to each of the plurality of word lines (WL0~WLn), and a charge share circuit (201) configured to short-circuit any of the plurality of word lines (WL0~WLn) to equalize the potential, wherein the plurality of word lines (WL0~WLn) are configured such that the word line (WL0~WLn) connected to the memory cell to be accessed is designated as a selected word line, and the word line drive circuit (200) is configured to short-circuit any of the plurality of word lines (WL0~WLn) to equalize the potential word lines (WL0~WLn) to equalize the potential, and the word line drive circuit (200) is configured to short-circuit any of the word lines (WL0~WLn) to equalize the potential, and the word line drive circuit (200) is configured to short-circuit any of the word lines (WL0~WLn) to equalize the word line In the first configuration, a control voltage (Va) of a first logic level (Vr, Vw) is supplied to the word lines, and a control voltage (Va) of a second logic level (GND) lower than the first logic level (Vr, Vw) is supplied to each unselected word line. When switching between unselected and selected word lines, the word line drive circuit (200) does not supply a control voltage (Va) to the selected and unselected word lines to be switched, creating a high impedance state. The charge share circuit (201) is configured to short-circuit the selected and unselected word lines to be switched, creating a charge share state with an intermediate potential (Vm) lower than the first logic level (Vr, Vw) and higher than the second logic level (GND).

[0103] The memory drive device (10x) of the first configuration includes a control circuit (202) configured to control a word line drive circuit (200) and a charge share circuit (201), and the word line drive circuit (200) and the charge share circuit (201) are configured to be able to switch between a first state in which the word line drive circuit (200) puts any of the word line drive circuits (200) into a high impedance state and the charge share circuit (201) enters a charge share state, a second state in which the charge share circuit (201) releases any of the shorted connections in the first state and is no longer in a charge share state, and a third state in which the word line drive circuit (200) supplies a control voltage (Va) to any of the word line drive circuits (200), and the control circuit (202) is preferably configured to switch between a word line drive circuit and a word line to switch to the first state before the second and third states, then to the second state after the first state, and then to the third state after the second state (second configuration).

[0104] The memory drive device (10x) in the second configuration includes a control circuit (202) which generates signal generation circuits (CC0~CCn) that generate control signals (A0~An, B0~Bn) that define a first timing for setting to a first state, a second timing for setting to a second state, and a third timing for setting to a third state, and the word line drive circuit (200) and charge share circuit (201) are configured to switch between the first state, second state, and third state based on the control signals (A0~An, B0~Bn) (third configuration).

[0105] The first to third memory drive device (10x) is configured such that the charge share circuit (201) can be switched on / off to enable the first terminal and the second terminal to conduct / non-conductive states, and comprises a plurality of switches (SW0~SWn) each with a first terminal connected to a plurality of word lines, and a charge share line (SL) connected to the second terminal of each of the plurality of switches (SW0~SWn), and is configured such that any of the plurality of switches (SW0~SWn) can be short-circuited via the charge share line (SL) by switching each of the plurality of switches (SW0~SWn) on / off (fourth configuration).

[0106] The memory device (1X) described in the specification is configured to include any of the first to fourth memory drive devices (10x), a memory cell array (100) in which a plurality of memory cells are arranged in a matrix along the horizontal direction in which a word line (WL0 to WLn) extends and a vertical direction orthogonal to the horizontal direction, a plurality of bit lines connected to each of the horizontally arranged memory cells that extend along the vertical direction, a bit line drive circuit (300) configured to supply a predetermined voltage to each of the plurality of bit lines, and a voltage generation circuit (30) configured to supply a control voltage (Va) to the word line drive control and a predetermined voltage to the bit line drive circuit (300) when accessing any of the plurality of memory cells (fifth configuration).

[0107] The electronic device (500) described in the specification is configured to include a memory device (1X) of a fifth configuration (sixth configuration).

[0108] The vehicle (Z) described in the specification is configured to have the electronic equipment of the sixth configuration (seventh configuration). [Explanation of Symbols]

[0109] 1X memory device 1Y memory device 10x Memory Drives 10y Memory Drive Unit 30 Voltage Generating Circuit 100 memory arrays 200-line decoder 201 Charge Share Circuit 202 Drive Controller 250 Delay Circuit 251 Andgate 252 Signal Control Circuit 253~255 Inverter 256 buffers 300-row decoder 500 Electronic equipment Nodes A and B Z Vehicle A0~An Switch Control Signal ADDR Address Data Signal Ai switch control signal B0~Bn Driver control signals C1, C2 Capacitors CC0~CCn Control Signal Generation Circuit CCi Control Signal Generation Circuit CLK clock signal CLKD delay signal GL Grand Line GND (Ground Voltage) Gi gate drive signal IV0~IVn Drivers IVi Driver R1 Resistor SI output signal SL ChargeShare Line SW0~SWn switches SWi Switch Ss smoothed signal Td delay time V1 drive signal V2 drive signal VL Power Line Va, Vb control voltage Vcc Power supply voltage Vm intermediate potential Vr Readout Voltage Vw write voltage WL0~WLn Wordline W Li Wordline n1~n4 Switching elements p1~p4 Switching elements

Claims

1. Multiple word lines connected to multiple memory cells, A word line drive circuit configured to supply a control voltage to each of the plurality of word lines, A charge share circuit configured to short-circuit any of the aforementioned word lines to equalize their potentials, Equipped with, The aforementioned multiple word lines, Select the word line connected to the memory cell to be accessed as the selected word line. The word lines connected to the memory cells that are not to be accessed are designated as non-selected word lines. The word line drive circuit is, The control voltage of the first logic level is supplied to the selected word line. Each of the unselected word lines is supplied with the control voltage of a second logic level lower than the first logic level. When switching between the non-selected word line and the selected word line, The word line drive circuit puts the selected word line and the unselected word line to be switched into a high impedance state without supplying the control voltage. The charge-sharing circuit is a memory drive device that, as an arbitrary, shorts the selected word line and the unselected word line to be switched, resulting in a charge-sharing state where the potential is an intermediate potential lower than the first logic level and higher than the second logic level.

2. The system includes a control circuit configured to control the word line drive circuit and the charge share circuit, The word line drive circuit and the charge share circuit switch between the unselected word line and the selected word line. The first state is when the word line drive circuit puts any of the words into the high impedance state and the charge share circuit is in the charge share state, The charge share circuit releases any of the shorted-out components in the first state, resulting in a second state where the charge share state is no longer in effect. The third state in which the word line drive circuit supplies the control voltage to any of the above, It is configured to be displaceable, The memory drive device according to claim 1, wherein the control circuit, when switching between the unselected word line and the selected word line, displaces to the first state before the second and third states, displaces to the second state after the first state, and displaces to the third state after the second state.

3. The control circuit includes a signal generation circuit that generates control signals that define a first timing for setting the system to the first state, a second timing for setting the system to the second state, and a third timing for setting the system to the third state. The memory drive device according to claim 2, wherein the word line drive circuit and the charge share circuit switch to the first state, the second state, and the third state based on the control signal.

4. The aforementioned charge sharing circuit is Multiple switches are configured to allow switching between a conductive and a non-conductive state between the first and second terminals by switching them on and off, with the first terminal connected to each of the multiple word lines, A charge share line connected to the second end of each of the aforementioned multiple switches, The memory drive device according to claim 1, comprising the on / off switching of each of the plurality of switches, which causes any of the plurality of switches to short-circuit each other via the charge share line.

5. The memory drive device according to claim 1, A memory cell array is configured in which the plurality of memory cells are arranged in a matrix along the horizontal direction in which the word line extends and the vertical direction perpendicular to the horizontal direction, A plurality of bit lines extending along the vertical direction and connected to each of the memory cells arranged in the horizontal direction, A bit line drive circuit configured to supply a predetermined voltage to each of the plurality of bit lines, A voltage generation circuit is configured to control the word line drive control and the bit line drive circuit by supplying the predetermined voltage when accessing any of the plurality of memory cells, A memory device equipped with the following features.

6. An electronic device comprising the memory device described in claim 5.

7. A vehicle equipped with the electronic equipment described in claim 6.

Images