Semiconductor memory

Abstract

To enhance the security of data stored in semiconductor memory devices. [Solution] The semiconductor memory device includes a control circuit, a first word line, and a memory array including a first memory cell capable of storing n bits, wherein the control circuit is configured to perform first and second write operations in response to first and second write instructions from an external memory controller, and to perform first and second read operations in response to first and second read instructions, and by performing the first or second write operation, the threshold voltage of the first memory cell is set to a first distribution and a second distribution, which are arranged in ascending order of voltage. n A distribution or a distribution including the third and fourth distributions. n It is configured to control to one of the following distributions, and at least a portion of the third distribution lies between the first and second distributions.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor memory devices.

Background Art

[0002] A NAND type flash memory is known as a semiconductor memory device, and a memory system including the NAND type flash memory and a memory controller for controlling the same is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To enhance the security of data stored in a semiconductor memory device.

Means for Solving the Problems

[0005] A semiconductor memory device according to one embodiment includes a control circuit, a first word line, and a memory array connected to the first word line and including a first memory cell capable of storing n bits (where n is an integer of 1 or more), wherein the control circuit is configured to perform a first write operation in response to a first write instruction from an external memory controller, a second write operation in response to a second write instruction from the memory controller, a first read operation in response to a first read instruction from the memory controller, and a second read operation in response to a second read instruction from the memory controller, and by performing the first write operation, the threshold voltage of the first memory cell is set to include a first distribution and a second distribution arranged in ascending order of voltage. n The system is configured to control the threshold voltage of the first memory cell to one of a number of distributions, and by performing the first read operation, it is configured to determine whether the threshold voltage of the first memory cell is in the first distribution or the second distribution based on the first voltage, and by performing the second write operation, it controls the threshold voltage of the first memory cell to one of a third distribution and a fourth distribution, which are arranged in ascending order of voltage. n The system is configured to control to one of the distributions, and by performing the second read operation, it is configured to determine whether the threshold of the first memory cell is the third distribution or the fourth distribution based on a second voltage that is higher than the first voltage, with at least a portion of the third distribution existing between the first and second distributions. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram illustrating the configuration of a memory system according to one embodiment. [Figure 2] This is a block diagram illustrating the configuration of a semiconductor memory device according to one embodiment. [Figure 3] This figure shows the circuit configuration of a memory cell array in a semiconductor memory device according to one embodiment. [Figure 4] This is a cross-sectional view of a semiconductor memory device according to one embodiment. [Figure 5]This figure shows the equivalent circuit of adjacent strings in a semiconductor memory device according to one embodiment. [Figure 6] This figure shows the threshold voltage distribution of a memory cell according to one embodiment. [Figure 7] This figure illustrates the threshold voltage distribution, normal mode, and special mode of a memory cell according to one embodiment. [Figure 8] This figure shows the circuit configuration of one block in a semiconductor memory device according to one embodiment. [Figure 9] This figure shows the circuit configuration of one block in a semiconductor memory device according to one embodiment. [Figure 10] This figure shows the circuit configuration of one block in a semiconductor memory device according to one embodiment. [Modes for carrying out the invention]

[0007] The semiconductor memory device according to this embodiment will be described in detail below with reference to the drawings. In the following description, elements having substantially the same function and configuration are denoted by the same reference numerals and will be described redundantly only when necessary. The embodiments shown below illustrate devices and methods for realizing the technical concept of this embodiment. The technical concept of the embodiments is not limited to the materials, shapes, structures, arrangements, etc., of the components described below. The technical concept of the embodiments may have various modifications to the claims.

[0008] [1. First Embodiment] A semiconductor memory device according to the first embodiment will be described using Figures 1 to 7.

[0009] [1-1. Overall configuration of the memory system] Figure 1 is a block diagram illustrating the configuration of a memory system according to one embodiment. As shown in Figure 1, the memory system 1 according to the first embodiment includes a memory controller 2 and semiconductor memory devices 5-8 (chip AD). The memory controller 2 is connected to the semiconductor memory devices 5-8 by a bus. Non-volatile memory such as NAND flash memory is used as the semiconductor memory devices 5-8. The memory controller 2 controls the operation of the semiconductor memory devices 5-8.

[0010] The memory controller 2 communicates with, for example, an external host computer (not shown). In response to write requests (or commands) and read requests (or commands) received from the host computer, the memory controller 2 instructs the semiconductor storage devices 5-8 to perform write and read operations. When the memory controller 2 receives a write command, it executes the write operation by issuing a write instruction to the semiconductor storage devices 5-8. When the memory controller 2 receives a read command, it executes the read operation by issuing a read instruction to the semiconductor storage devices 5-8. After a read operation is performed, the memory controller 2 transmits the data stored in the semiconductor storage devices 5-8 to the host computer.

[0011] The semiconductor memory devices 5-8 each have multiple memory cells and store data non-volatilely. The semiconductor memory devices 5-8 are individual identifiable semiconductor chips. For example, the semiconductor memory devices 5-8 are identified by individual chip enable signals. Alternatively, the semiconductor memory devices 5-8 are identified by pre-assigned individual chip addresses. Therefore, the semiconductor memory devices 5-8 are controlled independently by instructions from the memory controller 2.

[0012] The memory controller 2 transmits various signals to the semiconductor memory devices 5 to 8 via a bus and receives various signals from the semiconductor memory devices 5 to 8. The bus includes a plurality of signal lines and performs signal transmission and reception according to an instruction transmitted from the memory controller 2. The signals transmitted and received via the bus are, for example, a chip enable signal, a command latch enable signal, an address latch enable signal, a write enable signal, a read enable signal, an output instruction signal, a write protect signal, a data signal (including a data strobe signal), and a ready busy signal.

[0013] As shown in FIG. 1, the memory controller 2 includes a processor 61, a built-in memory 62, a NAND interface circuit 63, a buffer memory 64, and a host interface circuit 65.

[0014] The processor 61 is, for example, a central processing unit (CPU) and controls the operation of the entire memory controller 2. The processor 61 transmits a write instruction to the semiconductor memory devices 5 to 8 via the NAND interface circuit 63 in response to a write command for data received from an external host computer, for example. This function is a common function not only for the above-described write operation but also for read and erase operations. The host computer may be referred to as a host or a host device.

[0015] The built-in memory 62 is, for example, a semiconductor memory such as a RAM (Random Access Memory) or a DRAM (Dynamic RAM) and is used as a work area for the processor 61. The built-in memory 62 holds firmware for managing the semiconductor memory devices 5 to 8 and various management tables.

[0016] The NAND interface circuit 63 is connected to the semiconductor memory devices 5 to 8 via the above-described bus and performs communication with the semiconductor memory devices 5 to 8. The NAND interface circuit 63 transmits an operation instruction, an address, and write data to the semiconductor memory devices 5 to 8 according to an instruction from the processor 61. The NAND interface circuit 63 receives a status and read data from the semiconductor memory devices 5 to 8.

[0017] The buffer memory 64 temporarily holds data and the like received by the memory controller 2 from the semiconductor memory devices 5 to 8 and from the outside.

[0018] The host interface circuit 65 is connected to an external host computer and performs communication with the host computer. The host interface circuit 65 transfers, for example, commands received from the host computer to the processor 61 and the buffer memory 64, respectively.

[0019] [1-2. Configuration of Semiconductor Memory Device] A configuration example of the semiconductor memory device according to the first embodiment will be described with reference to FIG. 2. The semiconductor memory devices 5 to 8 have, for example, the same configuration. Therefore, in the following description, the configuration of the semiconductor memory device 5 among the semiconductor memory devices 5 to 8 will be described, and the description of the configurations of the semiconductor memory devices 6 to 8 will be omitted.

[0020] As shown in FIG. 2, the semiconductor memory device 5 includes a memory cell array 21 (memory), an input / output circuit 22 (i / o), a logic control circuit 24 (logic control), a register 26 (register), a sequencer 27 (sequencer), a voltage generation circuit 28 (voltage generation), a row decoder 30 (row decoder), a sense amplifier 31 (SA), an input / output pad group 32, and a logic control pad group 34.

[0021] As will be explained in more detail later, the memory cell array 21 includes a plurality of non-volatile memory cells (memory cell transistors MT, described later) associated with word lines and bit lines.

[0022] The input / output circuit 22 transmits and receives data signals to and from the memory controller 2. The input / output circuit 22 transfers the command and address in the data signal to the register 26. The input / output circuit 22 transmits and receives write data and read data to and from the sense amplifier 31.

[0023] The logic control circuit 24 receives signals from the memory controller 2, such as the chip enable signal, command latch enable signal, address latch enable signal, write enable signal, read enable signal, output instruction signal, and write protect signal. The logic control circuit 24 sends a ready busy signal to the memory controller 2 to notify the memory controller 2 of the state of the semiconductor storage device 5.

[0024] Register 26 holds the command and address. Register 26 transfers the address to the row decoder 30 and sense amplifier 31, and the command to the sequencer 27. The sequencer 27 receives the command and controls the entire semiconductor memory device 5 according to the sequence based on the received command. The sequencer 27 is sometimes referred to as the "control circuit".

[0025] As will be described in detail later, in this embodiment, the sequencer 27 performs either "normal mode" write and read operations or "special mode" write and read operations during write and read operations. Data written to the memory cell in special mode write operations can only be correctly read in special mode read operations and cannot be correctly read in normal mode read operations. As will be described in detail later, even within the same block, there are cases where normal mode and special mode are separated on a page-by-page basis. In this case, identification information that can distinguish between the addresses corresponding to normal mode pages and the addresses corresponding to special mode pages is stored in the memory cell array 21. The addresses in the memory cell array 21 where the identification information is stored are managed by the memory controller 2. Note that the identification information may also be stored in a ROM (Read Only Memory) (not shown) provided in the memory controller 2. In this case as well, the addresses in the ROM where the identification information is stored are managed by the memory controller 2, similar to the above.

[0026] The voltage generation circuit 28 generates the voltages necessary for data writing, reading, and erasing operations based on instructions from the sequencer 27. The voltage generation circuit 28 includes multiple drivers and supplies the generated voltages to the row decoder 30 and sense amplifier 31 according to the control of the sequencer 27. For example, the voltage generation circuit 28 supplies the generated voltage to the corresponding row decoder 30 based on the row address included in the instructed address.

[0027] The row decoder 30 selects a memory cell corresponding to the row address included in the instructed address, in accordance with the control of the sequencer 27. A voltage supplied from the driver set 29 via the row decoder 30 is applied to the memory cell of the selected row.

[0028] During a data read operation, the sense amplifier 31 detects the read data read from the memory cell onto the bit line and transfers the detected read data to the input / output circuit 22. During a data write operation, the sense amplifier 31 transfers the data to be written to the memory cell via the bit line. The sense amplifier 31 transfers the data corresponding to the instructed address to the input / output circuit 22 according to the control of the sequencer 27.

[0029] The input / output pad group 32 transfers data signals received from the memory controller 2 to the input / output circuit 22. The input / output pad group 32 transfers data signals received from the input / output circuit 22 to the memory controller 2. The logic control pad group 34 transfers various signals received from the memory controller 2 to the logic control circuit 24.

[0030] [1-3. Memory cell array configuration] The circuit configuration of the memory cell array 21 will be explained using Figure 3. Figure 3 is an equivalent circuit diagram of block BLK. As shown in the figure, block BLK includes multiple memory groups MG (MG0, MG1, MG2, ...). Memory group MG includes multiple strings 50.

[0031] In this embodiment, the string 50 includes eight memory cell transistors MT (MT0 to MT7) and two selection transistors ST (ST1, ST2). The eight memory cell transistors MT are connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2.

[0032] In this embodiment, a configuration in which the string 50 contains eight memory cell transistors MT is illustrated, but the configuration is not limited to this. For example, the number of memory cell transistors MT in the string 50 may be seven or less, or nine or more. The number of selection transistors ST is also not limited to the above configuration.

[0033] As will be explained in detail later, the memory cell transistor MT comprises a gate electrode GE that controls the on and off states of the transistor, and a charge storage layer CT that holds the charge injected by the write operation (see Figure 5). The memory cell transistor MT has a threshold voltage corresponding to the amount of charge held by the charge storage layer CT, and turns on when a voltage equal to or greater than the threshold voltage is applied to the gate electrode GE. When a write operation is performed on the memory cell transistor MT, that is, when electrons are injected into the charge storage layer CT of the memory cell transistor MT, the threshold voltage of the memory cell transistor MT changes. In the case of an N-type transistor, the threshold voltage of the memory cell transistor MT when electrons are injected into the charge storage layer CT is higher than the threshold voltage of the memory cell transistor MT when electrons are not injected into the charge storage layer CT. The memory cell transistor MT retains data non-volatilely through the change in threshold voltage caused by the injection of electrons into the charge storage layer CT.

[0034] As shown in Figure 3, the gate of the selection transistor ST1 in the memory group MG is connected to the select gate line SGD (SGD0, SGD1, ...). The gate of the selection transistor ST2 is connected to the select gate line SGS (SGS0, SGS1, ...). The select gate lines SGD and SGS are controlled independently by the row decoder 30. In this embodiment, a configuration in which there is one select gate line SGD and one SGS is illustrated, but the system is not limited to this configuration. There may be two or more select gate lines SGD and SGS. In other words, there may be two or more selection transistors ST1 and ST2.

[0035] The gate electrodes GE of memory cell transistors MT0 to MT7, which are included in the same memory group MG and belong to different bit lines BL, are connected to word lines WL0 to WL7, respectively. The word lines WL (WL0 to WL7) are independently controlled by the row decoder 30.

[0036] A block BLK is, for example, a data erasure unit. That is, data held by memory cell transistors MT contained within the same block BLK is erased all at once. If the memory cell is an N-type transistor, the threshold voltage of the memory cell transistor MT in the erased state is lower than the threshold voltage of the memory cell transistor MT in the written state.

[0037] Within the memory cell array 21, the drains of the selection transistors ST1 of multiple strings 50 arranged in the same row are connected to a common bit line BL(BL0~BL(L-1) (where L is a natural number greater than or equal to 3). Within the memory cell array 21, the sources of multiple selection transistors ST2 are commonly connected to the source line SL. [1-4. Cross-sectional structure of memory cell array]

[0038] An arbitrary cross-sectional structure of the memory cell array 21 will be described using Figure 4. The memory cell array 21 comprises wiring layers 10-12, a semiconductor substrate 13, a contact plug 16, a memory pillar MP, and a bit line BL.

[0039] As shown in Figure 4, a wiring layer 12 that functions as a select gate line SGS is provided above the semiconductor substrate 13. Above the wiring layer 12, eight wiring layers 11 that function as word lines WL0 to WL7 are provided. The eight wiring layers 11 are stacked along the Z direction. Above the wiring layer 11, a wiring layer 10 that functions as a select gate line SGD is provided.

[0040] The memory pillar MP has a longitudinal length in the Z direction and penetrates the wiring layers 10-12 to connect the semiconductor substrate 13 and the contact plug 16. The memory pillar MP includes a semiconductor layer. A memory cell transistor MT is formed in the region where the memory pillar MP and the word line WL face each other. Similarly, a selection transistor ST1 is formed in the region where the memory pillar MP and the select gate line SGD face each other. A selection transistor ST2 is formed in the region where the memory pillar MP and the select gate line SGS face each other. Single-crystal or polycrystalline silicon is used as the semiconductor included in the memory pillar MP. However, materials other than silicon may be used as the semiconductor layer. The semiconductor layer may be amorphous, or a hybrid layer of amorphous and polycrystalline materials.

[0041] In the Y direction, the memory pillar MP is sandwiched between wiring layer 10 (select gate line SGD), wiring layer 11 (word line WL), and wiring layer 12 (select gate line SGS). The memory pillar MP is also sandwiched between these wiring layers in the X direction. In other words, in the XY plane, the memory pillar MP is surrounded by the above-mentioned wiring layers. However, this embodiment is not limited to this configuration; it is sufficient that wiring layers 10 to 12 face the memory pillar MP.

[0042] The region of the semiconductor substrate 13 connected to the memory pillar MP is sometimes referred to as the "source electrode SE". The region of the contact plug 16 connected to the memory pillar MP is sometimes referred to as the "drain electrode DE".

[0043] Slits SLT are provided between adjacent blocks BLK in the Y direction. An insulating layer is provided in the slits SLT. However, contact plugs or the like for supplying (applying) voltage to a region provided in the semiconductor substrate 13 may be provided in the slits SLT. For example, a contact plug or groove-shaped conductor for connecting the source of the selection transistor ST2 to the source wire may be provided in the slits SLT.

[0044] A bit line BL is provided on the memory pillar MP. A contact plug 16 is provided between the memory pillar MP and the bit line BL to connect them.

[0045] [1-5. Equivalent Circuits] Figure 5 shows the equivalent circuit of adjacent strings in a semiconductor memory device according to one embodiment. As shown in Figure 5, one string 50 is provided on one memory pillar MP. Figure 5 shows two memory pillars MP1 and MP2. Memory cell transistors MT and selection transistors ST belonging to memory pillar MP1 are denoted with "-1", and memory cell transistors MT and selection transistors ST belonging to memory pillar MP2 are denoted with "-2". In the following description, if there is no need to distinguish between memory cell transistors MT and selection transistors ST belonging to memory pillars MP1 and MP2, they will not be denoted with "-1" or "-2".

[0046] String 50 is provided between the bit line BL and the source line SL and has a selection transistor ST1, i memory cell transistors MT (where i is an integer of 2 or more, and in this embodiment it is 8), and a selection transistor ST2 connected in series. String 50 is connected to the source line SL via the source electrode SE and to the bit line BL via the drain electrode DE. In this embodiment, since i is 8, memory cell transistors MT0 to MT7 are provided. The i memory cell transistors MT are connected in series between selection transistor ST1 and selection transistor ST2. The i memory cell transistors MT are arranged along the Z direction.

[0047] The source line SL is provided on the main surface of the semiconductor substrate 13 (see Figure 4). The source line SL may be configured as an unpatterned conductive layer extending over the region of the memory cell array 21, or as a linearly patterned conductive layer extending over the region. In other words, the source line SL extends in the X and Y directions. The source line SL may be formed from a conductive semiconductor in which a portion of the semiconductor substrate 13 is conductive, or it may be a metallic material formed on the semiconductor substrate 13.

[0048] Strings 50-1 and 50-2 are connected to a common bit line BL and a common source line SL, respectively. Word lines WL0-1 to WL7-1 are controlled independently of word lines WL0-2 to WL7-2, respectively. Select gate lines SGD1-1 and SGS1-1 are controlled independently of select gate lines SGD1-2 and SGS1-2, respectively.

[0049] In Figure 5, the memory cell transistor MT includes a channel CH, a charge storage layer CT, and a gate electrode GE. The channel CH is the portion of the memory cell transistor MT that functions as the channel. The charge storage layer CT holds the charge injected by the write operation. The threshold voltage of the memory cell transistor MT varies depending on the amount of charge held in the charge storage layer CT. The gate electrode GE is connected to the word line WL. The channel CH, the charge storage layer CT, and the gate electrode GE are insulated from each other by insulating layers.

[0050] The charge storage layer CT may be a floating gate such as a metal layer, or a charge trap layer such as a silicon nitride layer. The memory cell transistor MT may also be a memory cell equipped with a ferroelectric insulating layer. In this case, a ferroelectric insulating film is provided between the channel CH and the gate electrode GE, and the threshold voltage of the memory cell transistor MT changes as the dielectric constant changes.

[0051] The selection transistor ST includes a channel CH and a gate electrode GE. The selection transistor ST does not have a charge storage layer CT. The gate electrode GE of selection transistor ST1 is connected to the select gate line SGD1. The gate electrode GE of selection transistor ST2 is connected to the select gate line SGS1. Note that, unlike the example in Figure 5, the selection transistor ST may have a charge storage layer CT.

[0052] [1-6. Threshold voltage distribution of memory cells] Figure 6 shows the threshold voltage distribution of a memory cell used as a memory cell according to one embodiment. In Figure 6, a Triple Level Cell (TLC) is described as an example of a threshold voltage distribution. However, a Hexa Level Cell (HLC), Penta Level Cell (PLC), Quad Level Cell (QLC), Multi Level Cell (MLC), or Single Level Cell (SLC) may be used in the memory system 1. One memory cell can store n bits (n is an integer of 1 or more), and when n is 1 it is an SLC, when n is 2 it is an MLC, when n is 3 it is a TLC, when n is 4 it is a QLC, when n is 5 it is a PLC, and when n is 6 it is an HLC. Furthermore, in the threshold voltage distribution of each level cell, 2 n A distribution is formed. Since the memory cell shown in Figure 6 is a TLC (n=3), there are eight threshold voltage distributions as shown in Figure 6.

[0053] Figure 6 shows examples of the threshold voltage distribution, data allocation, and read voltage of a memory cell. The vertical axis of the threshold voltage distribution corresponds to the number of memory cells, and the horizontal axis corresponds to the threshold voltage Vth of the memory cell.

[0054] In TLC memory cells, each of the eight threshold voltage distributions is sometimes referred to as a write level. These write levels are called "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from lowest to highest threshold voltage. The "Er" level indicates the erase state. The memory controller 2 transitions the memory cell in the "Er" level to one of the "A" to "G" levels by repeatedly performing program and verify operations. The program operation is an operation that changes the threshold voltage of the memory cell to the higher voltage side. The verify operation is an operation that determines whether the threshold voltage of the memory cell, which has been changed by the program operation, has reached one of the "A" to "G" levels.

[0055] Of these threshold voltage distributions, two adjacent distributions can be called the "first distribution" and the "second distribution," respectively, in order from the lowest threshold voltage. The same applies to SLC, MLC, and QLC methods. Each of these write levels is assigned a different set of 3 bits, as shown below. These 3 bits are called the lower bit, middle bit, and upper bit.

[0056] In this embodiment, the write level and 3-bit data correspond as follows. “Er” level: “111” data "A" level: "110" data "B" level: "100" data "C" level: "000" data "D" level: "010" data "E" level: "011" data "F" Level: "001" Data G level: 101 data The 3-bit data above is represented in the order of Upper, Middle, and Lower.

[0057] The set of lower bits held by memory cells connected to the same word line is called a lower page, the set of middle bits is called a middle page, and the set of upper bits is called an upper page. For example, data writing and reading operations are performed in units of these pages.

[0058] Between adjacent threshold distributions, a verification voltage used for the write operation is set. Specifically, verification voltages AV, BV, CV, DV, EV, FV, and GV are set corresponding to the "A", "B", "C", "D", "E", "F", and "G" levels, respectively.

[0059] For example, the verify voltage AV is set between the maximum threshold voltage at the "Er" level and the minimum threshold voltage at the "A" level. When the verify voltage AV is applied to a memory cell transistor, memory cell transistors whose threshold voltage falls within the "Er" level are turned ON, and memory cell transistors whose threshold voltage falls within the threshold distribution of the "A" level or higher are turned OFF.

[0060] Other verify voltages BV, CV, DV, EV, FV, and GV are set similarly to verify voltage AV. Verify voltage BV is set between level "A" and level "B". Verify voltage CV is set between level "B" and level "C". Verify voltage DV is set between level "C" and level "D". Verify voltage EV is set between level "D" and level "E". Verify voltage FV is set between level "E" and level "F". Verify voltage GV is set between level "F" and level "G".

[0061] Between adjacent threshold voltage distributions, a read voltage is set for each read operation. For example, the read voltage AR, which determines whether the threshold voltage of a memory cell falls within the "Er" level or above the "A" level, is set between the maximum threshold voltage at the "Er" level and the minimum threshold voltage at the "A" level. The read voltage AR is smaller than the verify voltage AV. However, the read voltage AR may be the same as the verify voltage AV.

[0062] Other read voltages, BR, CR, DR, ER, FR, and GR, are set between adjacent levels, similar to read voltage AR. For example, read voltage BR is set between level "A" and level "B". Read voltage CR is set between level "B" and level "C". Read voltage DR is set between level "C" and level "D". Read voltage ER is set between level "D" and level "E". Read voltage FR is set between level "E" and level "F". Read voltage GR is set between level "F" and level "G".

[0063] During a read operation, a read voltage Vread is supplied to the non-selected WL (word line WL that is not the target of the read operation) to force the memory cell transistor MT corresponding to that WL into an ON state. The voltage Vread is set to a voltage value higher than the maximum threshold voltage of the highest threshold voltage distribution (e.g., "G" level). When the voltage Vread is applied to the gate of a memory cell transistor MT, it turns ON regardless of the data being stored.

[0064] When the above data allocation is applied, the lower bit of the page data (lower page data) is determined in the read operation by the read result using read voltages AR and ER. The middle bit of the page data (middle page data) is determined by the read result using read voltages BR, DR, and FR. The upper bit of the page data (upper page data) is determined by the read result using read voltages CR and GR. Thus, since the data for the lower, middle, and upper pages are determined by 2, 3, and 2 read operations, respectively, this data allocation is called the "2-3-2 code". Note that the data allocation for each memory cell is not limited to the "2-3-2 code" example shown in Figure 6. For example, the data allocation may be a "1-3-3 code". Also, if the memory cell is QLC (n=4), there are 16 threshold voltage distributions, and data allocations such as the "1-2-4-8 code" and the "3-4-4-4 code" are possible.

[0065] [1-7. Explanation of Normal Mode and Special Mode] Figure 7 will be used to explain the threshold voltage distribution and read operation for both the normal mode and the special mode. For the sake of explanation, Figure 7 will explain the SLC method. Therefore, Figure 7 shows two write levels: the "Er" level and the "A" level. The upper threshold voltage distribution in Figure 7 is the normal mode, and the lower distribution is the special mode (Stealth Mode). In the following explanation, the "Er" level in the normal mode will be referred to as the first distribution Er1, and the "A" level as the second distribution A2. On the other hand, the "Er" level in the special mode will be referred to as the third distribution Er3, and the "A" level as the fourth distribution A4.

[0066] By performing a normal mode write operation on a memory cell, the threshold voltage of that memory cell is controlled to the first distribution Er1 or the second distribution A2. On the other hand, by performing a special mode write operation on a memory cell, the threshold voltage of that memory cell is controlled to the third distribution Er3 or the fourth distribution A4.

[0067] In normal mode, when the threshold voltage of a memory cell is controlled to the second distribution A2, the program operation and verification operation are repeated until the threshold voltage reaches the verify voltage AV1. Similarly, in special mode, when the threshold voltage of a memory cell is controlled to the fourth distribution A4, the program operation and verification operation are repeated until the threshold voltage reaches the verify voltage AV2. As shown in Figure 7, the verify voltage AV2 is greater than the verify voltage AV1. Note that the threshold voltage distribution of the memory cell in its initial state is the first distribution Er1 regardless of the mode, so in special mode, when the threshold voltage of a memory cell is controlled to the third distribution Er3, the program operation and verification operation are repeated until the threshold voltage reaches the verify voltage ErV2.

[0068] By performing a normal mode read operation on a memory cell, it is determined whether the threshold value of the memory cell belongs to the first distribution Er1 or the second distribution A2, based on the normal mode read voltage AR1. By performing a special mode read operation on a memory cell, it is determined whether the threshold value of the memory cell belongs to the third distribution Er3 or the fourth distribution A4, based on the special mode read voltage AR2.

[0069] In normal mode, the maximum threshold voltage in the first distribution Er1 (the voltage corresponding to the high-voltage tail of that distribution) is less than a predetermined voltage. The minimum threshold voltage in the second distribution A2 (the voltage corresponding to the low-voltage tail of that distribution) is greater than a predetermined voltage, and the maximum threshold voltage in the second distribution A2 is less than the voltage Vread. For example, the predetermined voltage is 0V. In normal mode, the read voltage AR1 is set to a voltage approximately midway between the maximum threshold voltage in the first distribution Er1 and the minimum threshold voltage in the second distribution A2. In normal mode, the verify voltage AV1 is set to a voltage between the read voltage AR1 and the minimum threshold voltage in the second distribution A2. In special mode, the verify voltage AV2 is set to a voltage between the read voltage AR2 and the minimum threshold voltage in the fourth distribution A4.

[0070] In special mode, the third distribution Er3 is shifted to a higher voltage side compared to the first distribution Er1 in normal mode. As a result, at least a portion of the third distribution Er3 in special mode lies between the maximum threshold voltage of the first distribution Er1 and the minimum threshold voltage of the second distribution A2 in normal mode. In special mode, the maximum threshold voltage of the third distribution Er3 is greater than the readout voltage AR1 in normal mode. In other words, the readout voltage AR1 in normal mode overlaps with the third distribution Er3. In the example in Figure 7, the maximum threshold voltage of the third distribution Er3 is located on the higher voltage side than the minimum threshold voltage of the second distribution A2 in normal mode. In other words, the second distribution A2 and the third distribution Er3 overlap. However, the maximum threshold voltage of the third distribution Er3 in special mode may be located on the lower voltage side than the minimum threshold voltage of the second distribution A2 in normal mode.

[0071] On the other hand, the peak position of the fourth distribution A4 in the special mode is at a higher voltage than the peak position of the second distribution A2 in the normal mode, but the maximum threshold voltage in the fourth distribution A4 in the special mode is smaller than the voltage Vread, similar to the maximum threshold voltage in the second distribution A2 in the normal mode. In the example in Figure 7, the maximum threshold voltage in the fourth distribution A4 is at approximately the same position as the maximum threshold voltage in the second distribution A2. However, the maximum threshold voltage in the fourth distribution A4 may be lower or higher than the maximum threshold voltage in the second distribution A2.

[0072] The widths of the third distribution Er3 and the fourth distribution A4 in special mode are smaller than the widths of the first distribution Er1 and the second distribution A2 in normal mode, respectively. The readout voltage AR2 in special mode is greater than the readout voltage AR1 in normal mode and is set to a voltage approximately midway between the maximum threshold voltage in the third distribution Er3 and the minimum threshold voltage in the fourth distribution A4.

[0073] In Figure 7, since the maximum threshold voltage in the second distribution A2 and the maximum threshold voltage in the fourth distribution A4 are approximately the same, a common voltage Vread can be used for both the read operation on the first memory cell that underwent a normal mode write operation and the read operation on the second memory cell that underwent a special mode write operation. Note that voltage Vread is greater than both the normal mode read voltage AR1 and the special mode read voltage AR2. Since both the maximum threshold voltage in the second distribution A2 in normal mode and the maximum threshold voltage in the fourth distribution A4 in special mode are less than voltage Vread, an erase operation can be performed simultaneously on both the memory cell that underwent a normal mode write operation and the memory cell that underwent a special mode write operation.

[0074] As described above, when a batch erase operation is performed, the threshold voltage distribution of the memory cells in the initial state is the first distribution Er1, regardless of the mode. Therefore, in normal mode, when the threshold voltage of a memory cell is controlled to the first distribution Er1, no program operation is performed on that memory cell. In special mode, when the threshold voltage of a memory cell is controlled to the third distribution Er3, a program operation is performed on that memory cell. In both normal and special modes, when the threshold voltage of a memory cell is controlled to the second distribution A2 or the fourth distribution A4, a program operation is performed on that memory cell.

[0075] The normal mode write operation is sometimes referred to as the "first write operation." The special mode write operation is sometimes referred to as the "second write operation." The normal mode read operation is sometimes referred to as the "first read operation." The special mode read operation is sometimes referred to as the "second read operation." The memory controller 2 executes the first write operation, the second write operation, the first read operation, and the second read operation, respectively, in response to the first write instruction, the second write instruction, the first read instruction, and the second read instruction from the external memory controller. The normal mode read voltage AR1 is sometimes referred to as the "first voltage." The special mode read voltage AR2 is sometimes referred to as the "second voltage."

[0076] In the semiconductor memory device according to this embodiment, information for identifying the address of a memory cell (or page or block) that has been written in special mode is stored in register 26. When the semiconductor memory device performs a read operation, it is determined whether or not the memory cell was written in special mode based on the address of the memory cell to be read. If it is determined that the memory cell was written in special mode, a special mode read operation is performed on the memory cell. On the other hand, if it is determined that the memory cell was written in normal mode, a normal mode read operation is performed on the memory cell.

[0077] In the example above, information for identifying the address of a memory cell written in special mode is stored in register 26. However, information for identifying the address of a memory cell written in normal mode may be stored in register 26 along with or instead of this information.

[0078] As described above, the maximum threshold voltage in the third distribution Er3 in special mode is greater than the read voltage AR1 in normal mode. Therefore, if a read operation is performed using the read voltage AR1 in normal mode on a memory cell that has been written to the third distribution Er3 in special mode, the memory cell may be incorrectly determined to be at the "A" level. In other words, if a read operation is performed in normal mode on a memory cell that has been written to in special mode, it will not be possible to determine the correct data.

[0079] Therefore, without knowing whether a normal mode or special mode write operation was performed on the memory cell, it is impossible to correctly determine the write level of that memory cell. In particular, if the maximum threshold voltage in the third distribution Er3 of the special mode is located on the higher voltage side than the minimum threshold voltage in the second distribution A2 of the normal mode, the third distribution Er3 and the second distribution A2 overlap, making it almost impossible to determine the data stored in the memory cell.

[0080] In some cases, the write level of a semiconductor memory device can be measured by supplying voltage and signals from an external probe. However, using this method carries the risk of information stored in the semiconductor memory device being stolen by a malicious third party.

[0081] However, a third party who does not know which memory cells were written to using a special mode would likely use the same criteria to determine the data write level for all memory cells. Therefore, if a special mode write operation is performed on some of the memory cells in a semiconductor storage device, a third party will not be able to obtain the correct information, thus reducing the risk of information stored in the semiconductor storage device being stolen. In other words, the security of data stored in the semiconductor storage device can be enhanced.

[0082] In Figure 7, the SLC method is explained, and the configuration in which the first distribution Er1 and the third distribution Er3 correspond to the erase state of the memory cell is shown as an example, but the configuration is not limited to this. For example, the first and third distributions may correspond to the "F" level distribution in Figure 6, and the second and fourth distributions may correspond to the "G" level distribution.

[0083] [2. Second Embodiment] The semiconductor memory device according to the second embodiment will be described using Figures 8 to 10. The second embodiment is one application example of the semiconductor memory device according to the first embodiment. The configuration and read operation of the memory system according to the second embodiment are the same as those of the memory system according to the first embodiment, so the memory system according to the second embodiment will be described with reference to Figures 1 to 7. In this description of the embodiment, the same configuration and operation as in the first embodiment will be omitted.

[0084] Figures 8 to 10 show the circuit configuration of one block in a semiconductor memory device according to one embodiment. In these figures, the specific circuit configuration of "Block n" is shown, but "Block n-1" and "Block n+1" have the same circuit configuration as "Block n".

[0085] As shown in Figure 8, a string 50 is provided between each of the bit lines BLm-1, BLm, and BLm+1 and the source line SL. The configuration of each string 50 is as described in Figure 5, so a detailed explanation is omitted. In this embodiment, one page is composed of memory cells connected to the same word line WL within the same block. In this embodiment, an example is given of a configuration in which multiple memory cells connected to the same word line WL within the same string 50 are divided into normal mode and special mode.

[0086] In the example shown in Figure 9, a configuration is shown in which normal mode and special mode are mixed within a single block, "Block n". Specifically, special mode write and read operations are performed in memory cells connected to word lines WL0, WL1, and WL6. Normal mode write and read operations are performed in memory cells connected to other word lines WL. Pages corresponding to special mode are called special pages (SP-pages). Thus, even for memory cells connected to the same bit line BL, normal mode write and read operations are performed in one memory cell, while special mode write and read operations are performed in the other.

[0087] In the above case, in "Block n", information indicating that the pages corresponding to word lines WL0, WL1, and WL6 are special pages is stored in register 26. When the memory controller 2 receives a write command or read command from an external host computer, it determines whether the memory cell corresponding to the command is included in a special page. If it is determined that the target memory cell is included in a special page, the memory controller 2 performs a special mode write or read operation on that memory cell.

[0088] The example shown in Figure 10 illustrates a configuration in which all memory cells within a single block, "Block n," are in special mode. That is, special mode write and read operations are performed on memory cells connected to word lines WL0-7. In this case, "Block n" can be referred to as a special block.

[0089] As described above, the semiconductor memory device according to the second embodiment can also obtain the same effects as the first embodiment.

[0090] [3. Variant] In this embodiment, the SLC method has been described, but the above technical concept may also be applied to the MLC method, TLC method, QLC method, PLC method, or HLC method. In that case, the above normal mode and special mode may be applied to all write levels in each method, or to some write levels.

[0091] The memory controller 2 may perform a normal mode write operation (first write operation) or a special mode write operation (second write operation) based on a write command received from an external host computer. For example, the memory controller 2 may perform a first write operation based on a first write command and a second write operation based on a second write command. Similarly, the memory controller 2 may perform a normal mode read operation (first read operation) or a special mode read operation (second read operation) based on a read command received from an external host computer. For example, the memory controller 2 may perform a first read operation based on a first read command and a second read operation based on a second read command.

[0092] When the memory controller 2 executes a first write operation or a second write operation based on a command as described above, the memory controller 2 may determine, based on the command, which memory cell (first memory cell) will be subjected to the first write operation and which memory cell (second memory cell) will be subjected to the second write operation. In other words, if a first write operation is performed on the first memory cell based on the first write command described above, a first read operation is performed on the first memory cell based on the first read command corresponding to the first write operation command. Similarly, if a second write operation is performed on the second memory cell based on the second write command described above, a second read operation is performed on the second memory cell based on the second read command.

[0093] A write command issued from an external host computer may contain flag information indicating that the data to be stored in the semiconductor memory device contains highly confidential data. In this case, if the memory controller 2 detects that the write command received from the external host computer contains flag information, it may perform a special mode write operation on the data identified by the flag information (highly confidential data).

[0094] In this case, of the data stored in the semiconductor memory device by the above write command, only the data identified by the flag information may be written by a special mode write operation, while the remaining data may be written by a normal mode write operation. Alternatively, all of the data stored in the semiconductor memory device by a write command including the flag information may be written by a special mode write operation. Information for identifying the address of the memory cell to which data has been written by a special mode write operation is stored in register 26. When the semiconductor memory device performs a read operation, it is determined whether or not the memory cell to be read was written in special mode based on its address, and a read operation is performed based on the result of that determination.

[0095] Even if a special page SP-page or special block is not pre-configured as in the second embodiment, or if the write command issued from the host computer does not include flag information, a special mode write operation may be performed based on specific conditions or randomly. In this case as well, information for identifying the address of the memory cell to which data has been written by the special mode write operation is stored in register 26.

[0096] Although the present invention has been described above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified as appropriate without departing from the spirit of the invention. For example, a semiconductor memory device based on this embodiment, with additions, deletions, or design changes made by a person skilled in the art, is also included in the scope of the present invention as long as it retains the gist of the invention. Furthermore, the embodiments described above can be combined as appropriate as long as they do not contradict each other, and technical matters common to each embodiment are included in each embodiment even without explicit description.

[0097] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0098] 1: Memory system, 2: Memory controller, 5: Semiconductor memory device, 6: Semiconductor memory device, 7: Semiconductor memory device, 8: Semiconductor memory device, 10: Wiring layer, 11: Wiring layer, 12: Wiring layer, 13: Semiconductor substrate, 16: Contact plug, 21: Memory cell array, 22: Input / output circuit, 24: Logic control circuit, 26: Register, 27: Sequencer, 28: Voltage generation circuit, 29: Driver set, 30: Row decoder, 31: Sense amplifier, 32: Input / output pad group, 34: Logic control pad group, 50: String, 50-1: String, 61: Processor, 62: Internal memory, 63: Interface circuit, 64: Buffer memory, 65: Host interface circuit

Claims

1. A semiconductor memory device comprising a control circuit, a first word line, and a memory array connected to the first word line and including a first memory cell capable of storing n bits (where n is an integer of 1 or more), The aforementioned control circuit is It is configured to execute a first write operation in response to a first write instruction from an external memory controller, a second write operation in response to a second write instruction from the memory controller, a first read operation in response to a first read instruction from the memory controller, and a second read operation in response to a second read instruction from the memory controller. By performing the first write operation, the threshold voltage of the first memory cell is set to a first distribution and a second distribution, which are arranged in ascending order of voltage. ｎ It is configured to control one of the following distributions: The system is configured to determine whether the threshold value of the first memory cell is a first distribution or a second distribution based on the first voltage by performing the first read operation. By performing the second write operation, the threshold voltage of the first memory cell is set to include a third distribution and a fourth distribution arranged in ascending order of voltage. ｎ It is configured to control one of the following distributions: The system is configured to determine whether the threshold value of the first memory cell is the third distribution or the fourth distribution based on a second voltage that is higher than the first voltage, by performing the second read operation. A semiconductor memory device wherein at least a portion of the third distribution lies between the first distribution and the second distribution.

2. The semiconductor memory device according to claim 1, wherein the first voltage overlaps with the third distribution.

3. The semiconductor memory device according to claim 1, wherein the width of the fourth distribution is smaller than the width of the second distribution.

4. The semiconductor memory device according to claim 3, wherein the width of the third distribution is smaller than the width of the first distribution.

5. Further including the second word line, The memory array includes a second memory cell connected to the second word line and capable of storing n bits, The aforementioned control circuit is The first write instruction executes the first write operation on the first memory cell, The second write instruction executes the second write operation on the second memory cell, The first read operation is performed on the first memory cell by supplying a third voltage to the first word line in response to the first read instruction. The second read operation is performed on the second memory cell by supplying the third voltage to the second word line in response to the second read instruction. The semiconductor memory device according to claim 1, wherein the third voltage is greater than the first voltage and the second voltage.

6. Further including bit lines and source lines, The semiconductor memory device according to claim 5, wherein the first memory cell and the second memory cell are connected in series between the bit line and the source line.

7. Further including the second word line, The memory array includes a second memory cell connected to the second word line and capable of storing n bits, The first write operation includes a first program operation that changes the threshold voltage of the first memory cell to a higher voltage, and a first verify operation that checks the threshold voltage of the first memory cell after the first program operation. The second write operation includes a second program operation that changes the threshold voltage of the second memory cell to a higher voltage, and a second verify operation that checks the threshold voltage of the second memory cell after the second program operation. The aforementioned control circuit is The first program operation and the first verification operation are repeated until the threshold voltage of the first memory cell reaches the first verification voltage used for the first verification operation. The second program operation and the second verification operation are repeated until the threshold voltage of the second memory cell reaches the second verification voltage used for the second verification operation. The semiconductor memory device according to claim 1, wherein the second verify voltage is greater than the first verify voltage.

8. The semiconductor memory device according to claim 1, wherein the first distribution is a distribution corresponding to the erase state of the first memory cell.

9. The aforementioned control circuit is The semiconductor memory device according to claim 8, wherein the program operation is executed when the threshold voltage of the first memory cell is controlled to the third distribution.

10. The semiconductor memory device according to claim 9, wherein the control circuit does not perform a program operation to change the threshold voltage of the first memory cell to a higher voltage.

11. The semiconductor memory device according to claim 1, wherein the control circuit executes the first write operation based on a first write command received from an external host computer, executes the second write operation based on a second write command, executes the first read operation based on a first read command, and executes the second read operation based on a second read command.

12. Further including the second word line, The memory array includes a second memory cell connected to the second word line and capable of storing n bits, The aforementioned control circuit is If the first write operation is performed on the first memory cell based on the first write command, then the first read operation is performed on the first memory cell based on the first read command. The semiconductor memory device according to claim 10, wherein when the second write operation is performed on the second memory cell based on the second write command, the second read operation is performed on the second memory cell based on the second read command.

13. The aforementioned control circuit is If the command received from an external host computer contains flag information, the second write operation and the second read operation are executed. The semiconductor memory device according to claim 1, wherein if the aforementioned flag information is not included, the first write operation and the first read operation are performed.

Images