Method for manufacturing a light-emitting element and method for manufacturing a thin film of a III-V compound semiconductor

Abstract

This suppresses the formation of non-uniform layers in aluminum-containing III-V compound semiconductors. [Solution] A method for manufacturing a light-emitting element made of a III-V compound semiconductor having a structure in which a second layer containing aluminum is laminated on a first layer that does not contain aluminum, comprising: a first layer formation step of supplying raw material gases of each element constituting the first layer to form the first layer; a pre-supply step of supplying aluminum raw material gas first after the first layer has been formed; and a second layer formation step of supplying raw material gases of each element constituting the second layer after the pre-supply step to form the second layer.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a light-emitting element and a method for manufacturing a thin film of a group III-V compound semiconductor.

Background Art

[0002] Patent Document 1 discloses that a group III-V compound semiconductor light-emitting element has an n-type cladding layer, a light-emitting layer, and a p-type cladding layer in this order, and an undoped electron blocking layer is provided between the light-emitting layer and the p-type cladding layer. The light-emitting layer has a stacked structure formed by repeatedly stacking barrier layers and well layers. In the conduction band, the band gap of the electron blocking layer is larger than the band gaps of the barrier layer and the p-type cladding layer, and the band gap of the p-type cladding layer is larger than the band gap of the barrier layer. In the valence band, the band gap of the electron blocking layer is between the band gap of the barrier layer and the band gap of the cladding layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] A group III-V compound semiconductor containing aluminum may be used as a material for a semiconductor element. If this group III-V compound semiconductor forms a non-uniform layer, for example, the intensity of light may decrease or light of an unintended wavelength may be generated. An object of the present invention is to suppress the formation of a non-uniform layer in a group III-V compound semiconductor containing aluminum.

Means for Solving the Problems

[0005] The present invention relates to a method for manufacturing a light-emitting element, which is a method for manufacturing a light-emitting element made of a III-V compound semiconductor having a structure in which a second layer containing aluminum is laminated on a first layer that does not contain aluminum, and comprises: a first layer formation step of supplying raw material gases of each element constituting the first layer to form the first layer; a pre-supply step of supplying aluminum raw material gas first after the first layer has been formed; and a second layer formation step of supplying raw material gases of each element constituting the second layer after the pre-supply step to form the second layer. In this case, the aforementioned supply step may involve supplying the aluminum raw material gas for 1 second or more. Furthermore, the duration of the aforementioned pre-supply process may be 5 seconds or less. Furthermore, the aforementioned supply step may involve supplying only aluminum as the raw material gas among the elements constituting the second layer. Furthermore, the second layer formation step may involve supplying raw material gases for other elements constituting the second layer while maintaining the supply of aluminum raw material gas in the preceding supply step. Furthermore, the first layer may be a carrier confinement layer that confines carrier electrons. Furthermore, the first layer may be a layer containing either In or Ga, and either As or P. Furthermore, the first layer may be a layer containing In and P. Furthermore, the aforementioned second layer may be a light-emitting layer. Furthermore, the second layer may be a III-V compound semiconductor containing In, Ga, Al, and As.

[0006] From another perspective, the method for manufacturing a thin film of a III-V compound semiconductor to which the present invention applies is a method for manufacturing a thin film of a III-V compound semiconductor by epitaxially growing a III-V compound semiconductor containing a plurality of group III elements including aluminum and one or more group V elements, and the method comprises a step of supplying aluminum as a raw material gas before supplying the raw material gases of each element constituting the III-V compound semiconductor. [Effects of the Invention]

[0007] According to the present invention, the formation of non-uniform layers in a III-V compound semiconductor containing aluminum is suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows the cross-sectional configuration of a semiconductor layer-forming substrate to which this embodiment is applied. [Figure 2] This is a flowchart illustrating the manufacturing method for semiconductor layer-forming substrates. [Figure 3] This is a timing chart illustrating the manufacturing method for the barrier layer placed on the LCCL layer. [Figure 4] This figure shows the cross-sectional configuration of a semiconductor light-emitting element. [Figure 5] This is a flowchart illustrating the manufacturing method of semiconductor light-emitting devices. [Figure 6] This figure shows the cross-sectional configuration of the light-emitting element layer used for verification. [Figure 7A] This figure shows the results of the photoluminescence measurement for the first sample. [Figure 7B] This figure shows the results of the photoluminescence measurement for the second sample. [Figure 7C] This figure shows the results of the photoluminescence measurement for the third sample. [Figure 8A]It is a diagram showing the result of photoluminescence measurement when the growth substrate, the LCCL layer, the barrier layer, and the UCCL layer are laminated in the fourth sample. [Figure 8B] It is a diagram showing the result of photoluminescence measurement when the UCCL layer is removed in the fourth sample. [Figure 8C] It is a diagram showing the result of photoluminescence measurement when a part of the UCCL layer and the barrier layer is removed in the fourth sample. [Figure 8D] It is a diagram showing the result of photoluminescence measurement when a further part of the UCCL layer and the barrier layer is removed in the fourth sample. [Figure 8E] It is a diagram showing the result of photoluminescence measurement when the UCCL layer and the barrier layer are removed in the fourth sample. [Figure 9] It is a diagram showing the cross-sectional configuration of the light-emitting element layer for verification. [Figure 10] It is a diagram showing the result of photoluminescence measurement for the light-emitting element layer of the second comparative example.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the sizes, thicknesses, etc. of each part in the drawings referred to in the following description may be different from the actual dimensions. Further, hereinafter, regarding III-V compound semiconductors composed of three or more elements, the composition ratios of the respective elements may be described in an abbreviated form (for example, "AlGaInAsP", etc.).

[0010] <Configuration of the Semiconductor Layer Forming Substrate> FIG. 1 is a diagram showing the cross-sectional configuration of a semiconductor layer forming substrate 1 to which the present embodiment is applied. This semiconductor layer forming substrate 1 is a raw material for a semiconductor light-emitting element 2 (see FIG. 4) to be described later in the manufacture of the semiconductor light-emitting element 2. This semiconductor layer forming substrate 1 includes a growth substrate 100, a buffer layer 101, an etching stop layer 102, and a light-emitting element layer 10 formed by laminating a plurality of semiconductor layers.

[0011] [Growth substrate] In this embodiment, the growth substrate 100 is composed of a single crystal of a compound semiconductor (III-V group semiconductor). Examples of this type of growth substrate 100 include InP.

[0012] [Buffer layer] The buffer layer 101 is a layer for mitigating interstitial mismatch between the growth substrate 100 and the etching stop layer 102. In this embodiment, the buffer layer 101 is composed of a compound semiconductor (III-V group semiconductor) that is lattice-matched with the surface (growth plane) of the growth substrate 100.

[0013] [Etching stop layer] The etching stop layer 102 is a layer that prevents the layers after the etching stop layer 102 from being removed by etching when the growth substrate 100 is removed by etching. In this embodiment, the etching stop layer 102 is composed of a compound semiconductor (III-V group semiconductor) that is lattice-matched with the buffer layer 101. The removal of the growth substrate 100 by etching will be described later.

[0014] [luminescent layer] The light-emitting element layer 10 includes an n-type contact layer 11 laminated on the etching stop layer 102, a light-emitting layer 12 laminated on the n-type contact layer 11, and a p-type contact layer 13 laminated on the light-emitting layer 12. The components of the light-emitting element layer 10 will be described in order below.

[0015] (n-type contact layer) The n-type contact layer 11, which uses electrons as carriers, is a layer for providing an n-electrode (negative electrode portion 30: see Figure 3, described later). In this embodiment, the n-type contact layer 11 is made of a compound semiconductor (III-V group semiconductor) that is lattice-matched with the etching stop layer 102.

[0016] (Emitting layer) The light-emitting layer 12 has a so-called double heterojunction and quantum well structure, and is a layer that emits light when an electric current is applied.

[0017] The light-emitting layer 12 of this embodiment includes an n-type cladding layer 121 laminated on the n-type contact layer 11, an LCCL (Lower carrier confinement layer) layer 122 laminated on the n-type cladding layer 121, an active layer 123 laminated on the LCCL layer 122, an UCCL (Upper carrier confinement layer) layer 124 laminated on the active layer 123, and a p-type cladding layer 125 laminated on the UCCL layer 124. In the illustrated example, the active layer 123 has a multiple quantum well structure in which three barrier layers 1231 and two well layers 1232 are alternately laminated. The number of barrier layers 1231 and well layers 1232 is not particularly limited.

[0018] [n-type cladding layer] The n-type cladding layer 121, together with the p-type cladding layer 125, is a layer that implants and confines carriers (holes and electrons) into the active layer 123. In this embodiment, the n-type cladding layer 121 is composed of a compound semiconductor (III-V semiconductor) that is lattice-matched with the n-type contact layer 11. Here, it is preferable that the n-type cladding layer 121 has a larger band gap than the n-type contact layer 11. Furthermore, it is preferable that the n-type cladding layer 121 is doped with n-type impurities.

[0019] [LCCL layer] The LCCL layer 122 suppresses the diffusion of n-type impurities doped into the n-type cladding layer 121 into the active layer 123, and also functions as a carrier confinement layer that confines carriers. In this embodiment, the LCCL layer 122 is composed of a compound semiconductor (III-V semiconductor) that is lattice-matched with the n-type cladding layer 121. The LCCL layer 122 is not doped with n-type impurities. Furthermore, in this embodiment, the LCCL layer 122 is formed without aluminum as a group 5 element. The LCCL layer 122 is an example of a first layer that does not contain aluminum. Examples of elements constituting the LCCL layer 122 include a layer containing either In or Ga, and either As or P. More specifically, examples include a layer containing InP, InGaAsP, InGaAs, and InAsP. Furthermore, it is desirable that the LCCL layer 122 has a band gap that is different in wavelength from the emission wavelength of the active layer 123, so as not to absorb the light emitted by the active layer 123.

[0020] [Active layer] The active layer 123 is a layer that emits light through the recombination of electrons and holes. Furthermore, the active layer 123 in this embodiment is a layer having a so-called multiple quantum well structure (MQW) in which barrier layers 1231 and well layers 1232 are alternately stacked. In the illustrated example, the active layer 123 has two well layers 1232 and three barrier layers 1231, but the number of barrier layers 1231 and well layers 1232 is not limited to this. The active layer 123 (barrier layers 1231 and well layers 1232) basically does not contain n-type impurities or p-type impurities. However, during manufacturing, n-type impurities may diffuse from the n-type cladding layer 121 or p-type impurities may diffuse from the p-type cladding layer 125. The barrier layer 1231 placed on the LCCL layer 122 is an example of a second layer containing aluminum.

[0021] {barrier layer} The barrier layer 1231 is a layer that sandwiches the well layer 1232 together with other barrier layers 1231. In this embodiment, the barrier layer 1231 is composed of a compound semiconductor (III-V semiconductor) that is lattice-matched with the LCCL layer 122 and the UCCL layer 124. Preferably, In, Al, Ga, As, and P are used for the barrier layer 1231. Furthermore, it is preferable to use a direct-bandgap compound semiconductor (III-V semiconductor) for the barrier layer 1231.

[0022] Here, it is preferable that the barrier layer 1231 has a smaller band gap than the n-type cladding layer 121 and the p-type cladding layer 125. Furthermore, it is preferable that the barrier layer 1231 has a larger band gap than the well layer 1232.

[0023] {well layer} The well layer 1232 is a layer sandwiched between two adjacent barrier layers 1231. Therefore, the number of layers in the well layer 1232 is one less than the number of layers in the barrier layers 1231. In this embodiment, the well layer 1232 is composed of a compound semiconductor (III-V semiconductor) that is lattice-matched with the barrier layers 1231. Furthermore, it is preferable to use a direct-bandgap compound semiconductor (III-V semiconductor) for the well layer 1232. Here, it is preferable that the well layer 1232 has a smaller band gap than the n-type cladding layer 121 and the p-type cladding layer 125.

[0024] [UCCL layer] The UCCL layer 124 functions as a carrier confinement layer that suppresses the diffusion of p-type impurities doped into the p-type cladding layer 125 into the active layer 123 and confines carriers. In this embodiment, the UCCL layer 124 is composed of a compound semiconductor (III-V semiconductor) that is lattice-matched with the barrier layer 1231. Furthermore, the UCCL layer 124 is not doped with p-type impurities. Examples of elements that constitute the UCCL layer 124 include InP, InGaAsP, InGaAs, and InAsP.

[0025] [p-type cladding layer] The p-type cladding layer 125, together with the n-type cladding layer 121, is a layer that implants and confines carriers into the active layer 123. In this embodiment, the p-type cladding layer 125 is composed of a compound semiconductor (III-V semiconductor) that is lattice-matched with the UCCL layer 124.

[0026] (p-type contact layer) The p-type contact layer 13, which uses holes as carriers, is a layer for providing a p-electrode (positive electrode portion 20: see Figure 4, described later). In this embodiment, the p-type contact layer 13 is composed of a compound semiconductor (III-V group semiconductor) that is lattice-matched with the p-type cladding layer 125.

[0027] <Method for manufacturing semiconductor layer-forming substrates> Figure 2 is a flowchart illustrating the manufacturing method of the semiconductor layer-forming substrate 1. In this embodiment, the semiconductor layer-forming substrate 1 is obtained by forming a buffer layer 101, an etching stop layer 102, and a light-emitting element layer 10 on a growth substrate 100 using the MOCVD (Metal Organic Chemical Vapor Deposition) method.

[0028] [Buffer layer formation process] First, a carrier gas and raw material gases for each element constituting the buffer layer 101 (group III elements, group V elements, and elements constituting n-type impurities) are supplied into the chamber in which the growth substrate 100 is installed (step 1010). In step 1010, the buffer layer 101 is stacked on the growth substrate 100.

[0029] [Etching stop layer formation process] Next, a carrier gas is supplied to the chamber in which the growth substrate 100 with the buffer layer 101 stacked is placed, along with the raw material gases for each element constituting the etching stop layer 102 (group III elements, group V elements, and elements constituting n-type impurities) (step 1020). In step 1020, the etching stop layer 102 is stacked on the buffer layer 101.

[0030] [n-type contact layer formation process] Next, the growing substrate 100, on which the etching stop layer 102 has been laminated, is placed in a chamber into which the carrier gas is supplied, along with the raw material gases for each element constituting the n-type contact layer 11 (group III elements, group V elements, and elements constituting n-type impurities) (step 1030). In step 1030, the n-type contact layer 11 is laminated on the etching stop layer 102.

[0031] [n-type cladding layer formation process] Then, the carrier gas is continuously supplied to the chamber in which the growth substrate 100, on which the n-type contact layer 11 has been laminated, and the raw material gases for each element constituting the n-type cladding layer 121 (group III elements, group V elements, and elements constituting n-type impurities) are supplied (step 1040). In step 1040, the n-type cladding layer 121 is laminated on the n-type contact layer 11.

[0032] [LCCL layer formation process] Furthermore, a carrier gas is continuously supplied to the chamber in which the growth substrate 100, with the n-type cladding layer 121 stacked on top, is installed, along with the raw material gases for each element (group III elements, group V elements) that constitute the LCCL layer 122 (step 1050). In step 1050, the LCCL layer 122 is stacked on top of the n-type cladding layer 121.

[0033] [Active layer formation process] Next, a carrier gas is continuously supplied into the chamber where the growth substrate 100, with the LCCL layer 122 stacked on top of it, is installed. At the same time, raw material gases for each element (Group III and Group V elements) constituting the barrier layer 1231 and raw material gases for each element (Group III and Group V elements) constituting the well layer 1232 are supplied alternately (step 1060). In step 1060, an active layer 123 is formed on the LCCL layer 122 by alternately stacking the barrier layer 1231 and the well layer 1232.

[0034] In this embodiment, when supplying the raw material gases for each element (Group III elements, Group V elements) that constitute the barrier layer 1231 placed in contact with the LCCL layer 122, the timing of supplying the aluminum raw material gas is carefully considered. This suppresses the formation of a layer with uneven aluminum concentration on the LCCL layer 122, and the details of this will be described later.

[0035] [UCCL layer formation process] Next, the carrier gas is supplied to the chamber in which the growth substrate 100, with the active layer 123 stacked on top of it, is placed, along with the raw material gases for each element (Group III elements, Group V elements) that constitute the UCCL layer 124 (step 1070). In step 1070, the UCCL layer 124 is stacked on top of the active layer 123.

[0036] [P-type cladding layer formation process] Then, the carrier gas is continuously supplied to the chamber in which the growth substrate 100, with the UCCL layer 124 stacked on top, is placed, along with the raw material gases for each element constituting the p-type cladding layer 125 (group III elements, group V elements, and elements constituting p-type impurities) (step 1080). In step 1080, the p-type cladding layer 125 is stacked on top of the UCCL layer 124. As a result, the light-emitting layer 12 is formed on the n-type contact layer 11.

[0037] [p-type contact layer formation process] Next, a carrier gas is supplied to the chamber in which the growth substrate 100, with the p-type cladding layer 125 stacked on top of it, is placed, along with the raw material gases for each element constituting the p-type contact layer 13 (group III elements, group V elements, and elements constituting p-type impurities) (step 1090). In step 1090, the p-type contact layer 13 is stacked on top of the p-type cladding layer 125. As a result, a semiconductor layer formation substrate 1 is obtained by stacking a buffer layer 101, an etching stop layer 102, an n-type contact layer 11, an emissive layer 12, and a p-type contact layer 13 on a growth substrate 100 in this order.

[0038] <Method for manufacturing the active layer 123> Here, we will provide a more detailed explanation of the step of growing the barrier layer 1231 on the LCCL layer 122, which is part of the active layer formation process (step 1060) described above. Figure 3 is a timing chart illustrating the manufacturing method of the barrier layer 1231 placed on the LCCL layer 122. In Figure 3, the horizontal axis represents elapsed time (labeled "growth time" in the figure). Figure 3 also shows the relationship between the four processes (steps 1 to 4) performed in the manufacturing of the LCCL layer 122 and the barrier layer 1231 placed on the LCCL layer 122, and the various raw material gases supplied into the chamber in each process. Here, step 1 corresponds to step 1050 in Figure 2. Steps 3 and 4 correspond to the process of laminating the barrier layer 1231 on the LCCL layer 122 in step 1060. Step 2 is an interval to prevent the raw material gas for the LCCL layer 122 and the raw material gas for the barrier layer 1231 from mixing.

[0039] Here, we will explain using the example where the LCCL layer 122 is made of "InP" and the barrier layer 1231 is made of "InGaAlAs". In this embodiment, as described above, the LCCL layer 122 and the barrier layer 1231 are formed by MOCVD. Here, we will explain assuming that H2 (hydrogen) is the carrier gas, TMI (trimethylindium) is the In raw material gas, TMG (trimethylgallium) is the Ga raw material gas, TMA (trimethylaluminum) is the Al raw material gas, PH3 (phosphine) is the P raw material gas, and AsH3 (arsine) is the As raw material gas.

[0040] [1st step] In the first step, a carrier gas and various raw material gases (corresponding to the raw material gases for each element constituting the first layer), namely In raw material gas and P raw material gas, which will be used as raw materials for the LCCL layer 122 (corresponding to the first layer that does not contain aluminum), are supplied into the chamber. The first process is carried out over a first period T1, from the start time t0 of the first process to the end time t1 of the first process.

[0041] [Second process] In the second process, which follows the first process, the supply of the In raw material gas that was supplied in the first process is stopped. In the second process, a carrier gas and the P raw material gas that was supplied in the first process are supplied into the chamber. In the second process, the P raw material gas is supplied to suppress the loss of P from the surface of the InP layer, which would otherwise cause the surface of the InP layer to become rough. The second process is carried out over a second period T2, from the end time of the first process (start time of the second process) t1 to the end time of the second process t2.

[0042] [3rd step] In the third process, which follows the second process, the supply of P raw material gas, which was supplied in the second process, is stopped. Then, in the third process (corresponding to the previous supply process), carrier gas and Al raw material gas are supplied into the chamber. In this third process, only the Al raw material gas is supplied from the raw material gases for the barrier layer 1231 (corresponding to the second layer containing aluminum). The third process is carried out over a third period T3, from the end time of the second process (start time of the third process) t2 to the end time of the third process t3.

[0043] [4th step] In the fourth step, following the third step, in addition to the carrier gas and Al raw material gas that were flowing in the third step, the supply of raw material gases other than Al from the barrier layer 1231 (corresponding to the raw material gases of other elements that make up the second layer) is started. Specifically, in the fourth step, in addition to the carrier gas and Al raw material gas, In raw material gas, Ga raw material gas, and As raw material gas are supplied into the chamber. The fourth process is carried out over a fourth period T4, from the end time of the third process (start time of the fourth process) t3 to the end time of the fourth process t4.

[0044] <Configuration of semiconductor light-emitting element> Figure 4 shows the cross-sectional configuration of the semiconductor light-emitting element 2. As is clear from Figure 4, the semiconductor light-emitting element 2 does not include the growth substrate 100, buffer layer 101, and etching stop layer 102 that together constituted the semiconductor layer formation substrate 1 with the light-emitting element layer 10. The growth substrate 100, buffer layer 101, and etching stop layer 102 are removed in the growth substrate removal process (step 1116 (see Figure 5)) and etching stop layer removal process (step 1117 (see Figure 5)) described later.

[0045] The semiconductor light-emitting element 2 comprises a light-emitting layer 10 (see Figure 1), a positive electrode portion 20 connected to the p-type contact layer 13 of the light-emitting layer 10, and a negative electrode portion 30 connected to the n-type contact layer 11 of the light-emitting layer 10. Here, the positive electrode portion 20 functions as the p-electrode of the light-emitting layer 12 in the light-emitting layer 10. On the other hand, the negative electrode portion 30 functions as the n-electrode of the light-emitting layer 12 in the light-emitting layer 10. Furthermore, the positive electrode portion 20 also functions as a reflective film that reflects the light output from the light-emitting layer 12 in the light-emitting layer 10 to the positive electrode portion 20 side to the negative electrode portion 30 side. Here, the positive electrode portion 20 is formed on the lower side of each semiconductor light-emitting element 2 in the figure, covering almost the entire surface. In contrast, the negative electrode portion 30 is formed in an island-like manner in a part of the upper side of each semiconductor light-emitting element 2 in the figure.

[0046] [Positive electrode part] The positive electrode section 20 further comprises an internal p-electrode layer 21 laminated on the p-type contact layer 13 of the light-emitting element layer 10, a reflective layer 22 laminated on the internal p-electrode layer 21, a first bonding layer 23 laminated on the reflective layer 22, a second bonding layer 24 laminated on the first bonding layer 23, a support substrate 25 laminated on the second bonding layer 24, and an external p-electrode 26 laminated on the support substrate 25 and exposed to the outside.

[0047] (Internal p-electrode layer) The internal p-electrode layer 21 is provided to supply current to the light-emitting layer 12 of the light-emitting element layer 10 by diffusing it in the planar direction. The internal p-electrode layer 21 has a light-transmitting layer 211 with a plurality of through holes that penetrate in the thickness direction, and a plurality of columnar p-electrodes 212 provided to fill each of these through holes.

[0048] [Transparent layer] The light-transmitting layer 211 is insulating and transmits light emitted from the light-emitting layer 12 in the light-emitting layer 10. The light-transmitting layer 211 can be made of SiO2 or the like.

[0049] [Columnar p electrode] The columnar p-electrode 212 is conductive and makes ohmic contact with the p-type contact layer 13 of the light-emitting element layer 10. A material such as an Au alloy can be used for the columnar p-electrode 212.

[0050] (reflective layer) The reflective layer 22 is conductive and reflects the light emitted from the light-emitting layer 12 in the light-emitting layer 10. The reflective layer 22 can be made of a metal such as Au or an alloy.

[0051] (1st bonding layer) The first bonding layer 23 is conductive and is provided to bond the reflective layer 22 formed on the light-emitting layer 10 to the second bonding layer 24 formed on the support substrate 25. A chemically stable, low-melting-point Au-based eutectic metal or the like can be used for the first bonding layer 23.

[0052] (Second bonding layer) The second bonding layer 24 is conductive and is provided to bond the first bonding layer 23 to the support substrate 25. A chemically stable, low-melting-point Au-based eutectic metal or the like can be used for the second bonding layer 24.

[0053] (Support base) The support substrate 25 is conductive and is provided to physically support the light-emitting layer 10 obtained by removing the growth substrate 100 from the semiconductor layer formation substrate 1. In this example, a reflective layer 22 is provided between the light-emitting layer 10 (light-emitting layer 12) and the support substrate 25, so a material that absorbs light emitted from the light-emitting layer 12 can also be used as the support substrate 25. Furthermore, Ge wafers, Si wafers, GaAs wafers, GaP wafers, etc., can be used for the support substrate 25.

[0054] (external p electrode) The external p-electrode 26 is conductive and is provided for electrical connection to external wiring (not shown). Various metal materials can be used for the external p-electrode 26; for example, an Au alloy can be used. The external p-electrode 26 can also be constructed by laminating multiple metal layers.

[0055] [Negative electrode part] Various metals can be used for the negative electrode portion 30, and it can also be configured by laminating multiple metal layers.

[0056] <Manufacturing method for semiconductor light-emitting elements> Next, the manufacturing method of the semiconductor light-emitting element 2 shown in Figure 4 will be explained with specific examples. Figure 5 is a flowchart illustrating the manufacturing method of the semiconductor light-emitting element 2.

[0057] (Internal p-electrode layer formation process) First, an internal p-electrode layer 21 is formed on the p-type contact layer 13 of the light-emitting element layer 10 of the semiconductor layer formation substrate 1 (see Figure 1) (step 1111). However, in the internal p-electrode layer formation process of step 1111, a light-transmitting layer 211 is formed first (step 1111a), followed by the formation of a columnar p-electrode 212 (step 1111b).

[0058] (Transparent layer formation process) In step 1111a, the translucent layer formation process, SiO2 is deposited over the entire surface of the p-type contact layer 13 by the CVD (Chemical Vapor Deposition) method. Then, holes are drilled by etching in the areas where the columnar p-electrode 212 is to be formed, creating multiple through-holes. This results in a translucent layer 211 made of SiO2.

[0059] (Columnar p-electrode formation process) In step 1111b, the columnar p-electrode formation step, Au alloy is filled into each of the multiple through-holes formed in the translucent layer 211 by vapor deposition to form multiple columnar p-electrodes 212. As a result, an internal p-electrode layer 21 including the translucent layer 211 and multiple columnar p-electrodes 212 is obtained.

[0060] (Reflection layer formation process) Next, Au is deposited onto the internal p electrode layer 21 by vapor deposition to form a reflective layer 22 (step 1112).

[0061] (First bonding layer formation step) Next, an Au alloy is deposited onto the reflective layer 22 by vapor deposition to form the first bonding layer 23 (step 1113). At this point, the p-type contact layer 13 of the light-emitting element layer 10 of the semiconductor layer-forming substrate 1 has the internal p-electrode layer 21, the reflective layer 22, and the first bonding layer 23 laminated on it. Hereinafter, the semiconductor layer-forming substrate 1 with the internal p-electrode layer 21 to the first bonding layer 23 laminated on it will be referred to as the "first laminate".

[0062] (Second bonding layer formation process) In addition, a support substrate 25 made of a Si wafer is prepared separately from the first laminate described above. Then, an Au alloy is deposited on one side (surface) of this support substrate 25 by vapor deposition to form a second bonding layer 24 (step 1114). At this point, the second bonding layer 24 is deposited on the surface of the support substrate 25. The support substrate 25 with the second bonding layer 24 deposited on it is referred to as the "second laminate".

[0063] (Substrate bonding process) Subsequently, the first and second laminates are joined by heating and pressurizing while the first bonding layer 23 in the first laminate and the second bonding layer 24 in the second laminate are facing and in contact with each other (step 1115). At this point, the semiconductor layer-forming substrate 1 and the internal p-electrode layer 21 to the support substrate 25 are laminated together. Hereinafter, the laminated semiconductor layer-forming substrate 1 and the internal p-electrode layer 21 to the support substrate 25 will be referred to as the "third laminate".

[0064] (Growth substrate removal process) Next, wet etching is performed on the third laminate to separate the growth substrate 100 and the buffer layer 101 in the semiconductor layer formation substrate 1 from the light-emitting element layer 10 (step 1116).

[0065] (Etching stop layer removal process) Then, after removing the growth substrate 100 and the buffer layer 101, the etching stop layer 102 is etched and removed (step 1117). This removes the growth substrate 100, the buffer layer 101, and the etching stop layer 102 from the third laminate. At this point, the light-emitting element layer 10 and the internal p-electrode layer 21 to the support substrate 25 are stacked, and the n-type contact layer 11 of the light-emitting element layer 10 is exposed to the outside. Hereafter, the stacked form of the light-emitting element layer 10 and the internal p-electrode layer 21 to the support substrate 25 will be referred to as the "fourth laminate".

[0066] (Negative electrode part formation process) Next, a plurality of negative electrode portions 30 are formed on the n-type contact layer 11 of the light-emitting element layer 10 in the fourth laminate (step 1118). In this example, an Au alloy is deposited on the n-type contact layer 11 by vapor deposition to obtain the negative electrode portions 30. At this point, in the fourth laminate, which is formed by laminating the light-emitting element layer 10 and the internal p-electrode layer 21 to the support substrate 25, the plurality of negative electrode portions 30 are arranged in a matrix on the surface of the light-emitting element layer 10 on which the n-type contact layer 11 is formed. Hereinafter, the laminate formed by laminating the light-emitting element layer 10 with the internal p-electrode layer 21 to the support substrate 25 and the plurality of negative electrode portions 30 will be referred to as the "fifth laminate".

[0067] (Light-emitting element layer splitting process) In the light-emitting layer splitting process, grooves for fragmentation are formed in the light-emitting layer 10 of the fifth laminate using an etching method (step 1119). Here, first, photoresist is applied to the entire upper surface of the light-emitting layer 10 on which multiple negative electrode portions 30 are formed, and the photoresist present in the area where grooves are to be formed is removed by photolithography. As a result, a mask is formed on the upper surface of the light-emitting layer 10 such that each negative electrode portion 30 is covered with photoresist, and the area around each negative electrode portion 30 is exposed in a rectangular (approximately square) shape.

[0068] Next, etching (wet etching) is performed on the upper surface of the light-emitting layer 10, which has a mask made of photoresist. At this time, the etchant enters from the parts of the upper surface of the light-emitting layer 10 that are exposed because they are not covered by the mask, causing the light-emitting layer 10 to be eroded in the depth direction and forming grooves. Here, an etchant that erodes the light-emitting layer 10 but not the positive electrode portion 20 is used, so that the internal p-electrode layer 21 located at the boundary between the light-emitting layer 10 and the positive electrode portion 20 functions as an etching stop layer, and the positive electrode portion 20 maintains its original state (shape). Therefore, the grooves do not penetrate the fifth laminate and are formed only on the side of the light-emitting layer 10.

[0069] Next, the photoresist mask is removed using a release agent. As a result, multiple grooves are formed in the fifth laminate, which comprises the light-emitting element layer 10, the positive electrode portion 20, and the multiple negative electrode portions 30, in the light-emitting element layer 10. At this time, in the fifth laminate, one negative electrode portion 30 is placed for each of the divided light-emitting element layers 10.

[0070] (External electrode layer formation process) Next, an Au alloy is deposited onto the other side (back surface) of the support substrate 27 by vapor deposition to form an external p electrode 26 (step 1121).

[0071] (Support board division process) Finally, wet etching and laser irradiation are performed to divide the positive electrode portion 20 along the groove formed in step 1119, thereby dividing it into multiple semiconductor light-emitting elements 2 (step 1122). In this division process, each semiconductor light-emitting element 2 is separated into individual pieces so that each piece contains one negative electrode portion 30. As a result, a semiconductor light-emitting element 2 is obtained, each having a light-emitting element layer 10, a positive electrode portion 20, and a negative electrode portion 30.

[0072] <Effects> Here, in order to verify the emission wavelength emitted by the barrier layer 1231 created by this embodiment, a verification light-emitting element layer 5 was manufactured and photoluminescence measurements were performed. Figure 6 shows the cross-sectional configuration of the light-emitting element layer 5 used for verification. The light-emitting element layer 5 comprises an LCCL layer 122 laminated on the growth substrate 100, a barrier layer 1231 laminated on the LCCL layer 122, and a UCCL layer 124 as a cup layer laminated on the barrier layer 1231. Here, the LCCL layer 122 and the UCCL layer 124 are made of "InP", and the barrier layer 1231 is made of "InGaAlAs". Here, the LCCL layer 122 was made with a thickness of 0.3 [μm], the barrier layer 1231 with a thickness of 1.2 [μm], and the UCCL layer 124 with a thickness of 0.5 [μm].

[0073] The manufacturing process for this light-emitting layer 5 involves first placing a growth substrate 100 in a chamber, growing an LCCL layer 122 on the growth substrate 100 using the first step described above (see Figure 3), then growing a barrier layer 1231 using the second to fourth steps (see Figure 3), and finally growing an UCCL layer 124 on top of it. The inventors of the present invention prepared three types of samples by varying the time of the third step and performed photoluminescence measurements. For the first sample, the light-emitting layer 5 was created by running the third step for 0 seconds. For the second sample, the light-emitting layer 5 was created by running the third step for 1 second. For the third sample, the light-emitting layer 5 was created by running the third step for 5 seconds. Note that the first sample was created by running the fourth step after the second step without running the third step; in other words, the first sample is a first comparative example created without performing the third step (pre-supply step).

[0074] Next, the results of the photoluminescence measurements for the first to third samples will be explained with reference to Figures 7A to 7C. Figure 7A shows the results of photoluminescence measurements for the first sample. Figure 7B shows the results of photoluminescence measurements for the second sample. Figure 7C shows the results of photoluminescence measurements for the third sample. Figures 7A-C show wavelength [nm] on the horizontal axis and intensity [Volt] on the vertical axis. The wavelength of the primary peak is also shown. Here, the wavelength of the primary peak is the wavelength at which the measured intensity is highest. Furthermore, Figures 7A-C show the full width at half maximum (FWHM) of the primary peak. Here, the FWHM of the primary peak is defined as the wavelength at which the intensity is half of the maximum intensity, with λ1, λ2, ... λ being the wavelengths at which the intensity is half of the maximum intensity. n (n is an integer greater than or equal to 2) and λ1, λ2, ..., λ n The one with the longest wavelength among them is λ max From the shortest wavelength λ mim This is the value obtained by subtracting [a certain value].

[0075] As shown in Figure 7A, the wavelength of the main peak of the first sample is 1121.6 nm. Furthermore, the wavelengths at which the first sample exhibits half of its maximum intensity are 1092.1 nm and 1140.6 nm, and the full width at half maximum of the main peak is 48.5 nm. In Figure 7A, the intensity decreases as the wavelength increases from the main peak wavelength of 1121.6 nm, but the rate of decrease in intensity becomes smaller between wavelengths of 1160 and 1180 nm, and a second peak is formed at wavelength 1182 nm. This second peak is called a subpeak.

[0076] As shown in Figure 7B, the wavelength of the main peak of the second sample is 1119.9 nm. Furthermore, the wavelengths at which the intensity is half of the maximum intensity in the second sample are 1092.0 nm and 1139.2 nm, and the full width at half maximum of the main peak is 47.1. In the second sample, the subpeak that was present at a wavelength of 1182 nm in the first sample has disappeared.

[0077] As shown in Figure 7C, the wavelength of the main peak of the third sample is 1120.9 nm. Furthermore, the wavelengths at which the intensity is half of the maximum intensity in the third sample are 1092.0 nm and 1139.8 nm. The full width at half maximum of the main peak is 47.8 nm. In the third sample, the subpeak that was present at a wavelength of 1182 nm in the first sample has disappeared.

[0078] Thus, in the second and third samples prepared by performing a pre-supply process in which aluminum is supplied first, the subpeaks that were present in the first sample, which was not prepared by the pre-supply process, disappear. In this way, using the semiconductor light-emitting element 2 prepared by performing the pre-supply process suppresses the absorption of light emitted in the well layer 1232 (see Figure 1) by the barrier layer 1231 (see Figure 1), thereby improving the output.

[0079] The duration of the third step (pre-feeding step) is preferably 1 second or more to allow sufficient movement of the aluminum raw material gas. On the other hand, to protect the InP layer, the duration of the pre-feeding step is preferably 5 seconds or less.

[0080] [Verification of the location (layer) where subpeaks occur in the first comparative example (first sample)] To investigate the cause of the subpeaks, the inventors created a fourth sample similar to the first sample, etched the fourth sample to gradually remove parts of the stacked layers, and measured the photoluminescence intensity.

[0081] Figure 8A shows the results of photoluminescence measurements in the fourth sample when the growth substrate 100, LCCL layer 122, barrier layer 1231, and UCCL layer 124 are stacked. Figure 8B shows the results of photoluminescence measurements in the fourth sample when the UCCL layer 124 is removed. Figure 8C shows the results of photoluminescence measurements in the first sample when the UCCL layer 124 and a portion of the barrier layer 1231 are removed. Figure 8D shows the results of photoluminescence measurements in the fourth sample when the UCCL layer 124 and a further portion of the barrier layer 1231 are removed. Figure 8E shows the results of photoluminescence measurements in the fourth sample when the UCCL layer 124 and barrier layer 1231 are removed. In Figures 8A-E, the horizontal axis shows wavelength [nm] and the vertical axis shows intensity [Volt].

[0082] Figure 8A shows that the wavelength of the main peak of the fourth sample is 1120.9 nm. Furthermore, the wavelengths at which the intensity is half of the maximum intensity in the fourth sample are 1092.2 nm and 1140.1 nm, and the full width at half maximum of the main peak is 47.8 nm. In Figure 8A, the intensity decreases as the wavelength increases from the main peak at 1120.9 nm, but the rate of decrease in intensity becomes smaller between 1160 and 1180 nm, and a subpeak appears at 1182.0 nm.

[0083] Figure 8B shows that the wavelength of the main peak of the fourth sample is 1120.9 nm. Furthermore, the wavelengths at which the intensity is half of the maximum intensity in the fourth sample are 1094.4 nm and 1140.8 nm, and the full width at half maximum of the main peak is 46.4 nm. Furthermore, a subpeak is observed at a wavelength of 1182.0 [nm]. As mentioned above, since the UCCL layer 124 has been removed in Figure 8B, it is unlikely that the UCCL layer 124 is the main cause of the subpeak.

[0084] Figure 8C shows the photoluminescence intensity when the barrier layer 1231 is etched away to a thickness of 1.1 [μm], resulting in a barrier layer thickness of 0.1 [μm]. In Figure 8C, the wavelength of the main peak of the fourth sample is 1121.3 [nm]. In the fourth sample, the minimum wavelength at which the intensity is half of the maximum intensity is 1092.5 [nm], and the maximum wavelength is 1200.9 [nm], with a full width at half maximum of 108.4 [nm]. A subpeak is also observed at a wavelength of 1116.0 [nm].

[0085] Figure 8D shows the photoluminescence intensity when the barrier layer 1231 is further scraped away to a thickness of 0.07 [μm], until the thickness of the barrier layer 1231 is 0.03 [μm]. In Figure 8D, the main peak that occurred at a wavelength of 1121.0 ± 0.3 [nm] in Figures 8A-C has disappeared. On the other hand, in Figure 8D, a subpeak has appeared at a wavelength of 1186.0 [nm].

[0086] Figure 8E shows the photoluminescence intensity when the barrier layer 1231 is completely removed. In Figure 8E, the subpeaks that were present in Figure 8D have disappeared. Since the subpeaks disappear when the barrier layer 1231 is completely removed, it is thought that there is a cause for the subpeaks in the barrier layer 1231. Furthermore, since the intensity of the subpeaks remains almost unchanged from the thickness of the barrier layer 1231 from 0.1 [μm] to 0.03 [μm], it is thought that the main cause of the subpeaks is near the interface between the LCCL layer 122 and the barrier layer 1231. In other words, it is thought that a non-uniform layer is formed when the barrier layer 1231 begins to grow on the LCCL layer 122.

[0087] (Verification of the cause of the formation of non-uniform layers in barrier layer 1231) Furthermore, as a second comparative example, the inventors manufactured a verification light-emitting layer 6 in which an aluminum-free InGaAsP layer was used as the barrier layer 1233 instead of the barrier layer 1231 of the light-emitting layer 5 (see Figure 6), and performed photoluminescence measurements. Figure 9 shows the cross-sectional configuration of the light-emitting element layer 6 used for verification. This light-emitting element layer 6 differs from the light-emitting element layer 5 in that the barrier layer 1231 is a barrier layer 1233 that does not contain aluminum.

[0088] Figure 10 shows the results of a photoluminescence measurement performed on the light-emitting element layer 6. As shown in Figure 10, the wavelength of the main peak in the second comparative example is 1184.1 nm. Furthermore, the minimum wavelength at which the intensity is halved in the second comparative example is 1149.8 nm, and the maximum is 1202.9 nm. The full width at half maximum of the main peak is 53.2 nm. Also, in Figure 10, no second peak is present. In the second comparative example, no subpeaks are present, suggesting the formation of a uniform layer.

[0089] Comparing the results shown in Figure 10 and Figure 7A, a subpeak is observed in the light-emitting layer 5, while no subpeak is observed in the light-emitting layer 6. The difference between the light-emitting layer 5 and the light-emitting layer 6 lies in the fact that the barrier layer 1231 of the light-emitting layer 5 contains aluminum, while the barrier layer 1233 of the light-emitting layer 6 does not. Therefore, it is considered that the aluminum contained in the barrier layer 1231 is the cause of the non-uniform layer in the light-emitting layer 5. Furthermore, as mentioned above, it is considered that a non-uniform layer is formed when the barrier layer 1231 begins to grow on the LCCL layer 122. In this embodiment, when manufacturing a light-emitting element using a III-V compound semiconductor having a structure in which a barrier layer 1231 (e.g., an InGaAlAs layer) made of an aluminum-containing III-V compound is laminated on an LCCL layer 122 (e.g., an InP layer) made of an aluminum-free III-V compound, a first step is performed in which raw material gases of each element constituting the LCCL layer 122 are supplied to form the LCCL layer 122. Next, after the LCCL layer 122 is formed, a third step is performed in which aluminum raw material gas is supplied first, with an interval in between. Furthermore, after the third step, a fourth step is performed in which raw material gases of each element constituting the barrier layer 1231 are supplied to form the barrier layer 1231. According to this method for manufacturing a light-emitting element, by supplying aluminum raw material gas, which is less prone to migration on the LCCL layer 122, first in the third step, the concentrations of Ga, In, and Al that reach the surface of the LCCL layer in the fourth step become the same, and a uniform barrier layer 1231 grows. Here, "less prone to migration" means that migration of the Al element is less likely to occur compared to the In and Ga elements of Group III.

[0090] <Other> In this embodiment, a so-called multiple quantum well structure was employed in the active layer 123 of the light-emitting layer 12, but it is not limited to this. For example, a so-called single quantum well structure may be employed, or a simple double heterojunction structure may be employed.

[0091] Furthermore, in this embodiment, a semiconductor light-emitting element 2 including a light-emitting element layer 10 was described as having a reflective layer 22 as an example, but the structure of the semiconductor light-emitting element 2 can be modified as appropriate.

[0092] The present invention will be described in more detail below based on examples. However, the present invention is not limited to the following examples unless it exceeds the gist of the invention. Here, Table 1 shows the main materials of the semiconductor layer formation substrate 1 in Example 1.

[0093] [Table 1]

[0094] <Semiconductor layer formation substrate of Example 1> A wafer made of InP single crystal was used as the growth substrate 100. [luminescent layer] The configuration of the light-emitting element layer 10 is as follows. InP was used for the buffer layer 101. InGaAs was used for the etching stop layer 102. InP was used for the n-type contact layer 11. The structure of the light-emitting layer 12 is as follows: InP was used for the n-type cladding layer 121. InP was used for the LCCL layer 122. The structure of the active layer 123 is as follows: Here, the number of barrier layers 1231 is set to three, and from the bottom they are referred to as the first barrier layer 1231, the second barrier layer 1231, and the third barrier layer 1231. Also, the number of well layers 1232 is set to two, and from the bottom they are referred to as the first well layer 1232 and the second well layer 1232. InGaAlAs was used for the first, second, and third barrier layers 1231. InGaAlAs was used for the first and second well layers 1232. InP was used for the UCCL layer 124. InP was used for the p-type cladding layer 125. InGaAs was used for the p-type contact layer 15. [Explanation of Symbols]

[0095] 1...Semiconductor layer formation substrate, 2...Semiconductor light-emitting element, 5,6,10...Light-emitting element layer, 11...n-type contact layer, 12...Light-emitting layer, 13...p-type contact layer, 20...Positive electrode section, 21...Internal p-electrode layer, 22...Reflection layer, 23...First junction layer, 24...Second junction layer, 25...Support substrate, 26...External p-electrode, 30...Negative electrode section, 100...Growth substrate, 101...Buffer layer, 102...Etching stop layer, 121...n-type cladding layer, 122...LCCL layer, 123...Active layer, 124...UCCL layer, 125...p-type cladding layer, 1231...Barrier layer, 1232...Well layer

Claims

1. A method for manufacturing a light-emitting element made of a III-V compound semiconductor having a structure in which a second layer containing aluminum is laminated on a first layer that does not contain aluminum, A first layer formation step involves supplying raw material gases of each element constituting the first layer to form the first layer, After the first layer is formed, a pre-supply step is performed in which aluminum raw material gas is supplied first, Following the aforementioned supply step, a second layer formation step is performed in which raw material gases of each element constituting the second layer are supplied to form the second layer, A method for manufacturing a light-emitting element having

2. The aforementioned supply process involves supplying aluminum raw material gas for at least one second. A method for manufacturing a light-emitting element according to claim 1, characterized in that

3. The duration of the aforementioned supply process shall be within 5 seconds. A method for manufacturing a light-emitting element according to claim 2, characterized by the above.

4. The aforementioned supply process involves supplying only aluminum as the raw material gas among the elements that constitute the second layer. A method for manufacturing a light-emitting element according to claim 1, characterized in that

5. The second layer formation step involves supplying raw material gases for other elements constituting the second layer while maintaining the supply of aluminum raw material gas in the preceding supply step. A method for manufacturing a light-emitting element according to claim 1, characterized in that

6. The first layer is a carrier confinement layer that confines carrier electrons. A method for manufacturing a light-emitting element according to claim 1, characterized in that

7. The first layer is a layer comprising either In or Ga, and either As or P. A method for manufacturing a light-emitting element according to claim 6, characterized by the above.

8. The first layer is a layer containing In and P. A method for manufacturing a light-emitting element according to claim 7, characterized by the above.

9. The aforementioned second layer is a light-emitting layer. A method for manufacturing a light-emitting element according to claim 1, characterized in that

10. The second layer is a group III-V compound semiconductor containing In, Ga, Al, and As. A method for manufacturing a light-emitting element according to claim 8, characterized by the above.

11. A method for producing a thin film of a group III-V compound semiconductor by epitaxially growing a group III-V compound semiconductor containing multiple group III elements including aluminum and one or more group V elements, A process in which aluminum is supplied as a raw material gas before supplying the raw material gases for each element constituting the III-V compound semiconductor. A method for producing a thin film of a III-V group compound semiconductor having [a specific characteristic].

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