Light-emitting element

Abstract

To provide a light-emitting element that can improve light extraction efficiency while reducing the occurrence of defects in the semiconductor layer. [Solution] The first surface of the first semiconductor layer of the semiconductor structure has an inner region and an outer region that surrounds the inner region when viewed from above. The first protective film is placed in the outer region and not in the inner region. Both the inner and outer regions are rough surfaces, and the arithmetic mean roughness of the outer region is less than the arithmetic mean roughness of the inner region. In cross-sectional view, the side surface of the semiconductor structure is an inclined surface, and in top view, the area of ​​the first surface is larger than the area of ​​the second surface.

Description

Technical Field

[0001] The present disclosure relates to a light-emitting element.

Background Art

[0002] For example, as shown in Patent Document 1, in a light-emitting element, the light extraction efficiency can be improved by roughening the surface of a semiconductor layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present disclosure is to provide a light-emitting element capable of reducing the occurrence of chipping of a semiconductor layer while improving the light extraction efficiency.

Means for Solving the Problems

[0005] According to one aspect of the present disclosure, a light-emitting element includes a first semiconductor layer having a first surface and a second surface located on the opposite side of the first surface, a second semiconductor layer, and an active layer located between the second surface of the first semiconductor layer and the second semiconductor layer, the semiconductor structure having an inner region and an outer region surrounding the inner region in a top view, a first protective layer disposed in the outer region and not disposed in the inner region, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the second semiconductor layer, the inner region and the outer region being rough, the arithmetic mean roughness of the outer region being smaller than the arithmetic mean roughness of the inner region, in a cross-sectional view, a side surface of the semiconductor structure being an inclined surface, and in a top view, an area of the first surface being larger than an area of the second surface.

Effects of the Invention

[0006] According to this disclosure, it is possible to provide a light-emitting element that can improve light extraction efficiency while reducing the occurrence of defects in the semiconductor layer. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view of a light-emitting element according to an embodiment. [Figure 2] This is a schematic top view of a semiconductor structure according to an embodiment. [Figure 3] This is a schematic cross-sectional view of a light-emitting element according to a first modified example of the embodiment. [Figure 4] This is a schematic cross-sectional view of a light-emitting element according to a second modified embodiment. [Figure 5] This is a schematic top view of a semiconductor structure according to a third modified embodiment. [Figure 6] This is a schematic cross-sectional view illustrating one step in the manufacturing method of a light-emitting element according to an embodiment. [Figure 7] This is a schematic cross-sectional view illustrating one step in the manufacturing method of a light-emitting element according to an embodiment. [Figure 8] This is a schematic cross-sectional view illustrating one step in the manufacturing method of a light-emitting element according to an embodiment. [Figure 9] This is a schematic cross-sectional view illustrating one step in the manufacturing method of a light-emitting element according to an embodiment. [Figure 10] This is a schematic cross-sectional view illustrating one step in the manufacturing method of a light-emitting element according to an embodiment. [Figure 11] This is a schematic cross-sectional view illustrating one step in the manufacturing method of a light-emitting element according to an embodiment. [Figure 12] This is a schematic cross-sectional view illustrating one step in the manufacturing method of a light-emitting element according to an embodiment. [Figure 13] This is a schematic cross-sectional view illustrating one step in the manufacturing method of a light-emitting element according to an embodiment. [Figure 14] This is a schematic cross-sectional view illustrating one step in the manufacturing method of a light-emitting element according to an embodiment. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the drawings. The dimensions, materials, shapes, relative arrangements, etc. of the components described in the embodiments are not intended to be limiting unless otherwise specified, but are merely illustrative examples. The size and positional relationships of the members shown in each drawing may be exaggerated for clarity of explanation. In addition, in the following description, the same name and reference numeral indicate the same or identical member, and detailed explanations will be omitted as appropriate. In addition, in some cases, end view diagrams showing only the cut surface will be shown as cross-sectional views.

[0009] In the following description, terms indicating specific directions or positions (e.g., “up,” “down,” and other terms including these) may be used. However, these terms are used merely for clarity to indicate the relative directions or positions in the referenced drawings. If the relative directional or positional relationships expressed by terms such as “up,” “down,” etc., in the referenced drawings are the same, the arrangement in drawings other than those disclosed, actual products, etc., does not have to be the same as in the referenced drawings. In this specification, the positional relationship expressed as “up (or down)” includes, for example, the case where two members are assumed to be in contact with each other, and the case where the two members are not in contact but one member is located above (or below) the other member.

[0010] In the diagrams shown below, directions may be indicated by the X, Y, and Z axes. The X, Y, and Z axes are orthogonal to each other. For example, in this specification, the Z-axis direction is referred to as the first direction Z, the X-axis direction as the second direction X, and the Y-axis direction as the third direction Y.

[0011] As shown in Figure 1, the light-emitting element 1 according to the embodiment comprises a semiconductor structure 50, a first protective layer 41, a first electrode 61, and a second electrode 62.

[0012] <Semiconductor Structure> The semiconductor structure 50 is made of a nitride semiconductor. In this specification, the "nitride semiconductor" refers to, for example, In x Al y Ga 1-x-y It shall include semiconductors of all compositions in which the composition ratios x and y are varied within their respective ranges in the chemical formula N(0≦x≦1, 0≦y≦1, x + y≦1). Also, in the above chemical formula, those further including group V elements other than N (nitrogen), and those further including various elements added to control various physical properties such as conductivity type shall also be included in the "nitride semiconductor".

[0013] The semiconductor structure 50 has a first semiconductor layer 10, a second semiconductor layer 20, and an active layer 30. The active layer 30 is located between the first semiconductor layer 10 and the second semiconductor layer 20 in the first direction Z. The active layer 30 is a light-emitting layer that emits light, and has, for example, a MQW (Multiple Quantum Well) structure including a plurality of barrier layers and a plurality of well layers. The active layer 30 emits light having a peak wavelength of, for example, 210 nm or more and 580 nm or less. For example, the first semiconductor layer 10 has a semiconductor layer containing an n-type impurity, and the second semiconductor layer 20 has a semiconductor layer containing a p-type impurity. The n-type impurity is, for example, Si. The p-type impurity is, for example, Mg.

[0014] In the cross-sectional views such as FIG. 1, the semiconductor structure 50 is not hatched in order to make the boundaries of the respective layers in the semiconductor structure 50 easier to see.

[0015] The first semiconductor layer 10 has a first surface 11 and a second surface 12 located on the opposite side of the first surface 11 in the first direction Z.

[0016] FIG. 2 is a schematic top view of the semiconductor structure 50. The cross-section of the semiconductor structure 50 shown in FIG. 1 is the cross-section along line I-I of FIG. 2. In this specification, "top view" means observing the light-emitting element 1 from the side of the first surface 11. In addition to the directly visible parts, for parts that are not directly visible, the term "top view" may be used to describe as if they can be seen through.

[0017] The first surface 11 of the first semiconductor layer 10 has an inner region 11A and an outer region 11B that surrounds the inner region 11A when viewed from above. The outer region 11B is a region that extends from the outer edge of the first surface 11, for example, from 4 μm to 6 μm, when viewed from above. The width of the inner region 11A when viewed from above (width in the second direction X or width in the third direction Y) is, for example, from 10 μm to 50 μm, preferably from 30 μm to 50 μm. When viewed from above, the area of ​​the inner region 11A is larger than the area of ​​the outer region 11B.

[0018] The inner region 11A and the outer region 11B are rough surfaces, and the arithmetic mean roughness of the outer region 11B is less than the arithmetic mean roughness of the inner region 11A. For example, the arithmetic mean roughness of the inner region 11A is between 0.5 μm and 2 μm, and the arithmetic mean roughness of the outer region 11B is between 0.1 μm and 0.4 μm. The first surface 11 is the main surface from which light emitted by the active layer 30 is extracted. The rough surface of the first surface 11 improves the light extraction efficiency from the first surface 11.

[0019] The second surface 12 of the first semiconductor layer 10 has a first region 12A where the active layer 30 and the second semiconductor layer 20 are not located, and a second region 12B where the active layer 30 and the second semiconductor layer 20 are located. In the first region 12A, a portion of the first semiconductor layer 10 is exposed from the active layer 30 and the second semiconductor layer 20. The active layer 30 is located between the second region 12B of the second surface 12 of the first semiconductor layer 10 and the second semiconductor layer 20. In Figure 2, the outer edges of the first region 12A and the second region 12B of the second surface 12 are represented by dashed lines. In a top view, the area of ​​the first region 12A is smaller than the area of ​​the second region 12B.

[0020] The second semiconductor layer 20 has a third surface 20A located opposite the active layer 30 in the first direction Z. The semiconductor structure 50 has a side surface 50C. The side surface 50C of the semiconductor structure 50 includes the side surface of the first semiconductor layer 10 that connects the outer region 11B of the first surface 11 and the first region 12A of the second surface 12. The side surface 50C of the semiconductor structure 50 also includes the side surface (side surface of the first semiconductor layer 10, side surface of the active layer 30, and side surface of the second semiconductor layer 20) that connects the outer region 11B of the first surface 11 and the third surface 20A of the second semiconductor layer 20.

[0021] As shown in Figure 1, in a cross-sectional view, the side surface 50C of the semiconductor structure 50 is an inclined surface. In this specification, "cross-sectional view" means observing a cross-section through two different side surfaces 50C of the semiconductor structure 50 in the X-axis direction or the Y-axis direction. In the cross-sectional view, the width of the semiconductor structure 50 decreases from the first surface 11 side toward the first region 12A side of the second surface 12 and toward the third surface 20A side of the second semiconductor layer 20. In the cross-sectional view, the semiconductor structure 50 is trapezoidal. As shown in Figure 2, in a top view, the outer edge of the second surface 12 is located inward from the outer edge of the first surface 11. In a top view, the area of ​​the first surface 11 is larger than the area of ​​the second surface 12.

[0022] When the cross-sectional shape of the semiconductor structure 50 is trapezoidal, the angle between the first surface 11 and the side surface 50C in the cross-sectional view becomes acute, and the thickness of the semiconductor structure 50 becomes thinner, especially in the outer region 11B of the first surface 11, which tends to make the semiconductor structure 50 more prone to chipping. If the outer region 11B is roughened, the strength of the outer region 11B decreases compared to when it is not roughened, and chipping of the semiconductor structure 50 becomes even more likely. For this reason, it is conceivable not to roughen the outer region 11B, but in this case, the light extraction efficiency from the outer region 11B decreases.

[0023] According to this embodiment, the outer region 11B is made rough to improve the light extraction efficiency from the outer region 11B, while the arithmetic mean roughness of the outer region 11B is made smaller than the arithmetic mean roughness of the inner region 11A, thereby reducing the occurrence of defects in the outer region 11B of the semiconductor structure 50. For the inner region 11A, which is less prone to defects than the outer region 11B, the light extraction efficiency from the inner region 11A can be improved by making its arithmetic mean roughness larger than the arithmetic mean roughness of the outer region 11B.

[0024] <1st electrode> The first electrode 61 is positioned in the first region 12A of the second surface 12 and is electrically connected to the first semiconductor layer 10.

[0025] <Second electrode> The second electrode 62 is positioned in a region of the second semiconductor layer 20 facing the third surface 20A, and is electrically connected to the second semiconductor layer 20.

[0026] The first electrode 61 and the second electrode 62 can be, for example, a single layer of metal containing Ti, Rh, Au, Pt, Al, Ag, Rh, or Ru, or a laminated structure containing at least two of these metal layers.

[0027] <1st protective layer> The first protective layer 41 is positioned in the outer region 11B of the first surface 11. The first protective layer 41 covers the outer region 11B along its rough surface, and a rough surface is also formed on the upper surface of the first protective layer 41. As the material for the first protective layer 41, at least one insulating material from SiO2, SiON, and SiN can be used. By positioning the first protective layer 41 in the outer region 11B, the occurrence of chipping in the outer region 11B can be further reduced. In addition, the rough surface of the upper surface of the first protective layer 41 improves the efficiency of light extraction from the upper surface of the first protective layer 41.

[0028] The first protective layer 41 is not located in the inner region 11A of the first surface 11. This reduces the absorption of light extracted from the inner region 11A by the first protective layer 41.

[0029] <Second protective layer> The light-emitting element 1 according to the embodiment may further include a second protective layer 42. The second protective layer 42 covers the inner region 11A of the first surface 11 and the first protective layer 41. The second protective layer 42 covers the inner region 11A along the rough surface of the inner region 11A and covers the first protective layer 41 along the rough surface of the upper surface of the first protective layer 41, and a rough surface is also formed on the upper surface of the second protective layer 42. The arithmetic mean roughness of the upper surface of the second protective layer 42 covering the inner region 11A is greater than the arithmetic mean roughness of the upper surface of the second protective layer 42 covering the first protective layer 41. The material of the second protective layer 42 can be the same material as the material of the first protective layer 41. The second protective layer 42 can protect the inner region 11A while further reducing the occurrence of chipping in the outer region 11B.

[0030] <Insulating layer> The light-emitting element 1 according to this embodiment may further include an insulating layer 43. The insulating layer 43 covers the side surface 50C of the semiconductor structure 50. The upper surface 43A of the insulating layer 43, located on the side of the first surface 11, is covered by a first protective layer 41. The materials listed for the first protective layer 41 can be used as the material for the insulating layer 43. The insulating layer 43 can protect the side surface 50C of the semiconductor structure 50.

[0031] Figure 3 is a schematic cross-sectional view of a light-emitting element according to a first modified example of the embodiment. In this example, a portion 41A of the first protective layer 41 is located between the side surface 50C of the semiconductor structure 50 and the insulating layer 43. The first protective layer 41 is continuously arranged on the outer region 11B of the first surface 11 and the side surface 50C. This allows the portion of the semiconductor structure 50 between the outer region 11B and the side surface 50C to be protected by the first protective layer 41, thereby reducing the occurrence of chipping in the portion of the semiconductor structure 50 between the outer region 11B and the side surface 50C.

[0032] In the examples shown in Figures 1 and 3, the first protective layer 41 is placed over the entire outer region 11B. This reduces the occurrence of defects in the outer region 11B of the semiconductor structure 50 compared to when the first protective layer 41 is not placed over the entire outer region 11B.

[0033] In the light-emitting element according to the second modified embodiment shown in Figure 4, the first protective layer 41 is arranged to cover a portion of the outer region 11B. By reducing the portion of the outer region 11B to which the first protective layer 41 is located, light absorption in the outer region 11B can be reduced. To further reduce the occurrence of defects in the outer region 11B of the semiconductor structure 50, it is preferable that the first protective layer 41 covers more than half of the width of the outer region 11B in a cross-sectional view.

[0034] In the outer region 11B, the portion where the first protective layer 41 is not present is located on the inner region 11A side, and the second protective layer 42 covering the inner region 11A also covers the portion in the outer region 11B where the first protective layer 41 is not present. This reduces the occurrence of chipping in the portion of the outer region 11B where the first protective layer 41 is not present.

[0035] Figure 5 is a schematic top view of a semiconductor structure according to a third modified example of the embodiment. The outer region 11B of the first surface 11 has a first portion 11B1 that overlaps with the first region 12A of the second surface 12 in a top view, and a second portion 11B2 that overlaps with the second region 12B of the second surface 12 in a top view. The width of the first portion 11B1 in a top view (width in the second direction X in Figure 5) is greater than the width of the second portion 11B2 in a top view (width in the second direction X in Figure 5).

[0036] As shown in Figure 1, in the semiconductor structure 50, the thickness in the first direction Z of the portion including the first region 12A is thinner than the thickness in the first direction Z of the portion including the second region 12B. Therefore, the strength of the portion including the first region 12A tends to be lower than the strength of the portion including the second region 12B. Consequently, the strength of the first portion 11B1 of the outer region 11B that overlaps with the first region 12A in a top view tends to be lower.

[0037] According to the third modified example shown in Figure 5, by making the width of the first portion 11B1 of the outer region 11B that overlaps with the first region 12A in a top view larger than the width of the second portion 11B2 of the outer region 11B, the occurrence of chipping in the first portion 11B1 of the outer region 11B can be reduced.

[0038] As shown in Figure 1, the light-emitting element 1 according to this embodiment may further include a conductive film 63, a first reflective film 71, a second reflective film 72, a first conductive member 81, and a second conductive member 82.

[0039] <Conductive film> The conductive film 63 is placed on the third surface 20A of the second semiconductor layer 20. The second electrode 62 is placed in contact with the conductive film 63 and is electrically connected to the second semiconductor layer 20 via the conductive film 63. The conductive film 63 has the function of diffusing the current supplied through the second electrode 62 in the planar direction of the second semiconductor layer 20. As the material for the conductive film 63, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO, In2O3, etc. can be used.

[0040] <1st reflective film> The first reflective film 71 covers the surface of the semiconductor structure 50 opposite to the first surface 11 (the first region 12A of the second surface 12 and the third surface 20A of the second semiconductor layer 20). The first reflective film 71 also covers the conductive film 63, the first electrode 61, and the second electrode 62. The first reflective film 71 is reflective to light emitted by the active layer 30. The reflectance of the first reflective film 71 with respect to the peak wavelength of light emitted by the active layer 30 is 60% or more, preferably 70% or more.

[0041] The first reflective film 71 includes, for example, a dielectric multilayer film. The dielectric multilayer film includes, for example, alternatingly stacked SiO2 layers and Nb2O5 layers. Preferably, the first reflective film 71 is a dielectric multilayer film containing, for example, 2 to 6 pairs of Nb2O5 layers with a thickness of 10 nm to 100 nm and SiO2 layers with a thickness of 10 nm to 100 nm. By setting the thickness of each layer and the number of layers stacked in the first reflective film 71 in this way, good light reflectivity can be achieved. For example, the first reflective film 71 can be formed by creating an SiO2 layer with a thickness of 300 nm, and then stacking it on top of this to create a laminated structure containing 3 pairs of Nb2O5 layers with a thickness of 52 nm and SiO2 layers with a thickness of 83 nm. Other materials that can be used for the first reflective film 71 include, for example, TiO2, ZrO2, Al2O3, and AlN.

[0042] <Second reflective film> The second reflective film 72 is positioned in contact with the first reflective film 71. The second reflective film 72 is reflective to light emitted by the active layer 30. The reflectance of the second reflective film 72 with respect to the peak wavelength of light emitted by the active layer 30 is 60% or more, preferably 70% or more. The second reflective film 72 includes, for example, a single layer of Al or Ti, or a stacked structure thereof.

[0043] The insulating layer 43 described above covers the side surface 50C of the semiconductor structure 50, as well as the first reflective film 71 and the second reflective film 72.

[0044] <First conductive component> The first conductive member 81 is in contact with the first electrode 61 and is positioned on the insulating layer 43. The first conductive member 81 is electrically connected to the first electrode 61.

[0045] <Second conductive member> The second conductive member 82 is in contact with the second electrode 62 and is positioned on the insulating layer 43. The second conductive member 82 is electrically connected to the second electrode 62.

[0046] The first conductive member 81 and the second conductive member 82 can be, for example, a single metal layer containing Ti, Rh, or Au, or a laminated structure containing at least two of these metal layers.

[0047] An example of a method for manufacturing the light-emitting element 1 according to the embodiment will be described with reference to Figures 6 to 14.

[0048] As shown in Figure 6, a semiconductor structure 50 can be formed on the growth substrate 101. For example, a first semiconductor layer 10, an active layer 30, and a second semiconductor layer 20 are formed sequentially on the growth substrate 101 by the MOCVD (Metal Organic Chemical Vapor Deposition) method. The first surface 11 of the first semiconductor layer 10 faces the growth substrate 101.

[0049] As the growth substrate 101, an insulating substrate such as sapphire or spinel (MgA12O4) with one of the C-plane, R-plane, or A-plane as the main surface can be used. Alternatively, a conductive substrate such as SiC (including 6H, 4H, and 3C), ZnS, ZnO, GaAs, or Si may be used as the growth substrate 101.

[0050] After forming the semiconductor structure 50 on the growth substrate 101, a conductive film 63 is formed on the second semiconductor layer 20. For example, the conductive film 63 can be formed by sputtering.

[0051] After forming the conductive film 63, a portion of the second semiconductor layer 20 and a portion of the active layer 30 are removed by etching to form a first region 12A on the second surface 12 of the first semiconductor layer 10 opposite the first surface 11. The portion of the second surface 12 of the first semiconductor layer 10 where the active layer 30 and the second semiconductor layer 20 are located becomes the second region 12B.

[0052] After forming the first region 12A and the second region 12B on the second surface 12, the first electrode 61, the second electrode 62, the first reflective film 71, the second reflective film 72, the insulating layer 43, the first conductive member 81, and the second conductive member 82 are formed. The first electrode 61, the second electrode 62, the first reflective film 71, the second reflective film 72, the insulating layer 43, the first conductive member 81, and the second conductive member 82 can be formed, for example, by sputtering or CVD (Chemical Vapor Deposition).

[0053] For example, after forming the first electrode 61, the second electrode 62, and the first reflective film 71, a portion of the second semiconductor layer 20, a portion of the active layer 30, and a portion of the first semiconductor layer 10 are removed by etching to form a groove 90 in the semiconductor structure 50. The groove 90 does not reach the growth substrate 101. A portion of the first semiconductor layer 10 remains between the groove 90 and the first surface 11.

[0054] After forming the groove 90, an insulating layer 43 is formed. The insulating layer 43 covers the first reflective film 71 and the second reflective film 72. The insulating layer 43 also covers the side surface 50C of the semiconductor structure 50 that defines the side surface of the groove 90, and the surface 13 of the first semiconductor layer 10 that defines the bottom surface of the groove 90.

[0055] After the process shown in Figure 6, as shown in Figure 7, the side of the semiconductor structure 50 where the first conductive member 81 and the second conductive member 82 are located is joined to the support substrate 102 via the joining member 200. The joining member 200 covers the first conductive member 81, the second conductive member 82, and the insulating layer 43. The joining member 200 is also placed in the groove 90, and the insulating layer 43 is covered in the groove 90. Note that in Figure 7, the vertical positional relationship between the growth substrate 101 and the semiconductor structure 50 is reversed compared to Figure 6.

[0056] As the support substrate 102, for example, substrates such as sapphire, spinel, SiC, ZnS, ZnO, GaAs, and Si can be used.

[0057] The bonding member 200 is positioned between adjacent semiconductor structures 50 separated by a groove 90, and holds multiple semiconductor structures 50 together. The bonding member 200 is, for example, a resin member containing at least one of the following resins: epoxy resin, acrylic resin, or polyimide resin.

[0058] After bonding the semiconductor structure 50 to the support substrate 102, the growth substrate 101 is removed, exposing the first surface 11 of the first semiconductor layer 10, as shown in Figure 8. The growth substrate 101 can be removed by methods such as laser lift-off, grinding, polishing, or etching.

[0059] When separating the growth substrate 101 and the semiconductor structure 50 by laser lift-off, the laser lift-off can be performed even if the first surface 11 in contact with the growth substrate 101 is not separated in the XY plane by the groove 90. In this case, separation of the growth substrate 101 and the semiconductor structure 50 becomes easier compared to when the first surface 11 is separated in the XY plane. Alternatively, the semiconductor structure 50 may be separated into multiple parts on the growth substrate 101 by forming the groove 90 until it reaches the growth substrate 101. In this case, the step of removing the first semiconductor layer 10 for separating the semiconductor structure 50 into multiple parts, as described later, can be omitted after removing the growth substrate 101.

[0060] After exposing the first surface 11, the first semiconductor layer 10 is removed from the first surface 11 side by methods such as polishing or etching. Examples of polishing methods include CMP (Chemical Mechanical Polishing), and examples of etching methods include RIE (Reactive Ion Etching). The first semiconductor layer 10 is removed so that the first semiconductor layer 10 located above the groove 90 disappears. As a result, the semiconductor structure 50 is separated into multiple parts, as shown in Figure 9.

[0061] Furthermore, between adjacent semiconductor structures 50, the upper surface 200A of the bonding member 200 and the upper surface 43A of the end portion on the first surface 11 side of the insulating layer 43, which is located on the side surface 50C of the semiconductor structure 50, are exposed.

[0062] After the process shown in Figure 9, the first surface 11 is subjected to a first roughening treatment as shown in Figure 10. For example, the first surface 11 can be roughened by dry etching with a chlorine-containing gas or by wet etching using an alkaline solution such as TMAH (Tetramethylammonium hydroxide). In the first roughening treatment, for example, the first surface 11 can be roughened by the above dry etching or wet etching without covering the upper surface 43A of the insulating layer 43 and the upper surface 200A of the bonding member 200 with a mask. In the first roughening treatment, the entire surface of the first surface 11 exposed from the insulating layer 43 and the bonding member 200 is roughened. Note that the same name is used for the first surface 11 before and after roughening.

[0063] After the first roughening treatment, a first protective layer 41 is formed on the outer region 11B of the first surface 11, as shown in Figure 11. The first protective layer 41 can be formed, for example, by sputtering. The first protective layer 41 covers the outer region 11B that was roughened in the first roughening treatment. For example, the first protective layer 41 continuously covers the outer region 11B of adjacent semiconductor structures 50, the upper surface 43A of the insulating layer 43 located between adjacent semiconductor structures 50, and the upper surface 200A of the bonding member 200. The inner region 11A of the first surface 11 is exposed from the first protective layer 41.

[0064] After forming the first protective layer 41, the inner region 11A is subjected to a second roughening treatment, which is an additional roughening treatment. In the second roughening treatment, the outer region 11B covered by the first protective layer 41 is not roughened. By performing the second roughening treatment in addition to the first roughening treatment on the inner region 11A, the arithmetic mean roughness of the inner region 11A can be made greater than the arithmetic mean roughness of the outer region 11B, which is subjected only to the first roughening treatment, as shown in Figure 12.

[0065] In the second roughening treatment, the inner region 11A can be roughened by etching using the same type of gas or solution as in the first roughening treatment. It is preferable to use different conditions for the second roughening treatment than for the first roughening treatment. For example, the time for the second roughening treatment may be longer than that for the first roughening treatment. The temperature for the second roughening treatment may be higher than that for the first roughening treatment. The concentration of the gas or solution for the second roughening treatment may be higher than that for the second roughening treatment. Two or more combinations of these relationships between time, temperature, and concentration may be used. By using such conditions for the second roughening treatment, it is easier to make the arithmetic mean roughness of the inner region 11A greater than that of the outer region 11B.

[0066] After the second roughening treatment of the inner region 11A, a second protective layer 42 is formed to cover the inner region 11A and the first protective layer 41, as shown in Figure 13. The second protective layer 42 can be formed, for example, by sputtering.

[0067] After the step of forming the second protective layer 42, the bonding member 200 between adjacent semiconductor structures 50 is removed. For example, the second protective layer 42 and the first protective layer 41 on the upper surface 200A of the bonding member 200 can be removed by dry etching using a fluorine-containing gas, for example, by etching with a resist film as a mask. After this, the bonding member 200 can be removed by dry etching using an oxygen-containing gas, for example. The resist film can also be removed along with the bonding member 200.

[0068] The bonding members 200 located between adjacent semiconductor structures 50 are removed until the upper surface of the support substrate 102 is exposed, as shown in Figure 14. The bonding members 200 between the semiconductor structures 50 and the support substrate 102 remain. This results in a plurality of light-emitting elements 1 that are supported on the support substrate 102 via the bonding members 200 and are separated from each other.

[0069] Subsequently, for example, by irradiating the bonding member 200 from the support substrate 102 side with laser light, the bonding member 200 positioned between the semiconductor structure 50 and the support substrate 102 can be removed, separating the light-emitting element 1 from the support substrate 102. The second protective layer 42 of the light-emitting element 1, separated from the support substrate 102, is bonded to an adhesive sheet, for example. The light-emitting element 1 may be separated from the support substrate 102 after being bonded to the adhesive sheet. The first conductive member 81 and the second conductive member 82 of the light-emitting element 1, separated from the support substrate 102, function as external connection terminals that are bonded to a wiring board.

[0070] Embodiments of this disclosure may include the following light-emitting elements.

[0071] [Section 1] A semiconductor structure comprising: a first semiconductor layer having a first surface and a second surface located opposite the first surface; a second semiconductor layer; and an active layer located between the second surface of the first semiconductor layer and the second semiconductor layer, wherein the first surface has an inner region and an outer region surrounding the inner region in a top view, A first protective layer is provided in the outer region but not in the inner region, A first electrode electrically connected to the first semiconductor layer, A second electrode electrically connected to the second semiconductor layer, Equipped with, The inner region and the outer region are rough surfaces, and the arithmetic mean roughness of the outer region is less than the arithmetic mean roughness of the inner region. In cross-sectional view, the side surface of the semiconductor structure is an inclined surface. A light-emitting element in which, when viewed from above, the area of ​​the first surface is larger than the area of ​​the second surface. [Section 2] The semiconductor structure further comprises an insulating layer covering the side surface, The light-emitting element according to item 1, wherein a portion of the first protective layer is located between the side surface of the semiconductor structure and the insulating layer. [Section 3] The light-emitting element according to claim 1 or 2, further comprising a second protective layer covering the inner region and the first protective layer. [Section 4] The first protective layer is arranged to cover a portion of the outer region, The light-emitting element according to claim 3, wherein the second protective layer covers the portion of the outer region where the first protective layer is not disposed. [Section 5] The light-emitting element according to item 4, wherein the first protective layer covers more than half of the width of the outer region in a cross-sectional view. [Section 6] The second surface has a first region where the active layer and the second semiconductor layer are not disposed, and a second region where the active layer and the second semiconductor layer are disposed. The first electrode is positioned in the first region, The outer region has a first portion that overlaps with the first region in a top view, and a second portion that overlaps with the second region in a top view. A light-emitting element according to any one of claims 1 to 5, wherein the width of the first portion in a top view is greater than the width of the second portion in a top view. [Section 7] The arithmetic mean roughness of the aforementioned inner region is 0.5 μm or more and 2 μm or less. The light-emitting element according to any one of items 1 to 6, wherein the arithmetic mean roughness of the outer region is 0.1 μm or more and 0.4 μm or less.

[0072] The embodiments of this disclosure have been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. All forms that a person skilled in the art can implement by appropriately modifying the design based on the embodiments described above in this disclosure also fall within the scope of this disclosure, insofar as they encompass the gist of this disclosure. Furthermore, within the scope of the idea of ​​this disclosure, a person skilled in the art can conceive of various modifications and variations, and these modifications and variations also fall within the scope of this disclosure. [Explanation of symbols]

[0073] 1...Light-emitting element, 10...First semiconductor layer, 11...First surface, 11A...Inner region, 11B...Outer region, 11B1...First part, 11B2...Second part, 12...Second surface, 12A...First region, 12B...Second region, 20...Second semiconductor layer, 20A...Third surface, 30...Active layer, 41...First protective layer, 42...Second protective layer, 43...Insulating layer, 50...Semiconductor structure, 50C...Side surface, 61...First electrode, 62...Second electrode, 63...Conductive film, 71...First reflective film, 72...Second reflective film, 81...First conductive member, 82...Second conductive member, 101...Growth substrate, 102...Support substrate, 200...Bonding member

Claims

1. A semiconductor structure comprising: a first semiconductor layer having a first surface and a second surface located opposite the first surface; a second semiconductor layer; and an active layer located between the second surface of the first semiconductor layer and the second semiconductor layer, wherein the first surface has an inner region and an outer region surrounding the inner region in a top view, A first protective layer is provided in the outer region but not in the inner region, A first electrode electrically connected to the first semiconductor layer, A second electrode electrically connected to the second semiconductor layer, Equipped with, The inner region and the outer region are rough surfaces, and the arithmetic mean roughness of the outer region is less than the arithmetic mean roughness of the inner region. In a cross-sectional view, the side surface of the semiconductor structure is an inclined surface. A light-emitting element in which, when viewed from above, the area of ​​the first surface is larger than the area of ​​the second surface.

2. The semiconductor structure further comprises an insulating layer covering the side surface, The light-emitting element according to claim 1, wherein a portion of the first protective layer is located between the side surface of the semiconductor structure and the insulating layer.

3. The light-emitting element according to claim 1 or 2, further comprising a second protective layer covering the inner region and the first protective layer.

4. The first protective layer is arranged to cover a portion of the outer region, The light-emitting element according to claim 3, wherein the second protective layer covers the portion of the outer region where the first protective layer is not disposed.

5. The light-emitting element according to claim 4, wherein the first protective layer covers more than half of the width of the outer region in a cross-sectional view.

6. The second surface has a first region where the active layer and the second semiconductor layer are not disposed, and a second region where the active layer and the second semiconductor layer are disposed. The first electrode is positioned in the first region, The outer region has a first portion that overlaps with the first region in a top view, and a second portion that overlaps with the second region in a top view. The light-emitting element according to claim 1 or 2, wherein the width of the first portion in a top view is greater than the width of the second portion in a top view.

7. The arithmetic mean roughness of the aforementioned inner region is 0.5 μm or more and 2 μm or less. The light-emitting element according to claim 1 or 2, wherein the arithmetic mean roughness of the outer region is 0.1 μm or more and 0.4 μm or less.

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