Power supply device

Abstract

The present invention provides a power supply that can operate in both normal operation mode and sleep mode, and that does not cause a deviation from the expected value in the error voltage when the sleep mode is released. [Solution] The system includes an error amplifier 11 that receives a feedback voltage and a reference voltage as input and outputs an error signal; a phase compensation circuit 20 consisting of a phase compensation resistor 21 and a phase compensation capacitor 22 connected in series therewith, which compensates the phase of the error signal of the error amplifier 11 and generates an error voltage VC; a current source I1 that is activated when the output of the error amplifier 11 is inverted and charges the phase compensation capacitor of the phase compensation circuit 20; a switch 32 with one end connected to the connection node of the phase compensation resistor 21 and the phase compensation capacitor 22 and the other end connected to the current source I1; and a latch circuit 40 that turns on the switch 32 when operating in sleep mode and turns off the switch 32 when the error voltage VC reaches a predetermined level after the sleep mode is released.

Description

Technical Field

[0001] The present invention relates to a power supply device provided with a phase compensation circuit, and particularly to a technique effective when applied to a device that operates in two modes: a normal operation mode and a sleep mode.

Background Art

[0002] As a power supply device, for example, there was one shown in FIG. 8. This figure shows a circuit diagram of a DC / DC converter 100 having a sleep mode. Note that the sleep mode may sometimes be called a standby mode or a power saving mode. This DC / DC converter 100 includes a phase compensation circuit 120 that compensates for the phase of an error signal output by an error amplifier 110. The phase compensation circuit 120 includes a phase compensation resistor 121 and a phase compensation capacitor 122 connected in series thereto. During the sleep mode, the bias of the error amplifier 110, the oscillation circuit 130, the PWM comparator 140, and the gate driver 150 is stopped by the input of the sleep signal XSLP.

[0003] Such a DC / DC converter 100 is determined according to the comparison result between the error voltage VC input to the PWM comparator 140 and the RAMP voltage. Therefore, after the release of the sleep mode, the on-duty of the DC / DC converter 100 becomes unstable until the activation of the error amplifier 110 is completed. To prevent this, bias means 123 is required so that the error voltage VC becomes an appropriate value when the sleep mode is released. As a DC / DC converter having such bias means 123, there was one shown in Patent Document 1.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The biasing means 123 must be capable of charging the phase compensation capacitor 122 to an appropriate potential corresponding to the amplifier output when the sleep mode is released. Otherwise, the voltage VC input to the PWM comparator 140 when the sleep mode is released will deviate from the expected value. One objective of the present invention is to resolve this problem and prevent deviation from the expected value in the error voltage when the sleep mode is released. [Means for solving the problem]

[0006] To solve the above problems, a power supply device according to one embodiment is a power supply device that can operate in a normal operation mode and a sleep mode, and comprises: an error amplifier that receives a feedback voltage and a reference voltage as input and outputs an error signal; a phase compensation circuit consisting of a phase compensation resistor and a phase compensation capacitor connected in series therewith, which compensates the phase of the error signal of the error amplifier and generates an error voltage; a current source that is activated when the output of the error amplifier is inverted and charges the phase compensation capacitor of the phase compensation circuit; a switch with one end connected to the connection node of the phase compensation resistor and the phase compensation capacitor and the other end connected to the current source; and a latch circuit that turns on the switch when operating in the sleep mode and turns off the switch when the error voltage reaches a predetermined level after the sleep mode is released.

[0007] The error amplifier may be a transconductance amplifier, and the current source may include a transistor that uses a current mirror to control the current flowing to the transistor receiving the reference voltage input.

[0008] Furthermore, the power supply unit may be a DC / DC converter and include a PWM comparator that compares the error voltage with the RAMP voltage, a gate driver driven by the PWM signal output from the PWM comparator, and an output circuit driven by the output signal of the gate driver. After the sleep mode is released, the latch circuit may change state based on the PWM signal or the output signal of the gate driver, thereby turning off the switch.

[0009] Furthermore, the power supply unit may be an LDO and include a power transistor driven based on the error voltage and a limit circuit that detects when the error voltage falls below a lower threshold. The phase compensation circuit is positioned between the output of the error amplifier and the gate of the power transistor. After the sleep mode is released, the latch circuit may change state based on the output signal of the limit circuit, thereby turning off the switch. [Effects of the Invention]

[0010] According to one embodiment of the present invention, when the error amplifier wakes from sleep mode, the phase compensation capacitor starts charging due to the potential difference at the input of the error amplifier. Therefore, the timing of the start of charging is automatically controlled, and the startup speed can be adjusted according to the potential difference at the input of the error amplifier. This prevents deviations from the expected value when the sleep mode is woken, enabling stable operation. [Brief explanation of the drawing]

[0011] [Figure 1] This is a circuit diagram of the power supply device according to the first embodiment. [Figure 2] This is a circuit diagram of the power supply device according to the second embodiment. [Figure 3] This figure shows the timing chart for the circuit in Figure 2. [Figure 4] This is a circuit diagram of the power supply device according to the third embodiment. [Figure 5] This figure shows the timing chart for the circuit in Figure 4. [Figure 6] This is a circuit diagram of the power supply device according to the fourth embodiment. [Figure 7] This is a diagram showing the timing chart of the circuit in Figure 6. [Figure 8] This is a circuit diagram of a conventional power supply unit. [Modes for carrying out the invention]

[0012] Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 7. In the following embodiments, parts that are identical or equivalent to each other will be described with the same reference numerals.

[0013] (First Embodiment) 〈Circuit Configuration〉 A power supply device according to the first embodiment of the present invention will be described by taking a DC / DC converter as an example. FIG. 1 is a circuit diagram of a DC / DC converter 1 according to the first embodiment, which includes an error amplifier 11, a reference voltage generation circuit 12, an oscillation circuit 13, a PWM comparator 14, a gate driver 15, an output circuit 16, and a phase compensation circuit 20.

[0014] The error amplifier 11 generates an error signal of current according to the difference between the feedback voltage VFB of the output and a predetermined reference voltage VREF supplied from the reference voltage generation circuit 12. This error amplifier 11 may be a transconductance amplifier (gm amplifier), and the feedback voltage VFB is input to the inverting input terminal and the reference voltage VREF is input to the non-inverting input terminal. The reference voltage generation circuit 12 may be, for example, a series circuit of a resistor and a current source, and may generate a specific potential by applying an input voltage VIN.

[0015] The phase compensation circuit 20 has a phase compensation resistor 21 and a phase compensation capacitor 22 connected in series thereto, and is arranged between the connection node of the error amplifier 11 and the PWM comparator 14 and the ground. This compensates the phase of the error signal output by the error amplifier 11 and creates an error voltage VC from the error signal.

[0016] The PWM comparator 14 compares the error voltage VC with the sawtooth RAMP voltage output from the oscillation circuit 13 and outputs a PWM signal. The gate driver 15 includes a plurality of logic gates and drives the switch of the output circuit 16 based on the PWM signal.

[0017] The output circuit 16 generates a switching voltage by flowing a current through an inductor by turning on / off a high-side switch (not shown), smoothes it with an output capacitor, and outputs an output VOUT of a voltage stepped down from the input voltage VIN. This output VOUT is divided by a voltage divider composed of resistors Ra and Rb and input as a feedback voltage VFB to the inverting input terminal of the error amplifier 11.

[0018] On the other hand, one end of a switch 32 is connected to the connection node of the phase compensation resistor 21 and the phase compensation capacitor 22, and the other end of the switch 32 is connected to a current source I1. The current source I1 is activated by the output of the error amplifier, and the switch 32 is controlled to be on / off by a latch circuit 40. The latch circuit 40 may be an RS flip-flop or the like. In this case, the sleep signal XSLP and the sleep release signal XSLPB are input to the reset terminal, and the output signal of the PWM comparator 14 is input to the set terminal. The switch 32, the latch circuit 40, and the current source I1 form a biasing means for the phase compensation capacitor 22. Note that the switch 32 is always off in the normal operation mode.

[0019] <Operation at the time of transition to sleep mode> When the DC / DC converter 1 enters the sleep mode, a sleep signal XSLP is input to the sleep signal input terminal 50. As a result, the biasing of the error amplifier 11, the reference voltage generation circuit 12, the oscillation circuit 13, the PWM comparator 14, and the gate driver 15 is stopped, and all the transistors in the output stages built in these circuits are turned off. At the same time, the switch 31 is turned off, and although the charge of the output capacitor (not shown) built in the output circuit and connected to the output terminal gradually decreases, it is stored as it is, and the feedback voltage VFB is maintained. Also, at the same time, the switch 32 is turned on by the output (latch signal) of the latch circuit. On the other hand, the switch 33 is turned on, and the charge accumulated in the phase compensation capacitor 22 is discharged.

[0020] <Operation at the time of release from sleep mode> To exit sleep mode, the sleep-release signal XSLPB is input to the sleep signal input terminal 50. This restores the suspended biases of the error amplifier 11, reference voltage generation circuit 12, oscillator circuit 13, PWM comparator 14, and gate driver 15, and switches 33 are turned off. The output state of the latch circuit 40 does not change even when the sleep-release signal XSLPB is input, and switches 32 remain on, causing the error amplifier 11 to start up in that state. In conjunction with this startup, the current source I1 is activated, and the current flowing through it directly charges the phase compensation capacitor 22 without going through the phase compensation resistor 21.

[0021] By operating in this manner, the output of the error amplifier 11 can be rapidly increased to a predetermined voltage in synchronization with the operation of the error amplifier 11. Even in sleep mode, the path for charging the phase compensation capacitor 22 via the phase compensation resistor 21 of the output current of the error amplifier 11 is not interrupted, just as in normal operation, so there is no deviation from the expected value of the error voltage VC when the switch 32 is turned off. The timing of turning off the switch 32 is determined by inputting a set signal to the latch circuit 40 upon the first detection of the output of the subsequent PWM comparator, thereby changing its state. After that, the switch 32 is not turned on until sleep mode is entered again.

[0022] When the error amplifier 11 is released from sleep mode, charging of the phase compensation capacitor 22 via the switch 32 is initiated by the potential difference between the reference voltage VREF and the feedback voltage VFB at the input of the error amplifier 11. Therefore, the timing of the start of charging is automatically and appropriately controlled. Furthermore, the phase compensation capacitor 22 can be charged with a current amount corresponding to the potential difference between the reference voltage VREF and the feedback voltage VFB at the input of the error amplifier 11. Therefore, it can be started up slowly when the potential difference between the reference voltage VREF and the feedback voltage VFB is small, and quickly when the potential difference between the reference voltage VREF and the feedback voltage VFB is large. In addition, no distortion occurs in the error voltage VC when the switch 32 is turned off, and stable operation is possible immediately after startup.

[0023] (Second Embodiment) <Circuit Configuration> A power supply device according to a second embodiment of the present invention will be described using a DC / DC converter as an example. Figure 2 is a circuit diagram of the DC / DC converter 1 according to the second embodiment, showing a more detailed circuit configuration than the first embodiment. This figure also includes an error amplifier 11, a reference voltage generation circuit 12, a PWM comparator 14, a gate driver 15, an output circuit 16, and a phase compensation circuit 20. Note that the oscillation circuit is omitted from the illustration.

[0024] The error amplifier 11 is a transconductance amplifier (gm amplifier) ​​with a differential amplifier configuration, to which a feedback voltage VFB is input at the inverting input terminal and a reference voltage VREF is input at the non-inverting input terminal. The feedback voltage VFB changes the current flowing through the inverting input transistor Q1, which is made of an NMOS transistor. This current change is transmitted to a current mirror consisting of PMOS transistors Q3 and Q4, and further to a current mirror consisting of NMOS transistors Q7 and Q8. On the other hand, the reference voltage VREF changes the current flowing through the non-inverting input transistor Q2, which is made of an NMOS transistor, and this current change is transmitted to a current mirror consisting of PMOS transistors Q5 and Q6.

[0025] Therefore, the output of the error amplifier 11 is a push-pull output due to the current pulling between the PMOS transistor Q6 and the NMOS transistor Q8. With this configuration, the error amplifier 11 generates a current error signal corresponding to the difference between the output feedback voltage VFB and a predetermined reference voltage VREF supplied from the reference voltage generation circuit 12. This push-pull output of current charges and discharges the phase compensation capacitor 22 via the phase compensation resistor 21 of the phase compensation circuit 20, creating an error voltage VC. The configuration of the reference voltage generation circuit 12 may be a series circuit of a resistor and a current source, as described in the description of Embodiment 1. In this case, the current source may be formed by a transistor that is current-mirror connected to the transistor that constitutes the tail current source of the error amplifier 11.

[0026] On the other hand, as described in the description of Embodiment 1, in normal operation, switch 32 is off, and the current source I1 created by the current mirror consisting of PMOS transistor Q5 and PMOS transistor Q9 is disconnected from the phase compensation circuit 20. Therefore, in normal operation, the charge accumulated in the phase compensation capacitance is not affected by the current source I1.

[0027] The PWM comparator 14, which receives the error voltage VC at the non-inverting input terminal, outputs the result of comparing it with the RAMP signal input to the inverting input terminal as a PWM signal. Its operation is the same as described in Embodiment 1; when the feedback voltage VFB is lower than the reference voltage VREF, the error voltage VC becomes higher, and the frequency of the PWM signal becomes higher. Conversely, when the feedback voltage VFB is higher than the reference voltage VREF, the error voltage VC becomes lower, and the frequency of the PWM signal becomes lower.

[0028] The gate driver 15 is the same as that described in Embodiment 1, and comprises multiple logic gates that drive the switches of the output circuit 16 based on the PWM signal. An on-time control circuit 15b is provided to control the output period of the logic gates, and the logic circuit 15a is controlled so that the switches of the output circuit 16 can be driven smoothly.

[0029] The output circuit 16 has a push-pull output consisting of a high-side switch 16a and a low-side switch 16b that are totem-pole connected between the input voltage terminal and the ground terminal, with one end of inductor 16c connected to its output node. The other end of inductor 16c is connected to the other end of output capacitor 16d, which has one end grounded, and the connection node between inductor 16c and output capacitor 16d becomes the output VOUT.

[0030] In this embodiment as well, one end of a switch 32 is connected to the connection node between the phase compensation resistor 21 and the phase compensation capacitor 22, and the other end of the switch 32 is connected to a current source I1. The current source I1 is activated by the output of an error amplifier, and the switch 32 is controlled on / off by a latch circuit 40. The latch circuit 40 may be an RS flip-flop or the like, in which case the sleep signal XSLP and the sleep wake signal XSLPB are input to the reset terminal, and the output signal of the PWM comparator 14 is input to the set terminal. These switch 32, latch circuit 40, and current source I1 form a biasing means for the phase compensation capacitor 22. Note that the switch 32 is always off during normal operation mode, except during transient states when transitioning from sleep mode to normal operation mode.

[0031] <Behavior when transitioning to sleep mode> When the DC / DC converter 1 enters sleep mode, a sleep signal XSLP is input to the sleep signal input terminal (not shown). This stops the bias of the error amplifier 11, the reference voltage generation circuit 12, the oscillator circuit (not shown), the PWM comparator 14, and the gate driver 15, and turns off all the transistors in the output stage built into them. At the same time, the output of the latch circuit 40 turns on the switch 32, and the current source I1 is connected to the connection node of the phase compensation resistor 21 and the phase compensation capacitor 22. Alternatively, the bias of the error amplifier 11 may be stopped by stopping the tail current source I2. In this case, a delay may be introduced in stopping the tail current source I2 to allow for the discharge of the phase compensation capacitor 22, which will be described later.

[0032] Furthermore, when switch 31 is simultaneously turned off, the potential of VFB is raised, and the impedance of NMOS transistor Q8 decreases, causing the charge stored in phase compensation capacitor 22 to be drawn out and discharged. Therefore, the element corresponding to switch 33 in the first embodiment is NMOS transistor Q8 in this embodiment. The charge in output capacitor 16d connected to output VOUT decreases little by little but remains stored, and the feedback voltage VFB is maintained.

[0033] <Action when waking from sleep mode> To exit sleep mode, the sleep-release signal XSLPB is input to the sleep signal input terminal (not shown). This restores the suspended biases of the error amplifier 11, reference voltage generation circuit 12, oscillator circuit (not shown), PWM comparator 14, and gate driver 15, and switches 33 are turned off. The output state of the latch circuit 40 does not change even when the sleep-release signal XSLPB is input, and switches 32 remain on, and the error amplifier 11 starts up in that state. In conjunction with this startup, the current source I1, which includes the PMOS transistor Q9, is activated, and the current flowing through it directly charges the phase compensation capacitor 22 without going through the phase compensation resistor 21. Note that the sleep-release signal XSLPB is a signal with a different voltage level than the sleep signal XSLP; typically, if the sleep signal XSLP is a high-level signal, the sleep-release signal XSLPB is a low-level signal.

[0034] By operating in this manner, the output of the error amplifier 11 can be rapidly increased to a predetermined voltage in synchronization with the operation of the error amplifier 11. Even in sleep mode, the path for charging the phase compensation capacitor 22 via the phase compensation resistor 21 of the output current of the error amplifier 11 is not interrupted, just as in normal operation, so the error voltage VC does not deviate from the expected value when the switch 32 is turned off. The timing of turning off the switch 32 is determined by changing the state of the latch circuit 40 back to the set state upon the first detection of the output of the subsequent PWM comparator. After that, the switch 32 is not turned on until sleep mode is entered again.

[0035] When the error amplifier 11 is released from sleep mode, charging of the phase compensation capacitor 22 via the switch 32 is initiated by the potential difference between the reference voltage VREF and the feedback voltage VFB at the input of the error amplifier 11. Therefore, the timing of the start of charging is automatically and appropriately controlled. Furthermore, the phase compensation capacitor 22 can be charged with a current amount corresponding to the potential difference between the reference voltage VREF and the feedback voltage VFB at the input of the error amplifier 11. Therefore, it can be started up slowly when the potential difference between the reference voltage VREF and the feedback voltage VFB is small, and quickly when the potential difference between the reference voltage VREF and the feedback voltage VFB is large. In addition, no distortion occurs in the error voltage VC when the switch 32 is turned off, and stable operation is possible immediately after startup.

[0036] Figure 3 is a timing chart showing the operation of the DC / DC converter 1 shown in Figure 2. As shown at the bottom of this figure, the left and right sides show the sleep mode (indicated as AMP STANDBY), and the center shows the normal operation mode. Of particular interest in this timing chart are the changes in the voltage levels of the feedback voltage VFB, the reference voltage VREF, the RAMP voltage, and the error voltage VC.

[0037] First, looking at the changes in the voltage levels of the feedback voltage VFB and the reference voltage VREF, when the sleep-release signal XSLPB is applied, switch 31 is turned on and one end of resistor Rb is grounded, causing the voltage level of the feedback voltage VFB to decrease. Conversely, as the bias of the error amplifier 11 is restored, the voltage level of the reference voltage VREF rises and eventually becomes the same as the voltage level of the feedback voltage VFB, and the potential lines of the two voltages form a crossover point.

[0038] On the other hand, until reaching that crossover point, the voltage level of the feedback voltage VFB is higher than the voltage level of the reference voltage VREF, so the phase compensation capacitor 22 by the error amplifier 11 is not charged, and instead remains in a discharged state, so the error voltage VC is at its lowest level. The RAMP voltage also gradually decreases from the level that was stuck at VOUT, and reaches its lowest level at the aforementioned crossover point.

[0039] Until the crossover point is reached, the output circuit 16 of the DC / DC converter 1 does not operate, so the charge accumulated in the output capacitor 16d is consumed by the divider resistors Ra and Rb, causing the potential level of VOUT to continue to drop, and the feedback voltage VFB also continues to drop accordingly. At the crossover point, the output of the error amplifier finally inverts, causing the error voltage VC to rise, activating the current source I1 including transistor Q9, and initiating rapid charging of the phase compensation capacitor 22 through the switched-on switch 32. Eventually, the error voltage VC becomes equal to the RAMP voltage, and a pulse appears at the output of the PWM comparator 14.

[0040] The latch circuit 40, which had already received the sleep-deactivation signal XSLPB as a reset signal, recognizes the rising edge of this pulse as a set signal, changes its state, and turns off switch 32. This ends the rapid charging of the phase-compensated capacitor 22, and the system enters normal operating mode after the VOUT level rises.

[0041] In this embodiment, with this configuration, most of the biasing means for the phase compensation capacitance can be covered by a part of the error amplifier. This reduces the circuit size and enables highly accurate control.

[0042] (Third embodiment) <Circuit Configuration> A power supply device according to the third embodiment of the present invention will be described using a DC / DC converter as an example. Figure 4 is a circuit diagram of the DC / DC converter 1 according to the third embodiment, showing a modified version of the circuit configuration of the second embodiment. The circuit configuration in this figure is the same as that of the second embodiment, but the input path of the set signal to the latch circuit is different.

[0043] Figure 5 is a timing chart showing the operation of the DC / DC converter 1 shown in Figure 4. In the circuit configuration of the second embodiment, the set signal to the latch circuit 40 was input from the output signal of the PWM comparator 14. In this embodiment, the set signal to the latch circuit 40 is input from the high-side control signal HSICB of the gate driver 15. Therefore, the latch release signal from the latch circuit 40 to the switch 31 is applied with a slight delay compared to the second embodiment, and the phase compensation capacitor 22 is charged for a slightly longer period than in the second embodiment. The output from which the set signal input to the latch circuit 40 is performed should be appropriately selected based on the settings of circuit constants and other circumstances.

[0044] (Fourth Embodiment) <Circuit Configuration> A power supply device according to the fourth embodiment of the present invention will be described using an LDO as an example. Figure 6 is a circuit diagram of an LDO2 according to the fourth embodiment, which includes an error amplifier 11a and a power transistor Q16 that operates in response to its voltage output. In this circuit, part of the phase compensation circuit and the biasing means for the phase compensation capacitance are formed inside the error amplifier 11a, while the other part of the biasing means, the reference voltage generation circuit 12, the output circuit including the power transistor Q16, and the divider resistor for creating the feedback voltage are formed outside the error amplifier 11a.

[0045] The error amplifier 11a is a differential amplifier, with a reference voltage VREF input to the inverting input terminal and a feedback voltage VFB input to the non-inverting input terminal. The feedback voltage VFB changes the current flowing through the non-inverting input transistor Q2, which is made of an NMOS transistor, and the reference voltage VREF changes the current flowing through the inverting input transistor Q1, which is also made of an NMOS transistor. The current change in the inverting input transistor Q1 is transmitted to a current mirror consisting of PMOS transistors Q3 and Q4.

[0046] Therefore, the output of the error amplifier 11a becomes a push-pull output due to the current tug-of-war between the PMOS transistor Q4 and the non-inverting input transistor Q2. This output (non-inverting output) is converted into a voltage signal by a phase compensation circuit consisting of phase compensation resistors R1 and R2 and phase compensation capacitors C1 and C2, and is applied to the gate of the PMOS transistor Q15, which, together with the current source I3, constitutes the current amplification stage. The drain output of the PMOS transistor Q15 is applied to the gate of the power transistor Q16 from the connection node with the current source I3.

[0047] The output circuit consists of a power transistor Q16 and an output capacitor C3. One end of the output capacitor C3 is connected to the drain of the power transistor Q16, and the other end is connected to ground potential. Therefore, the source-drain output of the power transistor Q16 is smoothed by the output capacitor C3. In addition, the connection node between the drain of the power transistor Q16 and the output capacitor C3 is connected to one end of a divider resistor consisting of resistors Ra and Rb, and the voltage division of the output VOUT generated at this connection node is applied as a feedback voltage VFB to the non-inverting input terminal of the error amplifier.

[0048] In this embodiment, due to the configuration described above, when the feedback voltage VFB is smaller than the reference voltage VREF, the phase compensation capacitors C1 and C2 are charged, and conversely, when the feedback voltage VFB is larger than the reference voltage VREF, the phase compensation capacitors C1 and C2 are discharged. During the charging phase of the phase compensation capacitors C1 and C2, the impedance of the PMOS transistor Q15 is high and the error voltage VC is lowered, causing the power transistor Q16 to turn on deeply. Conversely, during the discharge phase of the phase compensation capacitors C1 and C2, the power transistor Q16 turns on only slightly. As a result, the VOUT level remains constant, and a stable power supply can be provided to a load (not shown).

[0049] In this embodiment, the biasing means for the phase compensation capacitors consists of current sources I1a, I1b, and I1c, switches S1, S2, and S3, a latch circuit 40, and a limit circuit 60. In normal operation, switches S1, S2, and S3 are off, and the current sources I1a, I1b, and I1c are disconnected from the phase compensation circuit. Therefore, in normal operation, the charge accumulated in the phase compensation capacitors C1 and C2 is not affected by the current sources I1a, I1b, and I1c. Current source I1a is formed by a current mirror consisting of PMOS transistors Q3 and Q10, and current source I1b is formed by a current mirror consisting of PMOS transistors Q3 and Q11. In addition, current source I1c is formed by a current mirror of PMOS transistors Q3 and Q12, and a current mirror of NMOS transistors Q13 and Q14.

[0050] In this embodiment, one end of switch S1 is connected to the connection node between one end of phase compensation resistor R1 and phase compensation capacitor C1, and the other end of switch S1 is connected to current source I1a. Also, one end of switch S2 is connected to the connection node between one end of phase compensation resistor R2 and phase compensation capacitor C2, and the other end of switch S2 is connected to current source I1b. Furthermore, one end of switch S3 is connected to the connection node between the other ends of phase compensation capacitors C1 and C2 and the drain of PMOS transistor Q15, and the other end of switch S3 is connected to current source I1c. Current sources I1a, I1b, and I1c are activated by the inverting output of error amplifier 11a, and switches S1, S2, and S3 are controlled on / off by latch circuit 40. Latch circuit 40 may be an RS flip-flop or the like, in which case the sleep signal XSLP and the sleep release signal XSLPB are input to the reset terminal, and the LIMDET signal output from limit circuit 60 is input to the set terminal. The limit circuit 60 monitors the error voltage VC and applies a high-level signal to the set terminal of the latch circuit 40 when the error voltage VC falls below the lower threshold. To account for minute fluctuations in the error voltage VC, the limit circuit 60 may be given hysteresis characteristics.

[0051] <Behavior when transitioning to sleep mode> When the LDO2 enters sleep mode, the sleep signal XSLP is input to the sleep signal input terminal (not shown). This stops the bias of the error amplifier 11a and the reference voltage generation circuit 12, and all transistors in the output stage built into them are turned off. Alternatively, the bias of the error amplifier 11a may be stopped by stopping the tail current source I2.

[0052] Furthermore, the input of the sleep signal XSLP turns on switches S1, S2, and S3 with the output signal SLAT of the latch circuit 40. As a result, a current source I1a is connected to the connection node between one end of the phase compensation resistor R1 and the phase compensation capacitor C1. Simultaneously, a current source I1b is connected to the connection node between one end of the phase compensation resistor R2 and the phase compensation capacitor C2. Moreover, a current source I1c is connected to the other ends of the respective phase compensation capacitors C1 and C2.

[0053] Furthermore, when switch S4 is simultaneously turned off, the potential of VFB is raised, but in this embodiment, the error voltage VC is maintained at the power supply voltage level. Therefore, the element corresponding to switch 33 in the first embodiment does not exist in this embodiment. The charge of the output capacitor C3 connected to output VOUT decreases little by little but remains stored, and the feedback voltage VFB is maintained.

[0054] <Action when waking from sleep mode> To exit sleep mode, a sleep-release signal XSLPB is input to the sleep signal input terminal (not shown). Here, the sleep-release signal XSLPB is a signal with a different voltage level than the sleep signal XSLP; typically, if the sleep signal XSLP is a high-level signal, the sleep-release signal XSLPB is a low-level signal. This restores the deactivated bias of the error amplifier 11a and the reference voltage generation circuit 12. The output state of the latch circuit 40 does not change even when the sleep-release signal XSLPB is input, switches S1, S2, and S3 remain ON, and the error amplifier 11a starts up in this state. In conjunction with this startup, current sources I1a, I1b, and I1c are activated, and the current flowing through them directly charges the phase compensation capacitors C1 and C2 without going through the phase compensation resistors R1 and R2. While the phase compensation capacitors C1 and C2 are charged by the current sources I1a and I1b, the current biasing by the current source I1c further accelerates the charging of these phase compensation capacitors.

[0055] By operating in this manner, the output of the error amplifier 11a can be rapidly increased to a predetermined voltage in synchronization with the operation of the error amplifier 11a. Even in sleep mode, the path for charging the phase compensation capacitors C1 and C2 via the phase compensation resistors R1 and R2 of the output current of the error amplifier 11a is not interrupted, just as in normal operation. Therefore, there is no deviation from the expected value of the error voltage VC due to the on / off switching of switches S1 and S2. The timing for disconnecting switches S1, S2 and S3 is determined by the detection of the error voltage VC level by the subsequent limit circuit 60. That is, the state of the latch circuit 40 is changed by the LIMDET signal from the limit circuit 60. After that, switches S1, S2 and S3 are not turned on again until sleep mode is entered again.

[0056] When the error amplifier 11 is released from sleep mode, charging of the phase compensation capacitors C1 and C2 via the paths of switches S1, S2, and S3 is initiated by the potential difference between the reference voltage VREF and the feedback voltage VFB input to the error amplifier 11a. Therefore, the timing of the start of charging is automatically and appropriately controlled. Furthermore, the phase compensation capacitors C1 and C2 can be charged with a current amount corresponding to the potential difference between the reference voltage VREF and VFB input to the error amplifier 11. Therefore, it can be started up slowly when the potential difference between the reference voltage VREF and the feedback voltage VFB is small, and quickly when the potential difference between the reference voltage VREF and the feedback voltage VFB is large. In addition, no distortion is generated in the error voltage VC by switching switches S1 and S2 on and off, enabling stable operation immediately after startup.

[0057] Figure 7 is a timing chart showing the operation of the LDO2 shown in Figure 6. As shown at the bottom of this figure, the left and right sides show the sleep mode (indicated as AMP STANDBY), and the center shows the normal operation mode. Of particular interest in this timing chart are the changes in the voltage levels of the feedback voltage VFB, reference voltage VREF, and error voltage VC.

[0058] First, looking at the changes in the voltage levels of the feedback voltage VFB and the reference voltage VREF, when the sleep-release signal XSLPB is applied, switch S4 is turned on and one end of resistor Rb is grounded, causing the voltage level of the feedback voltage VFB to decrease. Conversely, as the bias of the error amplifier 11a is restored, the voltage level of the reference voltage VREF rises and eventually becomes the same as the voltage level of the feedback voltage VFB, and the potential lines of the two voltages form a crossover point.

[0059] On the other hand, up to the crossover point, the voltage level of the feedback voltage VFB is higher than the voltage level of the reference voltage VREF, so the phase compensation capacitors C1 and C2 by the error amplifier 11a are not charged, and the voltage level of the error voltage VC is at the power supply voltage level.

[0060] Up until the crossover point, the output circuit of the LDO2 remains inactive, so the charge accumulated in the output capacitor C3 is consumed by the divider resistors Ra and Rb, causing the potential level of VOUT to continue to drop, and consequently, the feedback voltage VFB also continues to decrease. At the crossover point, the output of the error amplifier finally inverts, activating current sources I1a, I1b, and I1c, and rapid charging of phase compensation capacitors C1 and C2 begins through the switched-on switches S1, S2, and S3. As a result, the error voltage VC begins to decrease, and eventually falls below the lower threshold voltage (shown by the dotted line), causing a pulse to appear at the output LIMDET of the limit circuit 60.

[0061] The latch circuit 40, which had already received the sleep-release signal XSLPB as a reset signal, recognizes the rising edge of this pulse as a set signal, outputs a signal to release the latch, and turns off switches S1, S2, and S3. This ends the rapid charging of phase compensation capacitors C1 and C2, and the system enters normal operating mode after the VOUT level rises.

[0062] In this embodiment, with this configuration, most of the biasing means for the phase compensation capacitance can be covered by a part of the error amplifier. This reduces the circuit size and enables highly accurate control.

[0063] While embodiments of the present invention have been described above, various modifications are possible based on the spirit of the invention. For example, although the present invention was described using a step-down DC / DC converter as an example in the first to third embodiments above, it is also possible to apply the present invention to a step-up DC / DC converter. Similarly, although a shunt LDO was described using a shunt LDO as an example in the fourth embodiment above, it is also possible to apply the present invention to a series LDO.

[0064] Furthermore, in the above embodiment, the current source for charging the phase compensation capacitance is configured to use a current mirror to supply current to the input transistor receiving the reference voltage VREF, and the Miller ratio in this case was not specified. However, it goes without saying that the transistor size can be appropriately changed to obtain a suitable Miller ratio. [Explanation of symbols]

[0065] 1. 100: DC / DC converter 2: LDO 11, 11a, 110: Error amplifier 12, 111: Reference voltage generation circuit 13: Oscillator Circuit 14, 140: PWM comparator 15, 150: Gate Driver 15a: Logic Circuits 15b: On-time control circuit 16, 160: Output circuit 16a: High-side switch 16b: Low-side switch 16c: Inductor 16d: Output capacitor 20, 120: Phase compensation circuit 21, 121, R1, R2: Phase compensation resistors 22, 122, C1, C2: Phase compensation capacitance 23: Biasing Methods 31, 32, 33, S1, S2, S3, S4: Switch 40: Latch Circuit 50, 170: Sleep signal input terminals 60: Limit Circuit

Claims

1. A power supply unit capable of operating in normal operation mode and sleep mode, An error amplifier receives a feedback voltage and a reference voltage as inputs and outputs an error signal, A phase compensation circuit consisting of a phase compensation resistor and a phase compensation capacitor connected in series therewith, which compensates the phase of the error signal of the error amplifier and generates an error voltage, A current source which is activated when the output of the error amplifier is inverted and charges the phase compensation capacitance of the phase compensation circuit, A switch having one end connected to the connection node of the phase compensation resistor and the phase compensation capacitor, and the other end connected to the current source, A power supply device characterized by comprising a latch circuit that turns on the switch when operating in the sleep mode, and turns off the switch when the error voltage reaches a predetermined level after the sleep mode is released.

2. The error amplifier is a transconductance amplifier, The power supply device according to claim 1, characterized in that the current source includes a transistor that uses a current mirror to supply current to a transistor that receives the input of the reference voltage.

3. The aforementioned power supply device is a DC / DC converter, A PWM comparator compares the error voltage and the RAMP voltage, A gate driver driven by the PWM signal output from the PWM comparator, It has an output circuit driven by the output signal of the gate driver, The power supply device according to claim 1 or 2, characterized in that, after the sleep mode is released, the latch circuit changes state in response to the PWM signal or the output signal of the gate driver, and the switch is turned off.

4. The aforementioned power supply unit is an LDO, A power transistor driven based on the aforementioned error voltage, The system includes a limit circuit that detects when the error voltage falls below a lower threshold, The phase compensation circuit is placed between the output of the error amplifier and the gate of the power transistor. The power supply device according to claim 1 or 2, characterized in that, after the sleep mode is released, the latch circuit changes state in response to the output signal of the limit circuit and turns off the switch.

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