Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor with a long lifespan and excellent dielectric properties, regardless of the thickness of the dielectric layer. [Solution] The substrate has alternating layers of dielectric layers containing a perovskite-type compound represented by the general formula ABO3 and internal electrode layers. Between the dielectric layer and the internal electrode layer, there is an intermediate region containing copper. The thickness of the dielectric layer is 1.6 μm or less. The multilayer ceramic capacitor is characterized in that the ratio [a / t] of the copper concentration a (atomic%) in the intermediate region to the thickness t (μm) of the dielectric layer is 0.8 or more and 7.0 or less.

Description

[Technical Field]

[0001] This disclosure relates to multilayer ceramic capacitors. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC) has a structure in which dielectric layers and internal electrode layers are stacked alternately. Multilayer ceramic capacitors are used in various electronic devices such as mobile phones and personal computers.

[0003] In recent years, with the increasing multi-functionality and performance of electronic devices, there has been a demand for smaller and larger capacity multilayer ceramic capacitors. To meet these demands, it is effective to thin the dielectric layer and internal electrode layer and increase the number of layers. However, thinning the dielectric layer can reduce the electric field strength when the capacitor is in use, which can lead to a decrease in insulation reliability.

[0004] Therefore, various studies have been conducted to determine a configuration that can obtain desired characteristics even when the dielectric layer is thinned. One such configuration is known in which a layer containing different elements is formed between the dielectric layer and the internal electrode layer to increase interfacial resistance and improve the insulation reliability of the multilayer ceramic capacitor. For example, Patent Document 1 describes a multilayer ceramic capacitor in which a diffusion phase grain layer is present between the dielectric layer and the internal electrode layer, and it is stated that insulation degradation can be suppressed and the lifetime characteristics can be improved. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2006-319205 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, with conventional multilayer ceramic capacitors, the reliability improvement effect due to enhanced interfacial resistance caused by the addition of dissimilar elements, as described above, was sometimes not fully achieved. For example, when the thickness of the dielectric layer is varied to adjust the capacitance, the ratio of the interface to the dielectric layer also changes, which alters the contribution of enhanced interfacial resistance and sometimes prevents the expected lifetime value from being obtained.

[0007] The purpose of this disclosure is to provide a multilayer ceramic capacitor that has a long lifespan and excellent dielectric properties, regardless of the thickness of the dielectric layer. [Means for solving the problem]

[0008] One aspect of the present disclosure is a multilayer ceramic capacitor having a substrate in which dielectric layers containing a perovskite-type compound represented by the general formula ABO3 and internal electrode layers are alternately stacked, with an intermediate region containing copper between the dielectric layer and the internal electrode layer, the thickness of the dielectric layer being 1.6 μm or less, and the ratio [a / t] of the concentration a (atomic%) of copper in the intermediate region to the thickness t (μm) of the dielectric layer being 0.8 or more and 7.0 or less. [Effects of the Invention]

[0009] According to one aspect of this disclosure, it is possible to provide a multilayer ceramic capacitor that has a long lifespan and excellent dielectric properties, regardless of the thickness of the dielectric layer. [Brief explanation of the drawing]

[0010] [Figure 1] This is a perspective view showing a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 2] This is a cross-sectional view along line AA in Figure 1. [Figure 3] This is a cross-sectional view along line BB in Figure 1. [Figure 4]This graph shows the HALT (Half-Assisted Life) increase rate of a multilayer ceramic capacitor with 1% copper (Cu) in the internal electrode layer 12 compared to a conventional multilayer ceramic capacitor without copper (Cu) added to the internal electrode layer. [Figure 5] This is an enlarged view of region C in Figure 2. [Figure 6] This figure shows an example of the results of TEM-EDX analysis of a multilayer ceramic capacitor. [Figure 7] A flowchart shows a method for manufacturing a multilayer ceramic capacitor according to one embodiment. [Modes for carrying out the invention]

[0011] Embodiments of this disclosure will be described in detail below, but this disclosure is not limited to these embodiments. In this specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals to avoid redundant descriptions. In addition, the drawings show mutually orthogonal X, Y, and Z axes as appropriate. The X, Y, and Z axes define a fixed coordinate system fixed to the multilayer ceramic capacitor. The X, Y, and Z axes can correspond to the length, width, and height of a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component, if its external shape is substantially that of a rectangular parallelepiped.

[0012] [Basic Structure of Multilayer Ceramic Capacitors] Figure 1 is a perspective view showing a multilayer ceramic capacitor 100 according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view along line AA in Figure 1. Figure 3 is a cross-sectional view along line BB in Figure 1.

[0013] As shown in Figures 1 to 3, the multilayer ceramic capacitor 100 comprises a basic body 10 having a roughly rectangular parallelepiped shape. In the basic body 10, two opposing surfaces are referred to as the top surface and the bottom surface, and the four surfaces connecting the top surface and the bottom surface are referred to as the sides. Normally, the surface facing the circuit board when the multilayer ceramic capacitor is mounted on a circuit board is referred to as the bottom surface, but this is not limited to this.

[0014] In the examples shown in FIGS. 1 to 3, a first external electrode 20a and a second external electrode 20b are provided on first and second side surfaces 10a and 10b (see FIG. 2), which are two opposing side surfaces of the base body 10, respectively.

[0015] The first external electrode 20a extends from the first side surface 10a to four surfaces adjacent to the first side surface 10a. The second external electrode 20b extends from the second side surface 10b to four surfaces adjacent to the second side surface 10b. Also, the first external electrode 20a and the second external electrode 20b are spaced apart from each other. The external electrodes may be provided not only on two opposing side surfaces as long as they are on the surface of the base body 10.

[0016] The base body 10 has a structure in which a dielectric layer 11 containing a ceramic material that functions as a dielectric and an internal electrode layer 12 are alternately laminated.

[0017] The internal electrode layer 12 includes a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are alternately laminated. The edge of the first internal electrode layer 12a is drawn out to the surface of the base body 10 where the first external electrode 20a is provided, that is, the first side surface 10a in FIGS. 1 to 3. The edge of the second internal electrode layer 12b is drawn out to the surface of the base body 10 where the second external electrode 20b is provided, that is, the second side surface 10b in FIGS. 1 to 3. Thereby, the first internal electrode layer 12a and the second internal electrode layer 12b are alternately electrically connected to the first external electrode 20a and the second external electrode 20b. Therefore, the multilayer ceramic capacitor 100 has a structure in which a plurality of capacitor units are laminated. Note that the number of layers of the dielectric layer 11 and the number of layers of the internal electrode layer 12 in FIGS. 1 to 3 are merely examples for ease of explanation, and the multilayer ceramic capacitor according to the present embodiment may have a larger number of layers laminated.

[0018] The stacking direction in which the dielectric layer 11 and the internal electrode layer 12 are stacked is the first axis. As shown in Figures 1 to 3, when the first axis, which is the stacking direction, is the direction along the Z axis in a fixed coordinate system (Z-axis direction), the Z axis is the stacking direction in which the dielectric layer 11 and the internal electrode layer 12 are stacked, and the direction in which each internal electrode layer faces the other.

[0019] The axis perpendicular to the first axis, which is the stacking direction, is the second axis. As shown in Figures 1 to 3, when the second axis perpendicular to the first axis, which is the stacking direction, is along the X-axis (X-axis direction), the X-axis is the direction in which the internal electrode layer 12 is drawn out, and is the direction in which the first side surface 10a and the second side surface 10b of the base body 10 face each other, or the direction in which the first external electrode 20a and the second external electrode 20b face each other. In the examples shown in Figures 1 to 3, this electrode drawing direction (X-axis direction) is along the longitudinal direction of the base body 10.

[0020] The axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis is the third axis. As shown in Figures 1 to 3, when the third axis, which is perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis, is in the direction along the Y axis (Y-axis direction), the Y axis is the axis along the direction in which the third side surface 10c and the fourth side surface 10d of the four sides of the base body 10 face each other, and in the example shown in Figures 1 to 3, it is the direction along the width direction of the base body 10.

[0021] The X-axis, Y-axis, and Z-axis directions are mutually orthogonal. The stacking direction is not limited to the Z-axis, but can be any direction. For example, the first axis, which is the stacking direction, may be the X-axis in the X-direction, or the Y-axis in the Y-direction.

[0022] In this specification, while some figures illustrating a specific embodiment may be used to describe a general embodiment, the coordinate system used in one embodiment is interpreted and applied in a general embodiment as a general coordinate system with the stacking direction as the first axis. For example, what is described as the X, Y, and Z axes in Figures 1 to 3, where the stacking direction coincides with the Z direction as a specific embodiment, can be interpreted and applied in a general embodiment as the second, third, and first axes, respectively.

[0023] The region where the first internal electrode layer 12a connected to the first external electrode 20a and the second internal electrode layer 12b connected to the second external electrode 20b face each other is called the capacitance region 14. This capacitance region 14 is the region in the multilayer ceramic capacitor 100 that generates capacitance. In other words, the capacitance region 14 is the region where adjacent internal electrode layers connected to different external electrodes face each other via a dielectric layer.

[0024] In a capacitance section 14 formed by stacking a dielectric layer 11 and an internal electrode layer 12, the outermost part in the stacking direction (Z-axis direction) is composed of the internal electrode layer 12. Furthermore, cover layers 13 may be placed on the outer surfaces of the capacitance section 14 in the stacking direction, i.e., the outer surfaces of the outermost internal electrode layer 12 in the stacking direction.

[0025] The cover layer 13 is a layer containing a ceramic material that functions as a dielectric, and may have the same composition as the dielectric layer 11 or a different composition.

[0026] The configuration of the base body 10 is not limited to those shown in Figures 1 to 3, as long as the first internal electrode layer 12a and the second internal electrode layer 12b are exposed in different regions of the surface of the base body 10 and are conductive to different external electrodes. The different regions of the surface of the base body 10 may be the respective surface regions of opposing faces on the surface of the base body 10, the respective surface regions of adjacent faces, or different surface regions on the same face. The different external electrodes may extend from the surface in which the first internal electrode layer 12a and the second internal electrode layer 12b are exposed to the surface region of the laminate to other surfaces, as long as they are spaced apart from each other. In addition, although not shown in Figures 1 to 3, the base body 10 has a plurality of intermediate regions 40 between the dielectric layer 11 and the internal electrode layer 12 (details will be described later).

[0027] The region where the first internal electrode layers 12a connected to the first external electrode 20a face each other in the stacking direction without passing through the second internal electrode layer 12b connected to the second external electrode 20b is referred to as the first end margin 15a. Similarly, the region where the second internal electrode layers 12b connected to the second external electrode 20b face each other in the stacking direction without passing through the first internal electrode layer 12a connected to the first external electrode 20a is referred to as the second end margin 15b. Each end margin is a region where internal electrode layers connected to the same external electrode face each other in the stacking direction without passing through internal electrode layers connected to different external electrodes. The first end margin 15a and the second end margin 15b are regions where no capacitance is generated.

[0028] As shown in Figure 3, the region adjacent to the outside of the capacitance section 14 in the Y-axis direction is called the side margin 16. The side margin is the outer region adjacent to the capacitance section 14 on the side from which the internal electrode layer 12 is not drawn out. The side margin 16 is a region that does not generate electrical capacitance.

[0029] There are no particular restrictions on the size of the multilayer ceramic capacitor 100, and it can be appropriately selected according to the purpose. For example, it may be 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height; 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height; 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height; 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height; 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height; or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height. However, the sizes listed above for the multilayer ceramic capacitor 100 are merely examples, and multilayer ceramic capacitors are not limited to these sizes.

[0030] The dimensions of the multilayer ceramic capacitor 100 may be, for example, length > width ≥ height, width > length ≥ height, height > length ≥ width, or height > width ≥ length. The ceramic capacitor 100 shown in Figures 1 to 3 has length in the X-axis direction (electrode extraction direction), width in the Y-axis direction, and height in the Z-axis direction (stacking direction).

[0031] (Dielectric layer) The dielectric layer 11 contains a compound having a perovskite structure represented by the general formula ABO3 (also called a perovskite-type compound) as its main component. In this specification, "containing a specified component as a main component" means that the specified component is present in the largest amount of substance among the contained components.

[0032] There are no particular restrictions on the content of the perovskite-type compound in the dielectric layer 11, and it can be appropriately selected depending on the purpose. For example, it may contain 50 atomic% or more, 60 atomic% or more, 80 atomic% or more, 90 atomic% or more, or 95 atomic% or more. Furthermore, the perovskite structure may have fewer oxygen atoms than the stoichiometric composition. That is, the perovskite-type compound may be an ABO that deviates from the stoichiometric composition. 3-α This can also be expressed as (0≦α≦1: α represents a quantity outside the stoichiometric composition).

[0033] Examples of perovskite compounds include, for example, barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), and Ba that forms a perovskite structure 1-x-y Ca x Sr y Ti 1-z Zr z One or more of O3 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1) etc. can be used.

[0034] Ba 1-x-y Ca x Sr y Ti 1-z Zr z Specific examples of O3 include barium strontium titanate, barium calcium titanate, barium zirconate, barium titanium zirconate, calcium titanium zirconate, and barium calcium titanium zirconate.

[0035] Among these perovskite compounds, barium titanate (BaTiO3) is preferred from the viewpoint of excellent dielectric properties such as high dielectric constant and low dielectric loss. By including barium titanate as a perovskite compound in the dielectric layer 11, the capacitance of the multilayer ceramic capacitor 100 can be increased. The ceramic material in the dielectric layer 11 preferably contains barium titanate as a main component and may be composed only of barium titanate.

[0036] The dielectric layer 11 may contain additives other than the ceramic material described above. There are no particular restrictions on such additives, and they can be appropriately selected depending on the purpose. For example, zirconium (Zr), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er) Examples include elements or compounds containing one or more elements selected from (1), thulium (Tm), and ytterbium (Yb), or elements or compounds containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si), or glass containing oxides containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, potassium, and silicon.

[0037] The dielectric layer 11 may contain copper (Cu). If the dielectric layer 11 contains copper, the concentration of copper in the dielectric layer 11 is preferably 0.1 atomic percent or less, from the viewpoint of ensuring the insulating properties of the dielectric.

[0038] The thickness t (μm) of the dielectric layer 11 is 1.6 μm or less. Varying the thickness of the dielectric layer also changes the interface ratio to the dielectric layer, and therefore the contribution of strengthened interface resistance to improving lifetime characteristics changes. For example, if the thickness t of the dielectric layer 11 is greater than 1.6 μm, the contribution to improving lifetime characteristics may be low. Furthermore, if the thickness of the dielectric layer 11 exceeds 1.6 μm, the adverse effect on capacitance characteristics may become negligible. If the thickness t of the dielectric layer 11 is 1.6 μm or less, sufficient capacitance characteristics can be obtained. From the viewpoint of improving capacitance characteristics, the thickness t (μm) of the dielectric layer 11 is preferably 1.0 μm or less, more preferably 0.8 μm or less, and even more preferably 0.5 μm or less.

[0039] There are no particular restrictions on the method for measuring the thickness t (μm) of the dielectric layer 11, and it can be appropriately selected according to the purpose. For example, it can be evaluated based on cross-sectional observation of the multilayer ceramic capacitor 100. More specifically, the multilayer ceramic capacitor is polished along the X-axis or Y-axis to expose the YZ plane or XZ plane of the capacitance portion 14. At this time, it is preferable that the surface exposed by polishing is a surface near the center of the capacitance portion 14 in the X-axis or Y-axis direction. The exposed surface is imaged using a laser microscope or the like, and approximately 5 to 10 layers each from the center, upper end, and lower end in the Z-axis direction, which is the stacking direction of the dielectric layer 11, for a total of 15 to 20 dielectric layers 11. The thickness t (length in the Z-axis direction) of these dielectric layers 11 is measured at 1 / 4, 1 / 2, and 3 / 4 of the width of each dielectric layer, and the average value can be taken as the thickness t (μm) of the dielectric layer 11. When imaging with a laser microscope or the like, the dielectric layer 11 may be imaged in sections: the central part, the upper end, and the lower end in the Z-axis direction, which is the stacking direction of the dielectric layer 11. Alternatively, it may be imaged in sections representing 1 / 4, 1 / 2, and 3 / 4 of the dielectric layer width.

[0040] In the multilayer ceramic capacitor of this embodiment, it is preferable that the thickness t (μm) of the dielectric layer 11 is 1.6 μm or less, and the electric field strength of the multilayer ceramic capacitor is 50 V / μm or less.

[0041] Figure 4 is a graph showing the HALT lifetime increase rate of a multilayer ceramic capacitor containing 1% copper (Cu) in the internal electrode layer 12, compared to a conventional multilayer ceramic capacitor without copper (Cu) added to the internal electrode layer. The method for measuring the HALT lifetime in Figure 4 will be described later in the Examples section. From Figure 4, it can be seen that the HALT lifetime increase rate decreases as the thickness of the dielectric layer 11 increases beyond 1.6 μm, and as the electric field strength between the internal electrode layers 12 increases from 20 V / μm to 50 V / μm. On the other hand, if the thickness of the dielectric layer 11 is 1.6 μm or less, it can be seen that there is an excellent lifetime improvement effect, with the HALT lifetime increase rate exceeding 50% even at an electric field strength of 50 V / μm.

[0042] The electric field strength at the rated voltage, which serves as an indicator of the limit for the steady-state use of a multilayer ceramic capacitor, can be calculated from the rated voltage value and the thickness of the dielectric layer 11 between the internal electrode layers 12. Furthermore, the electric field strength during an overload acceleration test, sometimes used to indicate the quality level of a multilayer ceramic capacitor, can be calculated from the applied voltage value during a typical overload acceleration test, the high-temperature load test, and the thickness of the dielectric layer 11 between the internal electrode layers 12. The applied voltage during the high-temperature load test can range from 100% to 150% of the rated voltage, and up to 200% depending on the product application. The applied voltage is specified in the product specifications for each multilayer ceramic capacitor, and the manufacturer can use the applied voltage determined by the manufacturer.

[0043] From the viewpoint of the rate of increase in HALT lifetime as the electric field strength of the multilayer ceramic capacitor decreases, a value of 50V / μm or less is preferred, 40V / μm or less is more preferred, 30V / μm or less is even more preferred, and 20V / μm or less is particularly preferred. Furthermore, the electric field strength of these multilayer ceramic capacitors is preferably the electric field strength when the rated voltage is applied, and more preferably the electric field strength at high temperature load from the viewpoint of the safety factor for HALT lifetime.

[0044] (Internal electrode layer) The internal electrode layer 12 mainly contains a metal or alloy. For example, the internal electrode layer 12 may mainly contain base metals such as nickel (Ni) and tin (Sn), or alloys containing these. Alternatively, the internal electrode layer 12 may mainly contain precious metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing these. Among these, the internal electrode layer 12 is preferably made of Ni, from the viewpoint of having excellent electrical properties and reducing costs.

[0045] The main component in the first internal electrode layer 12a and the main component in the second internal electrode layer 12b may be the same or they may be different.

[0046] The internal electrode layer 12 may contain copper (Cu). If the internal electrode layer 12 contains Ni as its main component, Cu may form an alloy with Ni. The inclusion of copper in the internal electrode layer 12 increases the interfacial resistance between the internal electrode layer and the dielectric layer, which has the effect of extending the lifespan of the MLCC.

[0047] There are no particular restrictions on the concentration (atomic %) of copper in the internal electrode layer 12, and it can be appropriately selected according to the purpose, but it is preferably 2.5 atomic % or less, more preferably 2 atomic % or less, even more preferably 1.5 atomic % or less, and particularly preferably 1 atomic % or less. Setting the concentration (atomic %) of copper in the internal electrode layer 12 within the above range prevents a decrease in the continuity of the internal electrode layer 12 due to a decrease in the melting point of the internal electrode layer 12 caused by an excess amount of copper present in the internal electrode layer 12. Furthermore, from the viewpoint of improving the lifetime characteristics, the concentration (atomic %) of copper in the internal electrode layer 12 is preferably 0.2 atomic % or more, more preferably 0.3 atomic % or more, and even more preferably 0.5 atomic % or more.

[0048] There are no particular restrictions on the method for measuring the copper concentration in the internal electrode layer 12, and it can be appropriately selected according to the purpose. For example, the average value of the copper concentration (atoms) % in the region on the internal electrode side, excluding the intermediate region 40, can be used in the concentration distribution graph obtained by TEM-EDX analysis. If a strict boundary is required, the region of the internal electrode layer 12 may be defined as the region where the oxygen concentration is less than 5 atomic percent. Here, the copper concentration is the ratio of atoms to all elements contained in the internal electrode layer 12.

[0049] There are no particular restrictions on the thickness of the internal electrode layer 12, and it can be appropriately selected according to the purpose, but it is preferably 0.1 μm or more and 1.5 μm or less, and more preferably 0.3 μm or more and 1.0 μm or less.

[0050] If the thickness of the internal electrode layer 12 is less than 0.1 μm, the continuity of the internal electrode becomes significantly smaller due to reasons such as the ceramic dielectric easily diffusing and disappearing during firing, making it difficult to ensure its function as an internal electrode. If the thickness of the internal electrode layer 12 is 0.1 μm or more, its function as an internal electrode can be ensured. If the thickness of the internal electrode layer 12 is 1.5 μm or less, the capacitance can be increased by increasing the number of layers of the capacitance section 14 in a multilayer ceramic capacitor of the same size. In other words, a thickness of 1.5 μm or less for the internal electrode layer 12 is preferable from the viewpoint of obtaining a smaller multilayer ceramic capacitor with the same performance. From the viewpoint of enabling an increase in capacitance by increasing the number of layers, the thickness of the internal electrode layer 12 is preferably 0.5 μm or less, and more preferably 0.4 μm or less.

[0051] There are no particular restrictions on the method for measuring the thickness of the internal electrode layer 12, and it can be appropriately selected according to the purpose. For example, it can be measured using the same method as the method for measuring the thickness t of the dielectric layer 11.

[0052] (middle area) Figure 5 is an enlarged view of region C in Figure 2. As shown in Figure 5, the multilayer ceramic capacitor 100 according to this embodiment has an intermediate region 40 containing copper between the dielectric layer 11 and the internal electrode layer 12. Figure 5 is a schematic diagram in which the intermediate region 40 is shown as a continuous layer of constant thickness, but the intermediate region 40 is not limited to the illustrated form. For example, the intermediate region 40 may be discontinuous, and its thickness may vary depending on the location. The intermediate region 40 may be formed in the manufacturing of the multilayer ceramic capacitor 100 by segregation of elements between the two layers during a firing process (described in detail later) in which an unfired material for forming the dielectric layer 11 and an unfired material for forming the internal electrode layer 12 are laminated together.

[0053] The intermediate region 40 can be identified based on observation of the cross-section of the multilayer ceramic capacitor 100. For example, as described above regarding the method for measuring the thickness t of the dielectric layer 11, the YZ plane or XZ plane of the capacitance portion 14 is exposed. Then, line analysis is performed along the Z axis direction on the exposed surface using energy dispersive X-ray spectroscopy (EDX) with a transmission electron microscope (TEM), and a graph of the concentration distribution of each element is output. In the obtained graph, the region where the distribution range of the main component elements of the internal electrode layer 12 and the distribution range of the main component elements of the dielectric layer 11 overlap, or the region where there is a concentration gradient of the main component elements of the internal electrode layer 12 and the main component elements of the dielectric layer 11, is determined to be the intermediate region 40. If a strict boundary is required, the intermediate region 40 may be defined as the region where the oxygen concentration is 5 atomic percent or more and titanium (Ti), one of the main component elements of the dielectric layer 11, is 15 atomic percent or less.

[0054] Figure 6(a) shows an example of a concentration distribution graph obtained by TEM-EDX analysis of the XZ plane exposed by polishing the multilayer ceramic capacitor 100 according to this embodiment. Figure 6(b) is a part of the graph in Figure 6(a) enlarged in the vertical axis direction (enlarged view of the range from 0 atomic% to 4 atomic% concentration). Figures 6(a) and (b) show the analysis results of a multilayer ceramic capacitor 100 comprising a dielectric layer 11 made of barium titanate and an internal electrode layer 12 mainly composed of nickel. From Figures 6(a) and (b), a concentration gradient of nickel (Ni), as well as concentration gradients of oxygen (O), titanium (Ti), and barium (Ba), can be observed in the intermediate region 40 between the dielectric layer 11 and the internal electrode layer 12.

[0055] The intermediate region 40 contains Cu. Cu is a dissimilar element, that is, an element different from both the main component element constituting the dielectric layer 11 and the main component element constituting the internal electrode layer 12. The presence of such a dissimilar element between the dielectric layer 11 and the internal electrode layer 12 increases the interfacial resistance between the dielectric layer 11 and the internal electrode layer 12, thereby enabling high insulation reliability over a long period of time. In other words, the lifespan characteristics of the multilayer ceramic capacitor 100 can be improved.

[0056] The Cu contained in the intermediate region 40 may be segregated from the internal electrode layer 12 and / or the dielectric layer 11, preferably from the internal electrode layer 12, during the firing process in the manufacture of the multilayer ceramic capacitor 100. Since Cu diffuses more easily than other elements, it can be segregated in a sufficient amount between the internal electrode layer 12 and the dielectric layer 11 during the manufacturing process of the multilayer ceramic capacitor 100, thus easily increasing the interfacial resistance.

[0057] -Concentration of Cu- As described above, in the multilayer ceramic capacitor 100 according to this embodiment, Cu is present in the intermediate region 40. The inventors have diligently studied the relationship between the copper concentration in the intermediate region and the characteristics of the multilayer ceramic capacitor 100, and have found that by setting the ratio [a / t] of the copper concentration a (atomic%) in the intermediate region 40 to the thickness t (μm) of the dielectric layer 11 to 0.8 or more and 7.0 or less, it is possible to provide a multilayer ceramic capacitor 100 with a long lifespan and excellent dielectric properties.

[0058] Furthermore, the inventors have found that by setting the ratio [a / t] to 1.5 or more and 3.0 or less, a multilayer ceramic capacitor 100 with a long lifespan and superior dielectric properties can be provided. In this specification, superior dielectric properties mean having sufficient capacitance.

[0059] Thus, in the multilayer ceramic capacitor 100 according to this embodiment, the ratio [a / t] of the copper concentration a (atomic%) in the intermediate region to the dielectric layer thickness t (μm) is 0.8 or more and 7.0 or less. With this configuration, a long lifespan and excellent dielectric properties can be ensured, and high reliability can be achieved.

[0060] The lifetime characteristics of the multilayer ceramic capacitor 100 can be evaluated based on the length of time required for the insulation resistance to decrease to a predetermined value during a high-temperature load test. For this evaluation, for example, a highly accelerated limit test (HALT) can be used. In this highly accelerated limit test, a voltage that results in a predetermined electric field strength at a predetermined temperature (for example, a voltage that results in 25V / μm at 150°C) is continuously applied, and the time at which half of the tested multilayer ceramic capacitors exceed the leakage current threshold is defined as the 50% lifetime value of the HALT. A higher 50% lifetime value of the HALT indicates a longer lifetime.

[0061] The copper concentration a (atomic %) in the intermediate region 40 is not particularly limited as long as it satisfies the above ratio [a / t] and can be appropriately selected according to the purpose, but it is preferably 1 atomic % to 4.5 atomic %, more preferably 1.2 atomic % to 4 atomic %, even more preferably 1.3 atomic % to 3 atomic %, and particularly preferably 1.5 atomic % to 2.5 atomic %.

[0062] When the copper concentration a (atomic%) in the intermediate region 40 is 1 atomic% or more, Cu is distributed to cover the internal electrode layer 12 with a sufficient area ratio, thereby increasing the interfacial resistance and obtaining high lifetime characteristics. Furthermore, when the copper concentration a (atomic%) in the intermediate region 40 is 4.5 atomic% or less, the decrease in insulation due to the excess amount of Cu present in the intermediate region 40 is avoided, and excellent electrostatic characteristics are obtained. In particular, when the copper concentration a (atomic%) in the intermediate region 40 is 2.5 atomic% or less, high capacitance can be ensured.

[0063] The copper concentration a (atomic %) in the intermediate region 40 may be a value obtained by TEM-EDX analysis of the surface exposed by polishing, in the same manner as described for confirming the intermediate region 40. In this specification, the copper concentration a (atomic %) in the intermediate region 40 is defined as the maximum value of the copper concentration (atomic %) in the region recognized as the intermediate region 40 in the concentration distribution graph obtained by TEM-EDX analysis. The concentration distribution graph used is one from which background noise originating from the apparatus has been removed.

[0064] [Manufacturing method for multilayer ceramic capacitors] Next, a method for manufacturing the multilayer ceramic capacitor 100 described above will be explained. One embodiment of the present disclosure is a method for manufacturing a multilayer ceramic capacitor having a substrate in which a dielectric layer containing a perovskite-type compound represented by the general formula ABO3 and an internal electrode layer are alternately stacked, and an intermediate region containing copper is between the dielectric layer and the internal electrode layer. The method includes a stacking step of alternately stacking an unfired dielectric material to be the dielectric layer and an unfired internal electrode material to be the internal electrode layer to obtain a laminate, and a firing step of firing the laminate, wherein the ratio [a / t] of the copper concentration a (atomic%) in the intermediate region to the thickness t (μm) of the dielectric layer is 0.8 or more and 7.0 or less. Figure 7 is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor 100 according to one embodiment.

[0065] (Preparation process for unfired dielectric material (S1)) In the preparation step (S1) for the unfired dielectric material, a ceramic green sheet (unfired dielectric material) that will become the dielectric layer 11 after firing is prepared.

[0066] First, a ceramic powder for forming the dielectric layer is prepared. For the dielectric layer 11 of the multilayer ceramic capacitor 100, the ceramic material powder described above can be used. Therefore, the ceramic powder may contain a perovskite compound powder represented by the general formula ABO3, and preferably contains barium titanate.

[0067] Barium titanate can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate.

[0068] There are no particular restrictions on the method for synthesizing the ceramic powder that will be the main component of the dielectric layer 11, and it can be appropriately selected according to the purpose. Examples include the solid-phase method, the sol-gel method, and the hydrothermal method.

[0069] Depending on the purpose, certain additives may be added to the ceramic powder for dielectric layer formation. After wet mixing the ceramic powder for dielectric layer formation with or without additives, it is dried and pulverized. Then, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer are added to the obtained dielectric layer formation powder and wet mixed to prepare a dielectric layer formation slurry. The obtained dielectric layer formation slurry is coated onto a substrate such as polyethylene terephthalate (PET) film by methods such as the die coater method and the doctor blade method, and dried to obtain a ceramic green sheet (unfired dielectric layer material).

[0070] (Preparation process for unfired internal electrode material (S2)) In the preparation step (S2) for the unfired internal electrode material, the unfired internal electrode material that will become the internal electrode layer 12, i.e., the first internal electrode layer 12a and the second internal electrode layer 12b, is prepared. The main metal component of the unfired internal electrode material may be the same metal material as described above for the internal electrode layer 12 of the multilayer ceramic capacitor 100, for example, base metals such as Ni and Sn or alloys containing these. Alternatively, noble metals such as Pt, Pd, Ag, and Au, or alloys containing these may be used as the metal material. Because it has excellent electrical properties and can reduce costs, it is preferable for the metal material to contain Ni, and more preferably for Ni to be the main component.

[0071] Cu is added to the above metal material. Then, the metal material with added Cu, the organic binder, and the solvent are kneaded to obtain a metal paste (unfired internal electrode material). Note that Cu may also be added after the metal paste has been prepared from the main component metal material. Cu is preferably added as an oxide from the viewpoint of facilitating diffusion into the intermediate region 40 during the firing process. Examples of the Cu oxide include copper oxide.

[0072] The amount of Cu in the unfired internal electrode material can be adjusted so that the ratio [a / t] of the copper concentration a (atomic%) in the intermediate region after the firing process (S5) to the thickness t (μm) of the dielectric layer after the firing process (S5) is between 0.8 and 7.0. By adjusting the amount of Cu added as described above, the interfacial resistance between the dielectric layer 11 and the internal electrode layer 12 can be increased, resulting in high insulation reliability over the long term. In other words, high lifetime characteristics can be obtained. In this way, according to this embodiment, a multilayer ceramic capacitor 100 with excellent lifetime characteristics and electrostatic characteristics can be manufactured.

[0073] In this embodiment, the amount of Cu to be added during the manufacturing process of the multilayer ceramic capacitor can be adjusted based on the above ratio [a / t], which represents the relationship between the thickness t (μm) of the dielectric layer 11 and the copper concentration a (atomic %) in the intermediate region 40. Therefore, even when manufacturing a multilayer ceramic capacitor with a new design in which the thickness t of the dielectric layer 11 is changed, for example, the amount of Cu to be added can be easily adjusted. As a result, even when manufacturing a multilayer ceramic capacitor with a new design, a highly reliable product can be obtained.

[0074] Ceramic powder may be added as a co-material to the metal paste (unfired internal electrode material). The main component of the ceramic powder is not particularly limited, but it is preferable that it be the same as the ceramic powder used in the preparation step (S1) of the unfired dielectric material. When ceramic powder is added as a co-material, it can be added during the mixing of the metal paste.

[0075] (Lamination process (S3)) In the lamination process (S3), the metal paste obtained in the preparation process for the unfired internal electrode material (S2) is printed onto the surface of the ceramic green sheet obtained in the preparation process for the unfired dielectric material (S1) by methods such as screen printing and gravure printing. This allows a first internal electrode pattern, which will become the first internal electrode layer 12a, and a second internal electrode pattern, which will become the second internal electrode layer 12b, to be placed on the surface of the ceramic green sheet. Note that the method of forming the internal electrode pattern is not limited to printing, and can also be performed by methods such as plating, vacuum deposition, sputtering, and CVD using a mask.

[0076] The ceramic green sheets printed with the metal paste described above are stacked so that the internal electrode layer 12 is alternately drawn out to a pair of external electrodes 20a and 20b arranged in the longitudinal direction (X-axis direction) of the dielectric layer 11. Known techniques can be used for this stacking. For example, in order to form a side margin 16 which is the outer region in the Y-axis direction in the capacitance portion 14 on the side where the internal electrode layer 12 is not drawn out, an unfired dielectric material can be placed in the peripheral region where the internal electrode pattern with metal paste is not printed. Using the ceramic green sheets printed with metal paste as the stacking unit, the number of stacks in a stacking unit can range from 100 to 500 layers.

[0077] Next, a laminate is obtained by laminating cover sheets, which are unfired cover materials for forming a cover layer, on both the top and bottom of the laminate containing the ceramic green sheet and the internal electrode pattern, i.e., on both sides in the lamination direction (Z-axis direction). The cover sheets may be formed mainly using ceramic powder in the same manner as the unfired dielectric material for forming the dielectric layer. Alternatively, the cover sheets can be formed from the same material as the unfired dielectric material for forming the dielectric layer. The number of layered cover sheets may be 2 to 10 layers on each side.

[0078] A crimped body is obtained by pressing the resulting laminate in the lamination direction (Z-axis direction).

[0079] (Singulating process (S4)) The crimped body can be cut into individual pieces of a predetermined size by dicing with a dicing machine, laser cutting, or the like. Existing technologies can be used as appropriate for the method of individualization.

[0080] (Firing process (S5)) In the firing process (S5), the individual laminated bodies are fired. There are no particular restrictions on the firing conditions, and they can be appropriately selected according to the purpose, but it is preferable that the hydrogen concentration is 0.03% by volume or more and 1.0% by volume or less, and more preferably 0.05% by volume or more and 0.3% by volume or less. The composition of the reducing atmosphere other than hydrogen is nitrogen or argon. In the firing process (S5), the Cu that has been added to the unsintered material in advance segregates or diffuses at the interface, and an intermediate region 40 is formed.

[0081] The firing temperature in the firing process (S5) is preferably 1000°C to 1350°C, and more preferably 1150°C to 1300°C. The firing time in the firing process (S5) may be 30 minutes to 2 hours.

[0082] (External electrode formation process (S6)) In the external electrode formation process, the first external electrode 20a and the second external electrode 20b can be formed by plating or the like. This completes the multilayer ceramic capacitor 100 described above. [Examples]

[0083] The present disclosure will be described in more detail below based on examples.

[0084] <Fabrication of a 1A multilayer ceramic capacitor> A ceramic slurry was prepared by wet mixing a ceramic powder made of barium titanate with polyvinyl butyral (PVB) resin, a solvent, a plasticizer, a sintering aid powder which is a Si compound, and other additives such as rare earth elements. This ceramic slurry was coated onto a substrate film using a doctor blade to form a dielectric green sheet with a thickness of 0.5 μm after sintering.

[0085] A mixed powder was prepared by adding and mixing copper (CuO) in the form of copper oxide (CuO) powder to nickel powder. A metal paste (Cu-containing Ni paste) for forming the internal electrode layer was obtained by kneading this mixed powder with polyvinyl butyral (PVB) resin, a solvent, and a plasticizer. The amount of copper oxide added to the metal paste was adjusted so that the copper concentration in the intermediate region after sintering was 1.2 atomic percent. The metal paste was printed onto a dielectric green sheet to form the internal electrode layer pattern.

[0086] 500 dielectric green sheets printed with this metal paste were stacked, and then a dielectric green sheet serving as a cover layer was placed on each side in the stacking direction to form a laminate.

[0087] After the resulting laminate was compressed, it was cut to a predetermined size to obtain individual molded chips. The obtained molded chips were debindered in an N2 atmosphere, and a metal paste, which would serve as the base layer for the external electrodes, was applied by the dip method. Subsequently, the molded chips were placed in a firing furnace, and the firing furnace temperature (firing temperature) was raised to 1200°C in an atmosphere of H2 concentration 0.1 volume% and N2 concentration 99.9%, and firing was performed for 10 minutes. After firing, external electrodes were formed on the molded chips by plating, and a multilayer ceramic capacitor (MLCC) with dimensions of 1.0 mm × 0.5 mm × 0.5 mm was obtained.

[0088] [Measurement of the thickness t of the dielectric layer] The fabricated multilayer ceramic capacitor was polished from the external electrode side toward the center (i.e., along the X-axis) to expose the YZ plane where the dielectric layer and internal electrode layer are stacked. The exposed YZ plane was imaged using a laser microscope, and approximately 5 layers each were selected from the center, upper end, and lower end of the Z-axis direction, which is the stacking direction of the dielectric layer, for a total of 15 dielectric layers. The thickness (μm) of each dielectric layer along the Z-axis direction was measured at positions of 1 / 4, 1 / 2, and 3 / 4 of the dielectric layer width, and the average value was taken as the dielectric layer thickness t (μm).

[0089] [Measurement of copper concentration a in the intermediate region] Similar to the measurement of the dielectric layer thickness t described above, the YZ plane of the fabricated multilayer ceramic capacitor was exposed. Near the center in the Z-axis direction, a line analysis was performed along the Z-axis direction using energy-dispersive X-ray spectroscopy (TEM-EDX) with transmission electron microscopy, covering the range from one internal electrode layer to the dielectric layer adjacent to that internal electrode layer. In the graph of the atomic number concentration distribution of each element obtained from this line analysis, the highest value of Cu concentration was calculated in the intermediate region, which corresponds to the region where the oxygen concentration is 5 atomic percent or more and Ti, one of the main constituent elements of the dielectric layer, is 15 atomic percent or less. Using the same method, the maximum value in a total of three intermediate regions was calculated, and the average value was taken as the copper concentration a (atomic percent) in the intermediate region. Note that the above copper concentration a is the concentration of Cu (atomic percent) relative to all elements detected in the analysis, and is a value that excludes background noise originating from the measuring device.

[0090] <Manufacturing of multilayer ceramic capacitors 2A-9A and 1B-10B> As shown in Table 1, each multilayer ceramic capacitor was fabricated in the same manner as in the <Fabrication of Multilayer Ceramic Capacitor 1A>, except that the thickness t of the dielectric layer and the concentration a of copper in the intermediate region were changed. Multilayer ceramic capacitors 1B to 7B were fabricated using metal paste (Cu-free Ni paste).

[0091] (Examples 1-9 and Comparative Examples 1-10) The capacitance and lifetime characteristics of each obtained multilayer ceramic capacitor were measured as follows. The results are shown in Table 1.

[0092] [Measurement of capacitance] The fabricated multilayer ceramic capacitors were left at 150°C for 1 hour, then left under standard conditions (temperature 25°C, 1 atm) for 24 hours. Afterward, the capacitance (μF) was measured using an LCR meter (Keysight Technologies HP4284A) under conditions of 0.5V voltage and 1kHz frequency. The absolute difference between the capacitance of multilayer ceramic capacitors 1B-7B (without added Cu) and the capacitance of multilayer ceramic capacitors 1A-9A and 8B-10B (with added Cu) was defined as Δcapacitance. Specifically, Δcapacitance was calculated based on the following formula.

[0093] ΔCapacitance (%) = |(Capacitance of multilayer ceramic capacitor with added Cu - Capacitance of multilayer ceramic capacitor without added Cu) / Capacitance of multilayer ceramic capacitor without added Cu| In calculating the Δ capacitance, we compared capacitors with the same dielectric layer thickness t (for example, multilayer ceramic capacitor 1A and multilayer ceramic capacitor 1B, and multilayer ceramic capacitor 7A and multilayer ceramic capacitor 4B). The obtained Δ capacitance was evaluated based on the following evaluation criteria, and rated as "◎", "〇", and "×" in descending order of quality. "〇" or higher was considered a pass, and "×" was considered a fail. -Evaluation Criteria- ◎: Δ Capacitance is 5% or less ○: Δ capacitance is between 5% and 15%. ×: ΔCapacitance exceeds 15%

[0094] [Measurement of lifespan characteristics] Life characteristics were evaluated by highly accelerated life testing (HALT). For each of the 20 fabricated multilayer ceramic capacitors, a voltage with an electric field strength of 25 V / μm was applied at 150°C, and the leakage current was measured over time. The time at which 50% of the samples reached a leakage current of 2000 μA was recorded as the 50% HALT lifetime value. The 50% HALT lifetime value of multilayer ceramic capacitors 1B to 7B without added Cu and the 50% HALT lifetime value of multilayer ceramic capacitors 1A to 9A and multilayer ceramic capacitors 8B to 10B with added Cu were used to determine the HALT lifetime increase rate based on the following formula.

[0095] HALT lifetime increase rate = (50% HALT lifetime of multilayer ceramic capacitor with added Cu - 50% HALT lifetime of multilayer ceramic capacitor without added Cu) / 50% HALT lifetime of multilayer ceramic capacitor without added Cu In calculating the HALT lifetime increase rate, comparisons were made between capacitors with the same dielectric layer thickness t (for example, multilayer ceramic capacitor 1A and multilayer ceramic capacitor 1B, and multilayer ceramic capacitor 7A and multilayer ceramic capacitor 4B). The obtained HALT lifetime increase rates were evaluated based on the following evaluation criteria, and were rated as "◎", "〇", and "×" in descending order of quality. "〇" or higher was considered a pass, and "×" was considered a fail. -Evaluation Criteria- ◎: HALT life expectancy increase rate of 150% or more ○: HALT life expectancy increase rate is 50% or more but less than 150% ×: HALT life expectancy increase rate is less than 50%

[0096] [Table 1]

[0097] As shown in Table 1, Examples 1-4 and 7-9, where the ratio [a / t] was 3.0 or less, showed good results with small changes in capacitance. Furthermore, Examples 1-2 and 4-7, where the ratio [a / t] was 1.5 or more, showed good results with a high rate of increase in HALT lifetime.

[0098] On the other hand, Comparative Examples 1 to 7 were defective because they did not contain Cu in the intermediate region, resulting in low HALT lifetimes. Comparative Example 8 was defective because its ratio [a / t] was less than 0.8, resulting in little to no improvement in HALT lifetime. Comparative Example 9 was defective because its ratio [a / t] exceeded 7.0, leading to a deterioration in the continuity of the internal electrodes and failure to maintain capacitance. Comparative Example 10 was defective because its dielectric layer thickness exceeded 1.6 μm, resulting in a low interface ratio to the dielectric layer. Consequently, the interfacial effect of strengthening interface resistance on improving lifetime characteristics was not reflected, resulting in a low HALT lifetime and a defective product.

[0099] Although embodiments have been described in detail above, this disclosure is not limited to the embodiments described above. Furthermore, the embodiments described above can be modified, altered, replaced, added, deleted, and combined in various ways within the scope of the claims.

[0100] The aspects of this disclosure are, for example, as follows:

[0101] <1> The substrate has alternating layers of dielectric layers containing a perovskite-type compound represented by the general formula ABO3 and internal electrode layers. Between the dielectric layer and the internal electrode layer, there is an intermediate region containing copper. The thickness of the dielectric layer is 1.6 μm or less. The multilayer ceramic capacitor is characterized in that the ratio [a / t] of the copper concentration a (atomic%) in the intermediate region to the thickness t (μm) of the dielectric layer is 0.8 or more and 7.0 or less. <2> The aforementioned ratio [a / t] is between 1.5 and 3.0. <1> This is a multilayer ceramic capacitor as described above. <3> The thickness of the dielectric layer is 1.0 μm or less. <1> or <2> This is a multilayer ceramic capacitor as described above. <4> The electric field strength is 50 V / μm or less. <1> from <3> It is a multilayer ceramic capacitor as described in any of the following. <5> The electric field strength is calculated from the rated voltage of the multilayer ceramic capacitor and the thickness of the dielectric layer. <4> This is a multilayer ceramic capacitor as described above. <6> The electric field strength is calculated from the applied voltage during the high-temperature load test of the multilayer ceramic capacitor and the thickness of the dielectric layer. <4> This is a multilayer ceramic capacitor as described above. <7> The internal electrode layer contains nickel, <1> from <6> It is a multilayer ceramic capacitor as described in any of the following. <8> The perovskite compound represented by the general formula ABO3 contains barium titanate. <1> from <7> It is a multilayer ceramic capacitor as described in any of the following. [Explanation of symbols]

[0102] 10 Base Body 10a First side 10b Second side 11 Dielectric layer 12 Internal electrode layer 12a 1st internal electrode layer 12b Second internal electrode layer 13. Cover layer 14 Capacity part 15a First end margin 15b Second End Margin 16 Side margins 20a 1st external electrode 20b 2nd external electrode 91 Electrode section 100 Multilayer Ceramic Capacitors

Claims

1. General formula ABO ３ The body has a dielectric layer containing a perovskite-type compound represented by and an internal electrode layer that are alternately stacked, Between the dielectric layer and the internal electrode layer, there is an intermediate region containing copper. The thickness of the dielectric layer is 1.6 μm or less. A multilayer ceramic capacitor characterized in that the ratio [a / t] of the concentration a (atomic%) of copper in the intermediate region to the thickness t (μm) of the dielectric layer is 0.8 or more and 7.0 or less.

2. The multilayer ceramic capacitor according to claim 1, wherein the ratio [a / t] is 1.5 or more and 3.0 or less.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the thickness of the dielectric layer is 1.0 μm or less.

4. A multilayer ceramic capacitor according to claim 1 or 2, wherein the electric field strength is 50 V / μm or less.

5. The multilayer ceramic capacitor according to claim 4, wherein the electric field strength is calculated from the rated voltage of the multilayer ceramic capacitor and the thickness of the dielectric layer.

6. The multilayer ceramic capacitor according to claim 4, wherein the electric field strength is calculated from the applied voltage during a high-temperature load test of the multilayer ceramic capacitor and the thickness of the dielectric layer.

7. The multilayer ceramic capacitor according to claim 1 or 2, wherein the internal electrode layer contains nickel.

8. The aforementioned general formula ABO ３ The perovskite compound represented by contains barium titanate, as described in claim 1 or 2, for the multilayer ceramic capacitor.

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