Hierarchical layout design apparatus, hierarchical layout design program, and hierarchical layout design method

Abstract

The objective is to provide a hierarchical layout design system for semiconductor integrated circuits that enables efficient design. [Solution] The system comprises: a circuit layout means 39 for laying out circuits from the first layer module to the nth layer module; a first naming means 31 for assigning different names to each module from the first layer module to the nth layer module, and for assigning different names to the wiring used for connecting each layer module and for connecting circuits within the first layer module; a second naming means 32 for assigning the names given to the wiring within the first layer module to multiple terminals connected by said wiring, and for assigning names to the wiring that extends from the terminals within the first layer module to the boundary of the first layer module; and a first output control means 33 for creating a layout image in which the assigned terminal names are depicted and outputting this layout image to an output means.

Description

Technical Field

[0001] This invention relates to a hierarchical layout design apparatus for semiconductor integrated circuits, a program for hierarchical layout design, and a hierarchical layout design method.

Background Art

[0002] Conventional hierarchical layout techniques divide the design area for each constituent logic module to enable parallel work and thus shorten the construction period. However, since it is a bottom-up work form where it is assembled from the divided blocks of the terminal module, there is a problem that the design efficiency decreases conversely in the case of designing with a small number of people. The first problem is that the wiring path consistency cannot be achieved in the top-level design. The second problem is that batch processing cannot be applied with commercially available automatic placement and routing tools.

[0003] For example, assume that a semiconductor integrated circuit includes a logic module BUF_A and a logic module BUF_B in the lowest layer as shown in FIG. 1 in the logic circuit diagram. The logic module BUF_A includes an inverter circuit INV1_A and an inverter circuit INV1_B, and the logic module BUF_B includes an inverter circuit INV1_C and an inverter circuit INV1_D.

[0004] As shown in the layout image diagram in FIG. 2, assume that the person in charge A designs the logic module BUF_A, and as shown in the layout image diagram in FIG. 3, the person in charge B designs the logic module BUF_B. In this example, the case where the inverter circuit INV1_D in FIG. 3 is designed by a NAND circuit and used as an inverter circuit with positive logic is shown.

[0005] There was no agreement between person A and person B regarding the position of the wiring NET_BUF2 connecting the output terminal of logic module BUF_A and the input terminal of logic module BUF_B. As a result of selecting a track position that does not form a straight line extending horizontally in the diagram, a wiring track mismatch occurs, as indicated by the "X" mark in Figure 4 as the "point of track mismatch," making connection impossible.

[0006] Furthermore, Figure 5 shows the names of the design-specific automatic routing targets in the logic circuit diagram shown in Figure 1, circled in the diagram. In contrast, wiring within a logic module whose name is NET_LOCAL (indicated by an arrow in Figure 5) is not subject to automatic routing.

[0007] Patent Document 1 discloses a hierarchical design layout apparatus. This hierarchical design layout apparatus acquires a first netlist by an acquisition unit and extracts a second netlist from the first netlist by an extraction unit. It also executes a floor plan by a floor plan execution unit and performs temporary placement processing by a temporary placement processing unit. It sets wiring prohibition areas by a setting unit and performs CTS processing by a CTS processing unit. It executes temporary wiring processing by a temporary wiring processing unit and temporarily determines terminal positions by a temporary determination unit. It performs terminal position optimization processing by an optimization processing unit and executes layout processing for each lower-level block and also executes layout processing for higher levels by a hierarchical layout unit. In this way, by determining the terminal positions to the optimal positions in the hierarchical design layout, it is possible to improve design quality and shorten the design period.

[0008] Patent Document 2 discloses a layout design apparatus for semiconductor integrated circuits. This layout design apparatus comprises means for performing lower-level layout design by assembling a macroblock designed with pre-prepared preparation cells for correction; means for extracting layout information of at least unused preparation cells from the preparation cells for correction when the lower-level layout design is completed; and means for processing the extracted unused preparation cells for correction to be used in the higher-level layout design based on the extracted layout information. This eliminates the need to separately provide preparation cells for higher-level layout design, enabling further reduction in area and realizing effective layout design of signal wiring via large-capacity macroblocks within semiconductor integrated circuits.

[0009] Patent Document 3 discloses a hierarchical layout design method that divides data into layers and performs automatic placement and wiring for each layer. In this hierarchical layout design method, (a) after performing automatic placement within blocks, a model is created by extracting cells that have connection relationships from inside to outside the block in order to optimize the position of block terminals. Furthermore, in this hierarchical layout design method, (b) data is created by expanding the above model to a higher layer, and (c) temporary wiring is performed and block terminals are created at the intersections of the temporary wiring paths and the block frames. In addition, in this hierarchical layout design method, (d) wiring between the above block terminals is performed at the higher layer, and (e) wiring between the above block terminals and internal block cells is performed in each block.

[0010] According to the invention of Patent Document 3, the position of block terminals is determined based on a model that extracts only the necessary information from within the block, and its position and connection relationships at a higher level. This has the effect of optimizing terminal positions, avoiding detours, and reducing chip size. Furthermore, this invention has the effect of suppressing and reducing the increase in memory usage of the layout tool, as terminal positions can be optimized without expanding all the data within the block.

[0011] As described above, while conventional hierarchical layout designs aim to reduce man-hours and chip size, they have lacked consideration for avoiding defects and other issues when multiple designers work on the design in parallel. [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] Japanese Patent Publication No. 2008-009787 [Patent Document 2] Japanese Patent Publication No. 2013-254294 [Patent Document 3] Japanese Patent Application Publication No. 10-335473 [Overview of the Initiative] [Problems that the invention aims to solve]

[0013] The present invention aims to provide a hierarchical layout design apparatus, a hierarchical layout design program, and a hierarchical layout design method for semiconductor integrated circuits that enable efficient design by avoiding the occurrence of defects and other problems when multiple designers perform design work in parallel, thereby shortening the construction period. [Means for solving the problem]

[0014] A hierarchical layout design apparatus for a semiconductor integrated circuit according to an embodiment of the present invention comprises: a first layer module which is a circuit configured by connecting one or more instance cells; a second layer module which is a higher-level circuit of the first layer module configured by connecting one or more of the first layer modules; a third layer module which is a higher-level circuit of the second layer module configured by connecting one or more of the second layer modules; and similarly, an nth (n is a positive integer of 2 or more) layer module which is a higher-level circuit of the (n-1) layer module configured by connecting one or more (n-1) layer modules, wherein the hierarchical layout design apparatus for a semiconductor integrated circuit comprises: a circuit layout means for laying out the circuits from the first layer module to the nth layer module; and each of the first layer module to the nth layer module The system comprises: a first naming means for assigning different names to modules and for assigning different names to the wiring used for connections between each layer module and for connections between circuits within the first layer module; a second naming means for assigning the names assigned to the wiring within the first layer module to a plurality of terminals connected by said wiring as the names of those terminals, and for assigning names to wiring that extends from the terminals within the first layer module to the boundary of the first layer module; and a first output control means for creating a layout image for LVS verification to indicate whether the wiring within the first layer module conforms to a netlist, the layout image which depicts images of instance cells and terminals within the first layer module and the names of terminals assigned by the second naming means, but does not depict images of wiring, and outputs this layout image to an output means.

[0015] The hierarchical layout design program for a semiconductor integrated circuit according to an embodiment of the present invention comprises a computer provided in a hierarchical layout design apparatus for a semiconductor integrated circuit, which comprises: a first layer module that is a circuit composed of a number of instance cells connected together; a second layer module that is a higher-level circuit of the first layer module composed of one or more of the first layer modules connected together; a third layer module that is a higher-level circuit of the second layer module composed of one or more of the second layer modules connected together; and similarly, an nth layer module (where n is a positive integer of 2 or more) that is a higher-level circuit of the (n-1)th layer module composed of one or more of the (n-1)th layer modules connected together; a circuit layout means for laying out the circuits from the first layer module to the nth layer module; and each of the modules from the first layer module to the nth layer module. The invention is characterized by comprising: a first naming means that assigns different names to joules and assigns different names to the wiring used for connections between each layer module and for connections of circuits within the first layer module; a second naming means that assigns the names given to the wiring within the first layer module to a plurality of terminals connected by said wiring as the names of those terminals and also assigns names to wiring that extends from the terminals within the first layer module to the boundary of the first layer module; and a first output control means that functions as a layout image for LVS verification to show whether the wiring within the first layer module conforms to a netlist, the layout image which depicts images of instance cells and terminals within the first layer module and the names of terminals assigned by the second naming means, but does not depict images of wiring, and outputs this layout image to an output means.

[0016] A hierarchical layout design method for a semiconductor integrated circuit according to an embodiment of the present invention comprises: a first layer module which is a circuit configured by connecting one or more instance cells; a second layer module which is a higher-level circuit of the first layer module configured by connecting one or more of the first layer modules; a third layer module which is a higher-level circuit of the second layer module configured by connecting one or more of the second layer modules; and similarly, an nth (n is a positive integer of 2 or more) layer module which is a higher-level circuit of the (n-1)th layer module configured by connecting one or more (n-1)th layer modules, wherein the hierarchical layout design method for a semiconductor integrated circuit comprises: a first layer module which is a circuit configured by connecting one or more instance cells; a second layer module which is a higher-level circuit of the first layer module which is a circuit configured by connecting one or more (n-1)th layer modules; and a circuit layout means for laying out the circuits from the first layer module to the nth layer module; and different means for each of the modules from the first layer module to the nth layer module. The invention is characterized by comprising: a first naming step of assigning names to each layer module and assigning different names to the wiring used for connecting between each layer module and for connecting circuits within the first layer module; a second naming step of assigning the names given to the wiring within the first layer module to a plurality of terminals connected by said wiring as the names of those terminals, and assigning names to the wiring that extends from the terminals within the first layer module to the boundary of the first layer module; and a first output control step of creating a layout image for LVS verification to indicate whether the wiring within the first layer module conforms to a netlist, the layout image which depicts images of instance cells and terminals within the first layer module and the names of terminals assigned in the second naming step, but does not depict images of wiring, and outputting this layout image to an output means. [Brief explanation of the drawing]

[0017] [Figure 1] A logic circuit diagram of an example of a semiconductor integrated circuit. [Figure 2] Layout image diagram designed by person in charge A. [Figure 3] Layout image diagram designed by person in charge B. [Figure 4]A layout image diagram obtained by combining a layout image diagram designed by person in charge A and a layout image diagram designed by person in charge B. [Figure 5] A diagram showing the names of automatic wiring targets in the design of the logic circuit diagram shown in FIG. 1 surrounded by circles, a logic circuit diagram having a wiring named NET_LOCAL that is not a target of automatic wiring within a logic module, and a layout image diagram. [Figure 6] A configuration diagram of a computer that realizes a hierarchical layout design device according to an embodiment of the present invention. [Figure 7] A block diagram showing means and the like for realizing a hierarchical layout design device according to an embodiment of the present invention. [Figure 8] A logic circuit diagram having a hierarchical structure composed of first layer modules, second layer modules, ···, nth layer modules that can be designed in an embodiment of the present invention. [Figure 9] A logic circuit diagram within a first layer module that can be designed in an embodiment of the present invention. [Figure 10] A layout image diagram with names of terminals created according to an embodiment of the present invention attached to the logic circuit diagram within the first layer module. [Figure 11] A conventional layout image diagram when performing LVS verification. [Figure 12] A layout image diagram of an embodiment of the present invention when performing LVS verification. [Figure 13] A layout image diagram of a second layer module configured such that a plurality of first layer modules having the same layout by the same instance cell are connected and have inconsistent track positions. [Figure 14] Regarding the layout image diagram of FIG. 13, a layout image diagram of a second layer module modified so that the track positions match according to an embodiment of the present invention. [Figure 15] A layout image diagram showing layout wiring exposed according to an embodiment of the present invention. [Figure 16]A layout diagram showing that, according to an embodiment of the present invention, the wiring names of hierarchical modules are separated based on the set wiring names and returned to the inside of the module of a predetermined layer. [Figure 17] A flowchart illustrating the operation performed by embodiments of the present invention. [Figure 18] A flowchart illustrating the operation performed by embodiments of the present invention. [Modes for carrying out the invention]

[0018] Embodiments of the hierarchical layout design apparatus, hierarchical layout design program, and hierarchical layout design method of the present invention will be described below with reference to the attached drawings. In each figure, the same components are denoted by the same reference numerals, and redundant explanations are omitted. Figure 6 shows a computer configuration diagram that realizes the hierarchical layout design apparatus according to an embodiment of the present invention. That is, the CPU 10 configures the hierarchical layout design apparatus using programs and data in the main memory 11. An external storage interface 13, an input interface 14, a display interface 15, and a data input interface 16 are connected to the CPU 10 via a bus 12.

[0019] An external storage device 23 is connected to the external storage interface 13. The external storage device 23 stores programs and data necessary for the operation of this system, which the CPU 10 can read and use from the main memory 11 as needed. For this reason, as shown in Figure 7, the external storage device 23 stores a netlist 30, and also stores programs that implement the circuit layout means 39, the first naming means 31 and the second naming means 32, the first output control means 33, the first layer module wiring verification means 34, the second output control means 35, and the layout wiring means 36. The netlist 30 is created by a circuit design unit (not shown) and recorded therein for the hierarchical layout design apparatus of this embodiment to perform floor plan processing, placement processing, and wiring processing.

[0020] The input interface 14 is connected to input devices 24 such as a keyboard or touch panel and pointing devices 22 such as a mouse. The display interface 15 is connected to a display device 25 having a screen such as an LCD, and the display device 25 provides an output means. The data input interface 16 is connected to a network 26, and these networks 26 function as an input device unit for collecting various information and data. The display device 25 functions as an output means, but other output means such as a printer may also be provided. These output means also function as LVS verification layout image output means, which will be described later.

[0021] The hierarchical layout design apparatus according to an embodiment of the present invention comprises a first layer module which is a circuit formed by connecting one or more instance cells; a second layer module which is a higher-level circuit of the first layer module formed by connecting one or more of the first layer modules; a third layer module which is a higher-level circuit of the second layer module formed by connecting one or more of the second layer modules; and similarly, an nth layer module (where n is a positive integer of 2 or more) which is a higher-level circuit of the (n-1)th layer module formed by connecting one or more (n-1)th layer modules. The first layer module which is a circuit formed by connecting one or more instance cells is referred to as a logic module.

[0022] For example, as shown in Figure 8, the circuits inside the dashed boxes 51-1 and 51-2 are first-layer modules. Here, we show a second-layer module containing two first-layer modules, but there is no limit to this number. Of course, there is also no limit to the number of instance cells within a first-layer module. The higher-level circuit containing these two first-layer modules is enclosed in a dashed box 52, and the area within the dashed box 52 is the second-layer module. The second-layer module contains two first-layer modules, but this is an example; it may contain one or more. Furthermore, the higher-level circuit containing one (n-1)th-layer module is enclosed in a dashed box 53, and the area within the dashed box 53 is the nth-layer module. The nth-layer module contains one (n-1)th-layer module, but this is an example; it may contain one or more.

[0023] The circuit layout means 39 performs the circuit layout from the first layer module to the n-layer modules. In other words, it creates image information indicating the position of the module and the position of the circuit (device) according to the position information of the circuit (device) within each module, and makes it available for output to the output means. For example, it creates image information of the part of the image information shown in Figure 8, excluding the text.

[0024] The first naming means 31 assigns a different name to each module from the first layer module to the nth layer module, and also assigns a different name to each of the wires used for connecting each layer module and for connecting the circuits within the first layer module. Here, as shown in Figure 8, each module from the first layer module to the nth (=3) layer module is assigned and stored the names BUF_A, BUF_B, BUF_MID, and DESIGN_TOP, corresponding to their location information. In addition, the different names assigned to each of the wires used for connecting each layer module and for connecting the circuits within the first layer module are NET_BUF1, NET_BUF2, NET_BUF3, NET_LOCAL, IN, OUT, A, Z, etc., and these are also assigned and stored corresponding to their location information. A, Z, etc., are used with circuit names such as INV1_A, INV1_B, INV1_C, INV1_D, etc., while IN, OUT, etc., are used with module names of first-layer modules such as BUF_A, BUF_B, etc. NET_LOCAL is the name assigned to the wiring for the connections within the first-layer modules, and is assigned and stored in accordance with its location information. The database and rule information regarding the names of the input terminals, output terminals, and wiring between modules of each layer module, from the first-layer module to the nth-layer module, is stored in the external storage device 23, and the CPU 10 uses this to assign names.

[0025] The second naming means 32 assigns the name given to the wiring within the first layer module to the multiple terminals connected by the wiring as the name of the terminal, and also assigns a name to the wiring that extends from the terminals within the first layer module to the boundary of the first layer module. Specifically, as shown in Figure 9, when the name of the wiring between the output terminal of INV1_A of the inverter circuit of the first layer module, whose name is BUF_A, and the input terminal of INV1_B of the inverter circuit is NET_LOCAL, the second naming means 32 assigns this name NET_LOCAL to the multiple terminals connected by the wiring (Z of INV1_A and A of INV1_B as the name of the terminal; that is, the name of the multiple terminals Z of INV1_A and A of INV1_B) is NET_LOCAL.

[0026] The first output control means 33 creates a layout image for LVS verification to indicate whether the wiring in the first layer module conforms to the netlist, which depicts images of the instance cells and terminals in the first layer module and the names of the terminals assigned by the second naming means 32, but does not depict images of the wiring, and outputs this layout image to the output means.

[0027] The first output control means 33 operates, for example, to assign terminal names to the logic circuit diagram in Figure 9, as shown in the layout image in Figure 10. The first output control means 33 creates a layout image of the circuits in the first layer module (here, the inverter circuits INV1_A and INV1_B in Figure 9) as shown in Figure 10, to be used as an LVS verification layout image to indicate whether the wiring in the first layer module conforms to the netlist. The first output control means 33 then creates a layout image (Figure 10) in which the instance cells in the first layer module (the inverter circuits INV1_A and INV1_B in Figure 9), terminal images (A, Z, IN, OUT), and terminal names assigned by the second naming means 32 (NET_LOCAL for terminals INV1_A (Z) and INV1_B (A) are named) are drawn. This image is a layout image in which the wiring images are not drawn (Figure 10). The layout image thus created is output from an output means such as a display device 25. By visually inspecting the layout image output from the display device 25 or other output means, the layout designer can accurately determine whether the wiring within the first layer module conforms to the netlist, even without the actual wiring, by checking that the terminal names at both ends of the wiring match.

[0028] The first layer module wiring verification means 34 performs LVS verification to detect whether the wiring in the first layer module conforms to the netlist, based on the terminal names assigned by the second naming means 32 and the layout image of instance cells and terminals in the first layer module created by the first output control means 33. The circuit is represented by logical symbols as shown in Figure 9, and a comparison between the conventional device and the device of this embodiment is made when the naming by the first naming means 31 and the second naming means 32 is performed as shown in the figure. In the conventional device, LVS verification is performed by making connections LL between the terminals at both ends of the wiring, in a state where the terminal names at both ends of the wiring are not shown in the layout image, as shown in Figure 11. In contrast, in this embodiment, the terminal names at both ends of the wiring are shown in the layout image as shown in Figure 10, without making connections LL between the terminals at both ends of the wiring (in a temporary connection state), so LVS verification is performed based on the layout image. In other words, by ensuring that the terminal names at both ends of the wiring match (in this embodiment, the names of both ends are NET_LOCAL), it is confirmed that the circuit diagram created during the circuit design phase and the actually rewritten layout pattern are correctly matched (LVS verification). This allows for a more accurate verification than simply relying on the presence of line segments (wiring) to perform LVS verification.

[0029] Furthermore, the first naming means 31, when assigning a name to a wiring that connects multiple terminals in a state where multiple terminals are connected by wiring, in a state where the first layer module to the nth layer module exists, assigns the name by listing the names of each layer module from the first layer module to the ith layer module (where i is a positive integer less than or equal to (n-1)) to which the multiple terminals belong, and the name of the wiring to be assigned to the wiring between the multiple terminals. In other words, the name assigned to the terminals in the temporary connection shown in Figure 10, rather than the actual connection shown in Figure 11, is brought up to the circuit of the upper layer module and recognized and stored by the CPU 10 as an inter-block connection in the upper layer module. At this time, the assigned name is a combination of the instance name of the first layer module (logical module) and the terminal name inside the logical module, as follows. The reason for doing this is to make the wiring name unique in the upper layer module, and also to allow retrospectively to revert to the name inside the first layer module (logical module).

[0030] For example, in Figure 8, the first layer modules are 51-1 and 51-2, the second layer module is 52, and n=2. The "wiring connecting multiple terminals in a state where multiple terminals are connected by wiring" refers to the wiring 81 connecting inverter circuit INV1_A and inverter circuit INV1_B, the wiring 82 connecting first layer module 51-1 and first layer module 51-2, and the wiring 83 connecting inverter circuit INV1_C and inverter circuit INV1_D. According to rule R-1, which states that "the names of each layer module from the first layer module to which the multiple terminals belong up to the ith layer module (where i is a positive integer less than or equal to (n-1)) and the names of the wirings assigned to the wiring between the multiple terminals are listed together to assign names," wiring 81 becomes BUF_MID / BUF_A / NET_LOCAL, wiring 82 becomes BUF_MID / NET_BUF2, and wiring 83 becomes BUF_MID / BUF_B / NET_LOCAL (Figure 12). In this case, the names are listed according to rule R-2, which states that "the names of each layer module are listed from the top layer to the bottom layer, from the beginning to the end of the string, and a separator is placed between the names of each layer module and the names of the wirings," and the separator " / (slash)" is used. This makes it possible to clearly understand the hierarchical relationships and divisions of each layer module. Names are assigned to the terminals in this way, and the actual wiring process is not performed at this stage. In Figure 12, the dashed lines representing wires 81, 82, and 83 indicate that no wiring process will be performed.

[0031] The second output control means 35 receives instructions from the operator regarding which range of layers from the first layer module to the nth layer module should be output. It then creates an integrated image information by combining the names assigned by the first naming means within this range, the names assigned by the second naming means within this range, and the layout image created by the first output control means, and outputs this integrated image information to the output means. In other words, Figure 8 shows image information created from the first layer module to the second layer module, but it is not limited to this.

[0032] The second output control means 35, when a second layer module is constructed by connecting multiple first layer modules having the same layout and being the same instance cell, creates image information by performing layout wiring so that the wiring tracks match, and outputs it to the output means. In the case where the same logical module is arranged as multiple instance cells within a first layer module, the following is done. As shown in Figure 13, if the internal signal connections of first layer modules BUF_A, BUF_B, and BUF_C are located at different positions (mismatched track positions), the system has means to perform a correction process to change the connection positions in the layout image so that the internal wiring tracks match. In order to allow multiple instances to use the internal wiring tracks, the top level performs a grouping process that treats multiple wirings as a single wiring. As a result, the terminal positions are set so that the track connected to the terminal named NET_LOCAL in each first layer becomes a single line (Figure 14). Therefore, even if a situation like the one described in the conventional example in Figure 4 occurs, wiring mismatches can be prevented by integrating the results into the device of this embodiment and performing layout design.

[0033] The layout wiring means 36 creates image information by performing layout wiring based on the names assigned to multiple terminals, and outputs it to the output means. The first output control means 33 and the second output control means 35 do not display the layout wiring in the layout image, but rather assign names to the terminals as the basis. In contrast, the layout wiring means 36 displays the layout wiring in the layout image based on the names of the terminals that have already been assigned. The display changes from the state in Figure 12 where the layout wiring is not displayed to the state in Figure 15 where the layout wiring is displayed.

[0034] Herein, the layout wiring means 36 cuts the wiring extending from the terminals in the first layer module at the boundary of the first layer module to form the layout wiring of the first layer module.

[0035] According to rules R-1 and R-2, which state that "the names of each layer module from the first layer module to which the multiple terminals belong up to the ith layer module (where i is a positive integer less than or equal to (n-1)) and the names of the wirings assigned to the wirings between the multiple terminals are listed together to assign names," wiring 81 becomes BUF_MID / BUF_A / NET_LOCAL, wiring 82 becomes BUF_MID / NET_BUF2, and wiring 83 becomes BUF_MID / BUF_B / NET_LOCAL (Figure 15).

[0036] Thus, in this embodiment, connection information retrieved from the internal connections of lower-level modules is stored in a separate database (such as a layout database) from the original circuit diagram, and is then connected in the top-level module while maintaining the hierarchical structure. Taking Figure 15 as an example, the only connections visible from DESIGN_TOP are NET_BUF1 and NET_BUF3, which are inputs and outputs of BUF_MID. However, connection information that is contained within BUF_MID is not present in the circuit diagram of DESIGN_TOP, so connection information is supplemented by hooking up from the terminal division blocks.

[0037] Based on the wiring names set as described above, the names created by arranging them according to rules R-1 and R-2 are separated from the wiring names of the hierarchical modules and returned to the module of the predetermined layer. As shown in Figure 16, NET_LOCAL, IN, and OUT are returned. The connection data dropped from the higher layer is cut at the cell boundary of the logical module, as shown in Figure 15.

[0038] The processing by each of the above means is implemented by the flowchart program shown in Figures 17 and 18, and the hierarchical layout design method is performed. The operation will be explained below with reference to the flowchart. First, the circuit layout from the first layer module to the nth layer module is created (S11). Next, each layer module is assigned a name, and different names are assigned to the wiring used for connections between each layer module and for connections within the first layer module (S12). As a result, image information as shown in Figure 8 is created.

[0039] The names assigned to the wiring within the first layer module are assigned to the multiple terminals connected by that wiring as the names of those terminals, and the names of the wiring extending from the terminals within the first layer module to the boundary of the first layer module are also assigned (S13). For example, as shown in Figure 9, if the name of the wiring between the output terminal of INV1_A of the inverter circuit of the first layer module, whose name is BUF_A, and the input terminal of INV1_B of the inverter circuit is NET_LOCAL, then this name NET_LOCAL will be assigned to the multiple terminals connected by that wiring (Z of INV1_A and A of INV1_B) as the names of those terminals. The resulting layout image is shown in Figure 10 and is output to an output means such as a display device 25.

[0040] Next, based on the terminal names assigned as described above and the layout image of the instance cells and terminals within the created first layer module, LVS verification is performed to detect whether all the wiring within the first layer module conforms to the netlist (S14). In step S15, it is detected whether all the wiring within the first layer module conforms to the netlist.

[0041] If the process branches to NO in step S15, the process returns to step S11 and continues until it is confirmed that all wiring in the first layer module conforms to the netlist. If it is confirmed in step S15 that all wiring in the first layer module conforms to the netlist, the process branches to YES and proceeds to step S16. In the case where multiple terminals are connected by wiring and a name is to be assigned to the wiring connecting those multiple terminals, the names of each layer module from the first layer module to which the multiple terminals belong up to the i-th layer module (where i is a positive integer less than or equal to (n-1)) are listed together with the name of the wiring to be assigned to the wiring between the multiple terminals, and the name is assigned (S16). The result of the process in step S16 is shown in Figure 12.

[0042] Next, layout wiring is performed using the names assigned to multiple terminals to create image information, which is then output to the output means (S17). The result of this step S17 is shown in Figure 15. Thus, a layout image is output to the output means that includes all wiring connections, including those within the first layer module (logic module), in the layout image up to the top layer module. In this case, if the internal signal connections of the first layer module are located at different positions (mismatched track positions), a correction process is performed to change the connection positions in the layout image so that the internal wiring tracks match (within the parentheses of S17). As an example of the case where the internal signal connections of the first layer module are located at different positions (mismatched track positions), Figure 13 shows a state where the internal signal connections of first layer modules BUF_A, BUF_B, and BUF_C are located at different positions (mismatched track positions), and Figure 14 shows the result of changing the connection positions in the layout image so that the internal wiring tracks match.

[0043] Next, based on the wiring names set as described above, the names created by arranging them according to rules R-1 and R-2 as described above are separated from the wiring names of the hierarchical modules and returned to the module of the predetermined layer (S18). As shown in Figure 16, NET_LOCAL, IN, and OUT are returned. Here, rule R-1 is the rule that "names are assigned by arranging the names of each layer module from the first layer module to which the multiple terminals belong up to the i-th layer module (where i is a positive integer less than or equal to (n-1)) and the names of the wiring assigned to the wiring between the multiple terminals," and rule R-2 is the rule that, in this case, "the names of each layer module are arranged from the top layer to the bottom layer, from the beginning to the end of the string, and a separator is added between the names of each layer module and the names of the wiring." Note that the connection data dropped from the higher layer is cut at the cell boundary of the logical module, as shown in Figure 15.

[0044] In the hierarchical layout design apparatus, hierarchical layout design program, and hierarchical layout design method according to this embodiment, while utilizing the advantages of conventional hierarchical layout design, a method is applied to the wiring process (the process of adding wiring to the layout image) in which only the wiring work within each divided block is brought up to the upper layer and connected. This is expected to reduce both the construction period and the amount of work required. [Explanation of symbols]

[0045] 10 CPU 11 Main memory 12 buses 13 External storage interface 14 Input Interfaces 15 Display Interface 16. Data Input Interface 22 Pointing devices 23 External storage device 24 Input devices 25 Display device 26 Network 30 Netlists 31. First naming means 32. Second naming means 33 First output control means 34. Verification means for wiring within the first layer module 35 Second output control means 36 Layout wiring means 39 Circuit layout means

Claims

1. In a hierarchical layout design apparatus for a semiconductor integrated circuit, comprising: a first layer module which is a circuit formed by connecting one or more instance cells; a second layer module which is a higher-level circuit of the first layer module formed by connecting one or more of the first layer modules; a third layer module which is a higher-level circuit of the second layer module formed by connecting one or more of the second layer modules; and similarly, an nth (n is a positive integer of 2 or more) layer module which is a higher-level circuit of the (n-1)th layer module formed by connecting one or more (n-1)th layer modules, Circuit layout means for laying out the circuits from the first layer module to the n layer module, A first naming means that assigns a different name to each module from the first layer module to the nth layer module, and assigns a different name to each of the wirings used for connecting each layer module and for connecting circuits within the first layer module, A second naming means that assigns the names given to the connection wiring between circuits within the first layer module to the multiple terminals connected by said wiring as the names of those terminals, and also assigns names to the wiring that extends from the terminals within the first layer module to the boundary of the first layer module, A layout image for LVS verification to indicate whether the wiring in the first layer module conforms to the netlist, the layout image being created in which images of the instance cells and terminals in the first layer module and the names of the terminals assigned by the second naming means are drawn, but images of the wiring are not drawn, and a first output control means that outputs this layout image to an output means, A hierarchical layout design device characterized by comprising the following:

2. A first layer module wiring verification means performs LVS verification to indicate whether the wiring in the first layer module conforms to the netlist, based on the terminal names assigned by the second naming means and the layout image of the instance cells and terminals in the first layer module created by the first output control means. A hierarchical layout design apparatus according to claim 1, characterized by comprising the following:

3. The hierarchical layout design apparatus according to claim 1, wherein, in a state in which the first layer module to the nth layer module exist, when assigning a name to the wiring connecting the multiple terminals in a state in which the multiple terminals are connected by wiring, the first naming means assigns a name by lining up the names of each layer module from the first layer module to the i (where i is a positive integer less than or equal to (n-1)) layer module to which the multiple terminals belong and the name of the wiring to be assigned to the wiring between the multiple terminals.

4. The hierarchical layout design apparatus according to claim 3, characterized in that the first naming means arranges the names of each layer module from the top layer to the bottom layer, from the beginning to the end of the string, and separates between the names of each layer module and between the names of the wiring.

5. The hierarchical layout design apparatus according to claim 3, comprising: an operator providing instructions on which range of layers from the first layer module to the n layer modules to output; a second output control means for creating a single image information from the names assigned by the first naming means included in this range, the names assigned by the second naming means included in this range, and the layout image created by the first output control means; and outputting this single image information to the output means.

6. The hierarchical layout design apparatus according to claim 3, characterized in that the first output control means, when a second layer module is formed by connecting multiple first layer modules having the same layout with the same instance cell, performs layout wiring so that the wiring tracks match, creates image information, and outputs it to the output means.

7. The hierarchical layout design apparatus according to claim 3, further comprising a layout wiring means for creating image information by performing layout wiring based on names assigned to multiple terminals and outputting it to an output means.

8. The hierarchical layout design apparatus according to claim 7, characterized in that the layout wiring means cuts the wiring extending from the terminals in the first layer module at the boundary of the first layer module to form the layout wiring of the first layer module.

9. A computer provided in a hierarchical layout design apparatus for a semiconductor integrated circuit, comprising: a first layer module which is a circuit formed by connecting one or more instance cells; a second layer module which is a higher-level circuit of the first layer module formed by connecting one or more of the first layer modules; a third layer module which is a higher-level circuit of the second layer module formed by connecting one or more of the second layer modules; and similarly, an nth (n is a positive integer of 2 or more) layer module which is a higher-level circuit of the (n-1)th layer module formed by connecting one or more (n-1)th layer modules, Circuit layout means for laying out the circuits from the first layer module to the n layer modules, A first naming means that assigns a different name to each module from the first layer module to the nth layer module, and assigns a different name to each of the wires used for connecting each layer module and for connecting circuits within the first layer module. A second naming means that assigns the names given to the wiring within the first layer module to the multiple terminals connected by the wiring as the names of those terminals, and also assigns names to the wiring that extends from the terminals within the first layer module to the boundary of the first layer module. A layout image for LVS verification to indicate whether the wiring in the first layer module conforms to the netlist, wherein the layout image is created in which images of the instance cells and terminals in the first layer module and the names of the terminals assigned by the second naming means are drawn, but images of the wiring are not drawn, and a first output control means outputs this layout image to an output means. A hierarchical layout design program characterized by its function as such.

10. The aforementioned computer, A first layer module wiring verification means performs LVS verification to indicate whether the wiring in the first layer module conforms to a netlist, based on the terminal names assigned by the second naming means and the layout image of the instance cells and terminals in the first layer module created by the first output control means. The hierarchical layout design program according to claim 9, characterized in that it functions as such.

11. The hierarchical layout design program according to claim 9, characterized in that, when the first naming means configured by the computer assigns a name to the wiring connecting multiple terminals in a state where multiple terminals are connected by wiring in a state where multiple terminals are connected by wiring, the name of each layer module from the first layer module to the i (where i is a positive integer less than or equal to (n-1)) layer module to which the multiple terminals belong is listed side by side with the name of the wiring to be assigned to the wiring between the multiple terminals.

12. The hierarchical layout design program according to claim 11, characterized in that the first naming means configured by the computer arranges the names of each layer module from the top layer to the bottom layer, from the beginning to the end of the string, and separates between the names of each layer module and the names of the wiring.

13. The aforementioned computer, The hierarchical layout design program according to claim 11, characterized in that it receives instructions from an operator regarding which range of layers from the first layer module to the n layer modules to output, creates a single image information from the names assigned by the first naming means included in this range, the names assigned by the second naming means included in this range, and the layout image created by the first output control means, and functions as a second output control means that outputs this single image information to the output means.

14. The hierarchical layout design program according to claim 11, characterized in that, when a plurality of the first layer modules having the same layout with the same instance cell are connected to form the second layer module, the output control means configured by the computer performs layout wiring so that the wiring tracks match, creates image information, and outputs it to the output means.

15. The aforementioned computer, The hierarchical layout design program according to claim 11, characterized in that it functions as a layout wiring means that creates image information by performing layout wiring based on names assigned to multiple terminals and outputs it to an output means.

16. The hierarchical layout design program according to claim 15, characterized in that the layout wiring extending from terminals in the first layer module is cut at the boundary of the first layer module by the layout wiring means configured by the computer, thereby forming the layout wiring of the first layer module.

17. A hierarchical layout design method for a semiconductor integrated circuit comprising: a first layer module which is a circuit formed by connecting one or more instance cells; a second layer module which is a higher-level circuit of the first layer module formed by connecting one or more of the first layer modules; a third layer module which is a higher-level circuit of the second layer module formed by connecting one or more of the second layer modules; and similarly, an nth (n is a positive integer of 2 or more) layer module which is a higher-level circuit of the (n-1)th layer module formed by connecting one or more (n-1)th layer modules, A circuit layout step involves laying out the circuits from the first layer module to the n-th layer module, A first naming step involves assigning a different name to each module from the first layer module to the nth layer module, and assigning a different name to each of the wires used for connecting the layers modules and the circuits within the first layer module. A second naming step involves assigning the names given to the wiring within the first layer module to the multiple terminals connected by the wiring, and assigning names to the wiring that extends from the terminals within the first layer module to the boundary of the first layer module. A first output control step involves creating a layout image for LVS verification to indicate whether the wiring in the first layer module conforms to the netlist, the layout image which depicts images of the instance cells and terminals in the first layer module and the names of the terminals assigned by the second naming step, but does not depict images of the wiring, and outputting this layout image to an output means. A hierarchical layout design method characterized by comprising the following:

18. A first layer module wiring verification step, which performs LVS verification to indicate whether the wiring in the first layer module conforms to the netlist, based on the terminal names assigned in the second naming step and the layout image of the instance cells and terminals in the first layer module created in the first output control means step, The hierarchical layout design method according to claim 17, characterized by comprising the above.

19. The first naming step is characterized in that, when naming a wiring that connects multiple terminals in a state where multiple terminals are connected by wiring, in a state where the first layer module to the nth layer module exists, the naming is performed by listing the names of each layer module from the first layer module to the ith layer module (where i is a positive integer less than or equal to (n-1)) to which the multiple terminals belong, and the name of the wiring to be assigned to the wiring between the multiple terminals.

20. The hierarchical layout design method according to claim 19, characterized in that the first naming step involves arranging the names of each layer module from the top layer to the bottom layer, from the beginning to the end of the string, and affixing separators between the names of each layer module and between the names of the wiring.

21. The hierarchical layout design method according to claim 19, comprising: receiving instructions from an operator regarding which range of layers from the first layer module to the n layer modules to output; creating a single image information from the names assigned in the first naming step that are included in this range, the names assigned in the second naming step that are included in this range, and the layout image created in the first output control step; and outputting this single image information to an output means.

22. The hierarchical layout design method according to claim 19, characterized in that the output control step, when a second layer module is formed by connecting multiple first layer modules having the same layout with the same instance cell, performs layout wiring so that the wiring tracks match, creates image information, and outputs it to the output means.

23. The hierarchical layout design method according to claim 19, characterized by comprising a layout wiring step of creating image information by performing layout wiring according to names assigned to multiple terminals and outputting it to an output means.

24. The hierarchical layout design method according to claim 23, characterized in that the layout wiring step involves cutting the wiring extending from the terminals in the first layer module at the boundary of the first layer module to form the layout wiring of the first layer module.

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