Multilayer electronic components

Abstract

The present invention provides a multilayer electronic component with improved reliability, suppressed capacitance degradation, and reduced delamination and crack formation at the interface between the cover and capacitance forming sections. [Solution] A stacked electronic component according to one embodiment of the present invention includes a main body including a dielectric layer 111, a capacitance forming portion Ac including internal electrodes 121 and 122 arranged alternately with the dielectric layer in the thickness direction, and cover portions 112 and 113 arranged above and below the capacitance forming portion in the thickness direction, and an external electrode arranged on the main body, wherein the cover portion includes inner cover portions 112a and 113a adjacent to the capacitance forming portion and outer cover portions 112b and 113b adjacent to the outer surface of the cover portion, and when the average value of the long axis and short axis of the crystal grain is defined as the crystal grain size, and crystal grains with a crystal grain size of 500 nm or less are defined as first crystal grains and crystal grains with a crystal grain size of 1150 nm or more are defined as second crystal grains, the inner cover portion includes a plurality of first crystal grains and the outer cover portion includes a plurality of first crystal grains and a plurality of second crystal grains.

Description

[Technical Field]

[0001] This invention relates to a stacked electronic component. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC), a type of multilayer electronic component, is a chip-type capacitor that is mounted on the printed circuit boards of various electronic products such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and plays the role of charging or discharging electricity.

[0003] Multilayer ceramic capacitors offer the advantages of being small yet guaranteeing high capacitance and being easy to mount, making them suitable for use as components in various electronic devices. As computers, mobile devices, and other electronic equipment become smaller and more powerful, the demand for smaller and / or higher-capacitance multilayer ceramic capacitors is increasing.

[0004] Furthermore, as the operating environments for MLCCs become increasingly stringent, a higher level of reliability is required. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Korean Published Patent Gazette No. 10-2022-0057263 [Overview of the project] [Problems that the invention aims to solve]

[0006] One of the various objectives of the present invention is to provide a stacked electronic component with improved reliability.

[0007] One of the various objects of the present invention is to provide a multilayer electronic component in which a reduction in capacitance is suppressed.

[0008] One of the various objects of the present invention is to provide a multilayer electronic component in which the occurrence of delamination and cracks at the interface between the cover portion and the capacitance forming portion is suppressed.

[0009] However, the object of the present invention is not limited to the above-described content, and can be more easily understood in the process of explaining specific embodiments of the present invention.

Means for Solving the Problems

[0010] A multilayer electronic component according to an embodiment of the present invention includes a dielectric layer, a capacitance forming portion including internal electrodes alternately arranged with the dielectric layer in the thickness direction, and a main body including cover portions arranged above and below the capacitance forming portion in the thickness direction, and an external electrode arranged on the main body. The cover portion includes an inner cover portion adjacent to the capacitance forming portion and an outer cover portion adjacent to the outer surface of the cover portion. When the average value of the major axis length and the minor axis length of crystal grains is defined as the crystal grain size, crystal grains with a crystal grain size of 500 nm or less are defined as first crystal grains, and crystal grains with a crystal grain size of 1150 nm or more are defined as second crystal grains, the inner cover portion includes a plurality of first crystal grains, and the outer cover portion can include a plurality of first crystal grains and a plurality of second crystal grains.

[0011] A multilayer electronic component according to an embodiment of the present invention includes a dielectric layer, a capacitance forming portion including internal electrodes alternately arranged with the dielectric layer in the thickness direction, and a main body including cover portions arranged above and below the capacitance forming portion in the thickness direction, and an external electrode arranged on the main body. The cover portion includes an inner cover portion adjacent to the capacitance forming portion and an outer cover portion adjacent to the outer surface of the cover portion. When the average value of the major axis length and the minor axis length of crystal grains is defined as the crystal grain size, the outer cover portion can include a region where the standard deviation of the crystal grain size is two times or more larger than that of the inner cover portion.

Effects of the Invention

[0012] One of the various effects of the present invention is that by controlling the crystal grain size of the inner cover portion and the outer cover portion, it is possible to provide a stacked electronic component with improved reliability.

[0013] One of the various effects of the present invention is that it can provide a stacked electronic component with excellent capacity per unit volume.

[0014] One of the various effects of the present invention is the ability to provide a stacked electronic component in which delamination and crack formation are suppressed at the interface between the cover portion and the capacitance forming portion.

[0015] However, the diverse yet significant advantages and effects of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Brief explanation of the drawing]

[0016] [Figure 1] This is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view along the line I-I' in Figure 1. [Figure 3] This is a schematic cross-sectional view along the line II-II' in Figure 1. [Figure 4] This is a disassembled view of the main unit shown in Figure 1. [Figure 5] This is an enlarged view of region K in Figure 3. [Figure 6] This is a schematic, enlarged view of the K2 region in Figure 5. [Figure 7] This is a schematic, enlarged view of the K5 region in Figure 5. [Figure 8] This is a diagram illustrating the grain size of the crystals. [Figure 9] (a) is an image obtained by scanning the region corresponding to the K1 region in Figure 5 using an SEM, and (b) is an image obtained by scanning the region corresponding to the K2 region in Figure 5 using an SEM. [Figure 10] This is an image obtained by scanning the region corresponding to the K3 region in Figure 5 using an SEM. [Figure 11] (a) is an image scanned by SEM of the region corresponding to K4 in Figure 5, (b) is an image scanned by SEM of the region corresponding to K5 in Figure 5, (c) is an image scanned by SEM of the region corresponding to K6 in Figure 5, and (d) is an image scanned by SEM of the region corresponding to K7 in Figure 5. [Figure 12] This is a magnified image of the K8 region in Figure 10. [Figure 13] This drawing corresponds to Figure 3 of the first embodiment of the present invention. [Figure 14] This is a schematic perspective view of a stacked electronic component according to a second embodiment of the present invention. [Figure 15] This is the same as Figure 14, but with the external electrodes removed. [Figure 16] This is the same as Figure 15, but with the margins removed. [Figure 17] This is a schematic cross-sectional view along the line III-III' in Figure 14. [Modes for carrying out the invention]

[0017] Embodiments of the present invention will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present invention can be modified into several other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to give a more complete explanation of the present invention to a person of the ordinary skill. Accordingly, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for a clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0018] Furthermore, in order to clearly illustrate the present invention in the drawings, parts unrelated to the description have been omitted, and the size and thickness of each component shown are arbitrarily indicated for the convenience of explanation; therefore, the present invention is not necessarily limited by the illustrations. Also, components with the same function within the scope of the same concept are described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a certain component, unless otherwise stated to the contrary, it does not mean that other components are excluded, but rather that other components may be further included.

[0019] In drawings, the X direction can be defined as the first direction, the lamination direction, or the thickness (T) direction; the Y direction as the second direction or the length (L) direction; and the Z direction as the third direction or the width (W) direction.

[0020] Multilayer electronic components Figure 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention; Figure 2 is a schematic cross-sectional view along the line I-I' in Figure 1; Figure 3 is a schematic cross-sectional view along the line II-II' in Figure 1; Figure 4 is an exploded view of the main body of Figure 1; Figure 5 is an enlarged view of the K region in Figure 3; Figure 6 is a schematic enlarged view of the K2 region in Figure 5; Figure 7 is a schematic enlarged view of the K5 region in Figure 5; and Figure 8 is a diagram for explaining the crystal grain size.

[0021] The following describes in detail a multilayer electronic component 100 according to one embodiment of the present invention with reference to Figures 1 to 8. While a multilayer ceramic capacitor (MLCC) will be described as an example of a multilayer electronic component, the present invention is not limited to this and can be applied to various multilayer electronic components using ceramic materials, such as inductors, piezoelectric elements, varistors, or thermistors.

[0022] The length of the multilayer electronic component 100 may be greater than the width and thickness of the multilayer electronic component 100, but this disclosure is not limited thereto. For example, the length of the multilayer electronic component 100 may be shorter than the width of the multilayer electronic component 100. The width of the multilayer electronic component 100 may be less than or greater than the thickness of the multilayer electronic component 100, and this may vary depending on the target specifications and characteristics of the multilayer electronic component 100.

[0023] The length of the stacked electronic component 100 can be, for example, about 0.1 mm to 5.7 mm, the width of the stacked electronic component 100 can be, for example, about 0.05 mm to 5.0 mm, and the thickness of the stacked electronic component 100 can be, for example, about 0.05 mm to 5.0 mm.

[0024] An embodiment of the stacked electronic component 100 of this disclosure may include a main body 110 and external electrodes 131 and 132.

[0025] The main body 110 may include a dielectric layer 111 and internal electrodes 121 and 122 that are alternately arranged in the thickness direction with respect to the dielectric layer.

[0026] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be hexahedral or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 is not a perfectly straight hexahedron, but can be substantially hexahedral.

[0027] The main body 110 may have a first surface 1 and a second surface 2 facing each other in the thickness direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 facing each other in the length direction, a fifth surface 5 and a sixth surface 6 connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 facing each other in the width direction.

[0028] As margin regions where internal electrodes 121 and 122 are not placed overlap the dielectric layer 111, steps are created due to the thickness of the internal electrodes 121 and 122, and the corners connecting the first surface with the third, fourth, and fifth surfaces and / or the corners connecting the second surface with the third, fourth, and fifth surfaces may have a shape that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, due to the contraction behavior during the sintering process of the main body, the corners connecting the first surface 1 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 and / or the corners connecting the second surface 2 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 may have a shape that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, in order to prevent chipping defects, the corners connecting each face of the main body 110 can be rounded by performing a separate process to round the corners connecting the first face with the third, fourth, fifth, and sixth faces, and / or the corners connecting the second face with the third, fourth, fifth, and sixth faces.

[0029] On the other hand, in order to suppress the step difference caused by the internal electrodes 121 and 122, if the internal electrodes after lamination are cut so that they are exposed on the fifth surface 5 and sixth surface 6 of the main body, and then a single dielectric layer or two or more dielectric layers are laminated on both sides of the capacitance forming portion Ac in the third direction (width direction) to form side margin portions 114 and 115, the portions connecting the first surface with the fifth and sixth surfaces, and the portions connecting the second surface with the fifth and sixth surfaces, may not have a contracted form.

[0030] The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM). There is no particular limit to the number of dielectric layers stacked, and it can be determined considering the size of the multilayer electronic component. For example, the main body can be formed by stacking 400 or more dielectric layers.

[0031] The dielectric layer 111 can be formed by manufacturing a ceramic slurry containing ceramic powder, an organic solvent, and a binder, applying and drying the slurry on a carrier film to provide a ceramic green sheet, and then firing the ceramic green sheet. The ceramic powder is not particularly limited as long as sufficient capacitance can be obtained. For example, barium titanate-based (BaTiO3) powder can be used as the ceramic powder. More specifically, as the ceramic powder, barium titanate-based (BaTiO3) powder, normal dielectric powder of a CaZrO3 substrate, etc. can be used. More specifically, as the barium titanate-based (BaTiO3) powder, BaTiO3, (Ba 1-x Ca x )TiO3(0 < x < 1), Ba(Ti 1-y Ca y )O3(0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 < x < 1, 0 < y < 1), and Ba(Ti 1-y Zr y )O3(0 < y < 1) may be one or more of them, and the normal dielectric powder of the CaZrO3 substrate may be (Ca 1-x Sr x )(Zr 1-y Ti y )O3(0 < x < 1, 0 < y < 1).

[0032] In one embodiment, the dielectric layer 111 is BaTiO3, (Ba 1-x Ca x )TiO3(0 < x < 1), Ba(Ti 1-y Ca y )O3(0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3(0 < y < 1), and (Ca 1-x Sr x )(Zr 1-y Ti y)One or more of O3 (0 < x < 1, 0 < y < 1) can be included as a main component.

[0033] The main body 110 can include a dielectric layer 111, a capacitance forming portion Ac including internal electrodes 121 and 122 alternately arranged in the thickness direction with the dielectric layer, and cover portions 112 and 113 arranged above and below the capacitance forming portion in the thickness direction.

[0034] The cover portions 112 and 113 can include an upper cover portion 112 arranged above the capacitance forming portion Ac in the thickness direction and a lower cover portion 112 arranged below the capacitance forming portion Ac in the thickness direction.

[0035] Also, as a portion contributing to the formation of the capacitance of the capacitor, the capacitance forming portion Ac can be formed by repeatedly laminating a plurality of first internal electrodes 121 and second internal electrodes 122 with the dielectric layer 111 interposed therebetween. The lamination direction of the internal electrodes 121 and 122 can be the thickness direction or the width direction. In the present disclosure, an embodiment in which the lamination direction of the internal electrodes 121 and 122 is the thickness direction will be described as a reference.

[0036] The cover portions 112 and 113 can include inner cover portions 112a and 113a adjacent to the capacitance forming portion Ac and outer cover portions 112b and 113b adjacent to the outer surfaces of the cover portions 112 and 113.

[0037] In one embodiment, when the average value of the major axis length Lx and the minor axis length Sx of the crystal grains G is defined as the crystal grain size, the crystal grains with a crystal grain size of 500 nm or less are defined as first crystal grains G1, and the crystal grains with a crystal grain size of 1150 nm or more are defined as second crystal grains G2, the inner cover portions 112a and 113a include a plurality of first crystal grains G, and the outer cover portions 112b and 113b can include a plurality of first crystal grains G1 and a plurality of second crystal grains G2.

[0038] Referring to Figure 6, which shows an enlarged view of a portion of the cross-section of the inner cover portions 112a and 113a, the inner cover portions 112a and 113a, by containing multiple first crystal grains G1, can improve the bonding force with the capacitance forming portion Ac, thereby suppressing a decrease in the capacitance of the multilayer electronic component. Furthermore, by improving the interfacial bonding force between the capacitance forming portion Ac and the cover portions 112 and 113, delamination and interfacial cracking can be suppressed.

[0039] Referring to Figure 7, which shows an enlarged view of a portion of the cross-section of the outer cover portions 112b and 113b, the outer cover portions 112b and 113b are composed of a mixture of multiple first crystal grains G1 and multiple second crystal grains G2, which can block moisture from penetrating from the outside and improve moisture resistance reliability. In addition, it can increase the crack propagation path when cracks occur, thereby improving bending strength.

[0040] Referring to Figure 8, the grain size in this disclosure can mean the average value of the major axis length Lx and minor axis length Sx of the crystal grain G. The major axis length Lx of the crystal grain can mean the length of the longest straight line connecting two points that constitute the outer edge of the crystal grain G, the minor axis length Sx of the crystal grain can mean the length of the longest straight line perpendicular to the major axis of the crystal grain and connecting two points that constitute the outer edge of the crystal grain G, and the average value can mean the arithmetic mean.

[0041] The first crystal grain G1 has a typical grain size of 500 nm or less, while the second crystal grain G2 has a large grain size of 1150 nm or more. The second crystal grain G2 may be formed by abnormal grain growth. Abnormal grain growth refers to the phenomenon in which some crystal grains grow abnormally larger than the surrounding crystal grains during the sintering process. The inner cover portions 112a and 113a contain first crystal grains G1 with typical grain sizes due to normal grain growth, but the outer cover portions 112b and 113b contain a mixture of multiple first crystal grains G1 and multiple second crystal grains G2 due to abnormal grain growth, where some crystal grains grow abnormally larger than the surrounding crystal grains.

[0042] The formation of second crystal grains G2 due to abnormal crystal grain growth generally has side effects such as a decrease in dielectric constant, a decrease in insulation resistance, and a decrease in reliability, and it has been common practice to suppress its formation. However, these side effects mostly occur when abnormal crystal grain growth occurs in the dielectric layer or cover portion within the capacitance-forming portion Ac, specifically in a region adjacent to the capacitance-forming portion Ac. In the case of the outer cover portions 112b and 113b, even if second crystal grains G2 are formed, side effects such as a decrease in dielectric constant, a decrease in insulation resistance, and a decrease in reliability do not occur. On the contrary, the presence of a mixture of multiple first crystal grains G1 and multiple second crystal grains G2 in the outer cover portions 112b and 113b can block moisture penetrating from the outside, thereby improving moisture resistance reliability.

[0043] Furthermore, by including multiple first crystal grains G1 in the inner cover portions 112a and 113a, the bonding force with the capacitance forming portion Ac can be improved, thereby suppressing a decrease in the capacitance of the stacked electronic component.

[0044] In one embodiment, the inner cover portions 112a and 113a may have an average crystal grain size of 300 nm or less. This can further improve the bonding strength with the capacitance forming portion Ac, and further suppress the decrease in capacitance of the multilayer electronic component.

[0045] Here, the average grain size may be the arithmetic mean of the grain sizes of 100 or more grains.

[0046] On the other hand, the average size of the crystal grains contained in the outer cover portions 112b and 113b may be larger than the average crystal grain size of the inner cover portions 112a and 113a. For example, the average size of the crystal grains contained in the outer cover portions 112b and 113b can be 350 nm or more. However, since the outer cover portions 112b and 113b contain multiple first crystal grains G1 as well as second crystal grains G2, the average size of the crystal grains contained in the outer cover portions 112b and 113b and the average crystal grain size of the inner cover portions 112a and 113a may not differ significantly. For example, the average size of the crystal grains contained in the outer cover portions 112b and 113b may be twice or less the average crystal grain size of the inner cover portions 112a and 113a.

[0047] In one embodiment, the outer cover portions 112b and 113b may include regions where the standard deviation of the crystal grain size is at least twice that of the inner cover portion. The inner cover portions 112a and 113a, having a uniform crystal grain size, can improve the bonding strength with the capacitance forming portion Ac, thereby suppressing a decrease in the capacitance of the stacked electronic component. The outer cover portions 112b and 113b, having a non-uniform crystal grain size, can block moisture penetrating from the outside, thereby improving moisture resistance reliability. In this case, the outer cover portions 112b and 113b may include crystal grains with a crystal grain size of 1150 nm or more.

[0048] In one embodiment, the region of the cover portions 112 and 113 within 20 μm of the volume-forming portion Ac may have a standard deviation of crystal grain size that is more than twice that of the region of the cover portions 112 and 113 within 20 μm of the outer surface of the cover portions.

[0049] As described above, the average grain size of the crystal grains contained in the outer cover portions 112b and 113b may not differ significantly from that of the inner cover portions 112a and 113a. However, since the outer cover portions 112b and 113b contain multiple first crystal grains G1 and multiple second crystal grains G2, the standard deviation of the crystal grain size may differ significantly.

[0050] In one embodiment, the inner cover portions 112a and 113a may have a standard deviation of crystal grain size of 130 nm or less. This allows the inner cover portions 112a and 113a to have a uniform crystal grain size, which can further improve the bonding strength with the capacitance forming portion Ac and further suppress the decrease in capacitance of the multilayer electronic component.

[0051] In one embodiment, the outer cover portions 112b and 113b may have a standard deviation of grain size of 260 nm or more. This allows the outer cover portions 112b and 113b to have non-uniform grain sizes, enabling the formation of longer and more complex moisture penetration pathways and / or crack propagation pathways, thereby improving moisture resistance reliability and flexural strength.

[0052] Here, the standard deviation of crystal grain size may be a value obtained using the STDEV.P function (sample standard deviation) in Excel from the crystal grain sizes of 100 or more crystal grains.

[0053] On the other hand, it is not necessary for all crystal grains contained in the inner cover portions 112a and 113a to be first crystal grains of 500 nm or less; some large crystal grains may be included. However, it is preferable that the maximum size of the crystal grains contained in the inner cover portions 112a and 113a is 1100 nm or less.

[0054] If a second crystal grain G2 is formed in the inner cover portions 112a and 113a due to abnormal crystal grain growth, abnormal crystal grain growth may also occur in the dielectric layer 111 of the capacitance-forming portion Ac, potentially leading to a decrease in capacitance or a deterioration of the bonding strength between the capacitance-forming portion Ac and the dielectric layer 111.

[0055] In one embodiment, the maximum size of the crystal grains contained in the outer cover portions 112b and 113b may be 2300 nm or larger. Abnormal grain growth can form in the outer cover portions 112b and 113b, resulting in crystal grains of 2300 nm or larger, and even larger crystal grains of 4000 nm or larger can be observed.

[0056] In one embodiment, in the cross-section of the outer cover portions 112b and 113b in the thickness and width directions, the area ratio occupied by multiple second crystal grains G2 relative to the area of ​​the outer cover portions 112b and 113b may be 50% or more and 95% or less. Even if the number of first crystal grains G1 is greater than the number of second crystal grains G2, the area ratio occupied by multiple second crystal grains G2 can be 50% or more because the crystal grain size of the second crystal grains is large, thereby further improving moisture resistance reliability. However, if the area ratio occupied by multiple second crystal grains G2 exceeds 95%, the non-uniformity of the crystal grain size of the outer cover portions 112b and 113b will decrease, and there is a risk of crack generation due to external stress.

[0057] In one embodiment, in the cross-section of the inner cover portions 112a and 113a in the thickness and width directions, the area ratio of the first crystal grain G1 to the area of ​​the inner cover portions 112a and 113a may be 90% or more.

[0058] The crystal grains contained in the inner cover portions 112a and 113a do not all need to be first crystal grains of 500 nm or less; some large crystal grains may be included. However, when the area ratio of the first crystal grain G1 to the area of ​​the inner cover portions 112a and 113a is 90% or more, the bonding strength between the inner cover portions 112a and 113a and the capacitance forming portion Ac can be further improved, and the decrease in capacitance of the multilayer electronic component can be further suppressed.

[0059] In one embodiment, the ratio of the average thickness tco of the outer cover portion to the average thickness tc of the cover portions 112 and 113 (tco / tc) may be 50% or more and 80% or less. This makes it possible to further improve the bonding strength between the cover portions 112 and 113 and the volume-forming portion Ac according to the present invention, the effect of suppressing volume reduction, the effect of improving moisture resistance reliability, and the effect of improving bending strength.

[0060] The average thickness tc of the cover portions 112 and 113 may be, for example, 150 μm or less, 100 μm or less, 30 μm or less, or 20 μm or less. The average thickness tc of the cover portions 112 and 113 may be, for example, 5 μm or more or 10 μm or more. The average thickness tc of the cover portions 112 and 113 refers to the average thickness of the upper cover portion 112 and the lower cover portion 113, respectively.

[0061] In Figure 9, (a) is an image obtained by scanning the region corresponding to the K1 region in Figure 5 using an SEM, and (b) is an image obtained by scanning the region corresponding to the K2 region in Figure 5 using an SEM.

[0062] Figure 10 is an image obtained by scanning the region corresponding to the K3 region in Figure 5 using an SEM.

[0063] In Figure 11, (a) is an image scanned by SEM of the region corresponding to K4 in Figure 5, (b) is an image scanned by SEM of the region corresponding to K5 in Figure 5, (c) is an image scanned by SEM of the region corresponding to K6 in Figure 5, and (d) is an image scanned by SEM of the region corresponding to K7 in Figure 5.

[0064] Table 1 below shows the average grain size (Avg), standard deviation (Stdev), and maximum grain size (Max) for the K1-K7 region.

[0065] [Table 1]

[0066] To explain how the images in Figures 9 to 12 were obtained, first, the stacked electronic component 100 is polished up to the center in the length direction to expose the cross-section in the thickness and width directions. After this, the region corresponding to K1 to K7 from the capacitance formation part to the outer shell in the region corresponding to Figure 5 is scanned with a scanning electron microscope to obtain an image. The images in Figures 9 to 11 are images obtained by scanning a region of 22 μm × 22 μm, respectively. After this, the grain size can be determined from each image using an image analysis program such as ImageJ. In the images in Figures 9 to 11, the grains shown in color are the grains whose grain size was measured, with the closer to yellow being the smaller the grain size and the closer to red being the larger the grain size. In this way, by using an image analysis program, it is possible to obtain data on grain size by calculating the average values ​​of the major axis length Lx and minor axis length Sx of each grain, and as shown in Figures 9 to 11, the grain size can be distinguished by color, making it easy to analyze the grain size. On the other hand, crystal grains in which only a portion was scanned were excluded, and in Figure 9(a), which is the K1 region, crystal grains in the volume-forming region were excluded. Thus, crystal grains excluded from the crystal grain size analysis were not given a separate color in Figures 9 to 11.

[0067] Referring to Figure 9, it can be confirmed that in the inner cover portions 112a and 113a, K1 and K2, adjacent to the volume formation portion, the grain size is uniform and no large grains are observed. Furthermore, referring to Table 1 above, it can be confirmed that K1 and K2 consist of uniform grains, with an average grain size (Avg) of 300 nm or less and a standard deviation (Stdev) of grain size of 130 nm or less. While K1 and K2 are mostly composed of first grains, there is one instance with a maximum grain size of 1077 nm, indicating the presence of some large grains. However, no second grains larger than 1150 nm were observed.

[0068] Figure 10 corresponds to the K3 region, where all of the inner cover portions 112a, 113a and the outer cover portions 112b, 113b are observed, and large second crystal grains begin to be observed. Referring to Figure 12, which is an enlarged image of the K8 region in Figure 10, the boundary IF of the inner cover portions 112a, 113a and the outer cover portions 112a, 113a can be determined by connecting the second crystal grains G2-1, G2-2, G2-3, and G2-4 adjacent to the inner cover portions along the shortest path along the grain boundary.

[0069] Based on the boundary IF determined in this way, the average thickness tco of the outer cover portion can be obtained by averaging the thicknesses of the outer cover portions 112b and 113b measured at 10 points equally spaced in the width direction, the average thickness tci of the inner cover portion can be obtained by averaging the thicknesses of the inner cover portions 112a and 113a, and the average thickness tc of the cover portions 112b and 113b can be obtained by averaging the thicknesses of the cover portions 112 and 113. In this case, tco, tci, and tc may be measured at either the upper cover portion 112 or the lower cover portion 113. However, it is not limited to this, and may be an average of the values ​​measured at the upper cover portion 112 and the lower cover portion 113.

[0070] Referring to Figure 11, it can be confirmed that in the outer cover portions 112b and 113b, K4 to K7, multiple first grains G1 with a grain size of 500 nm or less and multiple second grains G2 with a grain size of 1150 nm or more are observed. Excluding the last region, K7, there is a tendency for the average grain size (Avg), standard deviation of grain size (Stdev), and maximum grain size (Max) to increase towards the outer surface of the cover portion.

[0071] In samples K4 and K5, grains with a maximum size (Max) of 3000 nm or more were observed, and in samples K6 and K7, grains with a maximum size (Max) of 4000 nm or more were observed, clearly indicating the occurrence of abnormal grain growth.

[0072] On the other hand, the method for manufacturing the cover portions 112 and 113 according to the present invention is not particularly limited. The cover portions 112 and 113 according to the present invention can be manufactured by adjusting the sintering temperature, sintering time, additives, etc., which are the main causes of abnormal grain growth.

[0073] For example, by adding Dy as an additive to the cover portions 112 and 113 and appropriately adjusting the sintering temperature and sintering time, abnormal grain growth can be induced only in the outer cover portions 112b and 113b.

[0074] In one embodiment, the number of Dy moles per 100 moles of Ti in the cover portions 112 and 113 may be 3.7 to 4.5. Dy is generally known to suppress grain growth when added to dielectric compositions. However, in one embodiment of the present invention, when a large amount of Dy is added to the cover portions 112 and 113 such that the number of Dy moles per 100 moles of Ti is 3.7 to 4.5, abnormal grain growth can be induced in the outer cover portions 112b and 113b, while uniform grain growth can be induced in the inner cover portions 112a and 113a.

[0075] To give a specific example, the cover parts 112 and 113 can be formed by manufacturing a ceramic slurry containing ceramic powder, an organic solvent, a binder, and an additive containing Dy, applying the slurry to a carrier film and drying it to form a ceramic green sheet, and then firing the ceramic green sheet. The ceramic powder is not particularly limited as long as sufficient capacitance can be obtained, but for example, barium titanate (BaTiO3) powder can be used as the ceramic powder. To give a more specific example, the ceramic powder can be barium titanate (BaTiO3) powder, a paraelectric powder based on CaZrO3, etc. To give a more specific example, the barium titanate (BaTiO3) powder can be BaTiO3, (Ba 1-x Ca x )TiO3(0 <x<1)、Ba(Ti 1-y Ca y )O3(0 <y<1)、(Ba1-x Ca x )(Ti 1-y Zr y )O3(0 < x < 1, 0 < y < 1) and Ba(Ti 1-y Zr y )O3(0 < y < 1) may be one or more of them, and the normal dielectric powder of the CaZrO3 substrate is (Ca 1-x Sr x )(Zr 1-y Ti y )O3(0 < x < 1, 0 < y < 1). Dy can be added in the form of Dy2O3 and can be added so that the number of moles of Dy is 3.7 - 4.5 with respect to 100 moles of Ti.

[0076] Therefore, the cover parts 112, 113 are BaTiO3, (Ba 1-x Ca x )TiO3(0 < x < 1), Ba(Ti 1-y Ca y )O3(0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3(0 < y < 1) and (Ca 1-x Sr x )(Zr 1-y Ti y )O3(0 < x < 1, 0 < y < 1), containing one or more of them as the main component and containing 3.7 - 4.5 moles of Dy with respect to 100 moles of Ti as the sub - component.

[0077] Also, the cover parts 112, 113 can contain Dy, Mg, Mn, and Si as additives, and with respect to 100 moles of Ti, the number of moles of Dy can satisfy 3.7 - 4.5, the number of moles of Mg can satisfy 0.18 - 0.22, the number of moles of Mn can satisfy 0.225 - 0.275, and the number of moles of Si can satisfy 1.17 - 1.43.

[0078] Furthermore, the cover portions 112 and 113 may further contain Ba as an additive, and the number of moles of Ba added as an additive per 100 moles of Ti may be 0.63 to 0.77.

[0079] Furthermore, as a more specific example of a method for measuring the elemental content of any one component of the stacked electronic component 100 in the present invention, the components can be analyzed using the energy dispersive X-ray spectroscopy (EDS) mode of a scanning electron microscope (SEM), the EDS mode of a transmission electron microscope (TEM), or the EDS mode of a scanning transmission electron microscope (STEM). First, an analytical sample is prepared by thinning it using a focused ion beam (FIB) in the area to be measured. Then, the damaged layer on the surface of the thinned sample is removed using xenon (Xe) or argon (Ar) ion milling, and after that, each component to be measured is mapped using an image obtained with SEM-EDS, TEM-EDS, or STEM-EDS to perform qualitative / quantitative analysis. In this case, the qualitative / quantitative analysis of each component can be expressed in terms of the content of each element, for example, by mass percentage (wt%), atomic percentage (at%), or mole percentage (mol%), or in terms of the content of other specific components relative to the content of a particular component.

[0080] Another method involves crushing the chip to select the region to be measured, and then analyzing the specific components of the selected region containing dielectric microstructure using instruments such as an inductively coupled plasma spectrometer (ICP-OES) or inductively coupled plasma mass spectrometer (ICP-MS).

[0081] In one embodiment, the dielectric layer 111 contains a plurality of first crystal grains G1, and the average value of the crystal grain size may be 300 nm or less. By having a crystal grain structure similar to that of the inner cover portions 112a and 113a, the interfacial bonding force between the capacitance forming portion Ac and the cover portions 112 and 113 can be improved, thereby suppressing delamination and interfacial cracking.

[0082] In one embodiment, the dielectric layer 111 may have a Dy mole count of 3.7 to 4.5 per 100 moles of Ti. By having a dielectric layer 111 with a composition similar to that of the inner cover portions 112a and 113a, the interfacial bonding force between the capacitance-forming portion Ac and the cover portions 112 and 113 can be further improved, thereby further enhancing the effect of suppressing delamination and interfacial cracks. Furthermore, the dielectric layer can be formed using a ceramic green sheet for forming the cover portions 112 and 113, thereby simplifying the process.

[0083] In this case, the dielectric layer 111 may have a ratio of 3.7 to 4.5 moles of Dy, 0.18 to 0.22 moles of Mg, 0.225 to 0.275 moles of Mn, and 1.17 to 1.43 moles of Si per 100 moles of Ti. Furthermore, the dielectric layer 111 may further contain Ba as an additive, with a ratio of 0.63 to 0.77 moles of Ba added as an additive per 100 moles of Ti.

[0084] Margin portions 114 and 115 can be arranged on the side surface of the volume-forming portion Ac.

[0085] The margin portions 114 and 115 may include a first margin portion 114 located on the fifth surface of the main body 110 and a second margin portion 115 located on the sixth surface. That is, the margin portions 114 and 115 can be located on both end surfaces in the width direction of the ceramic main body 110.

[0086] The margin portions 114 and 115 can refer to the regions between the interface between both ends of the first internal electrode 121 and the second internal electrode 122 and the body 110 in a cross-section obtained by cutting the body 110 in the width-thickness (WT) direction.

[0087] The margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0088] The margin portions 114 and 115 may be formed by applying conductive paste to the ceramic green sheet, except where the margin portions are formed, to form internal electrodes.

[0089] Furthermore, in order to suppress the step caused by the internal electrodes 121 and 122, after cutting the laminated internal electrodes so that they are exposed on the fifth and sixth surfaces 5 and 6 of the main body, a single dielectric layer or two or more dielectric layers can be laminated in the third direction (width direction) on both sides of the capacitance forming portion Ac to form margin portions 114 and 115.

[0090] On the other hand, the width wm of the margin portions 114 and 115 does not need to be particularly limited. The average width of the margin portions 114 and 115 may be, for example, 150 μm or less, 100 μm or less, 20 μm or less, or 15 μm or less. The average width of the margin portions 114 and 115 may be, for example, 5 μm or more or 10 μm or more. The average width of the margin portions 114 and 115 refers to the average width of the first margin portion 114 and the second margin portion 115, respectively. The average width of the margin portions 114 and 115 may be the average value of the widths measured at five equally spaced points in the thickness direction in the cross-section of the multilayer electronic component 100 in the width direction and thickness direction.

[0091] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122. The first internal electrode 121 and the second internal electrode 122 are arranged alternately so as to face each other across the dielectric layer 111 that constitutes the main body 110, and can be exposed on the third surface 3 and the fourth surface 4 of the main body 110, respectively.

[0092] The first internal electrode 121 is separated from the fourth surface 4 and exposed via the third surface 3, and the second internal electrode 122 can be separated from the third surface 3 and exposed via the fourth surface 4. The first external electrode 131 is positioned on the third surface 3 of the main body and connected to the first internal electrode 121, and the second external electrode 132 is positioned on the fourth surface 4 of the main body and connected to the second internal electrode 122.

[0093] In other words, the first internal electrode 121 is not connected to the second external electrode 132, but is connected to the first external electrode 131, and the second internal electrode 122 is not connected to the first external electrode 131, but is connected to the second external electrode 132. Therefore, the first internal electrode 121 can be formed at a certain distance from the fourth surface 4, and the second internal electrode 122 can be formed at a certain distance from the third surface 3. Furthermore, the first internal electrode 121 and the second internal electrode 122 may be arranged at a distance from the fifth and sixth surfaces of the main body 110.

[0094] The conductive metals contained in the internal electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, In, Sn, Al, W, Ti, and alloys thereof, but the present invention is not limited thereto.

[0095] The average thickness td of the dielectric layer 111 does not need to be particularly limited, but can be, for example, 0.1 μm to 10 μm. The average thickness te of the internal electrodes 121 and 122 does not need to be particularly limited, but can be, for example, 0.05 μm to 3.0 μm. Furthermore, the average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 can be arbitrarily set according to the desired characteristics and application. For example, in the case of electronic components for high-voltage electrical equipment to achieve miniaturization and high capacitance, the average thickness td of the dielectric layer 111 can be less than 2.8 μm, and the average thickness te of the internal electrodes 121 and 122 can be less than 1 μm. Also, in the case of electronic components for small IT to achieve miniaturization and high capacitance, the average thickness td of the dielectric layer 111 can be 0.4 μm or less, and the average thickness te of the internal electrodes 121 and 122 can be 0.4 μm or less.

[0096] The average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 refer to the dimensions of the dielectric layer 111 and the internal electrodes 121 and 122 in the first direction, respectively. The average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 can be measured by scanning the cross-sections of the main body 110 in the first and second directions with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the average thickness td of the dielectric layer 111 can be measured by taking the average value of the thickness at multiple points on one dielectric layer 111, for example, 30 points equally spaced in the second direction. Similarly, the average thickness te of the internal electrodes 121 and 122 can be measured by taking the average value of the thickness at multiple points on one internal electrode 121 or 122, for example, 30 points equally spaced in the second direction. The 30 equally spaced points can be specified in the capacitance forming section Ac. On the other hand, if such average value measurements are performed on 10 dielectric layers 111 and 10 internal electrodes 121 and 122, and then the average value is measured, the average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 can be further generalized.

[0097] External electrodes 131 and 132 can be arranged on the third surface 3 and fourth surface 4 of the main body 110.

[0098] The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132, which are arranged on the third surface 3 and fourth surface 4 of the main body 110, respectively, and connected to a first internal electrode 121 and a second internal electrode 122, respectively.

[0099] Referring to Figure 1, the external electrodes 131 and 132 can be positioned to cover both end faces of the margin portions 114 and 115 in the second direction.

[0100] In this embodiment, a structure in which the stacked electronic component 100 has two external electrodes 131 and 132 is described, but the number and shape of the external electrodes 131 and 132 can be changed depending on the form of the internal electrodes 121 and 122 and other purposes.

[0101] On the other hand, the external electrodes 131 and 132 can be formed using any material that has electrical conductivity, such as metal, and the specific material can be determined by considering electrical properties, structural stability, etc. Furthermore, they can have a multilayer structure.

[0102] For example, the external electrodes 131 and 132 may include electrode layers 131a and 132a placed on the main body 110, and plating layers 131b and 132b formed on the electrode layers 131a and 132a.

[0103] To give a more specific example for the electrode layers 131a and 132a, the electrode layers 131a and 132a may be firing electrodes containing a conductive metal and glass, or resin-based electrodes containing a conductive metal and resin.

[0104] Furthermore, the electrode layers 131a and 132a may be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body. Alternatively, the electrode layers 131a and 132a may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto the fired electrode.

[0105] The conductive metal contained in the electrode layers 131a and 132a can be any material with excellent electrical conductivity, but is not particularly limited. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and their alloys.

[0106] The plating layers 131b and 132b play a role in improving mounting characteristics. The types of plating layers 131b and 132b are not particularly limited and can be plating layers containing one or more of Ni, Sn, Pd, and their alloys, and can be formed in multiple layers.

[0107] To give a more specific example for the plating layers 131b and 132b, the plating layers 131b and 132b may be Ni plating layers or Sn plating layers, and may be in a form in which Ni plating layers and Sn plating layers are formed sequentially on the electrode layers 131a and 132a, or may be in a form in which Sn plating layers, Ni plating layers and Sn plating layers are formed sequentially. Furthermore, the plating layers 131b and 132b may include multiple Ni plating layers and / or multiple Sn plating layers.

[0108] Figure 13 is a drawing corresponding to Figure 3, which relates to the first embodiment of the present invention.

[0109] Referring to Figure 13, the volume forming portion Ac includes margin portions 114' and 115' arranged on both sides in the width direction, and these margin portions 114' and 115' may include inner margin portions 114a' and 115a' adjacent to the volume forming portion, and outer margin portions 114b' and 115b' adjacent to the outer surface of the margin portions.

[0110] In one embodiment, the inner margin portions 114a' and 115a' may contain a plurality of the first crystal grains G1, and the outer margin portions 114b' and 115b' may each contain a plurality of the first crystal grains G1 and the second crystal grains G2. This can further improve the moisture resistance reliability of the stacked electronic component.

[0111] In one embodiment, the average grain size of the inner margin portions 114a' and 115a' may be 300 nm or less.

[0112] In one embodiment, the ratio of the average width wmo of the outer margin portions 114b' and 115b' to the average width wm of the margin portions 114' and 115' may be 50% or more and 80% or less. This can further improve the bonding strength between the margin portions 114' and 115' and the volume-forming portion Ac, the volume reduction suppression effect, the moisture resistance reliability improvement effect, the bending strength improvement effect, and so on.

[0113] The average width of the outer margin portions 114b' and 115b', measured at 10 points equally spaced in the thickness direction, can be defined as wmo, the average width of the inner margin portions 114a' and 115a', the average width of the inner margin portions 114a' and 115a', the average width of the inner margin portions 114a' and 115a', and the average width of the margin portions 114' and 115', the average width of the margin portions 114' and 115', can be defined as wm. In this case, wmo, wmi, and wm may be measured at either the first margin portion 114' or the second margin portion 115'. However, it is not limited to this, and may be the average of the values ​​measured at the first margin portion 114' and the second margin portion 115'.

[0114] The margin portions 114' and 115' may be formed by applying a conductive paste to a ceramic green sheet having the same composition as the ceramic green sheet used to form the cover portions 112 and 113, except where the margin portions are formed, to form internal electrodes. In this case, the dielectric layer 111' and the margin portions 114' and 115' can have the same or similar composition as the cover portions 112 and 113. For example, the dielectric layer 111' and the margin portions 114' and 115' may have a Dy mole count of 3.7 to 4.5 per 100 moles of Ti. Alternatively, the dielectric layer 111' and the margin portions 114' and 115' may have a Dy mole count of 3.7 to 4.5 per 100 moles of Ti, a Mg mole count of 0.18 to 0.22, a Mn mole count of 0.225 to 0.275, and a Si mole count of 1.17 to 1.43 per 100 moles of Ti. Furthermore, the dielectric layer 111' and the margin portions 114' and 115' may further contain Ba as an additive, and the number of moles of Ba added as an additive per 100 moles of Ti may be 0.63 to 0.77.

[0115] In one embodiment, the outer margin portions 114b' and 115b' may include regions where the standard deviation of the crystal grain size is at least twice that of the inner margin portions 114a' and 115a'. This can further improve the moisture resistance reliability of the multilayer electronic component.

[0116] In this case, the outer margin portions 114b' and 115b' may contain crystal grains with a grain size of 1150 nm or larger.

[0117] In one embodiment, the region of the margin portions 114' and 115' within 20 μm from the volume-forming portion may have a standard deviation of crystal grain size that is more than twice that of the region of the margin portions 114' and 115' within 20 μm from the outer surface of the margin portion.

[0118] In one embodiment, the inner margin portions 114a' and 115a' may have a standard deviation of crystal grain size of 130 nm or less.

[0119] In one embodiment, the outer margin portions 114b' and 115b' may have a standard deviation of crystal grain size of 260 nm or more.

[0120] Figure 14 schematically shows a perspective view of a stacked electronic component according to a second embodiment of the present invention, Figure 15 is shown from Figure 14 with the external electrodes removed, Figure 16 is shown from Figure 15 with the margin removed, and Figure 17 schematically shows a cross-sectional view along line III-III' from Figure 14.

[0121] Referring to Figures 14 to 17, the stacked electronic component 100 according to the second embodiment of the present invention includes margin portions 114" and 115" arranged on both sides in the width direction of the capacitance forming portion Ac, and the margin portions 114" and 115" may include inner margin portions 114a" and 115a" adjacent to the capacitance forming portion and outer margin portions 114b" and 115b" adjacent to the outer surface of the margin portions.

[0122] In one embodiment, the inner margin portions 114a'' and 115a'' contain a plurality of the first crystal grains G1, and the outer margin portions 114b'' and 115b'' each contain a plurality of the first crystal grains G1 and the second crystal grains G2. This makes it possible to further improve the moisture resistance reliability of the stacked electronic component.

[0123] In a second embodiment of the present invention, the stacked electronic component 100" may be formed by cutting the stacked internal electrodes 121 and 122 so that they are exposed on the fifth and sixth surfaces 5 and 6 of the main body 110" in order to suppress steps caused by the internal electrodes 121 and 122, and then stacking a single dielectric layer or two or more dielectric layers on both sides of the capacitance forming portion Ac in the third direction (width direction) to form margin portions 114" and 115". In this case, the first internal electrode 121 may be exposed on the third, fifth and sixth surfaces of the main body 110", and the second internal electrode 122 may be exposed on the fourth, fifth and sixth surfaces of the main body 110".

[0124] The cover portions 112" and 113" include inner cover portions 112a" and 113a" and outer cover portions 112b" and 113b", and include the features of the embodiments described above, but unlike the embodiments described above, they can have a configuration in which both sides of the width direction of the cover portions 112" and 113" are covered by margin portions 114" and 115".

[0125] In this case, the average grain size of the inner margin portions 114a" and 115a" may be 300 nm or less. Also, the ratio of the average width of the outer margin portions 114b" and 115b" to the average width of the margin portions 114" and 115" may be 50% or more and 80% or less.

[0126] The margin portions 114" and 115" can be formed by laminating ceramic green sheets having the same composition as the ceramic green sheets used to form the cover portions 112" and 113" in the width direction on the fifth and sixth surfaces of the main body 110". In this case, the margin portions 114" and 115" can have the same or similar composition as the cover portions 112" and 113". For example, the margin portions 114" and 115" may have a Dy mole count of 3.7 to 4.5 per 100 moles of Ti. Also, the margin portions 114" and 115" may have a Dy mole count of 3.7 to 4.5 per 100 moles of Ti, a Mg mole count of 0.18 to 0.22, a Mn mole count of 0.225 to 0.275, and a Si mole count of 1.17 to 1.43 per 100 moles of Ti. Furthermore, the margin portions 114" and 115" may further contain Ba as an additive, and Ti The number of moles of Ba added as an additive per 100 moles may be between 0.63 and 0.77.

[0127] On the other hand, the dielectric layer 111" can have a different composition from the margin portions 114", 115" and the cover portions 112", 113".

[0128] For example, the margin portions 114" and 115" and the cover portions 112" and 113" each have a Dy mole count of 3.7 to 4.5 per 100 moles of Ti, while the dielectric layer 111" may have a Dy mole count of less than 3.7 per 100 moles of Ti. If a large amount of Dy is included, the capacitance may decrease, but according to this embodiment, the capacitance of the multilayer electronic component can be further improved by lowering the Dy content in the dielectric layer 111".

[0129] To ensure that the dielectric layer 111" has a different composition from the margin portions 114", 115" and the cover portions 112", 113", the dielectric layer 111" can be formed using a ceramic green sheet having a different composition from the ceramic green sheet used to form the margin portions 114", 115" and the cover portions 112", 113". In this case, because the dielectric layer 111" and the margin portions 114", 115" and the cover portions 112", 113" have different shrinkage rates, the chip shape may be convex or concave. In this case, by further including Ga in the ceramic green sheet used to form the margin portions 114", 115" and the cover portions 112", 113", the chip shape may be convex or concave. Therefore, in one embodiment, the margin portions 114", 115" and the cover portions 112", 113" may further contain Ga.

[0130] In one embodiment, the outer margin portions 114b'' and 115b'' may include regions where the standard deviation of the crystal grain size is at least twice that of the inner margin portions 114a'' and 115a''. This can further improve the moisture resistance reliability of the multilayer electronic component.

[0131] In one embodiment, the region of the margin portions 114" and 115" within 20 μm from the volume-forming portion may have a standard deviation of crystal grain size that is more than twice that of the region of the margin portions 114" and 115" within 20 μm from the outer surface of the margin portion.

[0132] In one embodiment, the inner margin portions 114a'' and 115a'' may have a standard deviation of crystal grain size of 130 nm or less.

[0133] In one embodiment, the outer margin portions 114b'' and 115b'' may have a standard deviation of grain size of 260 nm or more.

[0134] (Example of experiment) A ceramic slurry containing BaTiO3 powder, an organic solvent, a binder, and additives was prepared. The slurry was then applied to a carrier film and dried to prepare a ceramic green sheet. The additives were added in the following proportions per 100 moles of Ti in the BaTiO3 powder: 0.2 moles of Mg, 4.1 moles of Dy, 0.25 moles of Mn, 0.7 moles of Ba, and 1.3 moles of Si.

[0135] After applying the internal electrode paste onto the ceramic green sheet, it was laminated to form a volume-forming section, and the ceramic green sheet was laminated above and below the volume-forming section to form a laminate.

[0136] The laminate was cut to a predetermined chip size, and the cut chips were fired to form the main body 110. Next, external electrodes 131 and 132 were formed to produce a sample chip.

[0137] At this time, the sintering temperature and sintering time were adjusted so that the ratio of the average thickness tco of the outer cover portion to the average thickness tc of the cover portions 112 and 113 (tco / tc) satisfies Table 2 below.

[0138] For humidity resistance reliability, 400 sample chips were mounted on a PCB board for each test number. After applying a voltage of 150V for 15 hours under conditions of 85°C and 85% humidity, samples with an insulation resistance of 10kΩ or less were judged as defective, and the number of defective samples was recorded.

[0139] Capacitance was measured for 10 sample chips per test number. An LCR meter was used to measure the capacitance under the conditions of AC voltage 1Vrms and 1kHz, and the average value for each test number was calculated. The capacitance of test number 6 was set as the baseline value "100%", and the values ​​for test numbers 1 to 5 are listed relative to the capacitance of test number 5.

[0140] [Table 2]

[0141] In test numbers 2 to 4, where the ratio of the average thickness tco of the outer cover section to the average thickness tc of the cover sections 112 and 113 (tco / tc) was 50% to 80%, excellent moisture resistance reliability was ensured while suppressing capacity degradation.

[0142] On the other hand, in the case of test number 1, where the ratio of the average thickness tco of the outer cover portion to the average thickness tc of the cover portion 112 and 113 (tco / tc) is 90%, the capacity was 89% of that of test number 6, confirming that the capacity had decreased slightly.

[0143] Furthermore, in the case of test numbers 5 and 6, where the ratio of the average thickness tco of the outer cover portion to the average thickness tc of the cover portions 112 and 113 (tco / tc) is 30% or less, it can be confirmed that the moisture resistance reliability improvement effect was relatively worse compared to test numbers 1 to 4.

[0144] Although embodiments of the present invention have been described in detail above, the present invention is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims provided. Therefore, within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, and these also fall within the scope of the present invention.

[0145] Furthermore, the expression "one embodiment" as used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and describe the unique and distinct features of each embodiment. However, the present embodiments are not excluded from being realized in combination with features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description in the other embodiment that contradicts or is inconsistent with that matter.

[0146] The terms used in this disclosure are used solely to describe one embodiment and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of Symbols]

[0147] 100 Stacked Electronic Components 110 Main Unit 111 Dielectric layer 112, 113 Cover section 112a, 113a Inner cover section 112b, 113b Outer cover section 114, 115 Margin section 121, 122 Internal electrode 131, 132 External electrode 131a, 132a electrode layer 131b, 132b Plating layer

Claims

1. A main body comprising a dielectric layer, a capacitance forming section including internal electrodes arranged alternately with the dielectric layer in the thickness direction, and a cover section arranged above and below the capacitance forming section in the thickness direction, The body includes an external electrode disposed on the main body, The cover portion includes an inner cover portion adjacent to the volume forming portion and an outer cover portion adjacent to the outer surface of the cover portion. When the average of the major axis length and minor axis length of a crystal grain is defined as the crystal grain size, and crystal grains with a crystal grain size of 500 nm or less are defined as first crystal grains, and crystal grains with a crystal grain size of 1150 nm or more are defined as second crystal grains, The inner cover portion includes a plurality of first crystal grains, The outer cover portion is a stacked electronic component comprising a plurality of first crystal grains and a plurality of second crystal grains.

2. The stacked electronic component according to claim 1, wherein the inner cover portion has an average crystal grain size of 300 nm or less.

3. The stacked electronic component according to claim 1, wherein the outer cover portion includes a region in which the standard deviation of the crystal grain size is at least twice that of the inner cover portion.

4. The stacked electronic component according to claim 1, wherein the inner cover portion has a standard deviation of crystal grain size of 130 nm or less.

5. The stacked electronic component according to claim 1, wherein the outer cover portion has a standard deviation of crystal grain size of 260 nm or more.

6. The stacked electronic component according to claim 1, wherein the maximum size of the crystal grains contained in the inner cover portion is 1100 nm or less.

7. The stacked electronic component according to claim 1, wherein the maximum size of the crystal grains contained in the outer cover portion is 2300 nm or more.

8. In the cross-section of the outer cover portion in the thickness and width direction, The stacked electronic component according to claim 1, wherein the area ratio of the plurality of second crystal grains to the area of ​​the outer cover portion is 50% or more and 95% or less.

9. In the cross-section of the inner cover portion in the thickness and width direction, The stacked electronic component according to claim 1, wherein the area ratio of the first crystal grain to the area of ​​the inner cover portion is 90% or more.

10. The stacked electronic component according to claim 1, wherein the ratio of the average thickness of the outer cover portion to the average thickness of the cover portion is 50% or more and 80% or less.

11. The stacked electronic component according to claim 1, wherein the cover portion has a Dy mole count of 3.7 to 4.5 moles per 100 moles of Ti.

12. The cover portion satisfies the following conditions per 100 moles of Ti: the number of moles of Dy is 3.7 to 4.5, the number of moles of Mg is 0.18 to 0.22, the number of moles of Mn is 0.225 to 0.275, and the number of moles of Si is 1.17 to 1.43, as described in claim 1.

13. The laminated electronic component according to claim 1, wherein the dielectric layer contains a plurality of the first crystal grains and the average value of the crystal grain size is 300 nm or less.

14. The laminated electronic component according to claim 1, wherein the dielectric layer has a Dy mole count of 3.7 to 4.5 moles per 100 moles of Ti.

15. The laminated electronic component according to claim 1, wherein the dielectric layer has a ratio of 3.7 to 4.5 moles of Dy, 0.18 to 0.22 moles of Mg, 0.225 to 0.275 moles of Mn, and 1.17 to 1.43 moles of Si per 100 moles of Ti.

16. The capacity forming portion includes margin portions arranged on both sides in the width direction of the capacity forming portion, The margin portion includes an inner margin portion adjacent to the volume forming portion, and an outer margin portion adjacent to the outer surface of the margin portion. The inner margin portion contains a plurality of the first crystal grains, The stacked electronic component according to any one of claims 1 to 15, wherein the outer margin portion includes a plurality of first crystal grains and a plurality of second crystal grains, respectively.

17. The stacked electronic component according to claim 16, wherein the average grain size of the inner margin portion is 300 nm or less.

18. The stacked electronic component according to claim 16, wherein the ratio of the average width of the outer margin portion to the average width of the margin portion is 50% or more and 80% or less.

19. The cover portion and the margin portion each have a Dy mole count of 3.7 to 4.5 per 100 moles of Ti. The laminated electronic component according to claim 16, wherein the dielectric layer has a number of Dy moles per 100 moles of Ti that is less than 3.

7.

20. The stacked electronic component according to claim 19, wherein the cover portion and margin portion further contain Ga.

21. A main body comprising a dielectric layer, a capacitance forming section including internal electrodes arranged alternately with the dielectric layer in the thickness direction, and a cover section arranged above and below the capacitance forming section in the thickness direction, The body includes an external electrode disposed on the main body, The cover portion includes an inner cover portion adjacent to the volume forming portion and an outer cover portion adjacent to the outer surface of the cover portion. When the average of the major axis length and minor axis length of a crystal grain is defined as the crystal grain size, The aforementioned outer cover portion includes a region in which the standard deviation of the crystal grain size is at least twice that of the inner cover portion, in a stacked electronic component.

22. The stacked electronic component according to claim 21, wherein the region of the cover portion within 20 μm from the capacitance forming portion has a standard deviation of crystal grain size that is at least twice as large as the region of the cover portion within 20 μm from the outer surface of the cover portion.

23. The stacked electronic component according to claim 21, wherein the inner cover portion has a standard deviation of crystal grain size of 130 nm or less.

24. The stacked electronic component according to claim 21, wherein the outer cover portion has a standard deviation of crystal grain size of 260 nm or more.

25. The stacked electronic component according to claim 21, wherein the outer cover portion includes crystal grains having a crystal grain size of 1150 nm or more.

26. The stacked electronic component according to claim 21, wherein the inner cover portion has an average crystal grain size of 300 nm or less.

27. The stacked electronic component according to claim 21, wherein the ratio of the average thickness of the outer cover portion to the average thickness of the cover portion is 50% or more and 80% or less.

28. The stacked electronic component according to claim 21, wherein the cover portion has a Dy mole count of 3.7 to 4.5 moles per 100 moles of Ti.

29. The capacity forming portion includes margin portions arranged on both sides in the width direction of the capacity forming portion, The margin portion includes an inner margin portion adjacent to the volume forming portion, and an outer margin portion adjacent to the outer surface of the margin portion. The stacked electronic component according to any one of claims 21 to 28, wherein the outer margin portion includes a region in which the standard deviation of the crystal grain size is at least twice that of the inner margin portion.

30. The stacked electronic component according to claim 29, wherein the region of the margin within 20 μm from the capacitance forming portion has a standard deviation of crystal grain size that is at least twice as large as the region of the margin within 20 μm from the outer surface of the margin portion.

31. The stacked electronic component according to claim 29, wherein the ratio of the average width of the outer margin portion to the average width of the margin portion is 50% or more and 80% or less.

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