Multilevel inverter

Abstract

The challenge is to suppress the voltage drop in the bootstrap circuit. [Solution] The multilevel inverter 100 comprises a DC power supply unit 3, a plurality of inverter circuits 1, and a control device 6. Each of the plurality of inverter circuits 1 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4. The control device 6 comprises a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, a plurality of fourth gate drivers 64, a plurality of bootstrap circuits 71, a power supply unit 9, and a control unit 60. In the multilevel inverter 100, the capacitance of the capacitor C17 included in each of the plurality of first bootstrap circuits 71 is 10 μF or more and 50 μF or less.

Description

[Technical Field]

[0001] This disclosure relates to a multilevel inverter, and more particularly to a multilevel inverter comprising a bootstrap circuit. [Background technology]

[0002] Patent Document 1 discloses a switching element drive circuit for a 3-level neutral point clamp type inverter.

[0003] The neutral point clamp type inverter disclosed in Patent Document 1 comprises a series circuit of a first switching element, a second switching element, a third switching element, and a fourth switching element, a first clamp diode, a second clamp diode, and a series circuit of two smoothing capacitors (DC power supply section) that smooths the DC voltage and generates its neutral point potential.

[0004] Furthermore, the switching element driving circuit includes a first gate driving circuit (first gate driver) for driving a first switching element, a second gate driving circuit (second gate driver) for driving a second switching element, a third gate driving circuit (third gate driver) for driving a third switching element, and a fourth gate driving circuit (fourth gate driver) for driving a fourth switching element. Switching signals are input to the first gate driving circuit, the second gate driving circuit, the third gate driving circuit, and the fourth gate driving circuit by a control circuit (control unit).

[0005] Furthermore, the switching element drive circuit includes a gate power supply (power supply unit). In the switching element drive circuit, a capacitor is connected in parallel to the first gate drive circuit. The capacitor is charged by the gate power supply via a diode. The power supply for driving the gate of the first switching element is the voltage charged in the capacitor. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2018-133876 [Overview of the project] [Problems that the invention aims to solve]

[0007] In a multilevel inverter comprising multiple sets of first, second, third, and fourth switching elements disclosed in Patent Document 1, a voltage drop in the bootstrap circuit, which includes a capacitor and a diode, can be a problem.

[0008] The purpose of this disclosure is to provide a multilevel inverter capable of suppressing voltage drops in a bootstrap circuit. [Means for solving the problem]

[0009] A multilevel inverter according to one embodiment of the present disclosure comprises a DC power supply unit, a plurality of inverter circuits, and a control device. The DC power supply unit has a positive electrode, a negative electrode, and an intermediate potential point. The plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply unit. The control device controls the plurality of inverter circuits. Each of the plurality of inverter circuits is a neutral point clamp type inverter. Each of the plurality of inverter circuits has a first switching element, a second switching element, a third switching element, and a fourth switching element, and a first diode, a second diode, a third diode, and a fourth diode. The first diode, the second diode, the third diode, and the fourth diode are connected in antiparallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively. The control device comprises a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of bootstrap circuits, a power supply unit, and a control unit. The plurality of first gate drivers drive the first switching element of each of the plurality of inverter circuits. The plurality of second gate drivers drive the second switching element of each of the plurality of inverter circuits. The plurality of third gate drivers drive the third switching element of each of the plurality of inverter circuits. The plurality of fourth gate drivers drive the fourth switching element of each of the plurality of inverter circuits. The plurality of bootstrap circuits correspond one-to-one with the plurality of first gate drivers. Each of the plurality of bootstrap circuits supplies voltage to the corresponding first gate driver among the plurality of first gate drivers. The power supply unit supplies voltage to the plurality of bootstrap circuits. The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers. Each of the plurality of bootstrap circuits includes a capacitor and a diode connected in series with the capacitor. The capacitance of the capacitor included in each of the plurality of bootstrap circuits is 10 μF or more and 50 μF or less.

Advantages of the Invention

[0010] The multilevel inverter of the present disclosure has the effect of being able to suppress the voltage drop of the bootstrap circuit.

Brief Description of the Drawings

[0011] [Figure 1] FIG. 1 is a circuit diagram of a system including a multilevel inverter according to Embodiment 1. [Figure 2] FIG. 2 is an explanatory diagram of a current path when the switching circuit is in the first switching state in the same multilevel inverter. [Figure 3] FIG. 3 is an explanatory diagram of a discharge path and a charge path when the switching circuit is in the first switching state in the same multilevel inverter. [Figure 4] FIG. 4 is an explanatory diagram of a current path when the switching circuit is in the second switching state in the same multilevel inverter. [Figure 5] FIG. 5 is an explanatory diagram of a discharge path and a charge path when the switching circuit is in the second switching state in the same multilevel inverter. [Figure 6] FIG. 6 is an explanatory diagram of a current path when the switching circuit is in the third switching state in the same multilevel inverter. [Figure 7] FIG. 7 is an explanatory diagram of a discharge path and a charge path when the switching circuit is in the third switching state in the same multilevel inverter. [Figure 8] FIG. 8 is an explanatory diagram of voltage command values of each phase in the same multilevel inverter. [Figure 9] FIG. 9 is an explanatory diagram of a group of voltage vectors related to the same multilevel inverter. [Figure 10] FIG. 10 is a more detailed explanatory diagram of a group of voltage vectors related to the same multilevel inverter. [Figure 11]Figure 11 is a vector diagram illustrating the operation of the control unit in the multilevel inverter described above. [Figure 12] Figure 12 is a time chart showing the switching state of each phase of the multilevel inverter shown above. [Figure 13] Figure 13 is a time chart showing the on / off states of the first to fourth switching elements of the multilevel inverter described above. [Figure 14] Figure 14A is a timing chart showing the relationship between the control signal to the switching element and the current flowing through the control terminal of the switching element when the switching element is turned on. Figure 14B is a timing chart showing the relationship between the control signal to the switching element and the current flowing through the control terminal of the switching element when the switching element is turned off. [Figure 15] Figure 15A is a characteristic diagram showing the carrier frequency dependence of the voltage change of a capacitor included in a bootstrap circuit. Figure 15B is a characteristic diagram showing the capacitance dependence of the voltage change of a capacitor included in a bootstrap circuit. [Figure 16] Figure 16 is a graph showing the relationship between the minimum capacitance of the capacitor included in the bootstrap circuit, the carrier frequency, and the multilevel vector control (MLVC) ratio. [Figure 17] Figure 17 is a graph showing the relationship between the minimum capacitance of the capacitor in the bootstrap circuit and the carrier frequency. [Figure 18] Figure 18 is a graph showing the relationship between the minimum capacitance of the capacitor included in the bootstrap circuit and the multilevel vector control ratio. [Figure 19] Figure 19A is an explanatory diagram of the command voltage vector and the first voltage vector for a multilevel inverter according to a comparative example. Figure 19B is an explanatory diagram of the command voltage vector, zero vector and second voltage vector for the same multilevel inverter. [Figure 20]Figure 20 is a time chart of the switching state of each phase when the inverter circuit of each phase is controlled by replacing the first voltage vector with the zero vector and the second voltage vector in the same multilevel inverter as above. [Figure 21] Figure 21 is a time chart of the on / off states of the first to fourth switching elements when the inverter circuit is controlled in the same multilevel inverter by replacing the first voltage vector with the zero vector and the second voltage vector. [Figure 22] Figure 22 is a circuit diagram of a system equipped with a multilevel inverter according to Embodiment 2. [Figure 23] Figure 23 is an explanatory diagram of the current path when the switching circuit is in the first switching state in the multilevel inverter described above. [Figure 24] Figure 24 is an explanatory diagram of the discharge path when the switching circuit is in the first switching state in the multilevel inverter described above. [Figure 25] Figure 25 is an explanatory diagram of the current path when the switching circuit is in the second switching state in the same multilevel inverter. [Figure 26] Figure 26 is an explanatory diagram of the discharge path when the switching circuit is in the second switching state in the same multilevel inverter. [Figure 27] Figure 27 is an explanatory diagram of the current path when the switching circuit is in the third switching state in the same multilevel inverter. [Figure 28] Figure 28 is an explanatory diagram of the discharge and charge paths when the switching circuit is in the third switching state in the multilevel inverter described above. [Figure 29] Figure 29 is an explanatory diagram of the current path when the switching circuit is in the second switching state in the same multilevel inverter. [Modes for carrying out the invention]

[0012] (Embodiment 1) In the following, the multilevel inverter 100 according to Embodiment 1 will be described with reference to Figures 1 to 18.

[0013] (1) Overall configuration of the multilevel inverter The multilevel inverter 100 comprises, for example, a DC power supply unit 3, a plurality of inverter circuits 1 (three in the example of Figure 1), and a control device 6, as shown in Figure 1. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The control device 6 controls the plurality of inverter circuits 1. The "intermediate potential point M1" is the point where the potential is midway between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3.

[0014] The multilevel inverter 100 is a diode clamp type 3-level 3-phase inverter. In the multilevel inverter 100, each of the multiple inverter circuits 1 has an output terminal 41. In the multilevel inverter 100, an AC load RA1 is connected to multiple (three in the example in Figure 1) output terminals 41.

[0015] The AC load RA1 is, for example, a three-phase servo motor. In the multi-level inverter 100, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs the U-phase voltage, another is an inverter circuit 1V that outputs the V-phase voltage, and the remaining one is an inverter circuit 1W that outputs the W-phase voltage.

[0016] Each of the multiple inverter circuits 1 includes a switching circuit 10, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. Furthermore, each of the multiple inverter circuits 1 also includes a first clamp diode D5 and a second clamp diode D6. In the multilevel inverter 100, the potential of the intermediate potential point M1 is clamped by the first clamp diode D5 and the second clamp diode D6 of each inverter circuit 1.

[0017] In each switching circuit 10, the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series so that they are arranged in the order of first switching element Q1, second switching element Q2, third switching element Q3, and fourth switching element Q4 from the positive terminal P1 side to the negative terminal N1 side of the DC power supply unit 3.

[0018] In each inverter circuit 1, the first diode D1 is connected in reverse parallel to the first switching element Q1. The second diode D2 is connected in reverse parallel to the second switching element Q2. The third diode D3 is connected in reverse parallel to the third switching element Q3. The fourth diode D4 is connected in reverse parallel to the fourth switching element Q4. The cathode of the first clamp diode D5 is connected to the first connection point 11 between the first switching element Q1 and the second switching element Q2, and the anode is connected to the intermediate potential point M1. The anode of the second clamp diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4, and the cathode is connected to the intermediate potential point M1.

[0019] The control device 6 includes a plurality of (three in the example of Figure 1) first gate drivers 61, a plurality of (three in the example of Figure 1) second gate drivers 62, a plurality of (three in the example of Figure 1) third gate drivers 63, and a plurality of (three in the example of Figure 1) fourth gate drivers 64. The control device 6 also includes a plurality of (three in the example of Figure 1) bootstrap circuits 71 (hereinafter also referred to as first bootstrap circuits 71), a plurality of (three in the example of Figure 1) second bootstrap circuits 72, a plurality of (three in the example of Figure 1) third bootstrap circuits 73, a power supply unit 9, and a control unit 60.

[0020] Multiple first gate drivers 61 drive each first switching element Q1 of the multiple inverter circuits 1. Multiple second gate drivers 62 drive each second switching element Q2 of the multiple inverter circuits 1. Multiple third gate drivers 63 drive each third switching element Q3 of the multiple inverter circuits 1. Multiple fourth gate drivers 64 drive each fourth switching element Q4 of the multiple inverter circuits 1.

[0021] Multiple first bootstrap circuits 71 correspond one-to-one with multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 supplies voltage to the corresponding first gate driver 61. Multiple second bootstrap circuits 72 correspond one-to-one with multiple second gate drivers 62. Each of the multiple second bootstrap circuits 72 supplies voltage to the corresponding second gate driver 62. Multiple third bootstrap circuits 73 correspond one-to-one with multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 supplies voltage to the corresponding third gate driver 63. The power supply unit 9 supplies voltage to multiple fourth gate drivers 64.

[0022] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64.

[0023] (2) Details of the multilevel inverter The DC power supply unit 3 includes a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series. The DC power supply unit 3 further includes a first DC terminal 31 connected to a positive terminal P1 and a second DC terminal 32 connected to a negative terminal N1. In the DC power supply unit 3, the first end of the first capacitor C1 is connected to the first DC terminal 31, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the first capacitor C1 and the second capacitor C2 is an intermediate potential point M1. A DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32, for example. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1. "The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" does not mean that the capacitance of the second capacitor C2 is exactly the same as the capacitance of the first capacitor C1, but rather that the capacitance of the second capacitor C2 is within the range of 95% to 105% of the capacitance of the first capacitor C1.

[0024] In the following explanation, for the sake of clarity, the switching circuits 10 included in inverter circuit 1U may be referred to as switching circuit 10U, the switching circuits 10 included in inverter circuit 1V may be referred to as switching circuit 10V, and the switching circuits 10 included in inverter circuit 1W may be referred to as switching circuit 10W. Additionally, among the multiple output terminals 41, the output terminal 41 included in inverter circuit 1U may be referred to as output terminal 41U, the output terminal 41 included in inverter circuit 1V may be referred to as output terminal 41V, and the output terminal included in inverter circuit 1W may be referred to as output terminal 41W.

[0025] Each switching circuit 10 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4, each having a control terminal, a first main terminal, and a second main terminal. Each switching circuit 10 has, for example, an insulated-gate bipolar transistor (IGBT). Therefore, the control terminal, the first main terminal, and the second main terminal of each of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 in each switching circuit 10 are the gate terminal, the collector terminal, and the emitter terminal, respectively.

[0026] The control terminal of the first switching element Q1 of each switching circuit 10 is connected to the corresponding first gate driver 61 from among a plurality of first gate drivers 61. Similarly, the control terminal of the second switching element Q2 of each switching circuit 10 is connected to the corresponding second gate driver 62 from among a plurality of second gate drivers 62. Furthermore, the control terminal of the third switching element Q3 of each switching circuit 10 is connected to the corresponding third gate driver 63 from among a plurality of third gate drivers 63. Finally, the control terminal of the fourth switching element Q4 of each switching circuit 10 is connected to the corresponding fourth gate driver 64 from among a plurality of fourth gate drivers 64.

[0027] In each switching circuit 10, the first main terminal of the first switching element Q1 is connected to the positive terminal P1 of the DC power supply unit 3, and the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2. In addition, in each switching circuit 10, the second main terminal of the second switching element Q2 is connected to the first main terminal of the third switching element Q3. In addition, in each switching circuit 10, the second main terminal of the third switching element Q3 is connected to the first main terminal of the fourth switching element Q4, and the second main terminal of the fourth switching element Q4 is connected to the negative terminal N1 of the DC power supply unit 3.

[0028] In inverter circuit 1U, the third connection point 13 between the second switching element Q2 and the third switching element Q3 in switching circuit 10U is connected to output terminal 41U. Similarly, in inverter circuit 1V, the third connection point 13 between the second switching element Q2 and the third switching element Q3 in switching circuit 10V is connected to output terminal 41V. Similarly, in inverter circuit 1W, the third connection point 13 between the second switching element Q2 and the third switching element Q3 in switching circuit 10W is connected to output terminal 41W. The third connection point 13 of inverter circuit 1U is connected to, for example, the U phase of an AC load RA1 via output terminal 41U. Similarly, the third connection point 13 of inverter circuit 1V is connected to, for example, the V phase of an AC load RA1 via output terminal 41V. Similarly, the third connection point 13 of inverter circuit 1W is connected to, for example, the W phase of an AC load RA1 via output terminal 41W.

[0029] In each inverter circuit 1, the anode of the first diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In addition, in each inverter circuit 1, the anode of the second diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In addition, in each inverter circuit 1, the anode of the third diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. Furthermore, in each inverter circuit 1, the anode of the fourth diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0030] In each inverter circuit 1, the first diode D1 may be replaced with a parasitic diode of the IGBT constituting the first switching element Q1. Also, in each inverter circuit 1, the second diode D2 may be replaced with a parasitic diode of the IGBT constituting the second switching element Q2. Also, in each inverter circuit 1, the third diode D3 may be replaced with a parasitic diode of the IGBT constituting the third switching element Q3. Also, in each inverter circuit 1, the fourth diode D4 may be replaced with a parasitic diode of the IGBT constituting the fourth switching element Q4.

[0031] In each inverter circuit 1, the cathode of the first clamp diode D5 is connected to the first connection point 11 between the first switching element Q1 and the second switching element Q2. The anode of the first clamp diode D5 is connected to the intermediate potential point M1 of the DC power supply unit 3. In Embodiment 1, since the intermediate potential point M1 is connected to ground, the potential of the intermediate potential point M1 is 0V. In this case, if the voltage across the DC power supply unit 3 is Vdc, the potential of the positive electrode P1 is Vdc / 2, and the potential of the negative electrode N1 is -Vdc / 2.

[0032] The cathode of the second clamp diode D6 is connected to the intermediate potential point M1. The anode of the second clamp diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4.

[0033] Multiple first gate drivers 61 correspond one-to-one with multiple first switching elements Q1. Each of the multiple first gate drivers 61 is connected to the control terminal of the corresponding first switching element Q1. Each of the multiple first gate drivers 61 drives the corresponding first switching element Q1. The multiple first gate drivers 61 are connected to a control unit 60. The control unit 60 outputs multiple first control signals S1 (see Figure 2) that correspond one-to-one with the multiple first gate drivers 61. Each of the multiple first gate drivers 61 controls the first switching element Q1 to be on or off based on the given first control signal S1.

[0034] Multiple second gate drivers 62 correspond one-to-one with multiple second switching elements Q2. Each of the multiple second gate drivers 62 is connected to the control terminal of the corresponding second switching element Q2. Each of the multiple second gate drivers 62 drives the corresponding second switching element Q2. The multiple second gate drivers 62 are connected to a control unit 60. The control unit 60 outputs multiple second control signals S2 (see Figure 2) that correspond one-to-one with the multiple second gate drivers 62. Each of the multiple second gate drivers 62 controls the second switching element Q2 to be on or off based on the given second control signal S2.

[0035] Multiple third gate drivers 63 correspond one-to-one with multiple third switching elements Q3. Each of the multiple third gate drivers 63 is connected to the control terminal of the corresponding third switching element Q3. Each of the multiple third gate drivers 63 drives the corresponding third switching element Q3. The multiple third gate drivers 63 are connected to a control unit 60. The control unit 60 outputs multiple third control signals S3 (see Figure 2) that correspond one-to-one with the multiple third gate drivers 63. Each of the multiple third gate drivers 63 controls the on / off state of the third switching element Q3 based on the given third control signal S3.

[0036] Multiple fourth gate drivers 64 correspond one-to-one with multiple fourth switching elements Q4. Each of the multiple fourth gate drivers 64 is connected to the control terminal of the corresponding fourth switching element Q4. Each of the multiple fourth gate drivers 64 drives the corresponding fourth switching element Q4. The multiple fourth gate drivers 64 are connected to a control unit 60. The control unit 60 outputs multiple fourth control signals S4 (see Figure 2) that correspond one-to-one with the multiple fourth gate drivers 64. Each of the multiple fourth gate drivers 64 controls the on / off state of the fourth switching element Q4 based on the given fourth control signal S4.

[0037] Multiple first bootstrap circuits 71 correspond one-to-one with multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 supplies voltage to the corresponding first gate driver 61 among the multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 includes a diode D17, a resistor R17, and a capacitor C17 (also called a boost capacitor C17). In each first bootstrap circuit 71, the anode of diode D17 is connected to the positive terminal of the power supply unit 9 via diodes D27 and D37, and the cathode of diode D17 is connected to the first terminal of capacitor C17 via resistor R17. The first terminal of capacitor C17 is connected to the high-potential side power supply terminal 61H (see Figure 3) of the first gate driver 61, and the second terminal of capacitor C17 is connected to the low-potential side power supply terminal 61L (see Figure 3) of the first gate driver 61. The first bootstrap circuit 71 supplies the voltage necessary to turn on the first switching element Q1 in the first gate driver 61. Each of the multiple first bootstrap circuits 71 further has a Zener diode Z17 connected in parallel with the capacitor C17.

[0038] Multiple second bootstrap circuits 72 correspond one-to-one with multiple second gate drivers 62. Each of the multiple second bootstrap circuits 72 supplies voltage to the corresponding second gate driver 62 among the multiple second gate drivers 62. Each of the multiple second bootstrap circuits 72 includes a diode D27, a resistor R27, and a capacitor C27 (also called a boost capacitor C27). In each second bootstrap circuit 72, the anode of diode D27 is connected to the positive terminal of the power supply unit 9 via diode D37, and the cathode of diode D27 is connected to the first terminal of capacitor C27 via resistor R27. The first terminal of capacitor C27 is connected to the high-potential side power supply terminal 62H (see Figure 3) of the second gate driver 62, and the second terminal of capacitor C27 is connected to the low-potential side power supply terminal 62L (see Figure 3) of the second gate driver 62. The second bootstrap circuit 72 supplies the voltage necessary to turn on the second switching element Q2 in the second gate driver 62. Each of the multiple second bootstrap circuits 72 further has a Zener diode Z27 connected in parallel with the capacitor C27.

[0039] Multiple third bootstrap circuits 73 correspond one-to-one with multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 supplies voltage to the corresponding third gate driver 63 among the multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 includes a diode D37, a resistor R37, and a capacitor C37 (also called a boost capacitor C37). In each third bootstrap circuit 73, the anode of diode D37 is connected to the positive terminal of the power supply unit 9, and the cathode of diode D37 is connected to the first terminal of capacitor C37 via resistor R37. The first terminal of capacitor C37 is connected to the high-potential side power supply terminal 63H (see Figure 3) of the third gate driver 63, and the second terminal of capacitor C37 is connected to the low-potential side power supply terminal 63L (see Figure 3) of the third gate driver 63. The third bootstrap circuit 73 supplies the voltage necessary to turn on the third switching element Q3 in the third gate driver 63. Each of the multiple third bootstrap circuits 73 further has a Zener diode Z37 connected in parallel with the capacitor C37.

[0040] The power supply unit 9 supplies voltage to a plurality (3) of first bootstrap circuits 71, a plurality (3) of second bootstrap circuits 72, a plurality (3) of third bootstrap circuits 73, and a plurality (3) of fourth gate drivers 64. The power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91. The positive terminal of the power supply unit 9 is connected to the high-potential side power supply terminal 64H (see Figure 3) of each of the plurality of fourth gate drivers 64, and the negative terminal of the power supply unit 9 is connected to the low-potential side power supply terminal 64L (see Figure 3) of each of the plurality of fourth gate drivers 64.

[0041] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. In this way, the control unit 60 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control unit 60 includes a computer system. The computer system has one or more computers. The computer system mainly consists of a processor and memory as hardware. The function of the control unit 60 as the execution entity in this disclosure is realized by the processor executing a program recorded in the memory of the computer system. The program may be pre-recorded in the memory of the computer system, provided via a telecommunications line, or provided on a non-temporary recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) that can be read by the computer system. The processor of the computer system consists of one or more electronic circuits including semiconductor integrated circuits (ICs) or large-scale integrated circuits (LSIs). The multiple electronic circuits may be integrated onto a single chip or distributed across multiple chips. Multiple chips may be integrated into a single device, or they may be distributed across multiple devices.

[0042] The control unit 60 outputs multiple (three) first control signals S1 (see Figure 2) for controlling multiple (three) first switching elements Q1, multiple (three) second control signals S2 (see Figure 2) for controlling multiple (three) second switching elements Q2, multiple (three) third control signals S3 (see Figure 2) for controlling multiple third switching elements Q3, and multiple (three) fourth control signals S4 (see Figure 2) for controlling multiple (three) fourth switching elements Q4. Note that in Figure 2, only one of the three inverter circuits 1 (see Figure 1) is shown, and the remaining two inverter circuits 1 are not shown. Furthermore, in Figure 2, the illustration of the multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, multiple fourth gate drivers 64, multiple first bootstrap circuits 71, multiple second bootstrap circuits 72, multiple third bootstrap circuits 73, and power supply unit 9 as shown in Figure 1 is omitted. Also, in Figure 3, only one of the three inverter circuits 1 (see Figure 1) is shown, and the illustration of the remaining two inverter circuits 1 is omitted. Furthermore, in Figure 3, the illustration of the two first gate drivers 61, two second gate drivers 62, two third gate drivers 63, two fourth gate drivers 64, two first bootstrap circuits 71, two second bootstrap circuits 72, and two third bootstrap circuits 73 as shown in Figure 1 is omitted.

[0043] The three first control signals S1 include a first control signal S1U that controls the first switching element Q1 of the switching circuit 10U, a first control signal S1V that controls the first switching element Q1 of the switching circuit 10V, and a first control signal S1W that controls the first switching element Q1 of the switching circuit 10W.

[0044] The three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the switching circuit 10U, a second control signal S2V that controls the second switching element Q2 of the switching circuit 10V, and a second control signal S2W that controls the second switching element Q2 of the switching circuit 10W.

[0045] The three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the switching circuit 10U, a third control signal S3V that controls the third switching element Q3 of the switching circuit 10V, and a third control signal S3W that controls the third switching element Q3 of the switching circuit 10W.

[0046] The three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of the switching circuit 10U, a fourth control signal S4V that controls the fourth switching element Q4 of the switching circuit 10V, and a fourth control signal S4W that controls the fourth switching element Q4 of the switching circuit 10W.

[0047] Each of the multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher in potential than the first potential level.

[0048] The first potential level is, for example, 0V, and the second potential level is a potential level greater than the gate threshold voltage of the IGBT. In other words, for each of the multiple control signals (multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4), the first potential level is the potential level required to turn off the switching element corresponding to that control signal, and the second potential level is the potential level required to turn on the switching element corresponding to that control signal.

[0049] Each of the multiple first switching elements Q1 is turned on when the corresponding first control signal S1 is high and turned off when it is low. Similarly, each of the multiple second switching elements Q2 is turned on when the corresponding second control signal S2 is high and turned off when it is low. Similarly, each of the multiple third switching elements Q3 is turned on when the corresponding third control signal S3 is high and turned off when it is low. Similarly, each of the multiple fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is high and turned off when it is low.

[0050] In the multilevel inverter 100, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. In other words, in the multilevel inverter 100, the switching state of the switching circuit 10 in each of the three inverter circuits 1U, 1V, and 1W is controlled to one of the first switching state, a second switching state, or a third switching state. The first, second, and third switching states differ in the combination of on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from each other. In other words, in each of the multiple inverter circuits 1, the potential level of the output voltage changes in three levels depending on the state of the first to fourth switching elements Q1 to Q4. Regarding the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with each other.

[0051] The first switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are ON, and both the third switching element Q3 and the fourth switching element Q4 are OFF. Each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3 when controlled to the first switching state. In the first switching state, the potential of the third connection point 13 of each of the multiple inverter circuits 1 is at the potential level of the positive electrode P1 of the DC power supply unit 3 (for example, Vdc / 2).

[0052] The second switching state is a combination in which both the first switching element Q1 and the fourth switching element Q4 are in the off state, and both the second switching element Q2 and the third switching element Q3 are in the on state. Each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3 when controlled to the second switching state. In the second switching state, the potential of the third connection point 13 of each of the multiple inverter circuits 1 is at the potential level of the intermediate potential point M1 (for example, 0).

[0053] The third switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the off state, and both the third switching element Q3 and the fourth switching element Q4 are in the on state. Each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3 when controlled to the third switching state. In the third switching state, the potential of the third connection point 13 of each of the multiple inverter circuits 1 is at the potential level of the negative electrode N1 of the DC power supply unit 3 (for example, -Vdc / 2).

[0054] When the switching circuit 10 of the inverter circuit 1 is in the first switching state, as shown in Figure 2, current I1 flows through the path from the positive terminal P1 of the DC power supply unit 3 - the first switching element Q1 - the second switching element Q2 - the third connection point 13 - the output terminal 41, and the voltage value of the output voltage to the AC load RA1 (see Figure 1) is approximately Vdc / 2.

[0055] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, the capacitor C17 of the first bootstrap circuit 71 supplies the voltage necessary for the first gate driver 61 to turn on the first switching element Q1. Therefore, the charge on the capacitor C17 of the first bootstrap circuit 71 is discharged through the discharge path Ru1 of capacitor C17 - high-potential side power supply terminal 61H of the first gate driver 61 - low-potential side power supply terminal 61L of the first gate driver 61 - capacitor C17, as shown in Figure 3. As a result, the voltage across capacitor C17 in the first bootstrap circuit 71 decreases over time.

[0056] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, the capacitor C27 of the second bootstrap circuit 72 supplies the voltage necessary for the second gate driver 62 to turn on the second switching element Q2. Therefore, the charge on the capacitor C27 of the second bootstrap circuit 72 is discharged through the discharge path Ru2 of capacitor C27 - high-potential power supply terminal 62H of the second gate driver 62 - low-potential power supply terminal 62L of the second gate driver 62 - capacitor C27. As a result, the voltage across capacitor C27 in the second bootstrap circuit 72 decreases over time.

[0057] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, capacitor C17 is charged by capacitor C27 if the first condition is met. As shown in Figure 3, if the voltage across capacitor C17 is Vo1, the voltage across capacitor C27 is Vo2, the voltage across diode D17 is Vd1, the voltage across resistor R17 is VR1, and the voltage across second switching element Q2 is Vf2, then the first condition is Vo2 > (Vo1 + Vd1 + VR1 + Vf2). The charging path Ru21 that charges capacitor C17 by capacitor C27 is the path of capacitor C27 - resistor R27 - diode D17 - resistor R17 - capacitor C17 - first connection point 11 - second switching element Q2 - capacitor C27.

[0058] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state and the polarity of the output current is positive, as shown in Figure 4, current I1 flows through the path from the intermediate potential point M1 of the DC power supply unit 3 - the first clamp diode D5 - the second switching element Q2 - the third connection point 13 - the output terminal 41 (the path shown by the thick solid arrow), and the voltage value of the output voltage to the AC load RA1 becomes 0. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the third switching state, and the third switching state, respectively, current I1 flows through the path from the intermediate potential point M1 of the DC power supply unit 3 - the first clamp diode D5 of the inverter circuit 1U - the second switching element Q2 of the switching circuit 10U - the third connection point 13 - the output terminal 41.

[0059] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state and the polarity of the output current is negative, as shown in Figure 4, current I1 flows through the path from output terminal 41 - third connection point 13 - third switching element Q3 - second connection point 12 - second clamp diode D6 (the path indicated by the thick dashed arrow), and the output voltage value to the AC load RA1 becomes 0. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, second switching state, and first switching state, respectively, current I1 flows through the path from output terminal 41 - third connection point 13 - third switching element Q3 - second connection point 12 - second clamp diode D6 (the path indicated by the thick dashed arrow) in the inverter circuit 1U, and the output voltage value to the AC load RA1 becomes 0.

[0060] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the capacitor C27 of the second bootstrap circuit 72 supplies the voltage necessary for the second gate driver 62 to turn on the second switching element Q2. Therefore, the charge of the capacitor C27 of the second bootstrap circuit 72 is discharged through the discharge path Ru2 of capacitor C27 - high-potential side power supply terminal 62H of the second gate driver 62 - low-potential side power supply terminal 62L of the second gate driver 62 - capacitor C27, as shown in Figure 5. Also, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the capacitor C37 of the third bootstrap circuit 73 supplies the voltage necessary for the third gate driver 63 to turn on the third switching element Q3. Therefore, the charge on capacitor C37 of the third bootstrap circuit 73 is discharged through the discharge path Ru3: capacitor C37 - high-potential power supply terminal 63H of the third gate driver 63 - low-potential power supply terminal 63L of the third gate driver 63 - capacitor C37.

[0061] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, capacitor C27 is charged by capacitor C37 if the second condition is met, and capacitor C17 is charged by capacitor C27 if the third condition is met. As shown in Figure 5, if the voltages across capacitors C17, C27, and C37 are Vo1, Vo2, and Vo3 respectively, the voltages across diodes D17 and D27 are Vd1 and Vd2 respectively, the voltages across resistors R17 and R27 are VR1 and VR2 respectively, and the voltages across the second switching element Q2 and third switching element Q3 are Vf2 and Vf3 respectively, then the second condition is Vo3 > (Vo2 + Vd2 + VR2 + Vf3). The third condition is Vo2 > (Vo1 + Vd1 + VR1 + Vf2). The charging path Ru32, which charges capacitor C27 using capacitor C37, is the path of capacitor C37 - resistor R37 - diode D27 - resistor R27 - capacitor C27 - third connection point 13 - third switching element Q3 - capacitor C37. The charging path Ru21, which charges capacitor C17 using capacitor C27, is the path of capacitor C27 - resistor R27 - diode D17 - resistor R17 - capacitor C17 - first connection point 11 - second switching element Q2 - capacitor C27.

[0062] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, as shown in Figure 6, current I1 flows through the path from output terminal 41 - third connection point 13 - third switching element Q3 - fourth switching element Q4 - negative terminal N1 of the DC power supply unit 3, and the output voltage value to the AC load RA1 becomes -Vdc / 2. Also, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, capacitor C27 of the second bootstrap circuit 72 (see Figure 1) is charged by capacitor C37, so the voltage of capacitor C27 rises over time and capacitor C27 becomes fully charged. Also, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the capacitor C37 of the third bootstrap circuit 73 supplies the voltage necessary for the third gate driver 63 to turn on the third switching element Q3. Therefore, the charge in capacitor C37 of the third bootstrap circuit 73 is discharged through the discharge path Ru3: capacitor C37 - high-potential power supply terminal 63H of the third gate driver 63 - low-potential power supply terminal 63L of the third gate driver 63 - capacitor C37. Also, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, capacitor C37 is charged by the power supply unit 9 if the fourth condition is met, and capacitor C27 is charged by capacitor C37 if the fifth condition is met. As shown in Figure 7, if the voltage across the power supply unit 9 is Voo, the voltages across capacitors C27 and C37 are Vo2 and Vo3 respectively, the voltages across diodes D27 and D37 are Vd2 and Vd3 respectively, the voltages across resistors R27 and R37 are VR2 and VR3 respectively, and the voltages across the third switching element Q3 and fourth switching element Q4 are Vf3 and Vf4 respectively, then the fourth condition is Voo > (Vo3 + Vd3 + VR3 + Vf4). The fifth condition is Vo3 > (Vo2 + Vd2 + VR2 + Vf3). The charging path Ru93 for charging capacitor C37 by the power supply unit 9 is the path from the positive terminal of the power supply unit 9 - diode D37 - resistor R37 - capacitor C37 - second connection point 12 - fourth switching element Q4 - negative terminal of the power supply unit 9.The charging path Ru32 that charges capacitor C27 with capacitor C37 is the path of capacitor C37 - resistor R37 - diode D27 - resistor R27 - capacitor C27 - third connection point 13 - third switching element Q3 - capacitor C37.

[0063] The control unit 60 generates first to fourth control signals S1 to S4 (S1U to S4U) for the first to fourth switching elements Q1 to Q4 of inverter circuit 1U, first to fourth control signals S1 to S4 (S1V to S4V) for the first to fourth switching elements Q1 to Q4 of inverter circuit 1V, and first to fourth control signals S1 to S4 (S1W to S4W) for the first to fourth switching elements Q1 to Q4 of inverter circuit 1W, based on the voltage commands Vu, Vv, and Vw (see Figure 8) for the output voltages of inverter circuits 1U, 1V, and 1W, respectively.

[0064] As shown in Figure 8, the voltage command Vu and the voltage command Vv are, for example, sinusoidal signals with a phase difference of 120° from each other, and their respective values ​​(voltage command values) change over time. The length of one period for voltage commands Vu, Vv, and Vw is the same. The control unit 60 may also perform PI (Proportional Integral) control of the voltage commands Vu, Vv, and Vw based on the information output from the detection unit 8, which detects the state of the AC load RA1. When the AC load RA1 is a three-phase motor, the information output from the detection unit 8 includes, for example, at least one of the following: information from the detection results of multiple current sensors that detect the output current flowing through the U, V, and W phases of the AC load RA1, and information from the detection results of an encoder that detects the rotation speed, rotation angle, etc., of the three-phase motor.

[0065] The operation of one of the three inverter circuits 1 (for example, the U-phase inverter circuit 1U) will be described below. The operation of the V-phase inverter circuit 1V and the W-phase inverter circuit 1W is the same as the operation of the U-phase inverter circuit 1U. The output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with respect to each other.

[0066] The control unit 60 controls the multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, and multiple fourth gate drivers 64 by performing voltage vector control.

[0067] The voltage vector control in the control unit 60 will be explained in more detail below.

[0068] The control unit 60 stores a group of voltage vectors in advance. Each of the voltage vectors in the group is determined by a combination of potential levels at the connection point (third connection point 13) between the second switching element Q2 and the third switching element Q3 of the multiple inverter circuits 1. In other words, the group of voltage vectors is determined by the switching state of the switching circuit 10U corresponding to the U phase, the switching state of the switching circuit 10V corresponding to the V phase, and the switching state of the switching circuit 10W corresponding to the W phase. The number of voltage vectors included in the group of voltage vectors is 3 3 = 27 items

[0069] As shown in Figure 9, a group of voltage vectors contains three zero vectors V0p, V0n, and V0o, each with a magnitude of zero. Furthermore, a group of voltage vectors contains three zero vectors, each with a magnitude of (2 / 3). 1 / 2 It contains six voltage vectors V1, V2, V3, V4, V5, and V6, each with a voltage of 2Vdc and different directions. Furthermore, each group of voltage vectors has a magnitude of (2 / 3). 1 / 2 It includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, where Vdc is Vdc. Also, each group of voltage vectors has a magnitude of (2 / 3). 1 / 2 3 1 / 2It includes six voltage vectors V13, V14, V15, V16, V17, and V18, all of which are Vdc and have different directions. In Figure 9, the angle between any two adjacent voltage vectors among the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Also, the angle between any two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees. Note that Figure 9 is a vector diagram illustrating a group of voltage vectors on an orthogonal dq coordinate system.

[0070] A group of voltage vectors can be represented as shown in Figure 10, by indicating the first switching state, second switching state, and third switching state with the symbols "P", "0", and "N", respectively, and listing them in the order of U phase, V phase, and W phase.

[0071] As shown in Figure 10, the three zero vectors V0p, V0n, and V0o can be expressed as V0p[PPP], V0n[NNN], and V0o

[0000] , respectively. For example, V0p[PPP] expresses that, with respect to the zero vector V0p, the switching state of the U-phase switching circuit 10U is "P", the switching state of the V-phase switching circuit 10V is "P", and the switching state of the W-phase switching circuit 10W is "P". For example, a voltage vector with "p" attached, such as V10p, includes "P" but does not include "N". This is also true for the following. Similarly, a voltage vector with "n" attached, such as V10n, includes "N" but does not include "P". This is also true for the following. Furthermore, a voltage vector with "o" attached, such as V10o, includes "0" but does not include "P" or "N". When the switching state of the switching circuit 10 is "P", the potential of the third connection point 13 in the switching circuit 10 is the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "N", the potential of the third connection point 13 in the switching circuit 10 is the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "0", the potential of the third connection point 13 in the switching circuit 10 is the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0072] Also, the six voltage vectors V1, V2, V3, V4, V5, and V6 can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors without any of "p", "n", or "o" attached after the number attached to "V", such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], include "P" and "N" as the three-phase switching states.

[0073] Also, the twelve voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively.

[0074] Also, the six voltage vectors V13, V14, V15, V16, V17, and V18 can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0], respectively.

[0075] The control unit 60 converts the instantaneous value of the command voltage regarding the output voltage of each of the plurality of inverter circuits 1 into a command voltage vector V * (see FIG. 11). Let the d-axis component of the command voltage vector V * on the orthogonal d-q coordinate be Vd, and the q-axis component of the command voltage vector V * on the orthogonal d-q coordinate be Vq. Then, the command voltage vector V * can be obtained using Equation (1).

[0076]

Equation

[0077] The control unit 60 selects the command voltage vector V from a group of voltage vectors. * Select multiple (for example, five) voltage vectors adjacent to it. In the example in Figure 11, the multiple voltage vectors are V8p[PP0], V8n[00N], V13[P0N], V7p[P00], and V7n[0NN].

[0078] Command voltage vector V * The voltage vector closest to (hereinafter also called voltage vector VV1) and the command voltage vector V * The angle it makes is less than 30 degrees.

[0079] The control unit 60 controls the command voltage vector V within a predetermined control period Ts. * The resultant vector of the vertices of the equilateral triangle surrounding the command voltage vector V is the resultant vector of the command voltage vector V * To match. That is, the control unit 60 combines the voltage vector VV1 (V8p[PP0] and V8n[00N] in the example in Figure 11), the voltage vector V13[P0N], and the voltage vectors V7p[P00] and V7n[0NN] to form the command voltage vector V * This is to be matched. The control period Ts is one period of the carrier signal. In the control unit 60, within the control period Ts, the switching state of only one phase of the U-phase, V-phase, and W-phase in two voltage vectors arranged in time series changes between "P" and "0" or between "0" and "N", and the same voltage vector is output twice. In Figure 12, the output is in the order of voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N]. Figure 12 illustrates the case where the allocation time of voltage vectors V8p and V8n is T0, the allocation time of voltage vector V13 is T1, and the allocation time of voltage vectors V7p and V7n is T2 with respect to the control period Ts. For T0, T1, and T2, the command voltage vector V * Let Va, Vb, and Vc be the voltage vectors at the vertices of the equilateral triangle surrounding the point, and the command voltage vector V *Let V be the magnitude and θ be the angle. Determine T0, T1, and T2 such that equations (2) and (3) are satisfied. In equation (2), "j" is the imaginary unit. In the example in Figure 11, for example, the voltage vector Va is the voltage vector V8p[PP0] and V8n[00N], the voltage vector Vb is the voltage vector V13[P0N], and the voltage vector Vc is the voltage vector V7p[P00] and V7n[0NN].

[0080]

number

[0081]

number

[0082] In the example shown in Figure 12, the on / off states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 occur within the control period Ts as shown in Figure 13. In the example shown in Figure 13, the second switching element Q2 remains in the ON state for the entire duration of the control period Ts, resulting in a large voltage drop across the second bootstrap circuit 72.

[0083] Note that the command voltage vector V * Even if the result is the same as in Figure 11, the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.

[0084] Incidentally, in the multilevel inverter 100, when the potential level of the control signal S1 to each of the multiple first switching elements Q1 changes from a low level ("L" in Figure 14A) to a high level ("H" in Figure 14A), a pulsed current (see Figure 14A) flows to the control terminal of the first switching element Q1 that is turned on. As a result, the charge of the capacitor C17 of the bootstrap circuit 71 corresponding to the first switching element Q1 that is turned on is consumed.

[0085] Furthermore, in the multilevel inverter 100, when the potential level of the control signal S1 to each of the multiple first switching elements Q1 changes from a high level (H in Figure 14B) to a low level (L in Figure 14B), a pulsed current (see Figure 14B) flows to the control terminal of the first switching element Q1 that is turned off. As a result, the charge of the capacitor C17 of the bootstrap circuit 71 corresponding to the first switching element Q1 that is turned on is consumed.

[0086] Therefore, in the multilevel inverter 100, the higher the carrier frequency is to increase the frequency, the greater the charge consumption of capacitor C17. The carrier frequency is the frequency of the carrier signal, which is determined by the period of the carrier signal.

[0087] Figure 15A shows the carrier frequency dependence of the voltage change across capacitor C17. In Figure 15A, the time change of the voltage across capacitor C17 (the voltage across its terminals Vo1 as described above) is shown when the carrier frequency is changed, with the capacitance of capacitor C17 being 0.2 μF. In Figure 15A, "A1" shows the time change of the voltage across capacitor C17 when the carrier frequency is 6 kHz, "A2" shows the time change of the voltage across capacitor C17 when the carrier frequency is 12 kHz, and "A3" shows the time change of the voltage across capacitor C17 when the carrier frequency is 20 kHz.

[0088] Figure 15A shows that, assuming the capacitance of capacitor C17 remains the same, the voltage across capacitor C17 tends to decrease as the carrier frequency increases.

[0089] Figure 15B shows the capacitance dependence of the voltage change across capacitor C17. It shows the time change of the voltage across capacitor C17 when the capacitance of capacitor C17 is changed, with a carrier frequency of 20 kHz. In Figure 15B, "A4" shows the time change of the voltage across capacitor C17 when the capacitance of capacitor C17 is 0.2 μF, "A5" shows the time change of the voltage across capacitor C17 when the capacitance of capacitor C17 is 1 μF, and "A6" shows the time change of the voltage across capacitor C17 when the capacitance of capacitor C17 is 10 μF.

[0090] Figure 15B shows that, for the same carrier frequency, the voltage across capacitor C17 tends to decrease as the capacitance of capacitor C17 decreases.

[0091] The factors causing the voltage drop across each capacitor C17 in multiple first bootstrap circuits 71 have been explained with reference to Figures 14A and 14B, and the same applies to the factors causing the voltage drop across each capacitor C27 in multiple second bootstrap circuits 72 and the factors causing the voltage drop across each capacitor C37 in multiple third bootstrap circuits 73.

[0092] In the multilevel inverter 100, the capacitance of each capacitor C17 in the multiple first bootstrap circuits 71 is set to a value between 10μF and 50μF. In addition, in the multilevel inverter 100, the capacitance of each capacitor C27 in the multiple second bootstrap circuits 72 is set to a value between 10μF and 50μF. In addition, in the multilevel inverter 100, the capacitance of each capacitor C37 in the multiple third bootstrap circuits 73 is set to a value between 10μF and 50μF.

[0093] The capacitances of each capacitor C17, C27, and C37 are set, for example, according to the value of the carrier frequency. The method for determining the capacitances of each capacitor C17, C27, and C37 will be explained with reference to Figures 16-18, after the operation of the control unit of the multilevel inverter related to the comparative example has been explained with reference to Figures 19A, 19B, 20, and 21.

[0094] (3) Comparative Example In the comparative example of the multilevel inverter, the control unit performs a control that replaces some voltage vectors with other voltage vectors in voltage vector control in order to suppress the voltage drop of the capacitor in the bootstrap circuit.

[0095] The control unit selects the command voltage vector V from a group of voltage vectors. * Select multiple (for example, five) voltage vectors adjacent to (see Figure 19A). In the example in Figure 19A, the multiple voltage vectors are V8p[PP0], V8n[00N], V13[P0N], V7p[P00], and V7n[0NN].

[0096] The control unit has a command voltage vector V, which is the reference magnitude among multiple voltage vectors. * One of the two first voltage vectors VV1 (V8p[PP0] and V8n[00N] in the example of Figure 19A), which are the two voltage vectors VV1 closest to the zero potential, is replaced with a zero vector V0n[NNN] in a combination where the potential level of the third connection point 13 of the multiple inverter circuits 1 is at the negative potential, and at least one second voltage vector VV2 (V2[PPN] in the example of Figure 19A) which has the same direction as the first voltage vector VV1 but a different magnitude. The reference magnitude is, for example, (2 / 3) 1 / 2 ·Vdc. Therefore, the multiple voltage vectors include 12 voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], V12n[0N0]. Command voltage vector V * The two closest first voltage vectors VV1 and command voltage vector V * The angle it makes is less than 30 degrees.

[0097] The control unit sets the command voltage vector V to a composite vector of three voltage vectors other than the first voltage vector VV1 (V8p[PP0] and V8n[00N] in the example of Figure 19A) (V13[P0N], V7p[P00], and V7n[0NN] in the example of Figure 19B), the zero vector V0n[NNN], and at least one second voltage vector VV2. * Multiple first gate drivers, multiple second gate drivers, multiple third gate drivers, and multiple fourth gate drivers are controlled within a predetermined control period Ts (see Figure 20) to match this. In the comparative example, the predetermined control period Ts is, for example, two periods of the carrier signal.

[0098] In the example shown in Figure 20, the on / off states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 occur within the control period Ts as shown in Figure 21.

[0099] Furthermore, in the comparative example multilevel inverter, the control unit controls the command voltage vector V * The first voltage vector VV1 may be replaced with the zero vector V0n[NNN] and the second voltage vector VV2 only when the polarity of the corresponding command voltage is positive, or the first voltage vector VV1 may be replaced with the zero vector V0n[NNN] and the second voltage vector VV2 even when the polarity of the command voltage is negative.

[0100] In the comparative example of the multilevel inverter, complex control is required in the multilevel vector control by the control unit to replace the voltage vector, which can make it difficult to increase the carrier frequency.

[0101] (4) Relationship between the minimum capacitance of the capacitor in the bootstrap circuit, the carrier frequency, and the multilevel vector control (MLVC) ratio Figure 16 is a graph showing the simulation results of the relationship between the minimum capacitance of capacitor C17 included in the first bootstrap circuit 71, the carrier frequency, and the multilevel vector control (MLVC) ratio. "Minimum capacitance" refers to the lower limit of the capacitance of capacitor C17 required to maintain the gate voltage value necessary to turn the first switching element Q1 on and off. "MLVC ratio" indicates the ratio of voltage vector control of the comparative example to voltage vector control of Embodiment 1. A value of 0 for the MLVC ratio means that only voltage vector control of Embodiment 1 is performed, and voltage vector control of the comparative example is not performed. Furthermore, a value of MLVC ratio greater than 0 means that the frequency of voltage vector substitution in the voltage vector control of the comparative example is higher.

[0102] In Figure 16, the specified plane PL1, enclosed by a thick line, is the plane that defines the minimum capacitance of capacitor C17 required to maintain the gate voltage value (e.g., 11[V]) necessary to turn the first switching element Q1 on and off in capacitor C17. Therefore, if the capacitance of capacitor C17 is greater than the minimum capacitance of the point obtained by perpendicularly projecting any point of the combination of carrier frequency and MLVC ratio onto the specified plane PL1 in Figure 16, it is possible to maintain the gate voltage value necessary to turn the first switching element Q1 on and off in capacitor C17.

[0103] As can be seen from Figure 16, for example, when the carrier frequency is 6kHz and the MLVC ratio is 0%, the minimum capacitance of capacitor C17 is 10μF, and when the carrier frequency is 20kHz and the MLVC ratio is 0%, the minimum capacitance of capacitor C17 is 37μF.

[0104] Figure 17 is a graph showing the simulation results of the relationship between the minimum capacitance of capacitor C17 in the first bootstrap circuit 71 and the carrier frequency. From Figure 17, it can be seen that the minimum capacitance of capacitor C17 increases as the carrier frequency increases. Note that Figure 17 is the graph in Figure 16 when the HLVC ratio is 0%.

[0105] Figure 18 is a graph showing the relationship between the minimum capacitance of capacitor C17 in the first bootstrap circuit 71 and the MLVC ratio. Figure 18 shows the relationship between the minimum capacitance of capacitor C17 and the MLVC ratio for the cases of carrier frequencies of 6kHz, 10kHz, 16kHz, and 20kHz in Figure 16. From Figure 18, it can be seen that the minimum capacitance of capacitor C17 increases as the carrier frequency increases. Also from Figure 18, it can be seen that the minimum capacitance of capacitor C17 can be reduced by increasing the MLVC ratio.

[0106] The upper limit of the minimum capacitance of each capacitor C17 in the multiple first bootstrap circuits 71 is preferably 50μF, from the viewpoint of using a smaller capacitor than an aluminum electrolytic capacitor as capacitor C17. Therefore, the capacitance of each capacitor C17 in the multiple first bootstrap circuits 71 is preferably between 10μF and 50μF.

[0107] Each capacitor C17 in the multiple first bootstrap circuits 71 is, for example, a multilayer ceramic capacitor, a film capacitor, or a tantalum electrolytic capacitor.

[0108] We have described the minimum capacitance of each capacitor C17 in the multiple first bootstrap circuits 71, and the same applies to the minimum capacitance of each capacitor C27 in the multiple second bootstrap circuits 72 and the minimum capacitance of each capacitor C37 in the multiple third bootstrap circuits 73.

[0109] (5) Advantages In the multilevel inverter 100 according to Embodiment 1, the capacitance of the capacitor C17 included in each of the multiple first bootstrap circuits 71 is 10 μF or more and 50 μF or less.

[0110] According to the above configuration, it is possible to suppress the voltage drop of the first bootstrap circuit 71. More specifically, when the carrier frequency is in the range of 6kHz to 20kHz, the control unit 60 can maintain the voltage of the capacitor C17 of the multiple first bootstrap circuits 71 at or above the voltage required to switch the first switching element Q1 on and off, without performing special voltage vector control to replace the voltage vector.

[0111] Furthermore, in the multilevel inverter 100 according to Embodiment 1, the capacitance of the capacitor C27 included in each of the multiple second bootstrap circuits 72 is 10 μF or more and 50 μF or less.

[0112] With the above configuration, it is possible to suppress the voltage drop across capacitor C27 of the second bootstrap circuit 72.

[0113] Furthermore, in the multilevel inverter 100 according to Embodiment 1, the capacitance of each of the multiple third bootstrap circuits 73 is 10 μF or more and 50 μF or less.

[0114] According to the above configuration, it is possible to suppress the voltage drop across capacitor C37 of the third bootstrap circuit 73.

[0115] Furthermore, in the multilevel inverter 100 according to Embodiment 1, the DC-DC converter 91 included in the power supply unit 9 supplies voltage to the multiple fourth gate drivers 64 and the multiple third bootstrap circuits 73. As a result, the multilevel inverter 100 according to Embodiment 1 can be miniaturized while suppressing the voltage drop of each of the multiple third bootstrap circuits 73.

[0116] (Embodiment 2) In the following, the multi-level inverter 100A according to Embodiment 2 will be described based on Figures 22 to 29.

[0117] (1) Overall configuration of the multilevel inverter The multilevel inverter 100A comprises, for example, a DC power supply unit 3, a plurality of inverter circuits 1 (three in the example in Figure 22), and a control device 6, as shown in Figure 22. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The control device 6 controls the plurality of inverter circuits 1.

[0118] The multilevel inverter 100A is a T-type 3-level 3-phase inverter. In the multilevel inverter 100A, each of the multiple inverter circuits 1 has an output terminal 41. In the multilevel inverter 100A, an AC load RA1 is connected to multiple (three in the example of Figure 22) output terminals (AC terminals) 41. The AC load RA1 is, for example, a 3-phase servo motor. In the multilevel inverter 100A, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs the U-phase voltage, another is an inverter circuit 1V that outputs the V-phase voltage, and the remaining one is an inverter circuit 1W that outputs the W-phase voltage.

[0119] Each of the multiple inverter circuits 1 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4, and a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 are connected in antiparallel to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4, respectively. In each of the multiple inverter circuits 1, the first switching element Q1 and the second switching element Q2 are connected in series such that they are arranged in the order of first switching element Q1 and second switching element Q2 from the positive electrode P1 side to the negative electrode N1 side. That is, as shown in Figures 22 and 23, the series circuit of the first switching element Q1 and the second switching element Q2 (first circuit 111) is connected between the positive electrode P1 and the negative electrode N1. In each of the multiple inverter circuits 1, a series circuit (second circuit 112) of a third switching element Q3 and a fourth switching element Q4 is connected between an intermediate potential point M1 and an output point. The output point is the connection point 113 of the first switching element Q1 and the second switching element Q2. The second circuit 112 has a bidirectional switch including the third switching element Q3, the fourth switching element Q4, the third diode D3, and the fourth diode D4.

[0120] The control device 6 includes a plurality of (three in the example of Figure 22) first gate drivers 61, a plurality of (three in the example of Figure 22) second gate drivers 62, a plurality of (three in the example of Figure 22) third gate drivers 63, and a plurality of (three in the example of Figure 22) fourth gate drivers 64. The control device 6 also includes a plurality of (three in the example of Figure 22) bootstrap circuits 71 (hereinafter also referred to as first bootstrap circuits 71), a plurality of (three in the example of Figure 22) second bootstrap circuits 72, a power supply unit 9, and a control unit 60.

[0121] Multiple first gate drivers 61 drive the first switching elements Q1 of the multiple inverter circuits 1. Multiple second gate drivers 62 drive the second switching elements Q2 of the multiple inverter circuits 1. Multiple third gate drivers 63 drive the third switching elements Q3 of the multiple inverter circuits 1. Multiple fourth gate drivers 64 drive the fourth switching elements Q4 of the multiple inverter circuits 1.

[0122] Multiple first bootstrap circuits 71 correspond one-to-one with multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 supplies voltage to the corresponding first gate driver 61 from among the multiple first gate drivers 61. Multiple second bootstrap circuits 72 correspond to multiple third gate drivers 63 and multiple fourth gate drivers 64. Each of the multiple second bootstrap circuits 72 supplies voltage to the corresponding third gate driver 63 and the corresponding fourth gate driver 64 from among the multiple third gate drivers 63. The power supply unit 9 supplies voltage to the multiple second gate drivers 62.

[0123] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64.

[0124] (2) Details of the multilevel inverter The DC power supply unit 3 includes a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series. In the DC power supply unit 3, the first end of the first capacitor C1 is connected to the first DC terminal 31, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the first capacitor C1 and the second capacitor C2 is the intermediate potential point M1. The DC power supply unit 3 further includes a first DC terminal 31 connected to the positive terminal P1 and a second DC terminal 32 connected to the negative terminal N1. A DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32, for example. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1. "The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" does not mean that the capacitance of the second capacitor C2 is exactly the same as the capacitance of the first capacitor C1, but rather that the capacitance of the second capacitor C2 is within the range of 95% to 105% of the capacitance of the first capacitor C1.

[0125] In the following explanation, for convenience, the output terminal 41 included in inverter circuit 1U will be referred to as output terminal 41U, the output terminal 41 included in inverter circuit 1V will be referred to as output terminal 41V, and the output terminal included in inverter circuit 1W will be referred to as output terminal 41W.

[0126] Each inverter circuit 1 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4, each having a control terminal, a first main terminal, and a second main terminal. Each inverter circuit 1 has an IGBT, for example. Therefore, the control terminal, first main terminal, and second main terminal of each of the first switching element Q1, second switching element Q2, third switching element Q3, and fourth switching element Q4 in each inverter circuit 1 are the gate terminal, collector terminal, and emitter terminal, respectively.

[0127] The control terminal of the first switching element Q1 of each inverter circuit 1 is connected to the corresponding first gate driver 61 from among a plurality of first gate drivers 61. Similarly, the control terminal of the second switching element Q2 of each inverter circuit 1 is connected to the corresponding second gate driver 62 from among a plurality of second gate drivers 62. Furthermore, the control terminal of the third switching element Q3 of each inverter circuit 1 is connected to the corresponding third gate driver 63 from among a plurality of third gate drivers 63. Finally, the control terminal of the fourth switching element Q4 of each inverter circuit 1 is connected to the corresponding fourth gate driver 64 from among a plurality of fourth gate drivers 64.

[0128] In each inverter circuit 1, the first main terminal of the first switching element Q1 is connected to the positive terminal P1 of the DC power supply unit 3, the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2, and the second main terminal of the second switching element Q2 is connected to the negative terminal N1 of the DC power supply unit 3.

[0129] Furthermore, in each inverter circuit 1, the first main terminal of the third switching element Q3 is connected to the intermediate potential point M1, the second main terminal of the third switching element Q3 is connected to the second main terminal of the fourth switching element Q4, and the first main terminal of the fourth switching element Q4 is connected to the connection point 113. Therefore, the bidirectional switch of the second circuit 112 is a common-emitter bidirectional switch in which the second main terminals (emitter terminals) of the third switching element Q3 and the fourth switching element Q4 are connected to each other. The "intermediate potential point M1" is the point where the potential is midway between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3. In Embodiment 1, since the intermediate potential point M1 is connected to ground, the potential of the intermediate potential point M1 is 0V. In this case, if the voltage across the DC power supply unit 3 is Vdc, the potential of the positive electrode P1 is Vdc / 2, and the potential of the negative electrode N1 is -Vdc / 2.

[0130] In inverter circuit 1U, the connection point 113 between the first switching element Q1 and the second switching element Q2 is connected to the output terminal 41U. In inverter circuit 1V, the connection point 113 between the first switching element Q1 and the second switching element Q2 is connected to the output terminal 41V. In inverter circuit 1W, the connection point 113 between the first switching element Q1 and the second switching element Q2 is connected to the output terminal 41W. The connection point 113 of inverter circuit 1U is connected to, for example, the U phase of an AC load RA1 via the output terminal 41U. The connection point 113 of inverter circuit 1V is connected to, for example, the V phase of an AC load RA1 via the output terminal 41V. The connection point 113 of inverter circuit 1W is connected to, for example, the W phase of an AC load RA1 via the output terminal 41W.

[0131] In each inverter circuit 1, the anode of the first diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In addition, in each inverter circuit 1, the anode of the second diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In addition, in each inverter circuit 1, the anode of the third diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. Furthermore, in each inverter circuit 1, the anode of the fourth diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0132] In each inverter circuit 1, the first diode D1 may be replaced with a parasitic diode of the IGBT constituting the first switching element Q1. Also, in each inverter circuit 1, the second diode D2 may be replaced with a parasitic diode of the IGBT constituting the second switching element Q2. Also, in each inverter circuit 1, the third diode D3 may be replaced with a parasitic diode of the IGBT constituting the third switching element Q3. Also, in each inverter circuit 1, the fourth diode D4 may be replaced with a parasitic diode of the IGBT constituting the fourth switching element Q4.

[0133] Multiple first gate drivers 61 correspond one-to-one with multiple first switching elements Q1. Each of the multiple first gate drivers 61 is connected to the control terminal of the corresponding first switching element Q1 among the multiple first switching elements Q1. The multiple first gate drivers 61 drive the corresponding first switching elements Q1. The multiple first gate drivers 61 are connected to a control unit 60. The control unit 60 outputs multiple first control signals S1 (see Figure 23) that correspond one-to-one with the multiple first gate drivers 61. Each of the multiple first gate drivers 61 controls the first switching element Q1 to be on or off based on the given first control signal S1.

[0134] Multiple second gate drivers 62 correspond one-to-one with multiple second switching elements Q2. Each of the multiple second gate drivers 62 is connected to the control terminal of the corresponding second switching element Q2 among the multiple second switching elements Q2. The multiple second gate drivers 62 drive the corresponding second switching elements Q2. The multiple second gate drivers 62 are connected to a control unit 60. The control unit 60 outputs multiple second control signals S2 (see Figure 23) that correspond one-to-one with the multiple second gate drivers 62. Each of the multiple second gate drivers 62 controls the on / off state of the second switching element Q2 based on the given second control signal S2.

[0135] Multiple third gate drivers 63 correspond one-to-one with multiple third switching elements Q3. Each of the multiple third gate drivers 63 is connected to the control terminal of the corresponding third switching element Q3. The multiple third gate drivers 63 drive the corresponding third switching element Q3. The multiple third gate drivers 63 are connected to a control unit 60. The control unit 60 outputs multiple third control signals S3 (see Figure 2) that correspond one-to-one with the multiple third gate drivers 63. Each of the multiple third gate drivers 63 controls the on / off state of the third switching element Q3 based on the given third control signal S3.

[0136] Multiple fourth gate drivers 64 correspond one-to-one with multiple fourth switching elements Q4. Each of the multiple fourth gate drivers 64 is connected to the control terminal of the corresponding fourth switching element Q4 among the multiple fourth switching elements Q4. The multiple fourth gate drivers 64 drive the corresponding fourth switching element Q4. The multiple fourth gate drivers 64 are connected to a control unit 60. The control unit 60 outputs multiple fourth control signals S4 (see Figure 23) that correspond one-to-one with the multiple fourth gate drivers 64. Each of the multiple fourth gate drivers 64 controls the on / off state of the fourth switching element Q4 based on the given fourth control signal S4.

[0137] Multiple first bootstrap circuits 71 correspond one-to-one with multiple first gate drivers 61. Multiple first bootstrap circuits 71 supply voltage to the corresponding first gate drivers 61. Each of the multiple first bootstrap circuits 71 has a diode D17, a resistor R17, and a capacitor C17 (also called a boost capacitor C17), as shown in Figures 22 and 24. In each first bootstrap circuit 71, the anode of diode D17 is connected to the positive terminal of the power supply unit 9, and the cathode of diode D17 is connected to the first terminal of capacitor C17 via resistor R17. The first terminal of capacitor C17 is connected to the high-potential side power supply terminal 61H (see Figure 24) of the first gate driver 61, and the second terminal of capacitor C17 is connected to the low-potential side power supply terminal 61L (see Figure 24) of the first gate driver 61. The first bootstrap circuit 71 supplies the voltage necessary to turn on the first switching element Q1 in the first gate driver 61. Each of the multiple first bootstrap circuits 71 further has a Zener diode Z17 connected in parallel with the capacitor C17.

[0138] Multiple second bootstrap circuits 72 correspond to multiple third gate drivers 63 and multiple fourth gate drivers 64. Multiple second bootstrap circuits 72 supply voltage to the corresponding third gate drivers 63 and corresponding fourth gate drivers 64. Each of the multiple second bootstrap circuits 72 has a diode D27, a resistor R27 and a capacitor C27 (also called a boost capacitor C27). In each second bootstrap circuit 72, the anode of diode D27 is connected to the positive terminal of the power supply unit 9, and the cathode of diode D27 is connected to the first terminal of capacitor C27 via resistor R27. The first end of capacitor C27 is connected to the high-potential power supply terminal 63H (see Figure 24) of the third gate driver 63 and the high-potential power supply terminal 64H (see Figure 24) of the fourth gate driver 64, and the second end of capacitor C27 is connected to the low-potential power supply terminal 63L (see Figure 24) of the third gate driver 63 and the low-potential power supply terminal 64L (see Figure 24) of the fourth gate driver 64. The second bootstrap circuit 72 supplies the voltage necessary to turn on the third switching element Q3 in the third gate driver 63, and supplies the voltage necessary to turn on the fourth switching element Q4 in the fourth gate driver 64. Each of the multiple second bootstrap circuits 72 further has a Zener diode Z27 connected in parallel with capacitor C27.

[0139] The power supply unit 9 supplies voltage to multiple (three in the example of Figure 22) first bootstrap circuits 71, multiple (three in the example of Figure 22) second bootstrap circuits 72, and multiple (three in the example of Figure 22) second gate drivers 62. The power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91. The positive terminal of the power supply unit 9 is connected to the high-potential side power supply terminal 62H (see Figure 24) of each of the multiple second gate drivers 62, and the negative terminal of the power supply unit 9 is connected to the low-potential side power supply terminal 62L (see Figure 24) of each of the multiple second gate drivers 62.

[0140] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. In this way, the control unit 60 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control unit 60 includes a computer system. The computer system has one or more computers. The computer system mainly consists of a processor and memory as hardware. The function of the control unit 60 as the execution entity in this disclosure is realized by the processor executing a program recorded in the memory of the computer system. The program may be pre-recorded in the memory of the computer system, provided via a telecommunications line, or provided on a non-temporary recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) that can be read by the computer system. The processor of the computer system consists of one or more electronic circuits including semiconductor integrated circuits (ICs) or large-scale integrated circuits (LSIs). The multiple electronic circuits may be integrated onto a single chip or distributed across multiple chips. Multiple chips may be integrated into a single device, or they may be distributed across multiple devices.

[0141] The control unit 60 outputs multiple (three) first control signals S1 (see Figure 23) for controlling multiple (three) first switching elements Q1, multiple (three) second control signals S2 (see Figure 23) for controlling multiple (three) second switching elements Q2, multiple (three) third control signals S3 (see Figure 23) for controlling multiple third switching elements Q3, and multiple (three) fourth control signals S4 (see Figure 23) for controlling multiple (three) fourth switching elements Q4. Note that in Figure 23, only one of the three inverter circuits 1 is shown, and the remaining two inverter circuits 1 are not shown. Also, in Figure 23, the multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, multiple fourth gate drivers 64, multiple first bootstrap circuits 71, multiple second bootstrap circuits 72, and the power supply unit 9 are not shown. Furthermore, in Figure 24, only one of the three inverter circuits 1 is shown, and the remaining two inverter circuits 1 are omitted from the illustration. Also, in Figure 24, the two first gate drivers 61, the two second gate drivers 62, the two third gate drivers 63, the two fourth gate drivers 64, the two first bootstrap circuits 71, and the two second bootstrap circuits 72 are omitted from the illustration.

[0142] The three first control signals S1 include a first control signal S1U that controls the first switching element Q1 of the inverter circuit 1U, a first control signal S1V that controls the first switching element Q1 of the inverter circuit 1V, and a first control signal S1W that controls the first switching element Q1 of the inverter circuit 1W.

[0143] The three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of inverter circuit 1U, a second control signal S2V that controls the second switching element Q2 of inverter circuit 1V, and a second control signal S2W that controls the second switching element Q2 of inverter circuit 1W.

[0144] The three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the inverter circuit 1U, a third control signal S3V that controls the third switching element Q3 of the inverter circuit 1V, and a third control signal S3W that controls the third switching element Q3 of the inverter circuit 1W.

[0145] The three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of inverter circuit 1U, a fourth control signal S4V that controls the fourth switching element Q4 of inverter circuit 1V, and a fourth control signal S4W that controls the fourth switching element Q4 of inverter circuit 1W.

[0146] Each of the multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level. The first potential level is, for example, 0V, and the second potential level is a potential level greater than the gate threshold voltage of the IGBT. In other words, in each of the multiple control signals (multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4), the first potential level is the potential level required to turn off the switching element corresponding to that control signal, and the second potential level is the potential level required to turn on the switching element corresponding to that control signal.

[0147] Each of the multiple first switching elements Q1 is turned on when the corresponding first control signal S1 is high and turned off when it is low. Similarly, each of the multiple second switching elements Q2 is turned on when the corresponding second control signal S2 is high and turned off when it is low. Similarly, each of the multiple third switching elements Q3 is turned on when the corresponding third control signal S3 is high and turned off when it is low. Similarly, each of the multiple fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is high and turned off when it is low.

[0148] In the multilevel inverter 100A, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. In other words, in the multilevel inverter 100A, the switching state of each of the three inverter circuits 1U, 1V, and 1W is controlled to one of the first switching state, a second switching state, or a third switching state. The first, second, and third switching states differ in the combination of on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from each other. In other words, in each of the multiple inverter circuits 1, the potential level of the output voltage changes in three levels depending on the state of the first to fourth switching elements Q1 to Q4. Regarding the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with each other.

[0149] The first switching state is a combination in which both the first switching element Q1 and the third switching element Q3 are ON, and both the second switching element Q2 and the fourth switching element Q4 are OFF. Each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3 when controlled to the first switching state. In the first switching state, the potential of the connection point 113 of each of the multiple inverter circuits 1 is at the potential level of the positive electrode P1 of the DC power supply unit 3 (e.g., Vdc / 2).

[0150] The second switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the off state, and both the third switching element Q3 and the fourth switching element Q4 are in the on state. Each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3 when controlled to the second switching state. In the second switching state, the potential of the connection point 113 of each of the multiple inverter circuits 1 is at the potential level of the intermediate potential point M1 (for example, 0).

[0151] The third switching state is a combination in which both the first switching element Q1 and the third switching element Q3 are in the off state, and both the second switching element Q2 and the fourth switching element Q4 are in the on state. Each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3 when controlled to the third switching state. In the third switching state, the potential of the connection point 113 of each of the multiple inverter circuits 1 is at the potential level of the negative electrode N1 of the DC power supply unit 3 (for example, -Vdc / 2).

[0152] When the inverter circuit 1 is in the first switching state, as shown in Figure 23, current flows through the path from the positive electrode P1 of the DC power supply unit 3 - the first switching element Q1 - the connection point 113 - the output terminal 41, and the output voltage value to the AC load RA1 (see Figure 22) becomes Vdc / 2.

[0153] Furthermore, when the inverter circuit 1 is in the first switching state, the power supply unit 9 does not charge the capacitor C17 of the first bootstrap circuit 71. Instead, the capacitor C17 of the first bootstrap circuit 71 supplies the voltage necessary for the first gate driver 61 to turn on the first switching element Q1. Consequently, the charge on the capacitor C17 of the first bootstrap circuit 71 is discharged through the discharge path Ru1 of capacitor C17 - high-potential side power supply terminal 61H of the first gate driver 61 - low-potential side power supply terminal 61L of the first gate driver 61 - capacitor C17, as shown in Figure 24. As a result, the voltage across capacitor C17 in the first bootstrap circuit 71 decreases over time.

[0154] Furthermore, when the inverter circuit 1 is in the first switching state, the power supply unit 9 does not charge the capacitor C27 of the second bootstrap circuit 72. Instead, the capacitor C27 of the second bootstrap circuit 72 supplies the voltage necessary for the third gate driver 63 to turn on the third switching element Q3. Consequently, the charge on the capacitor C27 of the second bootstrap circuit 72 is discharged through the discharge path Ru3 of capacitor C27 - high-potential power supply terminal 63H of the third gate driver 63 - low-potential power supply terminal 63L of the third gate driver 63 - capacitor C27, as shown in Figure 24. As a result, the voltage across capacitor C27 in the second bootstrap circuit 72 decreases over time.

[0155] Furthermore, when inverter circuit 1 is in the second switching state (when it changes from the first switching state to the second switching state), current flows through the path of the DC power supply unit 3 from the intermediate potential point M1 - third switching element Q3 - fourth switching element Q4 - connection point 113 - output terminal 41 (see Figure 22), as shown in Figure 25, and the voltage value of the output voltage to the AC load RA1 becomes 0. More specifically, when inverter circuits 1U, 1V, and 1W are in the second switching state, third switching state, and third switching state, respectively, current flows through the path of the DC power supply unit 3 from the intermediate potential point M1 - third switching element Q3 of inverter circuit 1U - fourth switching element Q4 of inverter circuit 1U - connection point 113 - output terminal 41U.

[0156] Furthermore, when the inverter circuit 1 is in the second switching state, the capacitor C27 of the second bootstrap circuit 72 supplies the voltage necessary for the third gate driver 63 to turn on the third switching element Q3. Therefore, the charge of the capacitor C27 of the second bootstrap circuit 72 is discharged through the discharge path Ru3 of capacitor C27 - high-potential side power supply terminal 63H of the third gate driver 63 - low-potential side power supply terminal 63L of the third gate driver 63 - capacitor C27, as shown in Figure 26. Also, when the inverter circuit 1 is in the second switching state, the capacitor C27 of the second bootstrap circuit 72 supplies the voltage necessary for the fourth gate driver 64 to turn on the fourth switching element Q4. Therefore, the charge on capacitor C27 of the second bootstrap circuit 72 is discharged through the discharge path Ru4: capacitor C27 - high-potential power supply terminal 64H of the fourth gate driver 64 - low-potential power supply terminal 64L of the fourth gate driver 64 - capacitor C27.

[0157] Furthermore, when the inverter circuit 1 is in the third switching state, as shown in Figure 27, current flows through the path from the output terminal 41 - connection point 113 - second switching element Q2 - negative terminal N1 of the DC power supply unit 3, and the output voltage value to the AC load RA1 becomes -Vdc / 2. Also, when the inverter circuit 1 is in the third switching state, the capacitor C17 of the first bootstrap circuit 71 is charged by the power supply unit 9, so the voltage of capacitor C17 rises over time and capacitor C17 becomes fully charged. As shown in Figure 28, the charging path Ru91 that charges capacitor C17 by the power supply unit 9 is the path from the positive terminal of the power supply unit 9 - diode D17 - resistor R17 - capacitor C17 - connection point 113 - second switching element Q2 - negative terminal of the power supply unit 9.

[0158] Furthermore, when the inverter circuit 1 is in the third switching state, the power supply unit 9 charges the capacitor C27 of the second bootstrap circuit 72. The charging path Ru92 for charging the capacitor C27 by the power supply unit 9 is the path from the positive terminal of the power supply unit 9 - diode D27 - resistor R27 - capacitor C27 - fourth switching element Q4 - connection point 113 - second switching element Q2 - negative terminal of the power supply unit 9.

[0159] Furthermore, when inverter circuit 1 is in the second switching state (when it changes from the third switching state to the second switching state), for example, as shown in Figure 29, current flows through the path from output terminal 41 - connection point 113 - fourth switching element Q4 - third switching element Q3 - intermediate potential point M1, and the output voltage value to the AC load RA1 becomes 0. More specifically, when inverter circuits 1U, 1V, and 1W are in the second switching state, second switching state, and first switching state, respectively, current flows through the path from output terminal 41 of inverter circuit 1U - connection point 113 - fourth switching element Q4 - third switching element Q3 - intermediate potential point M1, and the output voltage value to the AC load RA1 becomes 0.

[0160] Here, when the inverter circuit 1 is in the second switching state, discharge occurs through the discharge paths Ru3 and Ru4 shown in Figure 26 above.

[0161] The control unit 60 generates, for example, first to fourth control signals S1 to S4 (S1U to S4U) for the first to fourth switching elements Q1 to Q4 of inverter circuit 1U, first to fourth control signals S1 to S4 (S1V to S4V) for the first to fourth switching elements Q1 to Q4 of inverter circuit 1V, and first to fourth control signals S1 to S4 (S1W to S4W) for the first to fourth switching elements Q1 to Q4 of inverter circuit 1W, based on voltage commands Vu, Vv, and Vw (see Figure 8) relating to the output voltages of inverter circuits 1U, 1V, and 1W, respectively.

[0162] As shown in Figure 8, the voltage command Vu and the voltage command Vv are, for example, sinusoidal signals with a phase difference of 120° from each other, and their respective values ​​(voltage command values) change over time. The length of one period for voltage commands Vu, Vv, and Vw is the same. The control unit 60 may also perform PI (Proportional Integral) control of the voltage commands Vu, Vv, and Vw based on the information output from the detection unit 8, which detects the state of the AC load RA1. When the AC load RA1 is a three-phase motor, the information output from the detection unit 8 includes, for example, at least one of the following: information from the detection results of multiple current sensors that detect the output current flowing through the U, V, and W phases of the AC load RA1, and information from the detection results of an encoder that detects the rotation speed, rotation angle, etc., of the three-phase motor.

[0163] The operation of one of the three inverter circuits 1 (for example, the U-phase inverter circuit 1U) will be described below. The operation of the V-phase inverter circuit 1V and the W-phase inverter circuit 1W is the same as the operation of the U-phase inverter circuit 1U. The output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with respect to each other.

[0164] The control unit 60 controls the plurality of first gate drivers 61, plurality of second gate drivers 62, plurality of third gate drivers 63, and plurality of fourth gate drivers 64 by performing voltage vector control. The control unit 60 performs voltage vector control in the same manner as in Embodiment 1. Within the control period Ts (see Figures 12 and 13), the control unit 60 controls the command voltage vector V * (See Figure 11) The resultant vector of the vertices of the equilateral triangle surrounding the command voltage vector V is * Multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, and multiple fourth gate drivers 64 are controlled to match this. The method of voltage vector control is the same as in Embodiment 1, so the explanation is omitted.

[0165] The factors causing the voltage drop across each capacitor C17 in the multiple first bootstrap circuits 71 are the same as in Embodiment 1. Similarly, the factors causing the voltage drop across each capacitor C27 in the multiple second bootstrap circuits 72 are the same as in Embodiment 1.

[0166] The upper limit of the minimum capacitance of each capacitor C17 in the multiple first bootstrap circuits 71 is preferably 50μF, from the viewpoint of using a smaller capacitor than an aluminum electrolytic capacitor as capacitor C17. Therefore, the capacitance of each capacitor C17 in the multiple first bootstrap circuits 71 is preferably between 10μF and 50μF.

[0167] Each capacitor C17 in the multiple first bootstrap circuits 71 is, for example, a multilayer ceramic capacitor, a film capacitor, or a tantalum electrolytic capacitor.

[0168] We have described the minimum capacitance of each capacitor C17 in the multiple first bootstrap circuits 71, and the same applies to the minimum capacitance of each capacitor C27 in the multiple second bootstrap circuits 72.

[0169] In the multilevel inverter 100A, the capacitance of each capacitor C17 in the multiple first bootstrap circuits 71 is set to a value between 10μF and 50μF. Furthermore, in the multilevel inverter 100A, the capacitance of each capacitor C27 in the multiple second bootstrap circuits 72 is set to a value between 10μF and 50μF.

[0170] (3) Advantages In the multilevel inverter 100A according to Embodiment 2, the capacitance of the capacitor C17 included in each of the multiple first bootstrap circuits 71 is 10μF or more and 50μF or less.

[0171] According to the above configuration, it is possible to suppress the voltage drop of the first bootstrap circuit 71. More specifically, when the carrier frequency is in the range of 6kHz to 20kHz, the control unit 60 can maintain the voltage of the capacitor C17 of the multiple first bootstrap circuits 71 at or above the voltage required to switch the first switching element Q1 on and off, without performing special voltage vector control to replace the voltage vector.

[0172] Furthermore, in the multi-level inverter 100A according to Embodiment 2, the capacitance of the capacitor C27 included in each of the multiple second bootstrap circuits 72 is 10μF or more and 50μF or less.

[0173] With the above configuration, it is possible to suppress the voltage drop across capacitor C27 of the second bootstrap circuit 72.

[0174] (modified version) Embodiments 1 and 2 described above are merely one of many embodiments of this disclosure. Embodiments 1 and 2 can be modified in various ways depending on the design, etc., as long as the objectives of this disclosure are achieved.

[0175] For example, each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 is not limited to IGBTs, but may be a MOSFET. In this case, the control terminal, first main terminal, and second main terminal of each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 are the gate terminal, drain terminal, and source terminal, respectively. In each switching circuit 10, the MOSFETs constituting each of the first switching element Q1, second switching element Q2, third switching element Q3, and fourth switching element Q4 are, for example, normally-off n-channel MOSFETs. Note that the MOSFETs are Si-based MOSFETs, but are not limited to Si-based MOSFETs; for example, they may be SiC-based MOSFETs.

[0176] Furthermore, each of the multiple first bootstrap circuits 71 includes a Zener diode Z17, but may also be configured without a Zener diode Z17. Similarly, each of the multiple second bootstrap circuits 72 includes a Zener diode Z27, but may also be configured without a Zener diode Z27.

[0177] Furthermore, the multilevel inverters 100 and 100A can be any multilevel inverter with three or more levels, for example, a five-level inverter.

[0178] (Aspect) The following embodiments are disclosed herein.

[0179] A multilevel inverter (100;100A) according to the first embodiment comprises a DC power supply unit (3), a plurality of inverter circuits (1), and a control device (6). The DC power supply unit (3) has a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1). The plurality of inverter circuits (1) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply unit (3). The control device (6) controls the plurality of inverter circuits (1). Each of the plurality of inverter circuits (1) is a neutral point clamp type inverter. Each of the plurality of inverter circuits (1) has a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4), and a first diode (D1), a second diode (D2), a third diode (D3), and a fourth diode (D4). The first diode (D1), second diode (D2), third diode (D3), and fourth diode (D4) are connected in antiparallel to the first switching element (Q1), second switching element (Q2), third switching element (Q3), and fourth switching element (Q4), respectively. The control device (6) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of bootstrap circuits (71), a power supply unit (9), and a control unit (60). The plurality of first gate drivers (61) drive each of the first switching elements (Q1) of the plurality of inverter circuits (1). The plurality of second gate drivers (62) drive each of the second switching elements (Q2) of the plurality of inverter circuits (1). The plurality of third gate drivers (63) drive each of the third switching elements (Q3) of the plurality of inverter circuits (1). Multiple fourth gate drivers (64) drive the fourth switching elements (Q4) of each of the multiple inverter circuits (1). Multiple bootstrap circuits (71) correspond one-to-one with multiple first gate drivers (61). Each of the multiple bootstrap circuits (71) supplies voltage to the corresponding first gate driver (61) among the multiple first gate drivers (61). The power supply unit (9) supplies voltage to the multiple bootstrap circuits (71).The control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64). Each of the plurality of bootstrap circuits (71) includes a capacitor (C17) and a diode (D17) connected in series with the capacitor (C17). The capacitance of the capacitor (C17) included in each of the plurality of bootstrap circuits (71) is between 10 μF and 50 μF.

[0180] According to this embodiment, it is possible to suppress the voltage drop of the bootstrap circuit (71). More specifically, according to this embodiment, it is possible to suppress the voltage drop of the capacitors (C17) of multiple bootstrap circuits (71).

[0181] In the multilevel inverter (100;100A) according to the second embodiment, in the first embodiment, the control unit (60) controls the command voltage vector (V) from a group of voltage vectors. * The command voltage vector (V) is the resultant vector of multiple voltage vectors corresponding to the vertices of the equilateral triangle surrounding it. * Multiple first gate drivers (61), multiple second gate drivers (62), multiple third gate drivers (63), and multiple fourth gate drivers (64) are controlled within a predetermined control period (Ts) to match the specified value. Each of the group of voltage vectors is determined by a combination of multiple potential levels in multiple inverter circuits (1).

[0182] In the third embodiment of the multilevel inverter (100), in the first or second embodiment, each of the plurality of inverter circuits (1) has a first clamp diode (D5) and a second clamp diode (D6). In each of the plurality of inverter circuits (1), a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) are connected in series between the positive electrode (P1) and the negative electrode (N1) in the order of first switching element (Q1), second switching element (Q2), third switching element (Q3), and fourth switching element (Q4) from the positive electrode (P1) side. In each of the plurality of inverter circuits (1), the cathode of the first clamp diode (D5) is connected to the first connection point (11) between the first switching element (Q1) and the second switching element (Q2), and the anode of the first clamp diode (D5) is connected to an intermediate potential point (M1). In each of the multiple inverter circuits (1), the anode of the second clamp diode (D6) is connected to the second connection point (12) between the third switching element (Q3) and the fourth switching element (Q4), and the cathode of the second clamp diode (D6) is connected to the intermediate potential point (M1). The third connection point (13) between the second switching element (Q2) and the third switching element (Q3) is connected to the output terminal (41) which is connected to an AC load.

[0183] A multilevel inverter (100A) according to the fourth embodiment is based on the first or second embodiment. In each of the plurality of inverter circuits (1), a first switching element (Q1) and a second switching element (Q2) are connected in series such that they are arranged in the order of first switching element (Q1) and second switching element (Q2) from the positive terminal (P1) side to the negative terminal (N1) side. In each of the plurality of inverter circuits (1), a series circuit of a third switching element (Q3) and a fourth switching element (Q4) is connected between an intermediate potential point (M1) and an output point. The output point is the connection point (113) between the first switching element (Q1) and the second switching element.

[0184] The multilevel inverter (100;100A) according to the fifth embodiment is based on any one of the first to fourth embodiments. In each of the plurality of inverter circuits (1), the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4) are each insulated-gate bipolar transistors.

[0185] In the sixth embodiment of the multilevel inverter (100;100A), in any one of the first to fifth embodiments, the capacitor (C17) included in each of the multiple bootstrap circuits (71) is a multilayer ceramic capacitor, a film capacitor, or a tantalum electrolytic capacitor.

[0186] According to this embodiment, it is possible to miniaturize the multilevel inverter (100;100A) compared to the case where an aluminum electrolytic capacitor is used as the capacitor (C17). [Explanation of Symbols]

[0187] 1. Inverter Circuit 3 DC power supply section 6 Control device 60 Control Unit 61. First Gate Driver 62 Second Gate Driver 63 Third Gate Driver 64. Gate 4 Driver 9 Power supply section 11. First connection point 12. Second connection point 13. Third connection point 71 Bootstrap Circuit (First Bootstrap Circuit) 100, 100A Multilevel Inverter 113 Connection point (output point) C17 Capacitor D1 First Diode D2 Second Bypass D3 Third Diode D4 4th diode D5 First clamp diode D6 Second clamp diode D17 Diode P1 positive electrode Q1 First switching components Q2 Second switching Q3 Third switching element Q4 Fourth switching element M1 Intermediate potential point N1 negative electrode Ts control period V0~V18 Voltage Vectors V * Command voltage vector VV1 First voltage vector VV2 Second voltage vector

Claims

1. A DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point, A plurality of inverter circuits connected between the positive and negative electrodes of the DC power supply unit, The system comprises a control device that controls the plurality of inverter circuits, Each of the aforementioned plurality of inverter circuits is a neutral point clamp type inverter, Each of the aforementioned plurality of inverter circuits is A first switching element, a second switching element, a third switching element, and a fourth switching element, The first switching element, the second switching element, the third switching element, and the fourth switching element are connected in antiparallel to each other, respectively, and include a first diode, a second diode, a third diode, and a fourth diode. The control device is A plurality of first gate drivers that drive the first switching element of each of the plurality of inverter circuits, A plurality of second gate drivers that drive the second switching element of each of the plurality of inverter circuits, A plurality of third gate drivers that drive the third switching element of each of the plurality of inverter circuits, A plurality of fourth gate drivers that drive the fourth switching element of each of the plurality of inverter circuits, Multiple bootstrap circuits that correspond one-to-one with the aforementioned multiple first gate drivers and supply voltage to the corresponding first gate drivers, A power supply unit that supplies voltage to the aforementioned multiple bootstrap circuits, It comprises a control unit that controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers, Each of the aforementioned bootstrap circuits is Capacitors and, The capacitor includes a diode connected in series with the capacitor, The capacitance of the capacitor included in each of the aforementioned bootstrap circuits is between 10 μF and 50 μF. Multilevel inverter.

2. The control unit, The plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers are controlled within a predetermined control period so that the composite vector of the plurality of voltage vectors corresponding to the vertices of the equilateral triangle surrounding the command voltage vector, each of which is determined by a combination of multiple potential levels in the plurality of inverter circuits, matches the command voltage vector. The multilevel inverter according to claim 1.

3. Each of the aforementioned plurality of inverter circuits is The first clamp diode and It has a second clamp diode, In each of the aforementioned plurality of inverter circuits, Between the positive electrode and the negative electrode, the first switching element, the second switching element, the third switching element, and the fourth switching element are connected in series in the order of the first switching element, the second switching element, the third switching element, and the fourth switching element from the positive electrode side. The cathode of the first clamp diode is connected to the first connection point between the first switching element and the second switching element, and the anode of the first clamp diode is connected to the intermediate potential point. The anode of the second clamp diode is connected to the second connection point between the third switching element and the fourth switching element, and the cathode of the second clamp diode is connected to the intermediate potential point. The third connection point between the second switching element and the third switching element is connected to an output terminal connected to an AC load. A multilevel inverter according to claim 1 or 2.

4. In each of the aforementioned plurality of inverter circuits, The first switching element and the second switching element are connected in series such that they are arranged in the order of the first switching element and the second switching element from the positive side to the negative side. The series circuit of the third switching element and the fourth switching element is connected between the intermediate potential point and the output point. The output point is the connection point between the first switching element and the second switching element. A multilevel inverter according to claim 1 or 2.

5. In each of the aforementioned plurality of inverter circuits, Each of the first switching element, the second switching element, the third switching element, and the fourth switching element is an insulated-gate bipolar transistor. A multilevel inverter according to any one of claims 1 to 4.

6. Each of the aforementioned bootstrap circuits includes a capacitor that is either a multilayer ceramic capacitor, a film capacitor, or a tantalum electrolytic capacitor. A multilevel inverter according to any one of claims 1 to 5.

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