Semiconductor device and its manufacturing method

Abstract

The present invention provides a semiconductor device equipped with a conductor plug advantageous for miniaturization, and a method for manufacturing the same. [Solution] The semiconductor device comprises a silicon substrate 11, a first conductor pattern (silicide layer 13) provided on the silicon substrate 11, an orientation control layer 15 formed in a part of the first conductor pattern 13, and a component formed on the orientation control layer 15. <001> The device comprises a conductor plug 16a containing a CoSn (cobalt-tin) phase whose direction is oriented in the direction normal to the silicon substrate 11, and a second conductor pattern (wiring 18) formed on the upper surface of the conductor plug 16a.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] To further increase the integration of semiconductor devices such as logic circuits and memories, it is effective to use conductive materials that do not easily increase in electrical resistance even when miniaturized for the conductive plugs of semiconductor devices. For example, when the thickness and width of a conductive material pattern are reduced, the contribution to electrical resistance due to the scattering of conduction electrons by the surface of the pattern becomes dominant, and the resistivity of the pattern increases. This phenomenon is particularly pronounced in Cu (copper) wiring, which has an isotropic Fermi velocity distribution and a long mean free path, and the development of conductive materials to replace copper is desirable.

[0003] As such materials, metals, alloys, and ceramic materials with anisotropic Fermi velocity distributions are being investigated. For example, ruthenium (Ru), which has a close-packed hexagonal structure, has an anisotropic Fermi velocity distribution and its resistivity depends on the crystal orientation. By ensuring that the crystal orientation with low resistivity is the direction in which the conductive pattern extends, the increase in resistivity due to surface scattering can be suppressed.

[0004] From this perspective, materials exhibiting one-dimensional electrical conductivity are considered ideal, and material predictions are being made through theoretical calculations. Non-patent document 1 reports that the intermetallic compound CoSn (cobalt-tin) is promising for fine wiring.

[0005] CoSn is a hexagonal intermetallic compound with a kagome lattice and a composition of 50:50 atomic percent. It has been reported that the resistivity of CoSn bulk single crystal samples exhibits a significant dependence on crystal orientation.

[0006] Non-patent document 2 states that the CoSn bulk single crystal sample is in the c-axis direction. <001> While the resistivity in the direction at room temperature is approximately 3 μΩcm, <001> It has been reported that the resistivity at room temperature in the (001) plane perpendicular to the direction is 100 μΩcm. Thus, CoSn is in multiple directions. <001> It is a quasi-one-dimensional conductive material that has low electrical resistivity only in one direction.

[0007] Non-patent documents 3 and 4 also report the anisotropic electrical resistivity of CoSn.

[0008] <001> To take advantage of CoSn's characteristic of having low electrical resistivity only in one direction, the direction in which the conductor plug made of CoSn extends must be <001> It is desirable to control the crystal orientation of CoSn so that it aligns with the desired direction.

[0009] For example, Non-Patent Document 5 describes forming a Pt / Ru buffer layer on an MgO(110) single crystal substrate and then forming a CoSn single crystal film on top of it. Also, Non-Patent Document 6 describes forming a CoSn single crystal film on a 4H-SiC(0004) single crystal substrate.

[0010] However, since silicon substrates are used in the manufacturing process of semiconductor devices, these technologies using MgO single crystal substrates or 4H-SiC single crystal substrates cannot be used in the manufacturing process of semiconductor devices. [Prior art documents] [Non-patent literature]

[0011] [Non-Patent Document 1] S. Kumar, et al., “Ultralow electron-surface scattering in nanoscale metals leveraging Fermi-surface anisotropy”, Physical Review Materials, Vol. 6, p. 85002, 2022, APS [Non-Patent Document 2] H. Huang, et al., “Flat-band-induced anomalous anisotropic charge transport and orbital magnetism in kagome metal CoSn”, Physical Review Letters, Vol. 128, p. 96601, 2022, APS [Non-Patent Document 3] WRMeier, et al., “Flat bands in the CoSn-type compounds”, Physical Review B, Volume 102, Page 075148, 2020, APS [Non-Patent Document 4] BCSales, et al., “Tuning the flat bands of the kagome metal CoSn with Fe, In, or Ni doping”, Physical Review Materials, Vol. 5, p. 44202, 2021, APS [Non-Patent Document 5] TRThapaliya, et al., “High-quality epitaxial thin films of topological kagome metal CoSn by magnetron sputtering”, Applied Physics Letters, Vol. 119, No. 20, 2021, AIP Publishing. [Non-Patent Document 6] S. Cheng, et al., “Epitaxial Kagome Thin Films as a Platform for Topological Flat Bands”, Nano Letters, Vol. 23, pp. 7107-7113, 2023, ACS Publications [Overview of the project] [Problems that the invention aims to solve]

[0012] In one aspect, the present invention aims to provide a semiconductor device equipped with a conductive plug advantageous for miniaturization and a method for manufacturing the same.

Means for Solving the Problem

[0013] According to one aspect of the following disclosure, a semiconductor device includes a substrate, a first conductor pattern provided on the substrate, an orientation control layer formed in a partial region of the first conductor pattern, a conductor plug formed on the orientation control layer and including a CoSn (cobalt tin) phase in which the <001> direction faces the normal direction of the substrate, and a second conductor pattern formed on the conductor plug.

[0014] In the semiconductor device, the orientation control layer may include a single-layer film of any one of Ru (ruthenium), Re (rhenium), Os (osmium), Zn (zinc), and Co (cobalt) or an alloy thereof, or a single-layer film of an alloy of any one of Ti (titanium), Hf (hafnium), Mg (magnesium), Zr (zirconium) and Co (cobalt).

[0015] In the semiconductor device, the orientation control layer may be a laminated film in which a Ta (tantalum) layer and the single-layer film are laminated in this order.

[0016] In the semiconductor device, it may further include an insulating layer provided on the first conductor pattern and having holes formed in the partial region, and the orientation control layer and the conductor plug may be provided in the holes.

[0017] In the semiconductor device, the orientation control layer may also be formed on the side surface of the hole.

[0018] In the semiconductor device, the first conductor pattern may be a conductor layer containing silicon.

[0019] In the semiconductor device, it has a gate insulating layer provided on the substrate and a gate electrode provided on the gate insulating layer, and the first conductor pattern may be a source region or a drain region provided on the substrate beside the gate electrode.

[0020] In the semiconductor device, the first conductor pattern and the second conductor pattern may be wirings.

[0021] According to another aspect of the following disclosure, a method of manufacturing a semiconductor device includes forming a first conductor pattern on a substrate, forming an orientation control layer on a partial region of the first conductor pattern, forming a conductor plug including a CoSn (cobalt tin) phase having a <001> direction facing a normal direction of the substrate on the orientation control layer, and forming a second conductor pattern on the conductor plug.

[0022] In the method of manufacturing the semiconductor device, as the orientation control layer, a single-layer film of any one of Ru (ruthenium), Re (rhenium), Os (osmium), Zn (zinc), and Co (cobalt) or an alloy thereof, or a single-layer film of an alloy of any one of Ti (titanium), Hf (hafnium), Mg (magnesium), Zr (zirconium) and Co (cobalt) may be formed.

[0023] In the method of manufacturing the semiconductor device, forming the orientation control layer may include forming a Ta (tantalum) layer on the partial region of the first conductor pattern and forming the single-layer film on the tantalum layer.

[0024] In the method of manufacturing the semiconductor device, forming the conductor plug may include forming a CoSn layer constituting the conductor plug on the orientation control layer while heating the substrate.

[0025] In the method of manufacturing the semiconductor device, further including forming an insulating layer on the first conductor pattern and forming a hole in the insulating layer in the partial region of the first conductor pattern, and in forming the orientation control layer, forming the orientation control layer in the hole, and in forming the conductor plug, forming the conductor plug on the orientation control layer formed in the hole.

[0026] In the above-described method for manufacturing a semiconductor device, the orientation control layer may be formed on a portion of the first conductor pattern and on the side surface of the hole. [Effects of the Invention]

[0027] According to the present invention, it is possible to provide a semiconductor device equipped with a conductive plug that is advantageous for miniaturization, and a method for manufacturing the same. [Brief explanation of the drawing]

[0028] [Figure 1] Figure 1 is a schematic diagram showing the crystal structure of CoSn. [Figure 2] Figures 2(a) to 2(c) are cross-sectional views of the samples used in the study. [Figure 3] Figure 3 shows the XRD spectra (X-Ray Diffraction) of the CoSn layer in Comparative Examples 1-3. [Figure 4] Figure 4 shows the XRD spectra of the CoSn layer in Examples 1-3. [Figure 5] Figure 5 shows the XRD spectra of the CoSn layer in Examples 4 and 5. [Figure 6] Figure 6 shows the XRD spectra of the CoSn layer in Examples 6-10. [Figure 7] Figure 7 is a table summarizing the results from Figures 3 to 6. [Figure 8] Figures 8(a) and 8(b) are cross-sectional views (part 1) of a semiconductor device during the manufacturing process according to the first embodiment. [Figure 9] Figures 9(a) and 9(b) are cross-sectional views (part 2) of a semiconductor device during the manufacturing process according to the first embodiment. [Figure 10] Figure 10 is a cross-sectional view (part 3) of a semiconductor device during the manufacturing process according to the first embodiment. [Figure 11] Figures 11(a) and (b) are cross-sectional views (part 1) of a semiconductor device during the manufacturing process according to the second embodiment. [Figure 12]Figures 12(a) and (b) are cross-sectional views (part 2) of a semiconductor device during the manufacturing process according to the second embodiment. [Figure 13] Figures 13(a) and (b) are cross-sectional views (part 3) of a semiconductor device during the manufacturing process according to the second embodiment. [Figure 14] Figure 14 is a cross-sectional view of a semiconductor device according to the third embodiment. [Figure 15] Figure 15 is a cross-sectional view of a semiconductor device according to the fourth embodiment. [Modes for carrying out the invention]

[0029] Embodiments of the present invention will be described below with reference to the drawings. Similar elements are denoted by the same reference numerals, and their descriptions are omitted.

[0030] The inventors of this application investigated whether CoSn (cobalt-tin) conductor plugs could be used in the manufacturing process of semiconductor devices. Therefore, we will first explain the crystal structure of CoSn.

[0031] Figure 1 is a schematic diagram showing the crystal structure of CoSn. In Figure 1, Co and Sn are each present in an atomic ratio of 50 at%. 50 Sn 50 The crystal structure is shown as an example.

[0032] As shown in Figure 1, Co 50 Sn 50 It is a hexagonal crystal with a space group of P6 / mmm, and the c-axis direction <001> It has a Kagome plane perpendicular to the direction. When referring to the CoSn phase below, it means the Co with the crystal structure shown in Figure 1. 50 Sn 50 This refers to...

[0033] This CoSn phase has a resistivity compared to the (001) plane. <001> It is a pseudo-one-dimensional conductive material with an extremely low directional resistivity of approximately 3 μΩcm. Therefore, <001> If a CoSn phase is formed so that its orientation is normal to the substrate, and a conductive plug can be constructed from this CoSn phase, the resistance of the conductive plug, in which current flows mainly along the direction normal to the substrate, can be reduced. Moreover, even if the diameter of the conductive plug is reduced, the increase in resistivity due to the scattering of conduction electrons on the surface of the conductive plug is suppressed, which is advantageous for miniaturizing the conductive plug. In particular, if the conductive plug can be formed on a silicon substrate, the conductive plug can be formed in the mass production process of existing semiconductor devices. Therefore, the inventors of this application investigated the orientation of thin films of CoSn formed on various substrates.

[0034] Figures 2(a) to 2(c) show cross-sectional views of the samples used in this study.

[0035] Of these, Figure 2(a) is a cross-sectional view of the samples according to Examples 1 to 3. As shown in Figure 2(a), in Examples 1 to 3, a silicon substrate 1 with a thermal oxide film 2 with a thickness of 500 nm formed on its surface was prepared, and a Ru (ruthenium) layer 3 was formed on the thermal oxide film 2 by magnetron sputtering. The surface of the Ru layer 3 is the (001) plane. The thickness of the Ru layer 3 was 1 nm for Example 1, 2 nm for Example 2, and 5 nm for Example 3. The film deposition conditions for the Ru layer 3 other than thickness were the same for Examples 1 to 3, with the substrate temperature at room temperature (approximately 30°C), the deposition pressure at 0.1 Pa, and the sputtering gas being Ar (argon) gas. The DC power applied between the Ru target and the substrate holder (not shown) was 100 W.

[0036] Subsequently, a 30 nm thick CoSn layer 4 was formed on the Ru layer 3 using magnetron sputtering. Here, by simultaneously sputtering the Co (cobalt) target and the Sn (tin) target, the Co and Sn atoms were each at a concentration of 50 at%. 50 Sn 50Layers were formed. The substrate temperature for forming the CoSn layer 4 was 400°C, the deposition pressure was 0.1 Pa, and the sputtering gas was Ar gas. The frequency of the RF power applied between the Co target and the substrate holder (not shown) was 13.56 MHz, and the power was 100 W. The frequency of the RF power applied between the Sn target and the substrate holder (not shown) was 13.56 MHz, and the power was 50 W.

[0037] Figure 2(a) also shows the normal direction n of the silicon substrate 1. The normal direction n is the direction perpendicular to the surface of the silicon substrate 1. The same applies to Figures 2(b) and (c) below.

[0038] Figure 2(b) is a cross-sectional view of the samples according to Examples 4 to 10. As shown in Figure 2(b), in Examples 4 to 10, an amorphous Ta layer 5 was formed on the thermal oxide film 2 by magnetron sputtering, and then a Ru layer 3 and a CoSn layer 4 were formed on top of it in that order. The thickness of the Ta layer 5 was 1 nm in Example 4 and 2 nm in Examples 5 to 10. The other conditions for forming the Ta layer 5 were the same in Examples 4 to 10, with a deposition pressure of 0.1 Pa, a substrate temperature of room temperature (approximately 30°C), and Ar gas as the sputtering gas. In addition, the DC power applied between the Ta target and the substrate holder (not shown) was 100 W.

[0039] The deposition conditions for Ru layer 3 were the same as those for Examples 1-3, except for the thickness of Ru layer 3. The thickness of Ru layer 3 was 2 nm in Examples 4-7 and 5 nm in Examples 8-10.

[0040] The deposition conditions for CoSn layer 4 were the same as those for Examples 1-3, except for the substrate temperature. The substrate temperature for deposition of CoSn layer 4 was 200°C in Example 6, 250°C in Example 7, 300°C in Example 8, 400°C in Examples 4, 5, and 9, and 500°C in Example 10. The thickness of CoSn layer 4 was 30 nm in all Examples 4-10.

[0041] FIG. 2(c) is a cross-sectional view of the samples according to Comparative Examples 1 to 3. As shown in FIG. 2(c), in Comparative Examples 1 to 3, without forming the Ru3 and Ta layers 5, the CoSn layer 4 was directly formed on the thermal oxide film 2 by magnetron sputtering. The film formation temperature of the CoSn layer 4 was room temperature (about 30° C.) in Comparative Example 1 and Comparative Example 2, and 400° C. in Comparative Example 3. The film formation conditions of the CoSn layer 4 other than this were the same as those in Examples 1 to 3, and the thickness thereof was 30 nm.

[0042] Furthermore, in Comparative Example 2, annealing was performed for 30 minutes with the substrate temperature set to 400° C. after the formation of the CoSn layer 4. The atmosphere for the annealing was a vacuum atmosphere with a pressure of 1×10 -5 Pa or less.

[0043] Note that, in Comparative Examples 1 and 3 and Examples 1 to 10, annealing was not performed after the formation of the CoSn layer 4.

[0044] The inventor of the present application obtained the XRD (X-Ray Diffraction) spectra of the CoSn layer 4 related to these samples in order to investigate the crystallinity of the CoSn layer 4 in each of Examples 1 to 10 and Comparative Examples 1 to 3.

[0045] First, the XRD spectra of Comparative Examples 1 to 3 in which the CoSn layer 4 is formed on the thermal oxide film 2 will be described.

[0046] FIG. 3 is the XRD spectrum of the CoSn layer 4 in Comparative Examples 1 to 3. The horizontal axis in FIG. 3 indicates the diffraction angle of the X-ray, and the vertical axis indicates the intensity of the diffracted X-ray.

[0047] The XRD spectrum was obtained using SmartLab manufactured by Rigaku Corporation. Here, a CuKα tube was used, and the X-ray output was set to 45 kV and 200 mA. The divergence slit was automatic, and a two-dimensional X-ray detector HyPix-3000 (manufactured by Rigaku Corporation) was used as the detector. The operating range of the diffraction angle was 10° or more and 100° or less, and the read width of the diffracted X-ray was 0.01°. In FIG. 3, the diffraction peak derived from the silicon substrate 1 is marked with the symbol "*". The same applies to FIGS. 4 to 6 described later.

[0048] As shown in Figure 3, in Comparative Example 1, in addition to the diffraction peak originating from the silicon substrate 1, 002 and 003 diffraction peaks of the CoSn phase were observed. However, these diffraction peaks were very weak in intensity. From this result, it was found that the CoSn phase in the CoSn layer 4 of Comparative Example 1 was hardly oriented and had poor crystallinity.

[0049] On the other hand, in Comparative Example 2, where annealing was performed after the formation of the CoSn layer 4, the diffraction peaks 001, 002, and 003 of the CoSn phase were observed more clearly than in Comparative Example 1.

[0050] In Comparative Example 2, the full width at half maximum (FWHM) of the rocking curve of the 002 diffraction peak was 13.0°. The FWHM of the rocking curve is an indicator of whether the crystal orientation is good, and a smaller value indicates better crystal orientation. In this embodiment, when the FWHM of the rocking curve of the 002 diffraction peak is greater than 0° and less than 13°, the CoSn phase is such that low resistance can be achieved in a conductor plug miniaturized to a diameter of 100 nm or less. <001> It is determined that the orientation is preferential in that direction. Based on this criterion, the CoSn phase in Comparative Example 2 is suitable for use as a conductor plug. <001> The preferred orientation in a given direction is insufficient.

[0051] Furthermore, numerous diffraction peaks were observed in Comparative Example 3. Excluding the diffraction peaks originating from the silicon substrate 1, indicated by "*", these diffraction peaks are explained by the CoSn phase. However, the intensity of the 002 diffraction peak was weaker than in Comparative Example 2. <001> No clear preference orientation in a particular direction could be identified.

[0052] As described above, in Comparative Examples 1 and 3, in which a CoSn layer 4 is formed on the thermal oxide film 2, <001> No clear preferred orientation in any particular direction was observed. In Comparative Example 2, <001> Although preferred orientation in a particular direction was confirmed, annealing is necessary after the formation of the CoSn layer 4 to achieve this preferred orientation.

[0053] Next, we will describe the XRD spectra of Examples 1 to 3, in which a CoSn layer 4 is formed on top of a Ru layer 3.

[0054] Figure 4 shows the XRD spectra of CoSn layer 4 in Examples 1-3. The meaning of the horizontal and vertical axes in Figure 4, and the method of acquiring the XRD spectra, are the same as in Comparative Examples 1-3 in Figure 3, so their explanation is omitted.

[0055] As shown in Figure 4, in all of Examples 1 to 3, after excluding the diffraction peaks originating from the silicon substrate 1, only the diffraction peaks of 001, 002, and 004 of the CoSn phase were observed. This is because the diffraction peaks originating from the silicon substrate 1 are in the direction n normal to the silicon substrate 1. <001> This indicates that the CoSn layer 4 contains CoSn phases that are preferentially oriented in a specific direction. This allows for the formation of a CoSn layer 4 with low electrical resistance along the normal direction n, which is advantageous for miniaturizing the conductor plug.

[0056] Furthermore, the intensity of the 002 diffraction peak increased in the order of Examples 1, 2, and 3, indicating that the intensity of the 002 diffraction peak increased as the thickness of the Ru layer 3 increased. In addition, when the full width at half maximum of the rocking curve of the 002 diffraction peak was measured, it was 12.9°, 10.8°, and 7.1° for Examples 1, 2, and 3, respectively. This indicates that as the thickness of the Ru layer 3 increases, the CoSn phase contained in the CoSn layer 4 increases. <001> This indicates a stronger orientation towards a particular direction.

[0057] Next, we will describe the XRD spectra of Examples 4 and 5, in which a CoSn layer 4 is formed on top of a Ta layer 5 (see Figure 2(b)).

[0058] Figure 5 shows the XRD spectra of the CoSn layer 4 in Examples 4 and 5. The meaning of the horizontal and vertical axes in Figure 5 and the method of obtaining the XRD spectra are the same as in Comparative Examples 1-3 in Figure 3, so the explanation is omitted. In addition, Figure 5 also shows the XRD spectrum of Example 2 to investigate the effect of the Ta layer 5 on the crystallinity of the CoSn layer 4. As mentioned above, Example 2 is an example in which the CoSn layer 4 is formed on a Ru layer 3 with a thickness of 2 nm, and differs from Examples 4 and 5 only in that there is no Ta layer 5.

[0059] As shown in Figure 5, in Examples 4 and 5, where the Ta layer 5 was formed, the diffraction intensities of 001, 002, and 004 of the CoSn phase were found to be stronger compared to Example 2, where the Ta layer 5 was not formed. Furthermore, when the full width at half maximum of the rocking curve of the 002 diffraction peak was measured, it was 10.8°, 4.8°, and 3.5° for Examples 2, 4, and 5, respectively. From these results, it can be seen that the thicker the Ta layer 5, the stronger the diffraction intensities of the CoSn phase contained in the CoSn layer 4. <001> It was found that the orientation towards a particular direction becomes stronger.

[0060] Next, the XRD spectra of Examples 6 to 10 will be described.

[0061] Figure 6 shows the XRD spectra of the CoSn layer 4 in Examples 6 to 10. As mentioned above, Examples 6 to 10 are all examples in which the Ta layer 5 is formed. However, the deposition temperature of the CoSn layer 4 differs in each of Examples 6 to 10. The deposition temperatures of the CoSn layer 4 in Examples 6 to 10 are 200°C, 250°C, 300°C, 400°C, and 500°C, respectively.

[0062] As shown in Figure 6, in all of Examples 6 to 10, the diffraction peaks 001, 002, and 004 of the CoSn phase were strongly observed. From these results, it can be concluded that in all of Examples 6 to 10, the CoSn phase contained in the CoSn layer 4 is located in the direction n normal to the silicon substrate 1. <001> It was found that the film preferentially oriented in a direction. Furthermore, the full width at half maximum of the rocking curve of the 002 diffraction peak was 4.1°, 3.7°, 3.5°, 3.2°, and 2.9° for Examples 6-10, respectively. From these results, it was found that the higher the deposition temperature of the CoSn layer 4, the more the CoSn layer 4 <001> It was found that the orientation towards a particular direction becomes stronger.

[0063] Figure 7 is a table summarizing the results from Figures 3 to 6.

[0064] As shown in Figure 7, in all of Examples 1 to 10, <001> A CoSn layer 4 with preferential orientation in the direction was obtained. In particular, the full width at half maximum of the rocking curve of the 002 diffraction peak was less than 13° in all of Examples 1 to 10, indicating that the CoSn phase was oriented to such an extent that it is possible to achieve low resistance in conductor plugs with a diameter of 100 nm or less. <001> It was found that orientation is preferred in a particular direction.

[0065] In contrast, no preferred orientation was observed in CoSn layer 4 in Comparative Examples 1 and 3. In Comparative Example 2, <001> Although a CoSn layer 4 with preferred orientation in the direction was obtained, the full width at half maximum (FMAX) of the rocking curve of the 002 diffraction peak was 13°, which is larger than the FMAX of all of Examples 1 to 10, indicating that the orientation was weaker than that of Examples 1 to 10. Furthermore, in Comparative Example 2... <001> In contrast to the case where annealing is required to preferentially orient the CoSn layer 4 in the direction, in Examples 1 to 10, the CoSn layer 4 does not need to be annealed. <001> We were able to prioritize orientation in a particular direction.

[0066] This result indicates that it is possible to form a Ru layer 3 and then a CoSn layer 4 on top of it. <001> It was confirmed that this method is effective in obtaining a CoSn layer 4 containing a CoSn phase preferentially oriented in that direction.

[0067] Furthermore, in Examples 4-10, where the Ta layer 5 is formed below the Ru layer 3, the full width at half maximum (FWHM) of the rocking curve of the 002 diffraction peak was smaller than that of Examples 1-3, where the Ta layer 5 was not formed. Therefore, forming the Ta layer 5 below the Ru layer 3 is beneficial for the CoSn phase. <001> It was found that strengthening the orientation in a particular direction is effective in further miniaturizing the conductor plug.

[0068] Furthermore, in all of Examples 1 to 10, the film deposition temperature of the CoSn layer 4 is set to 200°C or higher and 500°C or lower, so forming the CoSn layer 4 while heating the substrate is possible. <001> It was also revealed that this method is effective in generating a CoSn phase that is preferentially oriented in a particular direction.

[0069] As described above, the Ru layer 3 and the Ta layer 5 below it contain the CoSn phase contained in the CoSn layer 4. <001> It was revealed that it functions as an orientation control layer that preferentially orients in a certain direction. This is because Ru layer 3 has a close-packed hexagonal structure, and the lattice mismatch between the (001) plane of the hexagonal CoSn phase and the (001) plane of Ru is small. Therefore, even if it is a metal layer other than Ru layer 3, as long as it is a metal layer made of a close-packed hexagonal structure, the CoSn phase will be... <001> It functions as an orientation control layer that preferentially orients in a certain direction. Examples of such metals include Re (rhenium), Os (osmium), Zn (zinc), and Co (cobalt). The lattice mismatch between the (001) planes of these metals and the CoSn phase is 5% or less. Therefore, when these metal layers are formed such that their surfaces are (001) planes, the metal layers control the CoSn phase <001> They can be preferentially oriented in a particular direction. The same applies to alloys of these metals. Therefore, a single layer film of Ru, Re, Os, Zn, and Co, or an alloy thereof, may be formed with its surface being a (001) plane, and this single layer film may be used as an orientation control layer.

[0070] Furthermore, while Ti (titanium), Hf (hafnium), Mg (magnesium), and Zr (zirconium) exhibit large lattice mismatches of 10% or more with the CoSn phase in their elemental forms, the lattice mismatch with the (001) plane of the CoSn phase decreases when alloyed with Co. Therefore, a single layer of an alloy of one of Ti, Hf, Mg, or Zr with Co may be formed so that its surface is the (001) plane, and this single layer may be used as an orientation control layer.

[0071] The following describes a semiconductor device equipped with such an orientation control layer.

[0072] (First Embodiment) Figures 8 to 10 are cross-sectional views of a semiconductor device according to the first embodiment during the manufacturing process.

[0073] First, the process for obtaining the cross-sectional structure shown in Figure 8(a) will be explained. First, p-type or n-type impurities are ion-implanted into the surface layer of the silicon substrate 11 to form the source-drain region 12 of a MOS (Metal Oxide Semiconductor) transistor (not shown).

[0074] Next, a high-melting-point metal layer, such as a cobalt layer, is formed on the source-drain region 12 by sputtering. This high-melting-point metal layer is then heated to react with silicon, forming a silicide layer 13 on the source-drain region 12. The silicide layer 13 is a conductive layer containing silicon and is an example of the first conductive pattern.

[0075] Next, a silicon dioxide layer with a thickness of 1 nm to 100 nm is formed on the silicide layer 13 as an insulating layer 14 using the CVD (Chemical Vapor Deposition) method. Subsequently, contact holes 14a are formed in the insulating layer 14 by photolithography and patterning, exposing a portion of region R of the silicide layer 13 at the bottom of the contact holes 14a.

[0076] Next, as shown in Figure 8(b), a single layer of Ru is formed as an orientation control layer 15 by magnetron sputtering on the upper surface of the insulating layer 14, the side surface of the contact hole 14a, and a portion R of the silicide layer 13 exposed from the contact hole 14a. The surface of the Ru layer is the (001) plane. The thickness of the Ru layer is not particularly limited, and for example, as in Examples 1 to 10 described above, the Ru layer can be formed with a thickness of 1 nm to 5 nm. The deposition temperature of the Ru layer is also not particularly limited, and the Ru layer can be formed at a substrate temperature of 300°C to 500°C as in Examples 1 to 10 described above. The sputtering gas is, for example, Ar gas, and the deposition pressure is, for example, 0.01 Pa to 1 Pa. The DC power applied between the Ru target and the silicon substrate 1 can be set appropriately within a range including the values ​​in Examples 1 to 10 described above.

[0077] Furthermore, the orientation control layer 15 is not limited to the Ru layer. As mentioned above, a single layer film of any of Ru, Re, Os, Zn, and Co, or an alloy thereof, may be formed so that its surface is a (001) plane, and this single layer film may be used as the orientation control layer 15. In addition, a single layer film of an alloy of any of Ti, Hf, Mg, and Zr with Co may be formed so that its surface is a (001) plane, and this single layer film may be used as the orientation control layer 15.

[0078] Furthermore, a laminated film in which a Ta layer and a Ru layer with a thickness of 1 nm to 2 nm are stacked in this order may be formed as the orientation control layer 15.

[0079] Next, as shown in Figure 9(a), a CoSn layer 16 is formed on the orientation control layer 15 by magnetron sputtering, and the contact hole 14a is filled with this CoSn layer 16. The CoSn phase contained in the CoSn layer 16 has an atomic ratio of 50 at% for both Co and Sn, and belongs to a hexagonal crystal with a space group of P6 / mmm. Furthermore, within the contact hole 14a, the CoSn layer 16 is in a polycrystalline state consisting of multiple CoSn phases.

[0080] In Examples 1 to 10 (see Figure 7), the solid CoSn layer 4 was investigated, but as in this embodiment, even within the contact hole 14a, the CoSn phase is parallel to the normal direction of the silicon substrate 11 due to the action of the underlying orientation control layer 15. <001> The material is preferentially oriented in a particular direction. This is also true in the third and fourth embodiments described later, in which an orientation control layer 15 and a CoSn layer 16 are formed within the hole.

[0081] In particular, when a laminated film of a Ta layer and a Ru layer is formed as the orientation control layer 15, the CoSn phase is as shown in Examples 4 to 10 (see Figure 7). <001> This makes it possible to further improve the orientation in a particular direction.

[0082] The film deposition conditions for the CoSn layer 16 are not particularly limited; for example, the CoSn layer 16 can be formed under conditions where the substrate temperature is between 200°C and 500°C. By forming the CoSn layer 16 while heating the silicon substrate 11 in this way, as shown in Examples 1 to 10 of Figure 7, <001> A CoSn phase preferentially oriented in the direction can be generated in the CoSn layer 16.

[0083] Alternatively, the CoSn layer 16 may be formed by simultaneously sputtering the Co target and the Sn target, or by sputtering the CoSn alloy target. Furthermore, the sputtering gas is, for example, Ar gas, and the deposition pressure is, for example, 0.01 Pa or more and 1 Pa or less. The frequency and power of the RF power applied between each target and the silicon substrate 1 can be appropriately set within a range that includes the values ​​in Examples 1 to 10 described above.

[0084] Next, as shown in Figure 9(b), the orientation control layer 15 and the CoSn layer 16 are polished using the CMP (Chemical Mechanical Polishing) method to remove these layers from the upper surface of the insulating layer 14. As a result, the CoSn layer 16 remains in the hole 14a as a conductor plug 16a, while the orientation control layer 15 remains on the sides and bottom of the hole 14a.

[0085] The polishing conditions for this CMP method are not particularly limited, and this CMP can be performed using a slurry containing silica as an abrasive. This method of polishing conductive material using the CMP method and leaving residue inside holes and grooves is called the damascene method.

[0086] The diameter of the conductor plug 16a is not particularly limited. However, in order to miniaturize the semiconductor device, it is preferable that the diameter of the conductor plug 16a exposed on the upper surface of the insulating layer 14 be between 2 nm and 50 nm.

[0087] Subsequently, as shown in Figure 10, a copper film is formed on the insulating layer 14 and the conductor plug 16a by electroplating, and then the copper film is polished by the CMP method to leave it as wiring 18 in the wiring groove (not shown) of the insulating layer 14. Note that wiring 18 is an example of a second conductor pattern. This results in a structure in which the silicide layer 13 and the wiring 18 are electrically connected via the conductor plug 16a. The first conductor plug 16a connected to the silicide layer 13 on the source-drain region 12 in this way is also called a contact plug.

[0088] With the above steps, the basic structure of the semiconductor device according to this embodiment is complete.

[0089] According to the embodiment described above, since a Ru layer or the like is formed as the orientation control layer 15, the conductor plug 16a formed thereon <001> A CoSn phase is formed that is preferentially oriented in that direction. As mentioned above, CoSn <001> It is a quasi-one-dimensional conductive material that exhibits low resistivity only in the direction. Therefore, even if the diameter of the conductor plug 16a is reduced, the increase in the resistivity of the conductor plug 16a due to the scattering of conduction electrons on its side surface is suppressed, which is advantageous for miniaturizing semiconductor devices compared to the case where the conductor plug 16a is formed from copper.

[0090] (Second Embodiment) In the first embodiment, the conductor plug 16a was formed by the damascene method, as shown in Figures 9(a) and (b). In contrast, in this embodiment, the conductor plug 16a is formed by the subtractive method.

[0091] Figures 11 to 13 are cross-sectional views of a semiconductor device according to this embodiment during the manufacturing process. In Figures 11 to 13, the same elements described in the first embodiment are denoted by the same reference numerals as in the first embodiment, and their descriptions are omitted below.

[0092] First, as shown in Figure 11(a), the process shown in Figure 8(a) of the first embodiment is performed to form a source-drain region 12 and a silicide layer 13 on the silicon substrate 11.

[0093] Next, a single layer of Ru is formed on the silicide layer 13 as an orientation control layer 15 by magnetron sputtering. The deposition conditions for the Ru layer are the same as in the first embodiment and are therefore omitted.

[0094] Alternatively, instead of the Ru layer, a single layer of Re, Os, Zn, and Co, or an alloy thereof, may be formed as the orientation control layer 15. Furthermore, a single layer of an alloy of Ti, Hf, Mg, and Zr with Co may be formed as the orientation control layer 15.

[0095] Furthermore, a laminated film in which a Ta layer and a Ru layer with a thickness of 1 nm to 2 nm are stacked in this order may be formed as the orientation control layer 15.

[0096] Next, as shown in Figure 11(b), a CoSn layer 16 is formed on the orientation control layer 15 by magnetron sputtering to a thickness of 5 nm to 50 nm. The film deposition conditions for the CoSn layer 16 are the same as in the first embodiment, so their explanation is omitted.

[0097] The CoSn layer 16 is formed by the action of the orientation control layer 15 <001> It is formed to preferentially orient in the direction. In particular, as mentioned above, when a laminated film of a Ta layer and a Ru layer is formed as the orientation control layer 15, the CoSn layer 16 <001> This allows for greater orientation in a given direction.

[0098] Next, we will explain the process for obtaining the cross-sectional structure shown in Figure 12.

[0099] First, a photoresist is applied to the CoSn layer 16, and then exposed and developed to form a mask pattern 21 in a portion of region R. Alternatively, a hard mask such as a silicon dioxide layer may be formed as the mask pattern 21. Next, using the mask pattern 21 as a mask, the orientation control layer 15 and the CoSn layer 16 are dry-etched by RIE (Reactive Ion Etching). As a result, the CoSn layer 16 is left as a conductive plug 16a in a portion of region R, while the orientation control layer 15 remains beneath the conductive plug 16a.

[0100] The etching gas used in this RIE is not particularly limited. For example, a mixed gas of Cl2, BCl3, and CH3OH can be used as the etching gas. This method of forming the conductor plug 16a by photolithography and etching is called the subtractive method.

[0101] The diameter of the conductor plug 16a is not particularly limited, but to achieve miniaturization of the semiconductor device, it is preferable to set its diameter to 2 nm or more and 50 nm or less.

[0102] Next, as shown in Figure 12(b), a silicon dioxide layer is formed on the entire upper surface of the silicon substrate 11 as an insulating layer 14 to a thickness of 1 nm to 100 nm by CVD.

[0103] Next, as shown in Figure 13(a), the insulating layer 14 and the mask pattern 21 are polished by the CMP method, and these layers are removed from the conductor plug 16a.

[0104] Subsequently, as shown in Figure 13(b), copper wiring 18 is formed on the insulating layer 14 and the conductor plug 16a by performing the same steps as in Figure 10 of the first embodiment. This results in a structure in which the silicide layer 13 and the wiring 18 are electrically connected via the conductor plug 16a.

[0105] With the above steps, the basic structure of the semiconductor device according to this embodiment is complete.

[0106] According to the above-described embodiment, a Ru layer or the like is formed as the orientation control layer 15, similar to the first embodiment. <001> A CoSn phase preferentially oriented in a particular direction can be formed on the conductor plug 16a, enabling lower resistance and miniaturization of the conductor plug 16a.

[0107] (Third embodiment) In this embodiment, a CoSn conductor plug is applied to a semiconductor device equipped with a GAA (Gate All Around) type MOS transistor.

[0108] Figure 14 is a cross-sectional view of a semiconductor device according to this embodiment, which includes a GAA-type MOS transistor. The MOS transistor TR comprises a silicon substrate 30, a source region 31a, a drain region 31b, a gate electrode 32, a gate insulating layer 36, and first to third channel layers 37 to 39.

[0109] The method for forming the MOS transistor TR is not particularly limited. In this example, gate electrode-shaped sacrificial layers (not shown) and first to third channel layers 37 to 39 are alternately stacked on a silicon substrate 30 by epitaxial growth. The sacrificial layer (not shown) is, for example, a SiGe (silicon germanium) layer. The first to third channel layers 37 to 39 are, for example, silicon layers.

[0110] Next, source regions 31a and drain regions 31b of silicon are epitaxially grown on both sides of each channel layer 37-39 and on the silicon substrate 30. During this epitaxial growth, impurities with opposite conductivity types are introduced into the source region 31a and drain region 31b, respectively. The source region 31a and drain region 31b are examples of the first conductor pattern.

[0111] Subsequently, the sacrificial layer is removed by etching to form a cavity, and a gate insulating layer 36 of oxide or nitride is formed on the inner wall of the cavity. As an example, a high dielectric constant insulating layer such as an alumina (Al2O3) layer, which has a higher dielectric constant than silicon dioxide, can be formed as the gate insulating layer 36.

[0112] Then, a conductive film such as a titanium nitride film is formed on the surface of the gate insulating layer 36 as the gate electrode 32, and the cavity formed by the removal of the sacrificial layer is filled with the gate electrode 32. Through this process, the basic structure of a GAA structured MOS transistor TR is obtained.

[0113] Next, a silicon dioxide layer is formed as an insulating layer 14 on the source region 31a and the drain region 31b by CVD.

[0114] Then, contact holes 14a extending to the depths of each region 31a and 31b are formed in the insulating layer 14 by photolithography and etching.

[0115] Subsequently, by performing the steps shown in Figures 8 to 10 of the first embodiment, an orientation control layer 15 and a CoSn conductor plug 16a are formed inside the contact hole 14a, and then copper wiring 18 is formed on top of them.

[0116] According to such a semiconductor device, as in the first and second embodiments, a conductor plug 16a is formed on the orientation control layer 15, so the CoSn phase in the conductor plug 16a <001> Prioritizing orientation in a particular direction enables lower resistance and miniaturization of the conductor plug 16a. This makes it possible to achieve lower power consumption, higher speed, and miniaturization of semiconductor devices equipped with GAA-type MOS transistors TR.

[0117] (Fourth Embodiment) In the first to third embodiments, a conductor plug 16a was formed as the first contact plug connecting the silicide layer 13 and the wiring 18. In contrast, in this embodiment, a conductor plug 16a is formed as the second or subsequent via conductor.

[0118] Figure 15 is a cross-sectional view of the semiconductor device according to this embodiment.

[0119] As shown in Figure 15, this semiconductor device comprises a first insulating layer 50, a first wiring 51, a second insulating layer 52, and a second wiring 53.

[0120] Of these, the first insulating layer 50 and the second insulating layer 52 are interlayer insulating layers such as a silicon dioxide layer. The first wiring 51 and the second wiring 53 are both wirings made of copper, aluminum, etc., and are examples of the first conductor pattern and the second conductor pattern, respectively.

[0121] In this example, via holes 52a are formed in the second insulating layer 52 by photolithography and etching. Then, by performing the steps shown in Figures 8(a) to 9(b) of the first embodiment, an orientation control layer 15 and a conductor plug 16a are formed in that order within the via holes 52a, and the wirings 51 and 53 are electrically connected by the conductor plug 16a. The conductor plug 16a is a conductor plug formed in a layer above the first conductor plug of the first to third embodiments, and is also called a via conductor.

[0122] The diameter of the conductor plug 16a is not particularly limited. However, in order to miniaturize the semiconductor device, it is preferable that the diameter of the conductor plug 16a exposed on the surface of the second insulating layer 52 be 2 nm or more and 50 nm or less.

[0123] Similar to the first to third embodiments, in this embodiment as well, a conductor plug 16a is formed on the orientation control layer 15, so the CoSn phase in the conductor plug 16a <001> Preferential orientation in that direction, <001> This enables the directional conductor plug 16a to be made lower in resistance and smaller in size.

[0124] Although this embodiment has been described in detail above, this embodiment is not limited to the above. For example, in the first to third embodiments, semiconductor substrates such as silicon substrates 11 and 30 were used, but any substrate such as an insulating substrate may be used instead of a semiconductor substrate. In that case, a semiconductor layer made of a two-dimensional material such as an oxide semiconductor or a metal oxide dichalcogenide may be formed on the substrate as the channel of the transistor. [Explanation of Symbols]

[0125] 1...Silicon substrate, 2...Thermal oxide film, 3...Ru layer, 4...CoSn layer, 5...Ta layer, 11...Silicon substrate, 12...Source / drain region, 13...Silicide layer, 14...Insulating layer, 14a...Contact hole, 15...Orientation control layer, 16...CoSn layer, 16a...Conductor plug, 18...Wiring, 21...Mask pattern, 30...Silicon substrate, 31a...Source region, 31b...Drain region, 32...Gate electrode, 36...Gate insulating layer, 37-39...First to third channel layers, 50...First insulating layer, 51...First wiring, 52...Second insulating layer, 52a...Via hole, 53...Second wiring.

Claims

1. circuit board and A first conductor pattern provided on the substrate, An orientation control layer formed in a portion of the first conductor pattern, A conductor plug formed on the orientation control layer, containing a CoSn (cobalt-tin) phase whose <001> direction is oriented in the direction normal to the substrate, A second conductor pattern formed on the aforementioned conductor plug, Semiconductor device.

2. The orientation control layer includes a single layer film of any one of Ru (ruthenium), Re (rhenium), Os (osmium), Zn (zinc), and Co (cobalt) or an alloy thereof, or a single layer film of an alloy of any one of Ti (titanium), Hf (hafnium), Mg (magnesium), or Zr (zirconium) and Co (cobalt). The semiconductor device according to claim 1.

3. The orientation control layer is a laminated film formed by stacking a Ta (tantalum) layer and the single layer film in this order. The semiconductor device according to claim 2.

4. The device further comprises an insulating layer provided on the first conductor pattern, in which holes are formed in a portion of the region. The orientation control layer and the conductor plug are provided in the aforementioned hole. The semiconductor device according to any one of claims 1 to 3.

5. The orientation control layer is also formed on the side surface of the hole. The semiconductor device according to claim 4.

6. The first conductor pattern is a conductor layer containing silicon. The semiconductor device according to any one of claims 1 to 5.

7. A gate insulating layer provided on the substrate, It has a gate electrode provided on the gate insulating layer, The first conductor pattern is a source region or drain region provided on the substrate next to the gate electrode. The semiconductor device according to claim 6.

8. The first conductor pattern and the second conductor pattern are wiring. The semiconductor device according to any one of claims 1 to 5.

9. Forming a first conductive pattern on the substrate, Forming an orientation control layer in a portion of the first conductor pattern, A conductive plug containing a CoSn (cobalt-tin) phase is formed on the orientation control layer, with the <001> direction facing the normal direction of the substrate. Forming a second conductor pattern on the aforementioned conductor plug, A method for manufacturing a semiconductor device having [a certain feature].

10. As the orientation control layer, a single layer film of any one of Ru (ruthenium), Re (rhenium), Os (osmium), Zn (zinc), and Co (cobalt) or an alloy thereof, or a single layer film of an alloy of any one of Ti (titanium), Hf (hafnium), Mg (magnesium), or Zr (zirconium) and Co (cobalt) is formed. The method for manufacturing a semiconductor device according to claim 9.

11. Forming the orientation control layer means Forming a Ta (tantalum) layer in a portion of the first conductor pattern, This includes forming the monolayer film on the tantalum layer, A method for manufacturing a semiconductor device according to claim 9 or claim 10.

12. Forming the conductor plug includes forming the CoSn layer constituting the conductor plug on the orientation control layer while heating the substrate. A method for manufacturing a semiconductor device according to any one of claims 9 to 11.

13. Forming an insulating layer on the first conductor pattern, The present invention further comprises forming holes in the insulating layer in a portion of the first conductor pattern, In forming the orientation control layer, the orientation control layer is formed in the hole, In forming the conductor plug, the conductor plug is formed on the orientation control layer formed in the hole. A method for manufacturing a semiconductor device according to any one of claims 9 to 12.

14. In forming the orientation control layer, the orientation control layer is formed on a portion of the first conductor pattern and on the side surface of the hole. The method for manufacturing a semiconductor device according to claim 13.

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