Gate drive circuit

Abstract

To provide a highly efficient and compact gate drive circuit for a power converter that operates at high voltage and high frequency. [Solution] The gate drive circuit has two DC power supplies, the first and second power supplies V1 and V2. The half-bridge circuit has two switching elements Sa and Sb connected in series, and controls the gate signal to two different voltages by controlling the conduction state of the two switching elements Sa and Sb. Reactor L1 is connected to the path through which the gate signal flows, is magnetically coupled with the reactor L1 of the gate drive circuit of other semiconductor elements, and has a constant leakage inductance. Snubber capacitors Csa and Csb are connected in parallel to the switching elements Sa and Sb. During the dead time period, the switching elements Sa and Sb are soft-switched by the energy of the leakage inductance of reactor L1.

Description

Technical Field

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[0001] The present invention relates to a gate drive circuit for semiconductor elements in a power converter driven at high voltage and high frequency, and particularly to a gate drive circuit capable of achieving high frequency and high efficiency.

Background Art

[0002] In Patent Document 1, as shown in FIG. 1 of Patent Document 1, gate lines are magnetically coupled to each other in order to synchronize the gate signals of semiconductor elements connected in series. The magnetic flux of transformer TR1 is reset by diodes Df5, Dr5, Df6, and Dr6. By using this technique, the gate signals can be synchronized, so that the series connection of semiconductor elements can be easily realized.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] <00000?5>However, since the energy stored in the semiconductor element is consumed by the gate resistor Rg, there are the following problems when the frequency is increased. · The loss of the gate resistor increases, so that the resistor becomes large or a cooler is required, resulting in a high cost. <? · The power supply for the gate drive circuit becomes large in capacity, so that the entire device becomes large and expensive. · Since FET5(on), FET5(off), FET6(on), and FET(off) perform hard switching, the loss is large.

[0005] From the above, it is an object of the present invention to provide a gate drive circuit that is highly efficient and small in size in the gate drive circuit of a power converter driven at high voltage and high frequency. It should be noted that there seems to be a typo in the original text where "FET(off)" in ID=41 might be incorrect. Also, "<? " in ID=38 seems to be an incomplete or incorrect tag. But I translated based on the provided text as accurately as possible.[Means for solving the problem]

[0006] The present invention was devised in view of the above-mentioned conventional problems, and one aspect thereof is a gate drive circuit for on / off control that outputs a gate signal to each of a plurality of connected semiconductor elements, comprising: a first and second power supply which are two DC power supplies; a half-bridge circuit or push-pull circuit which has two switching elements connected in series and controls the gate signal to two types of voltage by controlling the conduction state of the two switching elements; a reactor which is connected to the path through which the gate signal flows, is magnetically coupled to the reactor of the gate drive circuit of the other semiconductor element and has a constant leakage inductance; and a snubber capacitor which is connected in parallel to the switching element, wherein the switching element is soft-switched by the energy of the leakage inductance of the reactor during the dead time period.

[0007] Furthermore, in one embodiment, the device comprises: a first power supply whose negative electrode is connected to the second terminal of the semiconductor element; a first diode whose anode is connected to the gate terminal of the semiconductor element and whose cathode is connected to the positive side of the first power supply; a second diode whose anode is connected to the positive electrode of the first power supply; a second power supply connected between the cathode of the second diode and the gate terminal of the semiconductor element; a half-bridge circuit or a push-pull circuit in which two of the switching elements are connected in series between the positive and negative electrodes of the second power supply; a snubber capacitor connected in parallel to the switching elements; and a reactor connected between the anode of the second diode and the connection point of the two switching elements.

[0008] Furthermore, in one embodiment, the present invention is characterized by comprising: a first power supply whose negative electrode is connected to the second terminal of the semiconductor element; a second power supply whose positive electrode is connected to the positive electrode of the first power supply; a half-bridge circuit or a push-pull circuit in which two of the switching elements are connected in series between the positive and negative electrodes of the second power supply; a snubber capacitor connected in parallel to the switching element; a first diode whose cathode is connected to the positive electrode of the second power supply and whose anode is connected to the gate terminal of the semiconductor element; a second diode whose cathode is connected to the anode of the first diode and whose anode is connected to the negative electrode of the second power supply; and a reactor connected between the connection point of the two switching elements and the connection point of the first diode and the second diode.

[0009] Furthermore, in one embodiment, the device comprises the first and second power supplies connected in series, the half-bridge circuit or the push-pull circuit in which two of the switching elements are connected in series between the positive terminal of the second power supply and the negative terminal of the first power supply, the snubber capacitor connected in parallel to the switching elements, the first diode with its cathode connected to the positive terminal of the second power supply and its anode connected to the gate terminal of the semiconductor element, the second diode with its cathode connected to the anode of the first diode and its anode connected to the negative terminal of the first power supply, and the reactor connected between the connection point of the two switching elements and the connection point of the first diode and the second diode, wherein the connection point of the first and second power supplies is connected to the second terminal of the semiconductor element. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a gate drive circuit for a power converter that operates at high voltage and high frequency that is highly efficient and compact. [Brief explanation of the drawing]

[0011] [Figure 1] A diagram showing the circuit configuration of the gate drive circuit in Example 1. [Figure 2]This figure shows an example of the operating waveform of the gate drive circuit in Example 1. [Figure 3] This figure shows the simulated waveform when the gate drive circuit is operated without magnetic coupling. [Figure 4] This figure shows the simulated waveform when the gate drive circuit is operated while magnetically coupled. [Figure 5] This figure shows an example of a soft switching operation waveform in Example 1. [Figure 6] A diagram showing the circuit configuration of the gate drive circuit in Example 2. [Figure 7] This figure shows an example of the operating waveform of the gate drive circuit in Example 2. [Figure 8] A diagram showing the circuit configuration of the gate drive circuit in Example 3. [Figure 9] This figure shows an example of the operating waveform of the gate drive circuit in Example 3. [Modes for carrying out the invention]

[0012] Embodiments 1 to 3 of the gate drive circuit in the present invention will be described in detail below with reference to Figures 1 to 9.

[0013] [Example 1] The gate drive circuit for on / off control in this embodiment 1 outputs a gate signal to each of the connected voltage-driven semiconductor elements. This embodiment 1 describes a gate drive circuit that can achieve high efficiency and miniaturization even at high frequencies while synchronizing the gate signals of the semiconductor elements to be driven.

[0014] Figure 1 shows the circuit configuration of the gate drive circuit in this embodiment 1. As shown in Figure 1, the semiconductor elements T1 and T2 to be driven are connected in series. The semiconductor elements T1 and T2 are, for example, FETs, but other semiconductor elements may also be used. The first drive circuit 1 outputs a gate signal Vgs1 to semiconductor element T1, and the second drive circuit 2 outputs a gate signal Vgs2 to semiconductor element T2.

[0015] First, the first drive circuit 1 will be described. The first drive circuit 1 has two DC power supplies (the first power supply V1 and the second power supply V2). The negative electrode of the first power supply V1 is connected to the second terminal (source terminal) of the semiconductor element T1. The anode of the first diode D1 is connected to the gate terminal of the semiconductor element T1, and the cathode is connected to the positive electrode of the first power supply V1. The anode of the second diode D2 is connected to the positive electrode of the first power supply V1. The positive electrode of the second power supply V2 is connected to the cathode of the second diode D2, and the negative electrode is connected to the gate terminal of the semiconductor element T1.

[0016] The half-bridge circuit is connected between the positive and negative electrodes of the second power supply V2. The half-bridge circuit is composed of switching elements Sa and Sb connected in series. The switching elements Sa and Sb have freewheeling diodes. Also, the half-bridge circuit may be a push-pull circuit. Snubber capacitors Csa and Csb are connected in parallel to the switching elements Sa and Sb.

[0017] The reactor L1 is connected to the path through which the gate signal Vgs1 flows. The reactor L1 of the first embodiment is connected between the connection point of the switching elements Sa and Sb and the anode of the second diode D2. The reactor L1 has a certain leakage inductance.

[0018] Next, the second drive circuit 2 will be described. The configuration of the second drive circuit 2 is the same as that of the first drive circuit 1. The second drive circuit 2 has two DC power supplies (the third power supply V3 and the fourth power supply V4). The negative electrode of the third power supply V3 is connected to the second terminal (source terminal) of the semiconductor element T2. The anode of the third diode D3 is connected to the gate terminal of the semiconductor element T2, and the cathode is connected to the positive electrode of the third power supply V3. The anode of the fourth diode D4 is connected to the positive electrode of the third power supply V3. The positive electrode of the fourth power supply V4 is connected to the cathode of the fourth diode D4, and the negative electrode is connected to the gate terminal of the semiconductor element T2.

[0019] The half-bridge circuit is connected between the positive and negative terminals of the fourth power supply V4. The half-bridge circuit is constructed by connecting switching elements Sc and Sd in series. The switching elements Sc and Sd have freewheeling diodes. Alternatively, the half-bridge circuit may be configured as a push-pull circuit. Snubber capacitors Csc and Csd are connected in parallel to the switching elements Sc and Sd.

[0020] The reactor L1 is connected to the path through which the gate signal Vgs2 flows. In this embodiment 1, the reactor L1 is connected between the connection point of the switching elements Sc and Sd and the anode of the fourth diode D4. The reactor L1 has a constant leakage inductance.

[0021] The circuit in Figure 1 magnetically couples the reactor L1 of the first drive circuit 1 and the reactor L1 of the second drive circuit 2 in order to synchronize the gate signals Vgs1 and Vgs2 of semiconductor elements T1 and T2 with each other.

[0022] In the following explanation, the voltages of the first to fourth power supplies V1 to V4 will be referred to as V1 to V4. The first diode D1 clamps the gate signal Vgs1 to voltage V1. The second diode D2 clamps the gate signal Vgs1 to voltage V1-V2. The third diode D3 clamps the gate signal Vgs2 to voltage V3. The fourth diode D4 clamps the gate signal Vgs2 to voltage V3-V4.

[0023] The gate-source capacitance Cgs1 of semiconductor element T1 represents the capacitance of semiconductor element T1 plus the capacitance due to an external capacitor, and the gate-source capacitance Cgs2 of semiconductor element T2 represents the capacitance of semiconductor element T2 plus the capacitance due to an external capacitor. The external capacitor may be omitted. However, if semiconductor elements T1 and T2 have built-in gate resistors, they are necessary because energy is consumed by the gate resistors.

[0024] In addition to synchronizing gate signals Vgs1 and Vgs2, reactor L1 can be used in combination with snubber capacitors Csa, Csb, Csc, and Csd to soft-switch the switching elements Sa, Sb, Sc, and Sd.

[0025] Specifically, the reactor L1 has a magnetic coupling coefficient of less than 1, and by utilizing its leakage inductance, it transfers energy without consuming energy from the snubber capacitors Csa, Csb, Csc, Csd and gate capacitors Cgs1, Cgs2, thereby achieving soft switching.

[0026] The advantages over Patent Document 1 are listed below. Since the switching elements Sa, Sb, Sc, and Sd are capable of soft switching, the losses of the switching elements Sa, Sb, Sc, and Sd are small, resulting in high efficiency and low noise. Since the gate capacitances of semiconductor elements T1 and T2 can be stored as current in the leakage inductance of reactor L1, losses are less affected by the number of switching cycles. • Because the energy stored in reactor L1 can be regenerated to the first to fourth power sources V1 to V4, the amount of power required for gate drive can be significantly reduced.

[0027] Next, we will describe the circuit's operation in detail. An example of the operating waveform is shown in Figure 2.

[0028] The circuit in Figure 1 can control the gate signal Vgs1 of semiconductor element T1 to two different gate voltages by controlling the conduction state of switching elements Sa and Sb. Possible gate voltages include the voltage V1 of the first power supply V1, the voltage V2 of the second power supply V2, and voltages resulting from combinations of the first power supply V1 and the second power supply V2 (subtraction or addition). In this embodiment 1, the two gate voltages are voltage V1 and voltage V1-V2. Similarly, the gate signal Vgs2 of semiconductor element T2 can be controlled to voltage V3 or voltage V3-V4 by controlling the conduction state of switching elements Sc and Sd.

[0029] First, let's describe the operation of the first drive circuit 1. By making the voltage V2 of the second power supply V2 greater than the voltage V1 of the first power supply V1, a negative bias can be applied. When the switching element Sa is made to conduct, current flows in the negative direction (IL1 < 0) through the reactor L1, and the gate signal Vgs1 is subjected to the voltage V1 - V2. At this time, because of the presence of the second diode D2, no overshoot occurs, and the maximum value of the gate signal Vgs1 is clipped to the voltage V1 - V2.

[0030] When the switching element Sb is made conductive, current flows in the positive direction (IL1>0) through the reactor L1, and the gate signal Vgs1 is subjected to the voltage V1 of the first power supply V1. At this time, due to the presence of the first diode D1, no overshoot occurs, and the maximum value of the gate signal Vgs1 is clipped to the voltage V1.

[0031] Next, we will describe the operation of the second drive circuit 2. By making the voltage V4 of the fourth power supply V4 greater than the voltage V3 of the third power supply V3, a negative bias can be applied. When the switching element Sc is made to conduct, current flows in the negative direction (IL2 < 0) through the reactor L1, and the gate signal Vgs2 is subjected to the voltage V3-V4. At this time, because of the presence of the fourth diode D4, no overshoot occurs, and the maximum value of the gate signal Vgs2 is clipped to the voltage V3-V4.

[0032] When the switching element Sd is made conductive, current flows in the positive direction (IL2>0) through the reactor L1, and the gate signal Vgs2 is subjected to the voltage V3 of the third power supply V3. At this time, due to the presence of the third diode D3, no overshoot occurs, and the maximum value of the gate signal Vgs2 is clipped to the voltage V3.

[0033] Next, we will discuss the tuning effect of the gate signals Vgs1 and Vgs2 by the reactor L1. Figure 3 shows the simulation waveform when the circuit in Figure 1 is operated without magnetic coupling, and Figure 4 shows the simulation waveform when the circuit in Figure 1 is operated with magnetic coupling.

[0034] The simulation conditions are shown in Table 1. The timing delay time in Table 1 represents the signal delay time setting values ​​for the first drive circuit 1 and the second drive circuit 2. The gate signal Vgs1 is set to lag behind the gate signal Vgs2, the on-time of switching element Sa is set to be 60ns shorter than the on-time of switching element Sc, and the on-time of switching element Sb is set to have a pulse width 60ns shorter than the on-time of switching element Sd.

[0035] [Table 1]

[0036] As can be seen by comparing Figure 3 and Figure 4, when magnetically coupled, gate signals Vgs1 and Vgs2 overlap and are in tune, but when operated without magnetic coupling, gate signals Vgs1 and Vgs2 are not in tune and a discrepancy occurs.

[0037] When magnetically coupled, if a discrepancy occurs between gate signals Vgs1 and Vgs2, a voltage is applied to the excitation inductance of reactor L1, generating opposite voltages in the first drive circuit 1 and the second drive circuit 2. This induced voltage acts to make currents iL1 and iL2 equal, thus synchronizing gate signals Vgs1 and Vgs2. From these results, it can be seen that the gate drive circuit of this embodiment 1 also achieves the same gate signal synchronization effect as in Patent Document 1.

[0038] Next, the soft switching operation of switching elements Sa and Sb will be explained. During the dead time period, switching elements Sa and Sb are soft-switched by the energy of the leakage inductance of reactor L1. Figure 5 shows an example of the operating waveform. Sections (1) and (2) in Figure 5 are dead times that are intentionally added or dead times that occur due to the characteristics of the constituent elements (for example, if switching element Sa is an nch MOSFET and switching element Sb is a pch MOSFET, this is the difference in conduction timing that occurs due to the difference in gate threshold voltages between switching element Sa and switching element Sb).

[0039] In section (1), soft switching can be achieved for both switching element Sa and switching element Sb by the following operation. Sa: During turn-off, current flows through the snubber capacitor Csa connected in parallel, resulting in zero-current switching. When both switching elements Sa and Sb are in the off state, the current in reactor L1 is commutated through the diode of switching element Sb, resulting in zero-voltage switching.

[0040] In section (2), soft switching can be achieved for both switching element Sa and switching element Sb by the following operation. When both switching elements Sa and Sb are in the off state, the current in reactor L1 is commutated through the diode of switching element Sb, resulting in zero-voltage switching. Sb: During turn-off, current flows through the snubber capacitor Csb connected in parallel, resulting in zero-current switching.

[0041] Furthermore, in order to achieve soft switching, the following equations (1) and (2) must hold. Here, vds is the drain-source voltage of the switching element, IL1max is the maximum current flowing through reactor L1, IL1min is the minimum current flowing through reactor L1, L1 is the inductance of reactor L1, Csa is the capacitance of snubber capacitor Csa, and Csb is the capacitance of snubber capacitor Csb.

[0042]

number

[0043]

number

[0044] By performing a similar operation in the second drive circuit 2, soft switching of the switching elements Sc and Sd can be achieved.

[0045] As described above, according to this embodiment 1, the series connection of semiconductor elements to be driven can be facilitated by synchronizing the gate signal with a magnetically coupled reactor. Furthermore, the leakage inductance of the coupling reactor allows the elements constituting the gate drive circuit to perform soft switching operation. In addition, the gate can be driven without consuming the energy of the gate capacitance due to the gate resistance. This makes it possible to realize a compact and highly efficient (low power consumption) gate drive circuit suitable for high voltage and high frequency switching.

[0046] [Example 2] The gate drive circuit for on / off control in this embodiment 2 outputs a gate signal to each of the connected voltage-driven semiconductor elements, similar to embodiment 1. This embodiment 2 describes a gate drive circuit that can achieve high efficiency and miniaturization even at high frequencies while synchronizing the gate signals of the semiconductor elements to be driven.

[0047] Figure 6 shows the circuit configuration of the gate drive circuit in this embodiment 2. As shown in Figure 6, the semiconductor elements T1 and T2 to be driven are connected in series. The first drive circuit 1 outputs a gate signal Vgs1 to semiconductor element T1, and the second drive circuit 2 outputs a gate signal Vgs2 to semiconductor element T2.

[0048] First, let's describe the first drive circuit 1. The first drive circuit 1 has two DC power supplies (first power supply V1 and second power supply V2). The negative terminal of the first power supply V1 is connected to the second terminal (source terminal) of the semiconductor element T1. The positive terminal of the second power supply V2 is connected to the positive terminal of the first power supply V1.

[0049] A half-bridge circuit is connected between the positive and negative terminals of the second power supply V2. The half-bridge circuit is constructed by connecting switching elements Sa and Sb in series. Switching elements Sa and Sb have freewheeling diodes. Alternatively, the half-bridge circuit may be a push-pull circuit. Snubber capacitors Csa and Csb are connected in parallel to the switching elements Sa and Sb.

[0050] The first diode D1 has its cathode connected to the positive terminal of the second power supply V2 and its anode connected to the gate terminal of semiconductor element T1. The second diode D2 has its cathode connected to the anode of the first diode D1 and its anode connected to the negative terminal of the second power supply V2.

[0051] The reactor L1 is connected to the path through which the gate signal Vgs1 flows. In this embodiment 2, the reactor L1 is connected between the connection point of the switching elements Sa and Sb and the connection point of the first diode D1 and the second diode D2. The reactor L1 has a constant leakage inductance.

[0052] Next, the second drive circuit 2 will be described. The configuration of the second drive circuit 2 is the same as that of the first drive circuit 1. The second drive circuit 2 has two DC power supplies (third power supply V3 and fourth power supply V4). The negative terminal of the third power supply V3 is connected to the second terminal (source terminal) of the semiconductor element T2. The positive terminal of the fourth power supply V4 is connected to the positive terminal of the third power supply V3.

[0053] A half-bridge circuit is connected between the positive and negative terminals of the fourth power supply V4. The half-bridge circuit is constructed by connecting switching elements Sc and Sd in series. The switching elements Sc and Sd have freewheeling diodes. Alternatively, the half-bridge circuit may be configured as a push-pull circuit. Snubber capacitors Csc and Csd are connected in parallel to the switching elements Sc and Sd.

[0054] The cathode of the third diode D3 is connected to the positive terminal of the fourth power supply V4, and the anode is connected to the gate terminal of the semiconductor element T2. The cathode of the fourth diode D4 is connected to the anode of the third diode D3, and the anode is connected to the negative terminal of the fourth power supply V4.

[0055] The reactor L1 is connected to the path through which the gate signal Vgs2 flows. In this embodiment 2, the reactor L1 is connected between the connection point of the switching elements Sc and Sd and the connection point of the third diode D3 and the fourth diode D4. The reactor L1 has a constant leakage inductance.

[0056] The circuit in Figure 6 magnetically couples the reactor L1 of the first drive circuit 1 and the reactor L1 of the second drive circuit 2 in order to synchronize the gate signals Vgs1 and Vgs2 of semiconductor elements T1 and T2 with each other.

[0057] In the following explanation, the voltages of the first to fourth power supplies V1 to V4 will be referred to as V1 to V4. The first diode D1 clamps the gate signal Vgs1 to voltage V1. The second diode D2 clamps the gate signal Vgs1 to voltage V1-V2. The third diode D3 clamps the gate signal Vgs2 to voltage V3. The fourth diode D4 clamps the gate signal Vgs2 to voltage V3-V4.

[0058] The gate-source capacitance Cgs1 of semiconductor element T1 represents the capacitance of semiconductor element T1 plus the capacitance due to an external capacitor, and the gate-source capacitance Cgs2 of semiconductor element T2 represents the capacitance of semiconductor element T2 plus the capacitance due to an external capacitor. The external capacitor may be omitted. However, if semiconductor elements T1 and T2 have built-in gate resistors, they are necessary because energy is consumed by the gate resistors.

[0059] In addition to synchronizing the gate signals Vgs1 and Vgs2, reactor L1 can be used in combination with snubber capacitors Csa, Csb, Csc, and Csd to soft-switch the switching elements Sa, Sb, Sc, and Sd.

[0060] Specifically, the reactor L1 has a magnetic coupling coefficient of less than 1, and by utilizing its leakage inductance, it transfers energy without consuming energy from the snubber capacitors Csa, Csb, Csc, Csd and gate capacitors Cgs1, Cgs2, thereby achieving soft switching.

[0061] The advantages over Patent Document 1 are listed below. Since the switching elements Sa, Sb, Sc, and Sd are capable of soft switching, the losses of the switching elements Sa, Sb, Sc, and Sd are small, resulting in high efficiency and low noise. Since the gate capacitances of semiconductor elements T1 and T2 can be stored as current in the leakage inductance of reactor L1, losses are less affected by the number of switching cycles. • Because the energy stored in reactor L1 can be regenerated to the first to fourth power sources V1 to V4, the amount of power required for gate drive can be significantly reduced.

[0062] Next, we will describe the circuit's operation in detail. An example of the operating waveform is shown in Figure 7.

[0063] The circuit in Figure 6 can control the gate signal Vgs1 of semiconductor element T1 to two different gate voltages by controlling the conduction state of switching elements Sa and Sb. Possible gate voltages include the voltage V1 of the first power supply V1, the voltage V2 of the second power supply V2, and voltages resulting from combinations of the first power supply V1 and the second power supply V2 (subtraction or addition). In this embodiment 2, the two gate voltages are voltage V1 and voltage V1-V2. Similarly, the gate signal Vgs2 of semiconductor element T2 can be controlled to voltage V3 or voltage V3-V4 by controlling the conduction state of switching elements Sc and Sd.

[0064] First, let's describe the operation of the first drive circuit 1. By making the voltage V2 of the second power supply V2 greater than the voltage V1 of the first power supply V1, a negative bias can be applied. When the switching element Sa is made to conduct, current flows in the negative direction (IL1 < 0) through the reactor L1, and the gate signal Vgs1 is subjected to the voltage V1 - V2. At this time, because of the presence of the second diode D2, no overshoot occurs, and the maximum value of the gate signal Vgs1 is clipped to the voltage V1 - V2.

[0065] When the switching element Sb is made conductive, current flows in the positive direction (IL1>0) through the reactor L1, and the gate signal Vgs1 is subjected to the voltage V1 of the first power supply V1. At this time, due to the presence of the first diode D1, no overshoot occurs, and the maximum value of the gate signal Vgs1 is clipped to the voltage V1.

[0066] Next, we will describe the operation of the second drive circuit 2. By making the voltage V4 of the fourth power supply V4 greater than the voltage V3 of the third power supply V3, a negative bias can be applied. When the switching element Sc is made to conduct, current flows in the negative direction (IL2 < 0) through the reactor L1, and the gate signal Vgs2 is subjected to the voltage V3-V4. At this time, because of the presence of the fourth diode D4, no overshoot occurs, and the maximum value of the gate signal Vgs2 is clipped to the voltage V3-V4.

[0067] When the switching element Sd is made conductive, current flows in the positive direction (IL2>0) through the reactor L1, and the gate signal Vgs2 is subjected to the voltage V3 of the third power supply V3. At this time, due to the presence of the third diode D3, no overshoot occurs, and the maximum value of the gate signal Vgs2 is clipped to the voltage V3.

[0068] The soft switching operation and the tuning effect of gate signals Vgs1 and Vgs2 are the same as in Example 1, so we will omit the explanation.

[0069] As described above, this embodiment 2 provides the same effects and advantages as embodiment 1.

[0070] [Example 3] The gate drive circuit for on / off control in this embodiment 3 outputs gate signals to multiple connected voltage-driven semiconductor elements, similar to embodiments 1 and 2. This embodiment 3 describes a gate drive circuit that can achieve high efficiency and miniaturization even at high frequencies while synchronizing the gate signals of the semiconductor elements to be driven.

[0071] Figure 8 shows the circuit configuration of the gate drive circuit in this embodiment 3. As shown in Figure 8, the semiconductor elements T1 and T2 to be driven are connected in series. The first drive circuit 1 outputs a gate signal Vgs1 to semiconductor element T1, and the second drive circuit 2 outputs a gate signal Vgs2 to semiconductor element T2.

[0072] First, let's describe the first drive circuit 1. The first drive circuit 1 has two DC power supplies (first power supply V1, second power supply V2). The first power supply V1 and the second power supply V2 are connected in series. The connection point between the first power supply V1 and the second power supply V2 is connected to the second terminal (source terminal) of the semiconductor element T1.

[0073] A half-bridge circuit is connected between the positive terminal of the second power supply V2 and the negative terminal of the first power supply V1. The half-bridge circuit is constructed by connecting switching elements Sa and Sb in series. Switching elements Sa and Sb have freewheeling diodes. Alternatively, the half-bridge circuit may be a push-pull circuit. Snubber capacitors Csa and Csb are connected in parallel to the switching elements Sa and Sb.

[0074] The first diode D1 has its cathode connected to the positive terminal of the second power supply V2 and its anode connected to the gate terminal of semiconductor element T1. The second diode D2 has its cathode connected to the anode of the first diode D1 and its anode connected to the negative terminal of the first power supply V1.

[0075] The reactor L1 is connected to the path through which the gate signal Vgs1 flows. In this embodiment 3, the reactor L1 is connected between the connection point of the switching elements Sa and Sb and the connection point of the first diode D1 and the second diode D2. The reactor L1 has a constant leakage inductance.

[0076] Next, the second drive circuit 2 will be described. The configuration of the second drive circuit 2 is the same as that of the first drive circuit 1. The second drive circuit 2 has two DC power supplies (third power supply V3 and fourth power supply V4). The third power supply V3 and the fourth power supply V4 are connected in series. The connection point between the third power supply V3 and the fourth power supply V4 is connected to the second terminal (source terminal) of the semiconductor element T2.

[0077] A half-bridge circuit is connected between the positive terminal of the fourth power supply V4 and the negative terminal of the third power supply V3. The half-bridge circuit is constructed by connecting switching elements Sc and Sd in series. The switching elements Sc and Sd have freewheeling diodes. Alternatively, the half-bridge circuit may be configured as a push-pull circuit. Snubber capacitors Csc and Csd are connected in parallel to the switching elements Sc and Sd.

[0078] The cathode of the third diode D3 is connected to the positive terminal of the fourth power supply V4, and the anode is connected to the gate terminal of the semiconductor element T2. The cathode of the fourth diode D4 is connected to the anode of the third diode D3, and the anode is connected to the negative terminal of the third power supply V3.

[0079] The reactor L1 is connected to the path through which the gate signal Vgs2 flows. In this embodiment 3, the reactor L1 is connected between the connection point of the switching elements Sc and Sd and the connection point of the third diode D3 and the fourth diode D4. The reactor L1 has a constant leakage inductance.

[0080] The circuit in Figure 8 magnetically couples the reactor L1 of the first drive circuit 1 and the reactor L1 of the second drive circuit 2 in order to synchronize the gate signals Vgs1 and Vgs2 of semiconductor elements T1 and T2 with each other.

[0081] In the following explanation, the voltages of the first to fourth power supplies V1 to V4 will be referred to as V1 to V4. The first diode D1 clamps the gate signal Vgs1 to voltage V2. The second diode D2 clamps the gate signal Vgs1 to voltage -V1. The third diode D3 clamps the gate signal Vgs2 to voltage V4. The fourth diode D4 clamps the gate signal Vgs2 to voltage -V3.

[0082] The gate-source capacitance Cgs1 of semiconductor element T1 represents the capacitance of semiconductor element T1 plus the capacitance due to an external capacitor, and the gate-source capacitance Cgs2 of semiconductor element T2 represents the capacitance of semiconductor element T2 plus the capacitance due to an external capacitor. The external capacitor may be omitted. However, if semiconductor elements T1 and T2 have built-in gate resistors, they are necessary because energy is consumed by the gate resistors.

[0083] In addition to synchronizing the gate signals Vgs1 and Vgs2, reactor L1 can be used in combination with snubber capacitors Csa, Csb, Csc, and Csd to soft-switch the switching elements Sa, Sb, Sc, and Sd.

[0084] Specifically, the reactor L1 has a magnetic coupling coefficient of less than 1, and by utilizing its leakage inductance, it transfers energy without consuming energy from the snubber capacitors Csa, Csb, Csc, Csd and gate capacitors Cgs1, Cgs2, thereby achieving soft switching.

[0085] The advantages over Patent Document 1 are listed below. Since the switching elements Sa, Sb, Sc, and Sd are capable of soft switching, the losses of the switching elements Sa, Sb, Sc, and Sd are small, resulting in high efficiency and low noise. • The gate capacitances of semiconductor elements T1 and T2 can be stored as current in the leakage inductance of reactor L1, so losses are less affected by the number of switching cycles. • Because the energy stored in reactor L1 can be regenerated to the first to fourth power sources V1 to V4, the amount of power required for gate drive can be significantly reduced.

[0086] Next, we will describe the circuit's operation in detail. An example of the operating waveform is shown in Figure 9.

[0087] The circuit in Figure 8 can control the gate signal Vgs1 of semiconductor element T1 to two different gate voltages by controlling the conduction state of switching elements Sa and Sb. Possible gate voltages include the voltage V1 of the first power supply V1, the voltage V2 of the second power supply V2, and voltages resulting from combinations of the first power supply V1 and the second power supply V2 (subtraction or addition). In this embodiment 3, the two gate voltages are voltage -V1 and voltage V2. Similarly, the gate signal Vgs2 of semiconductor element T2 can be controlled to voltage -V3 or voltage V4 by controlling the conduction state of switching elements Sc and Sd.

[0088] First, let's describe the operation of the first drive circuit 1. When the switching element Sa is activated, current flows in the negative direction (IL1 < 0) through the reactor L1, and a voltage of -V1 is applied to the gate signal Vgs1. At this time, due to the presence of the second diode D2, no overshoot occurs, and the maximum value of the gate signal Vgs1 is clipped to the voltage of -V1.

[0089] When the switching element Sb is made conductive, current flows in the positive direction (IL1>0) through the reactor L1, and the gate signal Vgs1 is subjected to the voltage V2. At this time, due to the presence of the first diode D1, no overshoot occurs, and the maximum value of the gate signal Vgs1 is clipped to the voltage V2.

[0090] Next, we will describe the operation of the second drive circuit 2. When the switching element Sc is made conductive, current flows in the negative direction (IL2 < 0) through the reactor L1, and a voltage of -V3 is applied to the gate signal Vgs2. At this time, due to the presence of the fourth diode D4, no overshoot occurs, and the maximum value of the gate signal Vgs2 is clipped to the voltage of -V3.

[0091] When the switching element Sd is made conductive, current flows in the positive direction (IL2>0) through the reactor L1, and the gate signal Vgs2 is subjected to a voltage V4. At this time, due to the presence of the third diode D3, no overshoot occurs, and the maximum value of the gate signal Vgs2 is clipped to the voltage V4.

[0092] The soft switching operation and the tuning effect of gate signals Vgs1 and Vgs2 are the same as in Example 1, so we will omit the explanation.

[0093] As described above, this embodiment 3 produces the same effects as embodiments 1 and 2.

[0094] Although the present invention has been described in detail only with respect to the specific examples described above, it will be obvious to those skilled in the art that a wide variety of modifications and alterations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and alterations fall within the scope of the claims.

[0095] For example, while Examples 1 to 3 described gate drive circuits for semiconductor elements connected in series, the same method can also be applied to gate drive circuits for semiconductor elements connected in parallel that require simultaneous driving.

[0096] Furthermore, while Examples 1 to 3 described two semiconductor elements T1 and T2 connected in series, there may be three or more semiconductor elements connected in series. When three or more semiconductor elements are connected in series, a method of magnetically coupling the reactors of the gate drive circuits of adjacent semiconductor elements can be considered. [Explanation of symbols]

[0097] 1, 2…First and second gate drive circuits, T1, T2…Semiconductor elements, V1~V4…First to fourth power supplies, Sa~Sd…Switching elements, D1~D4…First to fourth diodes, L1…Reactor, Csa~Csd…Snubber capacitors

Claims

1. A gate drive circuit for on / off control that outputs a gate signal to each of a plurality of connected semiconductor elements, The first and second power supplies are two DC power supplies, A half-bridge circuit or push-pull circuit having two switching elements connected in series, which controls the gate signal to two different voltages by controlling the conduction state of the two switching elements, A reactor connected to the path through which the gate signal flows, magnetically coupled to the reactor of the gate drive circuit of another semiconductor element, and having a constant leakage inductance, A snubber capacitor connected in parallel to the switching element, Equipped with, The gate drive circuit is characterized in that the switching element is soft-switched by the energy of the leakage inductance of the reactor during the dead time period.

2. The first power supply, whose negative electrode is connected to the second terminal of the semiconductor element, A first diode is provided, in which the anode is connected to the gate terminal of the semiconductor element and the cathode is connected to the positive side of the first power supply. A second diode, with its anode connected to the positive terminal of the first power supply, The second power supply is connected between the cathode of the second diode and the gate terminal of the semiconductor element, The half-bridge circuit or push-pull circuit, in which two of the switching elements are connected in series between the positive and negative terminals of the second power supply, The snubber capacitor connected in parallel to the switching element, The reactor connected between the anode of the second diode and the connection point of the two switching elements, The gate drive circuit according to claim 1, characterized by comprising the above.

3. The first power supply, whose negative electrode is connected to the second terminal of the semiconductor element, The second power supply, whose positive terminal is connected to the positive terminal of the first power supply, The half-bridge circuit or push-pull circuit, in which two of the switching elements are connected in series between the positive and negative terminals of the second power supply, The snubber capacitor connected in parallel to the switching element, A first diode has its cathode connected to the positive terminal of the second power supply and its anode connected to the gate terminal of the semiconductor element, A second diode has its cathode connected to the anode of the first diode and its anode connected to the negative terminal of the second power supply, The reactor connected between the connection point of the two switching elements and the connection point of the first diode and the second diode, The gate drive circuit according to claim 1, characterized by comprising the above.

4. The first and second power supplies connected in series, The half-bridge circuit or push-pull circuit, in which two of the switching elements are connected in series between the positive terminal of the second power supply and the negative terminal of the first power supply, The snubber capacitor connected in parallel to the switching element, A first diode has its cathode connected to the positive terminal of the second power supply and its anode connected to the gate terminal of the semiconductor element, A second diode has its cathode connected to the anode of the first diode and its anode connected to the negative terminal of the first power supply, The reactor connected between the connection point of the two switching elements and the connection point of the first diode and the second diode, The gate drive circuit according to claim 1, wherein the connection points of the first and second power supplies are connected to the second terminal of the semiconductor element.

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