Power semiconductor devices, electronic equipment and vehicles
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- KYOCERA CORP
- Filing Date
- 2025-01-24
- Publication Date
- 2026-08-05
AI Technical Summary
【0014】 本開示によれば、パワー半導体装置において、GaN-HEMTの誤点弧を低減でき、加えて、ゲート駆動力を向上できる。
Smart Images
Figure 2026126554000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a power semiconductor device, an electronic device, and a vehicle.
Background Art
[0002] A high electron mobility transistor (HEMT) using gallium nitride aluminum (GaN) as a semiconductor material is known. In Non-Patent Document 1, a circuit board using a GaN-HEMT is described.
Prior Art Documents
Non-Patent Documents
[0003]
Non-Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] As shown in Figure 11, the circuit mounted on the circuit board described in Non-Patent Document 1 has a cascode connection between the first transistor Q1 (GaN-HEMT) and the second transistor Q2 (MOSFET). Power semiconductor devices equipped with such circuit boards have the problem that the amplitude of noise generated in response to changes in the signal input to the gate terminal GT is large, making them prone to false firing. Specifically, the signal input to the gate terminal GT changes to a potential that turns off the second transistor Q2, causing the second transistor Q2 to be extinguished. Immediately afterward, current flows from the source terminal ST towards the gate of the first transistor Q1, which can cause the gate voltage of the first transistor Q1 to rise and potentially lead to false firing. Therefore, the present invention provides a power semiconductor device that reduces false firing in the first transistor Q1 and also improves the gate driving force, as well as electronic equipment and vehicles including this power semiconductor device. [Means for solving the problem]
[0005] One aspect of this disclosure is, (1) A substrate and The first external terminal, the second external terminal, and the third external terminal provided on the aforementioned substrate, A first transistor having a first source, a first drain connected to the third external terminal, and a first gate of a Schottky junction, A second transistor having a second source connected to the first external terminal, a second drain connected to the first source, and an isolated second gate connected to the second external terminal, Equipped with, The first transistor and the second transistor are connected in series between the first external terminal and the third external terminal. A resistor and a Zener diode are connected in series between the first external terminal and the second external terminal. Power semiconductor device.
[0006] (2) The Zener diode is connected in reverse between the first gate and the first external terminal of the first transistor, The resistor has one terminal connected to the second external terminal and the other terminal connected to the cathode of the Zener diode. (1) The power semiconductor device described above.
[0007] (3) The substrate is a multilayer substrate. (1) or (2) the power semiconductor device described above.
[0008] (4) The substrate is The first conductive layer has the second transistor, the Zener diode, and the resistor mounted on it. (3) The power semiconductor device described above.
[0009] (5) The substrate is The device has a second conductive layer that allows current flowing out of the resistor to flow into the first transistor, and current flowing out of the second external terminal to flow into the second transistor. (4) The power semiconductor device described above.
[0010] (6) The substrate is The device has a third conductive layer through which current flowing out from the second transistor flows into the first external terminal, and current flowing out from the Zener diode flows into the first external terminal. (5) The power semiconductor device described above.
[0011] (7) The power semiconductor device according to (6), wherein the direction of the current flowing through the second conductive layer is opposite to the direction of the current flowing through the third conductive layer.
[0012] (8) An electronic device comprising a power semiconductor device as described in any one of items (1) to (7).
[0013] (9) A vehicle equipped with a power semiconductor device as described in any one of items (1) to (7) or an electronic device as described in (8). [Effects of the Invention]
[0014] According to the present disclosure, in a power semiconductor device, it is possible to reduce the false point arcs of GaN-HEMTs, and in addition, it is possible to improve the gate driving force.
Brief Description of the Drawings
[0015] [Figure 1] It is a schematic diagram showing the configuration of the vehicle of the present embodiment. [Figure 2] It is a plan view when looking at the power semiconductor device of the present embodiment from above. [Figure 3] It is a circuit diagram of the power semiconductor device of the present embodiment. [Figure 4] It is a graph showing the switching waveform in the power semiconductor device of the present embodiment. [Figure 5] It is a graph showing the switching waveform in the power semiconductor device of the present embodiment. [Figure 6] It is a graph showing the high-speed Fourier transform waveform and its effective difference waveform of the VDS drain-source voltage waveform at turn-off in FIG. 5. [Figure 7] It is a schematic cross-sectional view of the third substrate. [Figure 8] It is a plan view when looking at the first conductive layer from above. [Figure 9] It is a plan view when looking at the second conductive layer from above. [Figure 10] It is a plan view when looking at the third conductive layer from below. [Figure 11] It is a circuit diagram of a conventional power semiconductor device.
Modes for Carrying Out the Invention
[0016] Hereinafter, the power semiconductor device according to the embodiment of the present disclosure will be described with reference to the drawings. Note that the drawings used in the following description are schematic diagrams, and the dimensional ratios on the drawings do not necessarily match the actual values. The dimensional ratios between the drawings also do not necessarily match the actual values.
[0017] [Configuration of the Vehicle] Figure 1 is a schematic diagram showing the configuration of vehicle 1 in this embodiment. Vehicle 1 comprises electronic equipment 10, a power supply 20, and a load device 30. Vehicle 1 includes automobiles such as gasoline cars, electric cars, and hybrid cars, as well as railway vehicles such as trains. The power supply 20 supplies power to the load device 30 via the electronic equipment 10. The load device 30 can be, for example, a solenoid or a motor, but any device that operates using electricity is acceptable. The electronic device 10 comprises a power semiconductor device 100 and a control device 200. The electronic device 10, under the control of the control device 200, converts the power supplied from the power supply 20 using the power semiconductor device 100 and supplies it to the load device 30. The power semiconductor device 100 does not have to be installed in the electronic device 10; it may be installed directly in the vehicle 1.
[0018] [Configuration of power semiconductor device] Figure 2 is a plan view of the power semiconductor device 100 of this embodiment, as seen from above, that is, from the side where the electronic components are mounted on the substrate. The power semiconductor device 100 includes a first substrate 101. The first substrate 101 includes a first external terminal (source terminal) ST, a second external terminal (gate terminal) GT, and a third external terminal (drain terminal) DT. The first substrate 101 may further include multiple substrates, and may also include a second substrate 102 and a third substrate 103. The second substrate 102 may have the first transistor Q1 mounted on it. The third substrate 103 may have the second transistor Q2, a Zener diode ZD, and a resistor R mounted on it.
[0019] In this specification, "electrically connected" includes cases where connections are made via "something that has some kind of electrical function." "Something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes, wiring, switching elements (such as transistors), resistive elements, diodes, inductors, capacitors, and other elements with various functions.
[0020] The source terminal ST may be part of the support substrate 104 and may be electrically connected to the first substrate 101 via the support substrate 104. The gate terminal GT may be electrically connected to the third substrate 103 by a first wire bonding 111. The drain terminal DT may be electrically connected to the second substrate 102 by a second wire bonding 112. The second substrate 102 and the third substrate 103 may be electrically connected by a third wire bonding 113, a fourth wire bonding 114, and a fifth wire bonding 115.
[0021] [Circuit Configuration] Figure 3 shows the circuit diagram of the power semiconductor device of this embodiment. As shown in Figure 3, the power semiconductor device 100 of this embodiment includes, as external terminals, a gate terminal GT to which a signal is input, a source terminal ST to which a ground potential is applied, and a drain terminal DT as an output terminal. A first transistor Q1 and a second transistor Q2 are cascode-connected between the drain terminal DT and the source terminal ST. The first transistor Q1 is a transistor (GaN-HEMT) with a Schottky junction gate. The second transistor Q2 is an N-channel transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET) with an isolated gate.
[0022] A resistor R is connected between the gate electrode of the first transistor Q1 and the gate terminal GT, and a Zener diode ZD is connected in reverse between the gate electrode of the first transistor Q1 and the source terminal ST. Furthermore, the gate terminal GT is connected to the gate electrode of the second transistor Q2, and the second transistor Q2 is switched on and off by the signal input to the gate terminal GT.
[0023] The power semiconductor device 100, which has the circuit shown in Figure 3, is not particularly limited, but for example, the second transistor Q2 is fired (turned on) when the signal input to the gate terminal GT is changed from 20V to a voltage such as 35V, which is higher than the threshold voltage of the second transistor Q2. Also, the constants of the elements constituting the circuit are set so that the second transistor Q2 is extinguished (turned off) when the signal input to the gate terminal GT is changed to a voltage such as 0V, for example. Furthermore, the resistor R is set to a value such as 47Ω, and the Zener diode ZD is set to a value such as 3V for its Zener voltage (breakdown voltage). For example, when the gate breakdown voltage of the first transistor Q1 is 5V and the gate breakdown voltage of the second transistor is 20V, it is necessary to apply different voltage drive signals to each. In order to apply these with a single drive voltage signal (for example, 10V), the gate drive voltage applied to the first transistor Q1 can be set to 3V using the Zener diode ZD and resistor R, and the gate drive voltage applied to the second transistor Q2 can be set to 10V. Furthermore, the drive timing of the first transistor Q1 and the second transistor Q2 can be adjusted based on the resistance value of resistor R.
[0024] In the power semiconductor device 100 of this embodiment, after turning off the second transistor Q2, a voltage such as 10V is applied to the gate terminal GT, causing current to flow from the gate terminal GT through the resistor R and the Zener diode ZD to the source terminal ST. This blocks the noise current flowing from the source terminal ST to the gate of the first transistor Q1, thereby reducing the noise peak.
[0025] Figures 4 and 5 show the switching waveforms (at 22A, 600V operation) of the power semiconductor device 100 of this embodiment. Figure 4 shows the changes in the VDS drain-source voltage (V), VGS gate voltage (V), and ID drain current (A) measured during turn-on. Figure 5 shows the changes in the VDS drain-source voltage (V), VGS gate voltage (V), and ID drain current (A) measured during turn-off. The power semiconductor device shown in Figure 10 is used as a comparative example. Compared to the comparative example, it can be seen that the rise time of the ID drain current in the power semiconductor device 100 of this embodiment is shorter, for example, during turn-on. This indicates that the power semiconductor device 100 of this embodiment achieves a reduction in inductance compared to the comparative example. Furthermore, the waveform of the VDS drain-source voltage during turn-off in Figure 5 is subjected to a Fast Fourier Transform, and the Fast Fourier Transform difference analysis results between the power semiconductor device 100 of this embodiment and the comparative example are shown in Figure 6. From Figure 6, it can be seen that the power semiconductor device 100 of this embodiment achieves noise reduction compared to the comparative example.
[0026] [Circuit board configuration] The third substrate 103 shown in Figure 2 may be a multilayer substrate. By using a multilayer substrate, a large current can be passed through the entire circuit. Figure 7 is a schematic cross-sectional view of the third substrate 103, and as an example, the third substrate 103 has three conductive layers. The third substrate 103 may have conductive layers and insulating layers stacked alternately, and may have a first conductive layer 131, a first insulating layer 134, a second conductive layer 132, a second insulating layer 135, and a third conductive layer 133 in this order.
[0027] The conductive layer may be made of metal. Examples of metals include copper, nickel, cobalt, and iron. The conductive layer may also contain other metals or metal semiconductor compounds.
[0028] The insulating layer may be a ceramic mainly composed of aluminum nitride. The main component is the component with the highest content, and may be a component present in 80% by mass or more. The insulating layer may also be mainly composed of silicon nitride, aluminum oxide, silicon carbide, or zirconia. The insulating layer may also be an amorphous solid, so-called glass, mainly composed of silicates, etc.
[0029] The main component of the insulating layer may be selected depending on the application of the third substrate 103. For example, if aluminum nitride is the main component, the thermal conductivity of the third substrate 103 can be increased. If aluminum oxide is the main component, the rigidity of the third substrate 103 can be increased, making it easier to thin. If silicon nitride is the main component, the toughness of the third substrate 103 can be increased.
[0030] The third substrate 103 may have through-hole vias 136 and blind vias 137. The through-hole vias 136 are vias that penetrate all layers, and the blind vias 137 are vias that penetrate the first conductive layer 131 and the first insulating layer 134. The through-hole vias 136 and blind vias 137 may be perpendicular to each layer.
[0031] Figure 8 is a top view of the first conductive layer 131. In Figure 8, the second transistor Q2, Zener diode ZD, and resistor R mounted on the first conductive layer 131 are shown by dotted lines. In areas where the first conductive layer 131 is not formed, the first insulating layer 134 may be exposed. The first conductive layer 131 may have regions A to I.
[0032] Figure 9 is a plan view of the second conductive layer 132 as seen from above. In areas where the second conductive layer 132 is not formed, the second insulating layer 135 may be exposed. The second conductive layer 132 may have regions J and K.
[0033] Figure 10 is a plan view of the third conductive layer 133 as seen from below, that is, from the opposite side where the electronic components are mounted on the substrate. The third conductive layer 133 may be formed over the entire surface of the third substrate 103, or the second insulating layer 135 may be exposed in areas where the third conductive layer 133 is not formed. The third conductive layer 133 may have a region L.
[0034] In Figures 8 to 10, the currents Ia, Ib, and Ic flowing through the third substrate 103 are indicated by arrows. The current Ia flowing out from the gate terminal GT flows into region B of the first conductive layer 131 through the first wire bonding (not shown) and into the resistor R electrically connected to region B. The current Ia flowing out from the resistor R flows into region D electrically connected to the resistor R and flows into region K of the second conductive layer 132 through the blind via 137 in region D.
[0035] The current Ia flowing into region K is divided into a current flowing into region K1 and a current flowing into region K2. Region K includes regions K1 and K2. A portion of the current Ia flowing into region K1 flows through the blind via 137 into region C of the first conductive layer 131, and flows through the fifth wire bonding (not shown) into the first transistor Q1 mounted on the second substrate 102. A portion of the current Ia flowing into region K2 flows through the blind via 137 into region G of the first conductive layer 131, and flows through the third wire bonding (not shown) into the first transistor Q1 mounted on the second substrate 102.
[0036] The current Ia flowing out from the first transistor Q1 flows into region H of the first conductive layer 131 through the fourth wire bonding (not shown). The current Ia flowing out from region H flows into the second transistor Q2, which is electrically connected to region H. The current Ia flowing out from the second transistor Q2 flows into region L of the third conductive layer 133 through the through-hole via 136, and the current Ia flowing out from region L flows into the source terminal ST via the support substrate (not shown).
[0037] The current Ib flowing out from the gate terminal GT flows into region B of the first conductive layer 131 through the first wire bonding (not shown). The current Ib that flows into region B flows into region J of the second conductive layer 132 through the blind via 137 in region B. The current Ib that flows into region J flows into region E of the first conductive layer 131 through the blind via 137 and flows into the second transistor Q2 which is electrically connected to region E.
[0038] The current Ib flowing out from the second transistor Q2 flows into region F, which is electrically connected to the second transistor Q2. The current Ib flowing into region F flows through the through-hole via 136 of region F into region L of the third conductive layer 133, and the current Ib flowing out from region L flows into the source terminal ST via the support substrate (not shown).
[0039] The current Ic flowing out from the gate terminal GT flows into region B of the first conductive layer 131 through the first wire bonding (not shown) and into the resistor R electrically connected to region B. The current Ic flowing out from resistor R flows into region D electrically connected to resistor R and into the Zener diode ZD electrically connected to region D.
[0040] The current Ic flowing out from the Zener diode ZD flows into region A, which is electrically connected to the Zener diode ZD. The current Ic flowing into region A flows through the through-hole via 136 in region A into region L of the third conductive layer 133, and the current Ic flowing out from region L flows into the source terminal ST via the support substrate (not shown).
[0041] The direction of current Ia may be reversed between the second conductive layer 132 and the third conductive layer 133. The direction of current Ib may also be reversed between the second conductive layer 132 and the third conductive layer 133. This reduces the inductance between the source terminal ST and the gate electrode of the first transistor Q1 in the aforementioned circuit, thereby reducing noise and reducing false firing.
[0042] As described above, the power semiconductor device 100 of this disclosure comprises a substrate (first substrate 101), a first external terminal (source terminal) ST, a second external terminal (gate terminal) GT, a third external terminal (drain terminal) DT, a first transistor Q1, and a second transistor Q2. The source terminal ST, gate terminal GT, and drain terminal DT are provided on the first substrate 101. The first transistor Q1 has a first source, a first drain connected to the drain terminal DT, and a first gate of a Schottky junction. The second transistor Q2 has a second source connected to the source terminal ST, a second drain connected to the first source, and an isolated second gate connected to the gate terminal GT. The first transistor Q1 and the second transistor Q2 are connected in series between the source terminal ST and the drain terminal DT. A resistor R and a Zener diode ZD are connected in series between the gate terminal GT and the source terminal ST. This blocks the noise current flowing from the source terminal ST towards the gate of the first transistor Q1, thereby reducing the noise peak. As a result, false firing in the first transistor Q1 can be reduced, and the gate driving force can be improved.
[0043] In this embodiment, the Zener diode ZD may be connected in reverse between the first gate and the source terminal ST of the first transistor Q1. The resistor R may have one terminal connected to the gate terminal and the other terminal connected to the cathode of the Zener diode ZD. This blocks the noise current flowing from the source terminal ST to the gate of the first transistor Q1, thereby reducing the noise peak. As a result, false firing in the first transistor Q1 can be reduced, and the gate driving force can be improved.
[0044] The first substrate 101 in this embodiment may be a multilayer substrate. This allows a large current to flow through the entire circuit.
[0045] In the third substrate 103 according to this embodiment, a first conductive layer on which the second transistor Q2, the Zener diode ZD, and the resistor R are mounted may be included. This allows the third substrate 103 to be a multilayer substrate, enabling a large current to flow through the entire circuit.
[0046] In the third substrate 103 according to this embodiment, a second conductive layer may be provided that allows current flowing out from the resistor R to flow into the first transistor Q1 and current flowing out from the gate terminal GT to flow into the second transistor Q2. This makes the third substrate 103 a multilayer substrate, allowing a large current to flow through the entire circuit.
[0047] In the third substrate 103 according to this embodiment, there may be a third conductive layer that allows current flowing out from the second transistor Q2 to flow into the source terminal ST, and also allows current flowing out from the Zener diode ZD to flow into the source terminal ST. This makes the third substrate 103 a multilayer substrate, and allows a large current to flow through the entire circuit.
[0048] In the third substrate 103 according to this embodiment, the direction of the current flowing through the second conductive layer 132 and the direction of the current flowing through the third conductive layer 133 may be opposite. This reduces the inductance between the source terminal ST and the gate electrode of the first transistor Q1, thereby reducing noise and reducing false firing.
[0049] The electronic device of this disclosure includes the power semiconductor device described above. This reduces malfunctions in the electronic device. Furthermore, electronic devices may include not only vehicles, but also home appliances such as refrigerators and air conditioners.
[0050] The vehicle of this disclosure is equipped with the above-mentioned power semiconductor device or electronic device. This reduces malfunctions in the vehicle. [Explanation of Symbols]
[0051] 1 vehicle 10 Electronic equipment 20 Power supply 30 Load device 100 Power Semiconductor Devices 101 First board 102 Second board 103 Third board 131 First conductive layer 132 Second conductive layer 133 Third conductive layer 200 Control device Q1 First transistor Q2 Second transistor ZD Zener diode R resistor GT gate terminal ST Source Terminal DT drain terminal
Claims
1. circuit board and The first external terminal, the second external terminal, and the third external terminal provided on the aforementioned substrate, A first transistor having a first source, a first drain connected to the third external terminal, and a first gate of a Schottky junction, A second transistor having a second source connected to the first external terminal, a second drain connected to the first source, and an isolated second gate connected to the second external terminal, Equipped with, The first transistor and the second transistor are connected in series between the first external terminal and the third external terminal. A resistor and a Zener diode are connected in series between the first external terminal and the second external terminal. Power semiconductor device.
2. The Zener diode is connected in reverse between the first gate and the first external terminal of the first transistor. The resistor has one terminal connected to the second external terminal and the other terminal connected to the cathode of the Zener diode. The power semiconductor device according to claim 1.
3. The power semiconductor device according to claim 1 or claim 2, wherein the substrate is a multilayer substrate.
4. The aforementioned substrate is The power semiconductor device according to claim 3, further comprising a first conductive layer on which the second transistor, the Zener diode, and the resistor are mounted.
5. The aforementioned substrate is The power semiconductor device according to claim 4, further comprising a second conductive layer that allows current flowing out from the resistor to flow into the first transistor and current flowing out from the second external terminal to flow into the second transistor.
6. The aforementioned substrate is The power semiconductor device according to claim 5, further comprising a third conductive layer that allows current flowing out from the second transistor to flow into the first external terminal and current flowing out from the Zener diode to flow into the first external terminal.
7. The power semiconductor device according to claim 6, wherein the direction of the current flowing through the second conductive layer and the direction of the current flowing through the third conductive layer are opposite.
8. An electronic device comprising a power semiconductor device as described in claim 1.
9. A vehicle comprising a power semiconductor device according to claim 1 or an electronic device according to claim 8.