Semiconductor equipment

Abstract

It suppresses tip warping without sacrificing usable surface area. [Solution] Inside the active trench 14, a first lower electrode 18 is formed below the first intermediate insulating film 17, and a first upper electrode 19 is formed above the first intermediate insulating film 17. Inside the dummy trench 15, a second lower electrode 21 is formed below the second intermediate insulating film 20, and a second upper electrode 22 is formed above the second intermediate insulating film 20. Gate wiring 27 is connected to the first lower electrode 18, the first upper electrode 19, and the second lower electrode 21. A metal film 24 is embedded in a striped opening 23a formed in the interlayer insulating film 23. The emitter electrode 25 is connected to the second upper electrode 22 and is connected to the base layer 9 and the source layer 10 via the metal film 24 embedded in the opening 23a. The metal film 24 has a higher Young's modulus than the emitter electrode 25 and the semiconductor substrate 1.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] A semiconductor device having a split dummy active (hereinafter referred to as SDA) structure has been developed in which the inside of a dummy trench is vertically divided by an intermediate insulating film, the lower electrode below the intermediate insulating film has a gate potential, and the upper electrode above the intermediate insulating film has an emitter potential. In the case of the SDA structure, since a gate current flows only through the lower electrode, heat is generated only in the lower region of the trench, and a thermal stress is likely to occur due to the temperature difference from the upper electrode. Therefore, the chip warps after energization such as in chip testing, and problems occur during die bonding. As an example, in a structure in which the inside of a trench is vertically divided by an intermediate insulating film, it has been proposed to reduce warping by arranging the trenches in a cross shape in plan view (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in order to arrange the trenches in a cross shape, it is necessary to increase the gate wiring, which has a problem of sacrificing the effective area.

[0005] <000003s4>The present disclosure has been made to solve the above problems, and an object thereof is to obtain a semiconductor device capable of suppressing warping of a chip without sacrificing the effective area.

Means for Solving the Problems

[0006] The semiconductor device according to this disclosure includes a semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, and a source layer of a first conductivity type formed on a part of the base layer; a first intermediate insulating film that divides the interior of an active trench vertically, formed from the upper surface of the semiconductor substrate through the base layer and the source layer to the drift layer; a first lower electrode formed below the first intermediate insulating film inside the active trench; a first upper electrode formed above the first intermediate insulating film inside the active trench; a second intermediate insulating film that divides the interior of a dummy trench vertically, formed from the upper surface of the semiconductor substrate through the base layer to the drift layer; and a second intermediate insulating film formed below the second intermediate insulating film inside the dummy trench. The semiconductor substrate comprises a second lower electrode formed thereon, a second upper electrode formed above the second intermediate insulating film inside the dummy trench, an interlayer insulating film formed on the semiconductor substrate so as to cover the active trench and the dummy trench, gate wiring connected to the first lower electrode, the first upper electrode and the second lower electrode, a metal film embedded in the interlayer insulating film in a stripe-like pattern along the active trench and the dummy trench in a plan view, and an emitter electrode formed on the interlayer insulating film, not extending into the opening, connected to the second upper electrode, and connected to the base layer and the source layer via the metal film embedded in the opening, wherein the metal film has a higher Young's modulus than the emitter electrode and the semiconductor substrate. [Effects of the Invention]

[0007] In this disclosure, by filling the stripe-shaped openings with a metal film with a high Young's modulus, the semiconductor substrate becomes less prone to deformation even when stress is applied. Therefore, the upward convex warping that occurs in SDA structures can be suppressed. Furthermore, there is no need to increase the number of gate wirings as in the conventional technology in which trenches are arranged in a cross shape. Thus, chip warping can be suppressed without sacrificing effective area. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view showing the main cell portion of the semiconductor device according to Embodiment 1. [Figure 3] This is an enlarged plan view of the area A enclosed by the wavy line in the main cell section of Figure 1. [Figure 4] This is a cross-sectional view of the end of an active trench along the longitudinal direction of the trench. [Figure 5] This is a cross-sectional view of the end of a dummy trench along the longitudinal direction of the trench. [Figure 6] This is a cross-sectional view along line I-II in Figure 5. [Figure 7] This is an enlarged plan view of the gate pad shown in Figure 1. [Figure 8] This is a cross-sectional view along line I-II in Figure 7. [Figure 9] Figure 1 is a cross-sectional view showing a temperature sense diode. [Figure 10] This figure shows the assembly defect rates for Embodiment 1 and the comparative example. [Figure 11] This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 1. [Figure 12] This is a cross-sectional view showing another modified example of the semiconductor device according to Embodiment 1. [Figure 13] This is a cross-sectional view showing another modified example of the semiconductor device according to Embodiment 1. [Figure 14] This is a cross-sectional view showing a semiconductor device according to Embodiment 2. [Figure 15] This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 2. [Figure 16] This is a cross-sectional view showing a semiconductor device according to Embodiment 3. [Modes for carrying out the invention]

[0009] A semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and repeated descriptions may be omitted.

[0010] Embodiment 1 FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1. The semiconductor substrate 1 is made of silicon and has a main cell portion 2 and a current sense portion 3. An IGBT or an RC-IGBT is formed in the main cell portion 2. The same structure as that of the main cell portion 2 is formed in the current sense portion 3. A gate pad 4, a temperature sense diode 5, and temperature sense diode pads 6 and 7 are formed on the semiconductor substrate 1.

[0011] FIG. 2 is a cross-sectional view showing the main cell portion of the semiconductor device according to Embodiment 1. In the semiconductor substrate 1, a p-type base layer 9 is formed on a drift layer 8. An n-type source layer 10 and a p-type contact layer 11 are formed on a part of the base layer 9. An n-type charge accumulation layer 12 is formed between the drift layer 8 and the base layer 9. A p-type collector layer 13 is formed under the drift layer 8. + type source layer 10 and p + type contact layer 11 are formed. An n + type charge accumulation layer 12 is formed between the drift layer 8 and the base layer 9. A p-type collector layer 13 is formed under the drift layer 8.

[0012] [[ID=1९]] An active trench 14 is formed from the upper surface of the semiconductor substrate 1 through the source layer 10, the base layer 9, and the charge accumulation layer 12 to the drift layer 8. A dummy trench 15 is formed from the upper surface of the semiconductor substrate 1 through the contact layer 11, the base layer 9, and the charge accumulation layer 12 to the drift layer 8. The depth of the active trench 14 and the depth of the dummy trench 15 are the same. The inner surfaces of the active trench 14 and the dummy trench 15 are covered with a gate insulating film 16.

[0013] The inside of the active trench 14 is vertically divided by a first intermediate insulating film 17. A first lower electrode 18 is formed inside the active trench 14 below the first intermediate insulating film 17. A first upper electrode 19 is formed inside the active trench 14 above the first intermediate insulating film 17.

[0014] The dummy trench 15 is divided vertically by the second intermediate insulating film 20. The second lower electrode 21 is formed below the second intermediate insulating film 20 inside the dummy trench 15. The second upper electrode 22 is formed above the second intermediate insulating film 20 inside the dummy trench 15.

[0015] An interlayer insulating film 23 is formed on the semiconductor substrate 1 so as to cover the active trench 14 and the dummy trench 15. A metal film 24 is embedded in an opening 23a formed in the interlayer insulating film 23. An emitter electrode 25 is formed on the interlayer insulating film 23. The emitter electrode 25 does not extend into the opening 23a, but is connected to the base layer 9 and the source layer 10 via the metal film 24 embedded in the opening 23a. A collector electrode 26 is formed on the lower surface of the semiconductor substrate 1 and is connected to the collector layer 13.

[0016] The emitter electrode 25 is an Al film, an Al and Ni multilayer film, or a Cu film. These materials are inexpensive, readily available, resistant to post-electrode formation processes, and resistant to assembly. For example, in wire bonding during assembly, wires are ultrasonically bonded while physically applying load and causing vibration. Therefore, the top electrode needs to have sufficient thickness and hardness to withstand ultrasonic bonding. However, if the top electrode is made only of a thick metal film 24, the chip will warp upwards in a concave direction during wafer processing. Therefore, the emitter electrode 25 is formed as the top electrode using one of the above materials.

[0017] The metal film 24 is made of tungsten, but is not limited to tungsten; it may also be made of tantalum, titanium, or titanium nitride, etc. The metal film 24 may also be a laminated film of multiple metal layers. The metal film 24 made of these materials has a higher Young's modulus than the emitter electrode 25 made of the above materials and the semiconductor substrate 1 made of silicon.

[0018] Figure 3 is an enlarged plan view of region A enclosed by the dashed line in the main cell section of Figure 1. Figure 2 corresponds to a cross-sectional view along line I-II in Figure 3. The emitter electrode 25 is omitted. Striped active trenches 14 and dummy trenches 15 are arranged parallel to each other in a plan view, and an interlayer insulating film 23 is formed on top of them. The opening 23a is formed in the interlayer insulating film 23 in a striped pattern along the active trenches 14 and dummy trenches 15 in a plan view. The high Young's modulus metal film 24 embedded in the opening 23a extends along the entire longitudinal direction of the trenches in the direction in which the active trenches 14 and dummy trenches 15 extend in a plan view. This makes it possible to suppress chip warping in the longitudinal direction of the trenches.

[0019] Figure 4 is a cross-sectional view of the end of an active trench along the longitudinal direction of the trench. The gate wiring 27 is connected to the first lower electrode 18 via a metal film 24 embedded in the contact hole 23b of the interlayer insulating film 23, and also to the first upper electrode 19 via a metal film 24 embedded in the contact hole 23c of the interlayer insulating film 23.

[0020] Figure 5 is a cross-sectional view of the end of the dummy trench along the longitudinal direction of the trench. Figure 6 is a cross-sectional view along line I-II in Figure 5. The gate wiring 27 is connected to the second lower electrode 21 via a metal film 24 embedded in the contact hole 23d of the interlayer insulating film 23. A contact hole 23e is formed that penetrates the interlayer insulating film 23 and reaches the second upper electrode 22. The emitter electrode 25 is connected to the second upper electrode 22 via a metal film 24 embedded in the contact hole 23e. The contact hole 23e is formed at the longitudinal end of the trench in the main cell region and at the terminal region on the outer circumference of the chip, but it may also be formed only at the terminal region. Since the second lower electrode 21 of the dummy trench 15 is at the gate potential and the second upper electrode 22 is at the emitter potential, the dummy trench 15 has an SDA structure.

[0021] In applications where motor isolation is a concern, such as motion control, there are limitations on dv / dt. By adopting an SDA structure, the gate-collector capacitance Cgc increases. This allows for a smaller ratio of gate-emitter capacitance Cge to Cgc (Cge / Cgc), thus reducing dv / dt during turn-on and increasing di / dt. Therefore, even when the user has dv / dt limitations, the turn-on loss Eon can be reduced.

[0022] Furthermore, in a typical single-stage trench, the dummy trench has no gate potential electrode, only an emitter potential electrode. When changing from a single-stage trench to an SDA structure, the volume of the gate electrode increases, thus increasing the amount of charge Qg required to drive the gate. An increase in Qg may necessitate the user designing a gate driver with a higher output than before, potentially leading to lost opportunities. Therefore, in the dummy trench 15 of the SDA structure, the gate insulating film 16 of the second lower electrode 21 is made thicker than the gate insulating film 16 of the second upper electrode 22. This reduces the volume of the gate electrode, making the Qg equivalent to that of a conventional single-stage trench.

[0023] Figure 7 is an enlarged plan view of the gate pad in Figure 1. Figure 8 is a cross-sectional view along line I-II in Figure 7. The gate pad 4 and gate wiring 27 are formed spaced apart from each other on the interlayer insulating film 23. A resistor 28 is formed on the semiconductor substrate 1 and covered with the interlayer insulating film 23. Contact holes 23f and 23g are formed in the interlayer insulating film 23. The gate wiring 27 is connected to one end of the resistor 28 via a metal film 24 embedded in the contact hole 23f. The gate pad 4 is connected to the other end of the resistor 28 via a metal film 24 embedded in the contact hole 23g. Thus, a metal film 24 is also used for the contacts of the resistor 28 around the gate pad 4.

[0024] Figure 9 is a cross-sectional view showing the temperature sense diode of Figure 1. The temperature sense diode 5 is formed on a semiconductor substrate 1 and covered with an interlayer insulating film 23. The anode electrode 29 and the cathode electrode 30 are formed on the interlayer insulating film 23 spaced apart from each other. The temperature sense diode 5 is a pn diode made of polysilicon. Contact holes 23h and 23i are formed in the interlayer insulating film 23. The anode electrode 29 is connected to one end of the temperature sense diode 5 via a metal film 24 embedded in the contact hole 23h. The cathode electrode 30 is connected to the other end of the temperature sense diode 5 via a metal film 24 embedded in the contact hole 23i. Thus, a metal film 24 is also used for the contacts of the temperature sense diode 5.

[0025] As described above, in this embodiment, by filling the stripe-shaped openings 23a with a metal film 24 with a high Young's modulus, the semiconductor substrate 1 becomes less prone to deformation even when stress is applied. Therefore, the upward convex warping that occurs in the SDA structure can be suppressed. Furthermore, there is no need to increase the number of gate wirings 27 as in the conventional technology in which trenches are arranged in a cross shape. Thus, chip warping can be suppressed without sacrificing effective area.

[0026] Furthermore, the metal film 24 is formed not only in the opening 23a of the main cell portion 2, but also in the contact holes 23b to 23i. As a result, the area occupied by the metal film 24 with a high Young's modulus on the chip surface is increased, which further suppresses the warping of the semiconductor substrate 1 due to the SDA structure.

[0027] Furthermore, active trenches 14 and dummy trenches 15 are formed in both the main cell section 2 and the current sensing section 3, and the emitter electrode 25 is connected to the base layer 9 and the source layer 10 via a metal film 24 embedded in the opening 23a. By using the metal film 24 in the current sensing section 3 in this way, the area occupied by the metal film 24 with a high Young's modulus on the chip surface becomes larger, which further suppresses the warping of the semiconductor substrate 1 due to the SDA structure.

[0028] The interlayer insulating film 23 is SiO2 such as TEOS or BPTEOS, and is deposited by CVD. However, compressive stress is generated in the SiO2 film and tensile stress is generated in the Si substrate, so when the interlayer insulating film 23 is SiO2, a force acts that causes it to warp upwards. Therefore, SiN is used as the interlayer insulating film 23. SiN has tensile stress as internal stress. As a result, compressive stress is generated in the semiconductor substrate 1, which can further suppress the upward warping that occurs in the SDA structure.

[0029] Figure 10 shows the assembly defect rates for Embodiment 1 and the comparative example. Chip warping increases as the size of the semiconductor substrate 1 increases. In particular, when the size of the semiconductor substrate 1 is 110 mm 2 In the comparative example, the assembly defect rate increases when the size exceeds this limit. On the other hand, in this embodiment, the size of the semiconductor substrate 1 is 110 mm 2 Even with the above conditions, the assembly defect rate does not increase.

[0030] Figure 11 is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 1. The metal film 24 has a higher Young's modulus and a lower coefficient of thermal expansion compared to silicon. Therefore, if the metal film 24 is directly attached to the semiconductor substrate 1, the difference between the two is large and delamination may occur. To address this, a barrier metal 31 with a higher coefficient of thermal expansion than the metal film 24 is formed between the semiconductor substrate 1 and the metal film 24 at the opening 23a. By sandwiching the barrier metal 31 with a high coefficient of thermal expansion between the two in this way, delamination can be prevented.

[0031] Figures 12 and 13 are cross-sectional views showing other modifications of the semiconductor device according to Embodiment 1. In the above embodiment, one active trench 14 and one dummy trench 15 were arranged alternately. However, the invention is not limited to this, and as shown in Figure 12, one active trench 14 and four dummy trenches 15 may be arranged alternately, or as shown in Figure 13, three active trenches 14 and three dummy trenches 15 may be arranged alternately.

[0032] Embodiment 2 Figure 14 is a cross-sectional view showing a semiconductor device according to Embodiment 2. In this embodiment, the metal film 24 is formed not only on the opening 23a but also on the upper surface of the interlayer insulating film 23. The metal film 24 embedded in the opening 23a and the metal film 24 on the upper surface of the interlayer insulating film 23 are at the same height from the upper surface of the semiconductor substrate 1. Since the metal film 24 has a higher Young's modulus than the interlayer insulating film 23, chip warping is suppressed not only in the longitudinal direction of the trench but also in the direction perpendicular to the trench. As a result, the maximum warping of the entire chip is suppressed more than in Embodiment 1.

[0033] Figure 15 is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 2. A barrier metal 31 with a higher coefficient of thermal expansion than the metal film 24 is formed between the semiconductor substrate 1 and the interlayer insulating film 23 and the metal film 24. By sandwiching the barrier metal 31 with a high coefficient of thermal expansion between the two in this way, delamination can be prevented.

[0034] Embodiment 3 Figure 16 is a cross-sectional view showing a semiconductor device according to Embodiment 3. In this embodiment, the emitter electrode 25, which is the upper electrode, is made of aluminum and has tensile stress as internal stress. On the other hand, the collector electrode 26, which is the lower electrode, is made of nickel vanadium or molybdenum and has compressive stress as internal stress. Since stress in the opposite direction to the internal stress generated in the SDA structure is generated in the collector electrode 26, the upward convex warping that occurs in the SDA structure can be suppressed. In addition, as in Embodiments 1 and 2, a metal film 24 with a high Young's modulus may be formed inside the opening 23a and contact holes 23b to 23i and on the upper surface of the interlayer insulating film 23. This can further suppress the warping of the semiconductor substrate 1 due to the SDA structure.

[0035] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. Various aspects of this disclosure are described below as appendices. (Note 1) A semiconductor substrate having a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and a first conductivity type source layer formed on a part of the base layer, A first intermediate insulating film divides the interior of the active trench formed from the upper surface of the semiconductor substrate through the base layer and the source layer to the drift layer into upper and lower sections, A first lower electrode formed below the first intermediate insulating film inside the active trench, A first upper electrode formed above the first intermediate insulating film inside the active trench, A second intermediate insulating film divides the interior of the dummy trench, which is formed from the upper surface of the semiconductor substrate through the base layer to the drift layer, into upper and lower sections. A second lower electrode formed below the second intermediate insulating film inside the dummy trench, A second upper electrode formed above the second intermediate insulating film inside the dummy trench, An interlayer insulating film formed on the semiconductor substrate so as to cover the active trench and the dummy trench, The gate wiring connected to the first lower electrode, the first upper electrode, and the second lower electrode, The interlayer insulating film includes a metal film embedded in openings formed in a stripe pattern along the active trench and the dummy trench in a plan view, The emitter electrode is formed on the interlayer insulating film, does not extend into the opening, is connected to the second upper electrode, and is connected to the base layer and the source layer via the metal film embedded in the opening, The semiconductor device is characterized in that the metal film has a higher Young's modulus than the emitter electrode and the semiconductor substrate. (Note 2) The semiconductor device according to Appendix 1, characterized in that the metal film is also formed on the upper surface of the interlayer insulating film and has a Young's modulus higher than that of the interlayer insulating film. (Note 3) The semiconductor device according to Appendix 1 or 2, further comprising a barrier metal formed between the semiconductor substrate and the metal film in the opening, the barrier metal having a higher coefficient of thermal expansion than the metal film. (Note 4) A first contact hole is formed that penetrates the interlayer insulating film and reaches the second upper electrode. The semiconductor device according to any one of the appendices 1 to 3, characterized in that the emitter electrode is connected to the second upper electrode via the metal film embedded in the first contact hole. (Note 5) A gate pad formed on the interlayer insulating film, The semiconductor substrate is formed on the aforementioned semiconductor substrate and further comprises a resistor covered with the aforementioned interlayer insulating film, The gate wiring is formed on the interlayer insulating film, A second contact hole and a third contact hole are formed in the interlayer insulating film. The gate wiring is connected to one end of the resistor via the metal film embedded in the second contact hole. The semiconductor device according to any one of the appendices 1 to 4, characterized in that the gate pad is connected to the other end of the resistor via the metal film embedded in the third contact hole. (Note 6) A temperature sense diode formed on the semiconductor substrate and covered with the interlayer insulating film, The device further comprises an anode electrode and a cathode electrode formed on the interlayer insulating film, The temperature sense diode is a pn diode made of polysilicon. A fourth contact hole and a fifth contact hole are formed in the interlayer insulating film. The anode electrode is connected to one end of the temperature sense diode via the metal film embedded in the fourth contact hole. The semiconductor device according to any one of the appendices 1 to 5, characterized in that the cathode electrode is connected to the other end of the temperature sense diode via the metal film embedded in the fifth contact hole. (Note 7) The semiconductor substrate has a main cell section and a current sensing section. The semiconductor device according to any one of the appendices 1 to 6, characterized in that the active trench and the dummy trench are formed in both the main cell portion and the current sense portion, and the emitter electrode is connected to the base layer and the source layer via the metal film embedded in the opening. (Note 8) The semiconductor device according to any one of the appendices 1 to 7, characterized in that the aforementioned metal film is made of tungsten. (Note 9) The semiconductor substrate further comprises a lower electrode formed on its lower surface, The emitter electrode has tensile stress as an internal stress, The semiconductor device according to any one of the appendices 1 to 8, characterized in that the lower electrode has compressive stress as internal stress. (Note 10) A semiconductor substrate having a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and a first conductivity type source layer formed on a part of the base layer, A first intermediate insulating film divides the interior of the active trench formed from the upper surface of the semiconductor substrate through the base layer and the source layer to the drift layer into upper and lower sections, A first lower electrode formed below the first intermediate insulating film inside the active trench, A first upper electrode formed above the first intermediate insulating film inside the active trench, A second intermediate insulating film divides the interior of the dummy trench, which is formed from the upper surface of the semiconductor substrate through the base layer to the drift layer, into upper and lower sections. A second lower electrode formed below the second intermediate insulating film inside the dummy trench, A second upper electrode formed above the second intermediate insulating film inside the dummy trench, An interlayer insulating film formed on the semiconductor substrate so as to cover the active trench and the dummy trench, The gate wiring connected to the first lower electrode, the first upper electrode, and the second lower electrode, An emitter electrode formed on the interlayer insulating film, connected to the second upper electrode, and connected to the base layer and the source layer via a contact hole formed in the interlayer insulating film, The semiconductor substrate comprises a lower electrode formed on the lower surface of the semiconductor substrate, The emitter electrode has tensile stress as an internal stress, The semiconductor device is characterized in that the lower electrode has compressive stress as an internal stress. (Note 11) The emitter electrode is made of aluminum. The semiconductor device according to Appendix 10, characterized in that the lower electrode is made of nickel vanadium or molybdenum. (Note 12) The semiconductor device according to any one of the appendices 1 to 11, characterized in that the semiconductor substrate is made of silicon. (Note 13) The semiconductor device according to any one of the appendices 1 to 12, characterized in that the interlayer insulating film is made of SiN. (Note 14) The size of the semiconductor substrate is 110 mm 2 A semiconductor device as described in any of the appendices 1 to 13, characterized by the above. (Note 15) A semiconductor device as described in any of the appendices 1 to 14, characterized by being an IGBT or RC-IGBT. [Explanation of Symbols]

[0036] 1 Semiconductor substrate, 2 Main cell section, 3 Current sense section, 4 Gate pad, 5 Temperature sense diode, 8 Drift layer, 9 Base layer, 10 Source layer, 14 Active trench, 15 Dummy trench, 17 First intermediate insulating film, 18 First lower electrode, 19 First upper electrode, 20 Second intermediate insulating film, 21 Second lower electrode, 22 Second upper electrode, 23 Interlayer insulating film, 23a Aperture, 23b~23i Contact holes, 24 Metal film, 25 Emitter electrode, 26 Collector electrode (bottom electrode), 27 Gate wiring, 28 Resistor, 29 Anode electrode, 30 Cathode electrode, 31 Barrier metal

Claims

1. A semiconductor substrate having a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and a first conductivity type source layer formed on a part of the base layer, A first intermediate insulating film divides the interior of the active trench formed from the upper surface of the semiconductor substrate through the base layer and the source layer to the drift layer into upper and lower sections, A first lower electrode formed below the first intermediate insulating film inside the active trench, A first upper electrode formed above the first intermediate insulating film inside the active trench, A second intermediate insulating film divides the interior of the dummy trench, which is formed from the upper surface of the semiconductor substrate through the base layer to the drift layer, into upper and lower sections. A second lower electrode formed below the second intermediate insulating film inside the dummy trench, A second upper electrode formed above the second intermediate insulating film inside the dummy trench, An interlayer insulating film formed on the semiconductor substrate so as to cover the active trench and the dummy trench, The gate wiring connected to the first lower electrode, the first upper electrode, and the second lower electrode, The interlayer insulating film includes a metal film embedded in openings formed in a stripe pattern along the active trench and the dummy trench in a plan view, The emitter electrode is formed on the interlayer insulating film, does not extend into the opening, is connected to the second upper electrode, and is connected to the base layer and the source layer via the metal film embedded in the opening. The semiconductor device is characterized in that the metal film has a higher Young's modulus than the emitter electrode and the semiconductor substrate.

2. The semiconductor device according to claim 1, characterized in that the metal film is also formed on the upper surface of the interlayer insulating film and has a Young's modulus higher than that of the interlayer insulating film.

3. The semiconductor device according to claim 1 or 2, further comprising a barrier metal formed between the semiconductor substrate and the metal film in the opening, the barrier metal having a higher coefficient of thermal expansion than the metal film.

4. A first contact hole is formed that penetrates the interlayer insulating film and reaches the second upper electrode. The semiconductor device according to claim 1 or 2, characterized in that the emitter electrode is connected to the second upper electrode via the metal film embedded in the first contact hole.

5. A gate pad formed on the interlayer insulating film, The semiconductor substrate is formed on the aforementioned semiconductor substrate and further comprises a resistor covered with the aforementioned interlayer insulating film, The gate wiring is formed on the interlayer insulating film, A second contact hole and a third contact hole are formed in the interlayer insulating film. The gate wiring is connected to one end of the resistor via the metal film embedded in the second contact hole. The semiconductor device according to claim 1 or 2, characterized in that the gate pad is connected to the other end of the resistor via the metal film embedded in the third contact hole.

6. A temperature sense diode formed on the semiconductor substrate and covered with the interlayer insulating film, The device further comprises an anode electrode and a cathode electrode formed on the interlayer insulating film, The temperature sense diode is a pn diode made of polysilicon. A fourth contact hole and a fifth contact hole are formed in the interlayer insulating film. The anode electrode is connected to one end of the temperature sense diode via the metal film embedded in the fourth contact hole. The semiconductor device according to claim 1 or 2, characterized in that the cathode electrode is connected to the other end of the temperature sense diode via the metal film embedded in the fifth contact hole.

7. The semiconductor substrate has a main cell section and a current sensing section. The semiconductor device according to claim 1 or 2, characterized in that the active trench and the dummy trench are formed in both the main cell portion and the current sense portion, and the emitter electrode is connected to the base layer and the source layer via the metal film embedded in the opening.

8. The semiconductor device according to claim 1 or 2, characterized in that the metal film is made of tungsten.

9. The semiconductor substrate further comprises a lower electrode formed on its lower surface, The emitter electrode has tensile stress as an internal stress, The semiconductor device according to claim 1 or 2, characterized in that the lower electrode has compressive stress as internal stress.

10. A semiconductor substrate having a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and a first conductivity type source layer formed on a part of the base layer, A first intermediate insulating film divides the interior of the active trench formed from the upper surface of the semiconductor substrate through the base layer and the source layer to the drift layer into upper and lower sections, A first lower electrode formed below the first intermediate insulating film inside the active trench, A first upper electrode formed above the first intermediate insulating film inside the active trench, A second intermediate insulating film divides the interior of the dummy trench, which is formed from the upper surface of the semiconductor substrate through the base layer to the drift layer, into upper and lower sections. A second lower electrode formed below the second intermediate insulating film inside the dummy trench, A second upper electrode formed above the second intermediate insulating film inside the dummy trench, An interlayer insulating film formed on the semiconductor substrate so as to cover the active trench and the dummy trench, The gate wiring connected to the first lower electrode, the first upper electrode, and the second lower electrode, An emitter electrode formed on the interlayer insulating film, connected to the second upper electrode, and connected to the base layer and the source layer via a contact hole formed in the interlayer insulating film, The semiconductor substrate comprises a lower electrode formed on the lower surface of the semiconductor substrate, The emitter electrode has tensile stress as an internal stress, The semiconductor device is characterized in that the lower electrode has compressive stress as an internal stress.

11. The emitter electrode is made of aluminum. The semiconductor device according to claim 10, characterized in that the lower electrode is made of nickel vanadium or molybdenum.

12. The semiconductor device according to claim 1 or 10, characterized in that the semiconductor substrate is made of silicon.

13. The semiconductor device according to claim 1 or 10, characterized in that the interlayer insulating film is made of SiN.

14. The size of the aforementioned semiconductor substrate is 110 mm ２ The semiconductor device according to claim 1 or 10, characterized in that it is as described above.

15. The semiconductor device according to claim 1 or 10, characterized in that it is an IGBT or an RC-IGBT.

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