Semiconductor device and method for manufacturing a semiconductor device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- ROHM CO LTD
- Filing Date
- 2025-01-24
- Publication Date
- 2026-08-05
Smart Images
Figure 2026126704000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.
Background Art
[0002] Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document has a plurality of leads. The leads are used as sites to attach solder when mounting the semiconductor device on a circuit board or the like.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
[0004] [Summary] When the mounting strength of a semiconductor device decreases, there are concerns about problems such as unintentional conduction failures.
[0005] The present disclosure has been conceived under the above circumstances, and an object thereof is to provide a semiconductor device and a method of manufacturing the semiconductor device capable of increasing the mounting strength.
[0006] The semiconductor device provided by the first aspect of the present disclosure includes a semiconductor element, a plurality of leads, and a sealing resin. Each of the plurality of leads includes a main body and a metal layer covering at least a part of the main body. At least one of the plurality of leads includes a covered portion covered by the sealing resin and an exposed portion exposed from the sealing resin. The main body in the exposed portion has a bottom surface facing the first side in the thickness direction of the semiconductor element, an end surface facing the first direction intersecting the thickness direction at the tip, and a concave surface located between the bottom surface and the end surface. The concave surface occupies only a part of the main body in the second direction intersecting the thickness direction and the first direction. The metal layer includes a bottom portion covering the bottom surface and a concave portion covering the concave surface.
[0007] A method for manufacturing a semiconductor device provided by a second aspect of this disclosure comprises the steps of: preparing a lead frame having a body including a rod-shaped portion extending in a first direction; mounting a semiconductor element on the lead frame; forming a sealing resin covering a part of the lead frame and the semiconductor element; and cutting the lead frame, wherein the rod-shaped portion includes a bottom surface facing a first side in a thickness direction intersecting the first direction and a concave surface recessed from the bottom surface, and after the step of preparing the lead frame and before the step of mounting the semiconductor element, a step of forming a metal layer including a bottom surface portion covering the bottom surface and a concave surface portion covering the concave surface, and in the step of cutting the lead frame, the concave surface is cut.
[0008] Other features and advantages of this disclosure will become more apparent from the detailed description below, with reference to the accompanying drawings. [Brief explanation of the drawing]
[0009] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a plan view of Figure 1, with the sealing resin indicated by dashed lines. [Figure 3] Figure 3 is a front view showing a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a left side view showing a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a right side view showing a semiconductor device according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view along the line VI-VI in Figure 2. [Figure 7] Figure 7 is an enlarged cross-sectional view of a key part, which is a magnified view of a portion of Figure 6. [Figure 8] Figure 8 is a cross-sectional view along the line VIII-VIII in Figure 2. [Figure 9] Figure 9 is a cross-sectional view of a key part showing the internal structure of a semiconductor element in a semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a partially enlarged plan view showing a bar-shaped portion of the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a partially enlarged bottom view showing a bar-shaped portion of the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a partially enlarged cross-sectional view taken along line XII-XII of FIG. 10. [Figure 13] FIG. 13 is a partially enlarged cross-sectional view taken along line XIII-XIII of FIG. 10. [Figure 14] FIG. 14 is a flowchart showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 15] FIG. 15 is a plan view showing one step of the manufacturing method shown in FIG. 14. [Figure 16] FIG. 16 is a partially enlarged plan view showing one step of the manufacturing method shown in FIG. 14. [Figure 17] FIG. 17 is a partially enlarged cross-sectional view taken along line XVII-XVII of FIG. 16. [Figure 18] FIG. 18 is a partially enlarged cross-sectional view taken along line XVIII-XVIII of FIG. 16. [Figure 19] FIG. 19 is a plan view showing one step of the manufacturing method shown in FIG. 14. [Figure 20] FIG. 20 is a partially enlarged plan view showing one step of the manufacturing method shown in FIG. 14. [Figure 21] FIG. 21 is a partially enlarged cross-sectional view taken along line XXII-XXII of FIG. 20. [Figure 22] FIG. 22 is a partially enlarged cross-sectional view taken along line XXIII-XXIII of FIG. 20. [Figure 23] FIG. 23 is a plan view showing one step of the manufacturing method shown in FIG. 14. [Figure 24] FIG. 24 is a partially enlarged cross-sectional view showing one step of the manufacturing method shown in FIG. 14. [Figure 25] FIG. 25 is a partially enlarged bottom view showing a bar-shaped portion of the first modification of the semiconductor device according to the first embodiment. [Figure 26]FIG. 26 is a partially enlarged bottom view showing the bar-shaped portion of the second modification of the semiconductor device according to the first embodiment. [Figure 27] FIG. 27 is a partially enlarged cross-sectional view showing the bar-shaped portion of the third modification of the semiconductor device according to the first embodiment. [Figure 28] FIG. 28 is a partially enlarged bottom view showing the bar-shaped portion of the semiconductor device according to the second embodiment. [Figure 29] FIG. 29 is a partially enlarged bottom view showing the bar-shaped portion of the semiconductor device according to the third embodiment. [Figure 30] FIG. 30 is a partially enlarged left side view showing the bar-shaped portion of the semiconductor device according to the fourth embodiment. [Figure 31] FIG. 31 is a partially enlarged cross-sectional view taken along line XXXI-XXXI of FIG. 30.
[0010] [Detailed Description] Hereinafter, preferred embodiments of the present disclosure will be specifically described with reference to the drawings.
[0011] In the present disclosure, terms such as "first", "second", "third", etc. are used merely for identification and are not intended to assign an order to those objects.
[0012] In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is located on object B in contact with object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, unless otherwise specified, "object A overlaps with object B when viewed in a certain direction" includes "object A overlapping all of object B" and "object A overlapping a part of object B." Also, in this disclosure, "a surface A facing direction B (one or the other side of it)" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is inclined with respect to direction B.
[0013] Figures 1 to 13 show a semiconductor device A1 according to the first embodiment. As shown in these figures, the semiconductor device A1 comprises a semiconductor element 1, a first semiconductor element 61, a second semiconductor element 62, a lead 7, a plurality of connecting members 8, and a sealing resin 9. The lead 7 includes a plurality of leads 71 to 74, and the plurality of connecting members 8 include a plurality of wires 81, 82, 84 to 87.
[0014] In these figures, the thickness direction of this disclosure is defined as the thickness direction z. The first side of the thickness direction z is referred to as the z1 side, and the second side opposite to the first side in the z direction is referred to as the z2 side. The direction perpendicular to the thickness direction z is defined as the first direction x. The direction perpendicular to both the thickness direction z and the first direction x is defined as the second direction y.
[0015] Semiconductor device A1 is used, for example, in electric vehicles or hybrid vehicles. Semiconductor device A1 controls the switching operation of switching elements such as IGBTs or MOSFETs. The package format of semiconductor device A1 is SOP (Small Outline Package), as can be seen from Figures 1 and 3 to 5. However, the package format of semiconductor device A1 is not limited to SOP.
[0016] The first semiconductor element 61 is a controller (control element) for a gate driver that drives switching elements such as IGBTs and MOSFETs. The first semiconductor element 61 includes a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmitting circuit for transmitting the PWM control signal to the semiconductor element 1, and a receiving circuit that receives an electrical signal from the semiconductor element 1.
[0017] As shown in Figure 6, the first semiconductor element 61 has a main surface 61a and a back surface 61b. The main surface 61a and the back surface 61b are separated in the thickness direction z. The main surface 61a is the upper surface of the first semiconductor element 61, and the back surface 61b is the lower surface of the first semiconductor element 61. The back surface 61b faces the lead 71.
[0018] As shown in Figures 2 and 6, the first semiconductor element 61 has a plurality of pads 611. The plurality of pads 611 are provided on the main surface 61a (the surface facing the same direction as the mounting surface 7111a of the island portion 7111 of the lead 71, which will be described later). The composition of each of the plurality of pads 611 includes, for example, Cu (copper).
[0019] The second semiconductor element 62 is a gate driver (driving element) for driving the switching element. The second semiconductor element 62 has a receiving circuit for receiving a PWM control signal, a circuit for driving the switching element based on the PWM control signal, and a transmitting circuit for transmitting an electrical signal to the first semiconductor element 61. The electrical signal may be, for example, an output signal from a temperature sensor located near the motor.
[0020] As shown in Figure 6, the second semiconductor element 62 has a main surface 62a and a back surface 62b. The main surface 62a and the back surface 62b are separated in the thickness direction z. The main surface 62a is the upper surface of the second semiconductor element 62, and the back surface 62b is the lower surface of the second semiconductor element 62. The back surface 62b faces the lead 72.
[0021] As shown in Figures 2 and 6, the second semiconductor element 62 has a plurality of pads 621. The plurality of pads 621 are provided on the main surface 62a (the surface facing the same direction as the mounting surface 7211a of the island portion 7211 of the lead 72, which will be described later). The composition of each of the plurality of pads 621 includes, for example, Cu (copper).
[0022] The semiconductor element 1 is an insulating element for transmitting PWM control signals and other electrical signals in an isolated state. The semiconductor element 1 is of the inductive type. An example of an inductive semiconductor element 1 is an isolated transformer. The semiconductor element 1 may also be of the capacitive type. An example of a capacitive semiconductor element 1 is a capacitor. Alternatively, the semiconductor element 1 may be a photocoupler.
[0023] As shown in Figures 6 to 9, the semiconductor element 1 has a main surface 1a and a back surface 1b. The main surface 1a and the back surface 1b are separated in the thickness direction z. The main surface 1a is the top surface of the semiconductor element 1, and the back surface 1b is the bottom surface of the semiconductor element 1. The back surface 1b faces the lead 71.
[0024] The semiconductor element 1 includes a functional section 115. The functional section 115 has multiple sets of upper windings 115a and lower windings 115b, with each set consisting of an upper winding 115a and a lower winding 115b. That is, the semiconductor element 1 has multiple upper windings 115a and multiple lower windings 115b. Figures 7 and 9 show one of the multiple sets of upper windings 115a and lower windings 115b. For example, the multiple sets of upper windings 115a and lower windings 115b are arranged along the longitudinal direction (second direction y) of the semiconductor element 1. A pair of upper windings 115a and lower windings 115b are spaced apart in the thickness direction z and face each other in the thickness direction z. In this embodiment, each pair of upper windings 115a and lower windings 115b are wound in a spiral shape in a planar winding. A pair of upper windings 115a and lower windings 115b are magnetically coupled. The first semiconductor element 61 transmits electrical signals in an insulated state by inductively coupling the upper winding 115a and the lower winding 115b in each pair of upper windings 115a and lower windings 115b.
[0025] As shown in Figures 2, 6, and 7, the semiconductor element 1 has a plurality of pads 111, 112. Each of the plurality of pads 111, 112 is provided on the main surface 13a. As shown in Figure 7, each pad 111 is conductive to one of the plurality of lower windings 115b, and each pad 112 is conductive to one of the plurality of upper windings 115a. The composition of each of the plurality of pads 111, 112 includes, for example, aluminum. As shown in Figures 2, 6, and 7, each of the plurality of pads 111 is joined to one of the plurality of wires 81, and each of the plurality of pads 112 is joined to one of the plurality of wires 82.
[0026] Furthermore, as shown in Figures 2 and 7, the semiconductor element 1 includes a seal ring portion 113. In a plan view, the seal ring portion 113 is formed along each of the four outer peripheries of the semiconductor element 1 and surrounds the outer periphery of the circuit formation region. The seal ring portion 113 is made of, for example, copper (Cu), aluminum (Al), or the like.
[0027] As shown in Figures 7 and 9, the semiconductor element 1 includes a semiconductor substrate 110, a protective film 1141, a passivation film 1142, a coil protective film 1143, a laminated structure 117, and a wiring section 118.
[0028] As the semiconductor substrate 110, a Si (silicon) substrate, a SiC (silicon carbide) substrate, etc., can be used. The semiconductor element 1 may use an insulating substrate such as a ceramic substrate or a resin substrate instead of the semiconductor substrate 110. The seal ring portion 113 is erected on the semiconductor substrate 110 and penetrates the laminated structure 117 in the thickness direction z. In this embodiment, the potential of the seal ring portion 113 is approximately the same as the potential of the semiconductor substrate 110.
[0029] The laminated structure 117 is formed on a semiconductor substrate 110. As shown in Figure 9, the laminated structure 117 includes a plurality of insulating layers 1171. The plurality of insulating layers 1171 are laminated on the upper surface of the semiconductor substrate 110. Except for the bottom insulating layer 1171 that is in contact with the upper surface of the semiconductor substrate 110, each of the plurality of insulating layers 1171 has a laminated structure with an etching stopper film below and an interlayer insulating film above. The bottom insulating layer 1171 consists only of an interlayer insulating layer. As the etching stopper film, for example, a SiN film (silicon nitride film), SiC film (silicon carbide film), SiCN film, etc. (silicon carbonitride film) can be used, and as the interlayer insulating film, for example, an SiO2 film (silicon oxide film) can be used. The dimension of the plurality of insulating layers 1171 in the thickness direction z is not limited in any way, but for example it is 2.4 μm. Note that the thickness of each of the plurality of insulating layers 1171 may be the same or different.
[0030] The upper winding 115a and the lower winding 115b are formed on different insulating layers 1171 in the laminated structure 117, and face each other with one or more insulating layers 1171 in between. In the illustrated example, the lower winding 115b is formed on the fourth insulating layer 1171 from the semiconductor substrate 110, and the upper winding 115a is formed on the 15th insulating layer 1171, with 10 insulating layers 1171 in between it and the lower winding 115b. Note that the number of insulating layers 1171 is not limited to the illustrated example and can be appropriately changed, for example, depending on the magnitude of the voltage applied to each pad 111 and each pad 112. The more insulating layers 1171 there are between the upper winding 115a and the lower winding 115b, the higher the dielectric strength of the semiconductor element 1 can be, but the thickness of the semiconductor element 1 (dimension z in the thickness direction) will increase. On the other hand, the fewer the number of insulating layers 1171 between the upper winding 115a and the lower winding 115b, the lower the dielectric strength of the semiconductor element 1, but the thinner the semiconductor element 1 (the dimension in the thickness direction z) can be.
[0031] The wiring section 118 electrically connects the multiple pads 111, 112 to the upper winding 115a and the lower winding 115b. The wiring section 118 includes multiple through-wirings 1181 and lead-out wirings 1182. As shown in Figure 9, each of the multiple through-wirings 1181 penetrates one or more insulating layers 1171 in the thickness direction z. In the example shown in Figure 9, the multiple through-wirings 1181 include those connecting the pad 111 to the lead-out wiring 1182, those connecting the lead-out wiring 1182 to the lower winding 115b, and those connecting the pad 112 to the upper winding 115a. The lead-out wiring 1182 is formed on the bottom insulating layer 1171. The lead-out wiring 1182 forms part of the conductive path between the pad 111 and the lower winding 115b.
[0032] The protective film 1141 is laminated on the laminated structure 117, as shown in Figure 9. The passivation film 1142 is laminated on the protective film 1141, as shown in Figure 9. The coil protective film 1143 is on the passivation film 1142 and selectively covers the region directly above the upper winding 115a, as shown in Figure 9. As can be seen from Figure 9, the protective film 1141, the passivation film 1142, and the coil protective film 1143 have pad openings formed to expose each pad 111 and each pad 112. The protective film 1141 contains, for example, SiO2 and has a thickness of about 150 nm. The passivation film 1142 contains, for example, SiN and has a thickness of about 1000 nm. The coil protective film 1143 contains, for example, polyimide and has a thickness of about 4000 nm. The constituent materials and thicknesses of the protective film 1141, passivation film 1142, and coil protective film 1143 are not limited to the examples described above.
[0033] The structure of the semiconductor element 1 is not limited to the examples described above. For example, the upper winding 115a and the lower winding 115b are not limited to being wound planarly around a single insulating layer 1171, but may be wound three-dimensionally across multiple insulating layers 1171. However, in order to suppress an increase in the thickness of the semiconductor element 1, it is preferable that the upper winding 115a and the lower winding 115b are each wound planarly around a single insulating layer 1171.
[0034] In semiconductor device A1, the second semiconductor element 62 requires a higher power supply voltage than the first semiconductor element 61. Therefore, a potential difference is generated between the first semiconductor element 61 and the second semiconductor element 62. Thus, the first circuit, which includes the first semiconductor element 61, and the second circuit, which includes the second semiconductor element 62, are insulated from each other by the semiconductor element 1. The components of the first circuit include the first semiconductor element 61, a lead 71 and multiple leads 73, multiple wires 81, 84, 86, and a part of the semiconductor element 1 (each pad 111 and each lower winding 115b, etc.). The components of the second circuit include the second semiconductor element 62, a lead 72 and multiple leads 74, multiple wires 82, 85, 87, and a part of the semiconductor element 1 (each pad 112 and each upper winding 115a, etc.). The first circuit and the second circuit have relatively different potentials. In semiconductor device A1, the potential of the second circuit is higher than the potential of the first circuit. Furthermore, semiconductor element 1 relays the mutual signals between the first and second circuits. For example, in inverter devices for electric vehicles and hybrid vehicles, while the voltage applied to the ground of the first semiconductor element 61 is around 0V, the voltage applied to the ground of the second semiconductor element 62 may transiently exceed 600V. Depending on the specifications of the inverter device, the voltage applied to the ground of the second semiconductor element 62 may exceed 3750V.
[0035] The semiconductor device A1 may include leads 7. The leads 7 constitute a conductive path between a plurality of semiconductor elements 1, a first semiconductor element 61, and a second semiconductor element 62, and a wiring board on which the semiconductor device A1 is mounted. The leads 7 may be obtained, for example, from the same lead frame. The leads 7 may have leads 71, leads 72, a plurality of leads 73, and a plurality of leads 74.
[0036] As shown in Figures 1 and 2, leads 71 and 72 are positioned apart from each other in the first direction x. In semiconductor device A1, semiconductor element 1 and first semiconductor element 61 are mounted on lead 71, and second semiconductor element 62 is mounted on lead 72.
[0037] As shown in Figure 2, the lead 71 includes a covered portion 711 and an exposed portion 712. The covered portion 711 is covered by the sealing resin 9. The exposed portion 712 is exposed from the sealing resin 9.
[0038] The covering portion 711 includes an island portion 7111 and two extension portions 7112.
[0039] As shown in Figures 6 and 7, the island portion 7111 has a mounting surface 7111a facing the second side z2 in the thickness direction z. As shown in Figures 7 and 10, the semiconductor element 1 is bonded to the mounting surface 7111a via a bonding material 55, and the first semiconductor element 61 is bonded via a conductive bonding material 619. The conductive bonding material 619 is, for example, solder, metal paste, or sintered metal. The bonding material 55 may be, for example, solder, metal paste, or sintered metal, or an insulating adhesive. The island portion 7111 is covered with a sealing resin 9. In the illustrated example, the island portion 7111 is rectangular in plan view. The thickness of the island portion 7111 is, for example, 100 μm or more and 300 μm or less.
[0040] As shown in Figures 2, 6, and 7, the island portion 7111 has a plurality of through holes 713. Each of the multiple through holes 713 penetrates the island portion 7111 in the thickness direction z and extends along the second direction y. In a plan view, at least one of the multiple through holes 713 is located between the semiconductor element 1 and the first semiconductor element 61. The multiple through holes 713 are arranged along the second direction y. Unlike the illustrated example, the island portion 7111 does not necessarily have to have a plurality of through holes 713.
[0041] As shown in Figure 2, the two extensions 7112 extend from both sides of the island portion 7111 in the second direction y. The two extensions 7112 are located apart from each other in the second direction y. At least one of the two extensions 7112 is connected to the ground of the first semiconductor element 61 via one of the plurality of wires 86.
[0042] In a plan view, the exposed portion 712 extends along the first direction x. As shown in Figure 3, when viewed in the second direction y, the exposed portion 712 is bent in a gull-wing shape.
[0043] As shown in Figure 2, the lead 72 includes a covered portion 721 and an exposed portion 722. The covered portion 721 is covered by the sealing resin 9. The exposed portion 722 is exposed from the sealing resin 9.
[0044] The covering portion 721 has an island portion 7211 and two extension portions 7212.
[0045] As shown in Figures 6 and 7, the island portion 7211 has a mounting surface 7211a facing the second side z2 in the thickness direction z. As shown in Figure 7, the second semiconductor element 62 is bonded to the mounting surface 7211a via a conductive bonding material 629. Each conductive bonding material 129,149 is, for example, solder, metal paste, or sintered metal. The island portion 7211 is covered with a sealing resin 9. In the illustrated example, the island portion 7211 is rectangular in plan view. The thickness of the island portion 7211 is, similar to the island portion 7111, for example, 100 μm to 300 μm.
[0046] As shown in Figure 2, the two extensions 7212 extend from both sides of the island portion 7211 in the second direction y. The two extensions 7212 are located apart from each other in the second direction y. At least one of the two extensions 7212 is connected to the ground of the second semiconductor element 62 via one of the plurality of wires 87.
[0047] In a plan view, the exposed portion 722 extends along the first direction x. As shown in Figure 3, when viewed in the second direction y, the exposed portion 722 is bent in a gull-wing shape.
[0048] As shown in Figures 1 and 2, the multiple leads 73 are located in a first direction x opposite to the island portion 7211 of lead 72 with respect to the island portion 7111 of lead 71. The multiple leads 73 are arranged along a second direction y. At least one of the multiple leads 73 conducts to the first semiconductor element 61 via one of the multiple wires 88. The multiple leads 73 include a plurality (six in the illustrated example) of intermediate leads 73A and two side leads 73B. The two side leads 73B are located one on each side of the plurality of intermediate leads 73A in the second direction y. Each of the two side leads 73B is located in the second direction y between one of the two extensions 7112 of lead 71 and the intermediate lead 73A closest to that extension 7112.
[0049] As shown in Figures 2 and 6, each of the multiple leads 73 (multiple intermediate leads 73A and two side leads 73B) has a covered portion 731 and an exposed portion 732. The covered portion 731 is covered with a sealing resin 9. In the illustrated example, the dimension of each covered portion 731 of the two side leads 73B in the first direction x is greater than the dimension of each covered portion 731 of the multiple intermediate leads 73A in the first direction x. As shown in Figures 2 and 6, the exposed portion 732 is connected to the covered portion 731 and is exposed from the sealing resin 9. In plan view, the exposed portion 732 extends along the first direction x. As can be seen from Figures 2 to 4, when viewed along the second direction y, the exposed portion 732 is bent in a gull-wing shape. The shape of the exposed portion 732 is equal to the shape of each exposed portion 712 of the lead 71.
[0050] The shape, arrangement, and number of the multiple leads 73 are not limited to the illustrated example. For example, there may be fewer or more leads 73 than in the illustrated example (eight). Also, for example, some of the multiple leads 73 may be positioned outward from either of the two extensions 7112 of the lead 71.
[0051] As shown in Figures 1 and 2, the multiple leads 74 are located in the first direction x on the opposite side of the multiple leads 73 from the island portion 7111 of the lead 71. The multiple leads 74 are arranged along the second direction y. At least one of the multiple leads 74 is conductive to the second semiconductor element 62 via one of the multiple wires 85. The multiple leads 74 include multiple (six in the illustrated example) intermediate leads 74A and two side leads 74B. The two side leads 74B are located one on each side of the multiple intermediate leads 74A in the second direction y. In the second direction y, one of the two extensions 7212 of the lead 72 is located between one of the two side leads 74B and the intermediate lead 74A closest to that side lead 74B.
[0052] As shown in Figures 2 and 6, each of the multiple leads 74 (multiple intermediate leads 74A and two side leads 74B) has a covered portion 741 and an exposed portion 742. The covered portion 741 is covered by a sealing resin 9. In the illustrated example, the dimension of each covered portion 741 of the two side leads 74B in the first direction x is greater than the dimension of each covered portion 741 of the multiple intermediate leads 74A in the first direction x. As shown in Figures 2 and 6, the exposed portion 742 is connected to the covered portion 741 and is exposed from the sealing resin 9. In plan view, the exposed portion 742 extends along the first direction x. As can be understood from Figures 2, 3 and 5, when viewed along the second direction y, the exposed portion 742 is bent in a gull-wing shape. The shape of the exposed portion 742 is equal to the shape of the two exposed portions 722 of the lead 72.
[0053] The shape, arrangement, and number of the multiple leads 74 are not limited to the illustrated example. For example, there may be fewer or more leads 74 than in the illustrated example (eight). Also, for example, the two side leads 74B may each be located between one of the two extensions 7212 of the lead 72 and the intermediate lead 74A that is closest to the extension 7212 in the second direction y.
[0054] Leads 71, 72, 73, and 74 each have a body 75 and a metal layer 76. The body 75 may contain metals or alloys thereof, such as Cu (copper), Ni (nickel), and Fe (iron). The metal layer 76 covers at least a portion of the body 75 and may consist of one or more layers containing metals or alloys thereof, such as Sn (tin), Ni (nickel), Pd (palladium), Au (gold), and Ag (silver).
[0055] Figures 10 to 13 show the exposed portion 712 in more detail. The specific configuration described with reference to these figures may be similarly provided by exposed portions 722, 732, and 742, and in this embodiment, these configurations are common to exposed portions 712, 722, 732, and 742.
[0056] The body 75 in the exposed portion 712 may have a bottom surface 751, an end surface 752, two side surfaces 753, a top surface 754, and a concave surface 755. The bottom surface 751 is the surface facing z1 in the thickness direction z. The top surface 754 is the surface facing z2 in the thickness direction z. The end surface 752 is located at the tip of the exposed portion 712 and is situated between the bottom surface 751 and the end surface 752 in the thickness direction z. In the illustrated example, the end surface 752 faces a first direction x. The two side surfaces 753 are located on both sides of the first direction x and are situated between the bottom surface 751 and the top surface 754 in the thickness direction z.
[0057] The concave surface 755 is located between the bottom surface 751 and the end surface 752. As is clearly shown in Figure 12, the concave surface 755 is recessed z2 side of the bottom surface 751 in the thickness direction z. Also, the concave surface 755 is recessed inward (to the right in the figure) from the end surface 752 in the first direction x. The depth of the concave surface 755 in the thickness direction z is not limited in any way, and may be, for example, 1 / 4 to 3 / 4 times the thickness of the main body 75 in the thickness direction z at the exposed portion 712.
[0058] The concave surface 755 occupies only a portion of the body 75 in the second direction y. In the illustrated example, the concave surface 755 is separated from the two side surfaces 753 in the second direction y.
[0059] The specific shape of the concave surface 755 is not limited in any way. The concave surface 755 may be a semicircular shape, a semielliptical shape, a polygonal shape, etc., when viewed in the thickness direction z. As shown in Figures 10 and 11, in the illustrated example, the concave surface 755 is a semielliptical shape when viewed in the thickness direction z. The three-dimensional shape of the concave surface 755 may be, for example, a concave curved surface, a bent surface, etc. As shown in Figures 12 and 13, in the illustrated example, the concave surface 755 is composed of a concave curved surface. The size of the concave surface 755 in the second direction y is larger as it approaches the first side z1 in the thickness direction z.
[0060] The metal layer 76 in the exposed portion 712 may include a bottom portion 761, two side portions 763, a top portion 764, and a concave portion 765. The bottom portion 761 covers the bottom surface 751. The two side portions 763 cover the two side portions 763. The top portion 764 covers the top surface 754. The concave portion 765 covers the concave surface 755. The concave portion 765 only needs to cover at least a portion of the concave surface 755. In the illustrated example, the concave portion 765 is connected to the bottom surface 751. Also, the concave portion 765 covers the entire concave surface 755. The end face 752 may be entirely exposed from the metal layer 76.
[0061] Each of the multiple connecting members 8 provides electrical conductivity between two parts that are separated from each other. As described above, the multiple connecting members 8 include multiple wires 81, 82, 84-87. The multiple connecting members 8 may be bonding ribbons or plate-shaped metal members instead of multiple wires 81, 82, 84-87 (bonding wires).
[0062] Each of the multiple wires 81, 82, 84-87 contains a metallic material, which is copper or a copper alloy (for example, a palladium-copper alloy). In other words, each of the multiple wires 81, 82, 84-87 is a copper wire. Each of the multiple wires 81, 82, 84-87 may also consist of a core material (for example, containing copper) and a surface layer (for example, palladium) covering the core material. In this embodiment, the multiple wires 82, 84-87 may not contain copper or a copper alloy as the metallic material, but may instead contain gold, aluminum, or silver.
[0063] Each of the multiple wires 81 is connected to one of the multiple pads 111 of the semiconductor element 1 and one of the multiple pads 611 of the first semiconductor element 61, as shown in Figures 2 and 7. Each wire 81 provides electrical conductivity between the semiconductor element 1 and the first semiconductor element 61. The multiple wires 81 are arranged along the second direction y.
[0064] Each of the multiple wires 82 is joined to one of the multiple pads 112 of the semiconductor element 1 and one of the multiple pads 621 of the second semiconductor element 62, as shown in Figures 2 and 7. Each wire 81 provides electrical conductivity between the semiconductor element 1 and the second semiconductor element 62. The multiple wires 81 are arranged along the second direction y. In a plan view, each of the multiple wires 81 straddles the island portion 7111 of the lead 71 and the island portion 7211 of the lead 72.
[0065] Each of the multiple wires 84 is connected to one of the multiple pads 611 of the first semiconductor element 61 and to the covering portion 731 of one of the multiple leads 73, as shown in Figure 2. Each wire 88 provides electrical conductivity between the first semiconductor element 61 and one of the multiple leads 73.
[0066] Each of the multiple wires 85 is connected to one of the multiple pads 621 of the second semiconductor element 62 and to the covering portion 741 of one of the multiple leads 74, as shown in Figure 2. Each wire 85 provides electrical conductivity between the second semiconductor element 62 and one of the multiple leads 74.
[0067] Each of the multiple wires 86 is connected to one of the multiple pads 611 of the first semiconductor element 61 and to two extensions 7112, as shown in Figure 2. Each of the multiple wires 86 provides electrical conductivity between the first semiconductor element 61 and the lead 71. Note that the number of wires 86 is not limited to multiple; it may be just one.
[0068] Each of the multiple wires 87 is connected to one of the multiple pads 621 of the second semiconductor element 62 and one of the two extensions 7212, as shown in Figure 2. Each of the multiple wires 87 provides electrical conductivity between the second semiconductor element 62 and the lead 72. Note that the number of multiple wires 87 is not limited to multiple; it may be just one.
[0069] As shown in Figure 1, the sealing resin 9 covers the semiconductor element 1, the first semiconductor element 61 and the second semiconductor element 62, a portion of the lead 7, and a plurality of connecting members 8. The sealing resin 9 has electrical insulating properties. The sealing resin 9 insulates the components of the first circuit (e.g., lead 71) and the components of the second circuit (e.g., lead 72) from each other. The sealing resin 9 is made of a material including, for example, black epoxy resin. In the illustrated example, the sealing resin 9 is rectangular in plan view.
[0070] As shown in Figures 2 to 5, the sealing resin 9 has a top surface 91, a bottom surface 92, a pair of side surfaces 93, and a pair of side surfaces 94.
[0071] As shown in Figures 3 to 5, the top surface 91 and the bottom surface 92 are located apart from each other in the thickness direction z. The top surface 91 and the bottom surface 92 face opposite each other in the thickness direction z. Each of the top surface 91 and the bottom surface 92 is substantially flat.
[0072] As shown in Figures 3 to 5, the pair of sides 93 are connected to the top surface 91 and the bottom surface 92, and are located apart from each other in the first direction x. From one side 93 of the pair of sides 93 located on the first direction x, two exposed portions 712 and the exposed portions 732 of the multiple leads 73 are exposed. From the other side 93 of the pair of sides 93 located on the first direction x, two exposed portions 722 and the exposed portions 742 of the multiple leads 74 are exposed.
[0073] As shown in Figures 3 to 5, the pair of sides 94 are connected to the top surface 91 and the bottom surface 92, and are located apart from each other in the second direction y. As shown in Figure 1, the leads 71, 72, multiple leads 73, and multiple leads 74 are located apart from the pair of sides 94.
[0074] The applications of semiconductor device A1 are not limited; for example, it can be used in inverter devices in electric vehicles. In the motor driver circuit of an inverter device, a half-bridge circuit including low-side (low-potential) switching elements and high-side (high-potential) switching elements is commonly configured. In the following explanation, we will assume that these switching elements are MOSFETs.
[0075] In a low-side switching element, the reference potential between the source of the switching element and the gate driver that drives the switching element is both ground. On the other hand, in a high-side switching element, the reference potential between the source of the switching element and the gate driver that drives the switching element is both the potential at the output node of the half-bridge circuit.
[0076] As the potential at the output node changes depending on the drive of the high-side switching element and the low-side switching element, the reference potential of the gate driver that drives the high-side switching element changes. When the high-side switching element is on, this reference potential is equivalent to the voltage applied to the drain of the high-side switching element (for example, 600V or more). In semiconductor device A1, the ground of the first semiconductor element 61 and the ground of the second semiconductor element 62 are separated. Therefore, when semiconductor device A1 is used as a gate driver to drive the high-side switching element, a voltage equivalent to the voltage applied to the drain of the high-side switching element is transiently applied to the ground of the second semiconductor element 62.
[0077] Next, an example of a manufacturing method for semiconductor device A1 will be described below with reference to Figures 14 to 24.
[0078] As shown in Figure 14, the manufacturing method of the semiconductor device A1 according to this embodiment includes the steps of preparing a lead frame 700, forming a metal layer 760, mounting a semiconductor element 1, forming a sealing resin 9, and cutting the lead frame 700.
[0079] In the process of preparing the lead frame 700, the lead frame 700 is prepared as shown in Figure 15. At this point, the lead frame 700 consists only of the main body 750. The main body 750 may include metals such as Cu (copper), Ni (nickel), Fe (iron), or alloys thereof. The lead frame 700 may include, for example, the island portion 7111, the portion that will become the island portion 7211, a plurality of rod-shaped portions 7501, and an outer frame 780 and a dam bar 790 that connect them.
[0080] As shown in Figures 16 to 18, each rod-shaped portion 7501 extends along a first direction x. Each rod-shaped portion 7501 may have a bottom surface 7510, two side surfaces 7530, a top surface 7540, and a concave surface 7550.
[0081] The bottom surface 7510 is the surface facing z1 in the thickness direction z. The top surface 7540 is the surface facing z2 in the thickness direction z. The two side surfaces 7530 are located on both sides in the first direction x and are situated between the bottom surface 7510 and the top surface 7540 in the thickness direction z.
[0082] The concave surface 7550 is recessed z2 side of the bottom surface 7510 in the thickness direction z. The concave surface 7550 occupies only a portion of the main body 750 in the second direction y. In the illustrated example, the concave surface 7550 is separated from the two sides 7530 in the second direction y.
[0083] The specific shape of the concave surface 7550 is not limited in any way. The concave surface 7550 may be circular, elliptical, polygonal, etc., when viewed in the thickness direction z. In the illustrated example, the concave surface 7550 is elliptical when viewed in the thickness direction z. The three-dimensional shape of the concave surface 7550 may be, for example, a concave curved surface, a bent surface, etc. In the illustrated example, the concave surface 7550 is composed of a concave curved surface. Such a concave surface 7550 can be formed, for example, by etching, punching, etc., on a metal plate material.
[0084] Next, as shown in Figure 19, a metal layer 760 is formed. In this figure, for ease of understanding, the areas where the metal layer 760 is formed are hatched. In this example, the metal layer 760 is formed to cover almost the entire body 750. The metal layer 760 may consist of one or more layers containing metals such as Sn (tin), Ni (nickel), Pd (palladium), Au (gold), Ag (silver), or alloys thereof. The metal layer 760 is formed, for example, by a plating process.
[0085] As shown in Figures 20 to 22, the metal layer 760 in the rod-shaped portion 7501 may include a bottom portion 7610, two side portions 7630, a top portion 7640, and a concave portion 7650. The bottom portion 7610 covers the bottom surface 7510. The two side portions 7630 cover the two side portions 7530. The top portion 7640 covers the top surface 7540. The concave portion 7650 covers the concave surface 7550. The concave portion 7650 only needs to cover at least a portion of the concave surface 7550. In the illustrated example, the concave portion 7650 is connected to the bottom surface 7510. Also, the concave portion 7650 covers the entire concave surface 7550.
[0086] Next, as shown in Figure 23, a step of mounting the semiconductor element 1 is performed. The first semiconductor element 61 and the second semiconductor element 62 may be mounted at the same time as this step. After this step, a step of connecting multiple connecting members 8 may be performed. Then, a step of forming the sealing resin 9 is performed. In Figure 23, the sealing resin 9 is shown by dashed lines. In addition to the area shown by dashed lines, resin molded portions may be formed at any other location.
[0087] Next, the lead frame 700 is cut. The lead frame 700 is cut along the two cutting lines CL shown in Figure 23. Alternatively, multiple cutting lines (not shown) may be used to cut, for example, the dam bar 790 at appropriate locations.
[0088] The cutting line CL intersects the concave surface 7550. That is, in the process of cutting the lead frame 700, the concave surface 7550 is cut. The cutting method for cutting the lead frame 700 is not limited in any way. In the example shown in Figure 24, cutting is performed using molds M1 and M2. Molds M1 and M2 are positioned facing each other with the cutting line CL in between, and intersecting in the thickness direction z. This results in the lead frame 700 being cut at the concave surface 7550. This cutting forms a lead 7 having a body 75 and a metal layer 76. A cut surface is formed on the exposed portion 712 of the lead 7, and this cut surface becomes the end face 752. In addition, one side each of the cut concave surface 7550 and concave portion 7650 becomes concave surface 755 and concave portion 765. By going through the above process, a semiconductor device A1 is obtained.
[0089] Next, we will explain the operation of semiconductor device A1.
[0090] According to this embodiment, as shown in Figures 12 and 13, the semiconductor device A1 can be mounted on a circuit board SU having an insulating plate SU1 and a wiring pattern SU2 using solder SL. In this mounting, the solder SL adheres to the concave portion 765. This increases the mounting strength of the semiconductor device A1 to the circuit board SU using solder SL.
[0091] The concave surface 755 occupies only a portion of the main body 75 in the second direction y. As a result, as shown in Figure 13, the solder SL bites into the lead 7. This makes it possible to more effectively increase the mounting strength of the semiconductor device A1.
[0092] The concave surface 755 is separated from the two side surfaces 753. As a result, in Figure 13, the solder SL bites into the central portion of the exposed portion 712 in the second direction y. This is preferable for improving mounting strength.
[0093] As shown in Figure 12, the concave portion 765 is connected to the bottom portion 761, making it easier to adhere the solder SL to both the bottom portion 761 and the concave portion 765.
[0094] As shown in Figures 23 and 24, in the manufacturing method of semiconductor device A1, the concave surface 7550 is cut when the lead frame 700 is cut. This makes it possible to form the concave surface 755 located at the tip of the exposed portion 712 more reliably and easily.
[0095] Figures 25 to 31 show modified examples and other embodiments of the present disclosure. In these figures, elements identical or similar to those in the above embodiments are denoted by the same reference numerals. Furthermore, the configurations of the parts in each modified example and each embodiment can be combined with each other as appropriate, to the extent that no technical inconsistencies arise.
[0096] Figure 25 shows a first modified example of semiconductor device A1. In this modified semiconductor device A11, the concave surface 755 is polygonal in shape when viewed in the thickness direction z, and is rectangular.
[0097] Figure 26 shows a second modified example of semiconductor device A1. In this modified example, semiconductor device A12, the concave surface 755 is polygonal in shape when viewed in the thickness direction z, and is triangular.
[0098] The mounting strength can be increased by semiconductor devices A11 and A12. Furthermore, as can be seen from these modifications, the specific shape of the concave surface 755 as viewed in the thickness direction z is not limited in any way.
[0099] Figure 27 shows a third modified example of semiconductor device A1. In this modified example, semiconductor device A13, the concave surface 755 is composed of a bent surface. In the illustrated cross-section, the concave surface 755 is composed of a bent surface containing three intersecting planes. In this modified example as well, the size of the concave surface 755 in the second direction y increases as it approaches the first side z1 in the thickness direction z.
[0100] The semiconductor device A13 can increase mounting strength. Furthermore, as can be seen from these modifications, the specific cross-sectional shape of the concave surface 755 is not limited in any way.
[0101] Figure 28 shows a semiconductor device according to a second embodiment of the present disclosure. In the semiconductor device A2 of this embodiment, the concave surface 755 is in contact with one of the two side surfaces 753 and separated from the other when viewed in the thickness direction z. That is, the concave surface 755 is recessed inward in the second direction y from one of the side surfaces 753.
[0102] The semiconductor device A2 can increase the mounting strength. Furthermore, as can be understood from this embodiment, the specific position of the concave surface 755 as viewed in the thickness direction z is not limited in any way.
[0103] Figure 29 shows a semiconductor device according to a third embodiment of the present disclosure. In the semiconductor device A3 of this embodiment, the concave surface 755 includes a plurality of isolation regions 7551. The number of isolation regions 7551 is not limited in any way, and in the illustrated example there are two.
[0104] The two separation regions 7551 are separated from each other in the second direction y. A portion of the bottom surface 751 is interposed between the two separation regions 7551. The two separation regions 7551 are individually in contact with the two side surfaces 753 when viewed in the thickness direction z. Each of the two separation regions 7551 is recessed inward in the second direction y from each of the two side surfaces 753.
[0105] The semiconductor device A3 enhances mounting strength. Furthermore, the solder SL penetrates the lead 7 in multiple isolation regions 7551. This further increases mounting strength.
[0106] Figures 30 and 31 show a semiconductor device according to a fourth embodiment of the present disclosure. In the semiconductor device A4 of this embodiment, the metal layer 76 in the exposed portion 712 further includes an end face portion 762. In Figure 30, hatching is applied to the end face portion 762 for ease of understanding.
[0107] The end face portion 762 covers at least a portion of the end face 752. In the illustrated example, the end face portion 762 covers the first side z1 portion of the end face 752 in the thickness direction z. The second side z2 portion of the end face 752 in the thickness direction z is exposed from the end face portion 762. The end face portion 762 may cover the entire end face 752. The end face portion 762 connects to the concave surface 755. The end face portion 762 connects to the bottom surface portion 761.
[0108] The end face portion 762 may be formed, for example, in the process of cutting the lead frame 700 shown in Figure 24, when a portion of the metal layer 760 is stretched by the mold M2 and adheres to the end face 752.
[0109] The semiconductor device A4 can increase the mounting strength. Furthermore, as shown in Figure 31, in this embodiment, solder SL can adhere to the end face portion 762. This further increases the mounting strength of the semiconductor device A4.
[0110] The semiconductor device and method for manufacturing the semiconductor device described herein are not limited to the embodiments described above. The specific configuration of the semiconductor device and method for manufacturing the semiconductor device described herein can be modified in various ways.
[0111] [Note 1] Semiconductor device (1), Multiple leads (7), A sealing resin (9) and, Each of the plurality of leads (7) includes a body (75) and a metal layer (76) that covers at least a portion of the body (75), At least one of the plurality of leads (7) includes a covered portion (711) covered by the sealing resin (9) and an exposed portion (712) exposed from the sealing resin (9), The main body (75) in the exposed portion (712) has a bottom surface (751) facing the first side (z1) in the thickness direction (z) of the semiconductor element (1), an end surface (752) facing the first direction (x) intersecting the thickness direction (z) at the tip, and a concave surface (755) located between the bottom surface (751) and the end surface (752). The concave surface (755) occupies only a portion of the main body (75) in the second direction (y) intersecting the thickness direction (z) and the first direction (x). The semiconductor device (A1) comprises a metal layer (76) including a bottom portion (761) that covers the bottom surface (751) and a concave portion (765) that covers the concave surface (755). [Note 2] The semiconductor device (A1) as described in Appendix 1, wherein the main body (75) in the exposed portion (712) has two sides (753) facing opposite directions in the second direction. [Note 3] The semiconductor device (A1) according to Appendix 2, wherein the metal layer (76) includes two side portions (763) that cover the two side portions (753). [Note 4] The semiconductor device (A1) according to Appendix 2 or 3, wherein the concave surface (755) is separated from the two side surfaces (753). [Note 5] The semiconductor device (A2) according to Appendix 2 or 3, wherein the concave surface (755) is in contact with either of the two side surfaces (753). [Note 6] The semiconductor device (A3) according to Appendix 2 or 3, wherein the concave surface (755) includes two separate regions (7551) that are individually in contact with the two side surfaces (753). [Note 7] The semiconductor device (A1) according to any one of the appendices 1 to 6, wherein the concave surface (755) is semicircular or semi-elliptical when viewed in the thickness direction (z). [Note 8] The concave surface (755) is polygonal in shape when viewed in the thickness direction (z), as described in any of appendices 1 to 6 (A11). [Note 9] The concave surface (755) is formed by a concave curved surface, as described in any of appendices 1 to 8 (A1). [Note 10] The concave surface (755) is formed by a curved surface, as described in any of appendices 1 to 8 (A13). [Note 11] The semiconductor device (A1) according to any one of the appendices 1 to 8, wherein the size of the concave surface (755) in the second direction (y) increases as it approaches the first side (z1) in the thickness direction (z). [Note 12] The semiconductor device (A4) according to any one of appendices 1 to 11, wherein the metal layer (76) includes an end face portion (762) that covers at least a part of the end face (752). [Note 13] The end face portion (762) is connected to the concave portion (765), and is a semiconductor device (A4) as described in Appendix 12. [Note 13-1] The end face portion (762) is connected to the bottom face portion (761) and is a semiconductor device (A4) as described in either Appendix 12 or 13. [Note 14] The semiconductor element (1) is an insulating signal transmission element, A semiconductor device (A1) according to any one of the appendices 1 to 13, further comprising a first semiconductor device (61) and a second semiconductor device (62) that transmit and receive signals in an insulated state from each other by the semiconductor device (1). [Note 15] A step of preparing a lead frame (700) having a main body (750) including a rod-shaped portion (7501) extending in a first direction (x), A step of mounting a semiconductor element (1) onto the lead frame (700), A step of forming a sealing resin (9) that covers a part of the lead frame (700) and the semiconductor element (1), The process includes cutting the lead frame (700), The rod-shaped portion (7501) includes a bottom surface (7510) facing the first side (z1) in the thickness direction (z) intersecting the first direction (x), and a concave surface (7550) recessed from the bottom surface (7510). After the step of preparing the lead frame (700) and before the step of mounting the semiconductor element (1), the process includes a step of forming a metal layer (760) including a bottom portion (7610) that covers the bottom surface (7510) and a concave portion (7650) that covers the concave surface (7550). A method for manufacturing a semiconductor device (A1), wherein the concave surface (7550) is cut in the step of cutting the lead frame (700). [Explanation of Symbols]
[0112] A1, A11, A12, A13, A2, A3, A4: Semiconductor equipment 1: Semiconductor element 1a: Main surface 1b: Back side 7: Lead 8: Connecting member 9: Sealing resin 11: Semiconductor substrate 13a: Main surface 55: Bonding material 61: First semiconductor element 61a: Main surface 61b: Reverse side 62: Second semiconductor element 62a: Main surface 62b: Reverse side 71, 72, 73: Lead 73A: Intermediate lead 73B: Side lead 74: Lead 74A: Middle lead 74B: Side lead 75: Main unit 76: Metal layer 81, 82, 84, 85, 86, 87, 88: Wire 91:Top surface 92: Bottom 93: Side view 94: Side view 110: Semiconductor substrate 111: Pad 112: Pad 113: Seal ring section 115: Functional part 115a: Upper winding 115b: Lower winding 117: Laminated Structure 118:Wiring section 129: Conductive bonding material 149: Conductive bonding material 611: Pad 619: Conductive bonding material 621: Pad 629: Conductive bonding material 700: Lead frame 711: Covering part 712 :Exposed part 713: Through hole 721: Covering part 722 :Exposed part 722b:Exposed part 732 :Exposed part 741: Covering part 742 :Exposed part 750: Main unit 751: Bottom 752: End face 753: Side view 754: Top surface 755: Concave 760: Metal layer 761: Bottom part 762: End face part 763: Side part 764:Top section 765: Concave part 780: Outer frame 790: Dam Bar 1141 :Protective film 1142: Passivation membrane 1143: Coil protective film 1171: Insulating layer 1181: Through-hole wiring 1182: Output wiring 7111: Island Department 7111a: Mounting surface 7112 :Extension part 7211: Island Department 7212 :Extension part 7222 :Exposed part 7501: Rod-shaped part 7510: Bottom 7530: Side view 7540: Top surface 7550: Concave 7551: Separation area 7610: Bottom part 7630: Side part 7640:Top section 7650: Concave part CL: Cutting line M1, M2: Mold SL: Solder SU: Circuit board SU1: Insulating board SU2: Wiring pattern x :1st direction y: Second direction z: thickness direction z1 :1st side z2: Second side
Claims
1. Semiconductor elements and Multiple leads, A sealing resin and, Each of the plurality of leads includes a body and a metal layer covering at least a portion of the body, At least one of the plurality of leads includes a covered portion covered by the sealing resin and an exposed portion exposed from the sealing resin, The main body in the exposed portion has a bottom surface facing the first side in the thickness direction of the semiconductor element, an end surface at the tip facing the first direction intersecting the thickness direction, and a concave surface located between the bottom surface and the end surface. The concave surface occupies only a portion of the main body in the thickness direction and in a second direction intersecting the first direction. The semiconductor device comprises a metal layer including a bottom portion that covers the bottom surface and a concave portion that covers the concave surface.
2. The semiconductor device according to claim 1, wherein the body in the exposed portion has two sides facing opposite directions in the second direction.
3. The semiconductor device according to claim 2, wherein the metal layer includes two side portions that cover the two sides.
4. The semiconductor device according to claim 2, wherein the concave surface is separated from the two side surfaces.
5. The semiconductor device according to claim 2, wherein the concave surface is in contact with either of the two sides.
6. The semiconductor device according to claim 2, wherein the concave surface includes two separate regions that are individually in contact with the two side surfaces.
7. The semiconductor device according to claim 1, wherein the concave surface is semicircular or semielliptical in shape when viewed in the thickness direction.
8. The semiconductor device according to claim 1, wherein the concave surface has a polygonal shape when viewed in the thickness direction.
9. The semiconductor device according to claim 1, wherein the concave surface is formed by a concave curved surface.
10. The semiconductor device according to claim 1, wherein the concave surface is formed by a bent surface.
11. The semiconductor device according to claim 1, wherein the size of the concave surface in the second direction increases as it approaches the first side in the thickness direction.
12. The semiconductor device according to any one of claims 1 to 11, wherein the metal layer includes an end face portion that covers at least a part of the end face.
13. The semiconductor device according to claim 12, wherein the end face portion is connected to the concave portion.
14. The aforementioned semiconductor element is an insulating signal transmission element. The semiconductor device according to claim 1, further comprising a first semiconductor element and a second semiconductor element that transmit and receive signals in an insulated state from each other by the aforementioned semiconductor element.
15. A step of preparing a lead frame having a main body including a rod-shaped portion extending in a first direction, A step of mounting a semiconductor element onto the lead frame, A step of forming a sealing resin that covers a part of the lead frame and the semiconductor element, The process includes cutting the lead frame, The rod-shaped portion includes a bottom surface facing the first side in the thickness direction intersecting the first direction and a concave surface recessed from the bottom surface. After the step of preparing the lead frame, and before the step of mounting the semiconductor element, the process includes forming a metal layer that includes a bottom portion covering the bottom surface and a concave portion covering the concave surface. A method for manufacturing a semiconductor device, wherein the concave surface is cut in the step of cutting the lead frame.