Semiconductor device, method for monitoring propagation length, and method for manufacturing a semiconductor device.

Abstract

We provide technology that can estimate propagation length. [Solution] The evaluation semiconductor element 1Q comprises a diffusion layer DL formed in a semiconductor substrate and a pair of contact portions CT1, CT2, and CT3 electrically connected to the diffusion layer DL. The pair of contact portions CT1, CT2, and CT3 are separated by a distance D1 in the X direction. The width L3 of contact portion CT3 in the X direction is smaller than the width L2 of contact portion CT2 in the X direction. The width L2 is smaller than the width L1 of contact portion CT1 in the X direction.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a method for monitoring propagation length, and a method for manufacturing a semiconductor device, and more particularly to a semiconductor device equipped with an evaluation semiconductor element, a method for monitoring propagation length using a semiconductor device, and a method for manufacturing a semiconductor device using a propagation length monitoring method. [Background technology]

[0002] As described in Patent Document 1, a method is used in which an evaluation semiconductor element is prepared to measure the resistance between multiple contact points, and the measurement results from the evaluation semiconductor element are fed back to the mass production line.

[0003] Furthermore, the Transfer Length Method (TLM) is known as a technique for measuring the characteristics of semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In the TLM method, the contact resistance at the point where the contact portion and the diffusion layer are in contact, as well as the resistance of the diffusion layer connecting the pair of contact portions, are measured while varying the distance between a pair of contacts, and the propagation length is calculated from these measurement results. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2008-277769 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Typically, propagation length is calculated assuming that the sheet resistance of the contact area and the sheet resistance of the diffusion layer are equal. Therefore, if the sheet resistance of the contact area and the sheet resistance of the diffusion layer are different, the propagation length cannot be calculated using conventional methods. If the width of the contact area becomes smaller than the propagation length, the contact resistance increases, and the on-resistance of the MOSFET increases. Consequently, there is a risk that the performance of the semiconductor device will deteriorate.

[0006] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0007] A semiconductor device in one embodiment includes an evaluation semiconductor element. The evaluation semiconductor element comprises a diffusion layer formed in a semiconductor substrate and a pair of first contact portions, a pair of second contact portions, and a pair of third contact portions electrically connected to the diffusion layer. The pair of first contact portions are separated by a first distance in a first direction in a plan view. The pair of second contact portions are separated by a first distance in a first direction. The pair of third contact portions are separated by a first distance in a first direction. The third width of the third contact portion in the first direction is smaller than the second width of the second contact portion in the first direction. The second width is smaller than the first width of the first contact portion in the first direction. [Effects of the Invention]

[0008] According to one embodiment, the propagation length can be estimated. Furthermore, the performance of the semiconductor device can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a perspective view showing an overview of the evaluation semiconductor device used in the TLM method. [Figure 2] Figure 2 is the equivalent circuit diagram of Figure 1. [Figure 3] Figure 3 is a graph showing the measurement results using the TLM method. [Figure 4] Figure 4 is a plan view showing the evaluation semiconductor element in Embodiment 1. [Figure 5] Figure 5 is a cross-sectional view showing the evaluation semiconductor element in Embodiment 1. [Figure 6] Figure 6 is a graph showing the measurement results by the TLM method in Embodiment 1. [Figure 7] Figure 7 is a plan view showing the wafer in Embodiment 1 and the form of the semiconductor device. [Figure 8] Figure 8 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1. [Figure 9] Figure 9 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 8. [Figure 10] Figure 10 is another cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 8. [Figure 11] Figure 11 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 9. [Figure 12] Figure 12 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 11. [Figure 13] Figure 13 is another cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 11. [[ID=3憨1]] [Figure 14] Figure 14 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 12. [Figure 15] Figure 15 is another cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 12. [Figure 16] Figure 16 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 14. [Figure 17] Figure 17 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 16. [Figure 18] Figure 18 is another cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 16. [Figure 19] Figure 19 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 17.

Embodiments for Carrying Out the Invention

[0010] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0011] Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction is the vertical direction, depth direction, or thickness direction of a structure. Also, expressions such as "plan view" or "planar view" used in this application mean that the surface formed by the X and Y directions is called a "plane," and this "plane" is viewed from the Z direction.

[0012] (Embodiment 1) <Findings obtained through the inventor's research> First, we will explain the new findings obtained through the inventor's research using Figures 1 to 3.

[0013] Figure 1 shows an overview of the evaluation semiconductor device used in the TLM method. As shown in Figure 1, a diffusion layer DL is formed in the semiconductor substrate SUB. The diffusion layer DL is an impurity region having n-type or p-type conductivity. A pair of contact regions CT are formed on the diffusion layer DL. The contact regions CT consist of a conductive film, such as a metal film.

[0014] The contact portion CT has a width W in the Y direction and a width L in the X direction. The pair of contact portions CT are separated by a distance D in the X direction. Here, the propagation length L T It is shorter than the width L.

[0015] Figure 2 is the equivalent circuit diagram of Figure 1. Contact resistor R CL R is the contact resistance of the contact portion CT and the diffusion layer DL, and the diffusion resistance R is the contact resistance of the contact portion CT and the diffusion layer DL. DL This is the resistance of the diffusion layer DL that connects the pair of contact parts CT.

[0016] As shown in Figure 3, when the semiconductor substrate SUB is made of silicon (Si), it is assumed that the sheet resistance of the contact portion CT and the sheet resistance of the diffusion layer DL are equal. Therefore, by changing the distance D, the propagation length L can be changed. T It can be estimated.

[0017] In recent years, semiconductor devices equipped with MOSFETs formed on compound semiconductor substrates such as silicon carbide (SiC) substrates have become widely used. Compared to silicon, SiC has an dielectric breakdown field strength that is about an order of magnitude greater. Therefore, in power MOSFETs using SiC substrates, the drift region that maintains the breakdown voltage can be reduced to about 1 / 10th, and the impurity concentration can be increased by about 100 times, theoretically reducing the device resistance by more than three orders of magnitude. In addition, since the band gap of SiC is about three times larger than that of Si, power MOSFETs using SiC substrates can operate at high temperatures.

[0018] Here, the inventors of this application have found that when the semiconductor substrate SUB is made of SiC, the sheet resistance of the contact portion CT is greater than the sheet resistance of the diffusion layer DL, and the actual propagation length L T However, the propagation length L was estimated assuming that the semiconductor substrate SUB is a Si substrate. T It was found to be smaller than [the specified value]. Also, when the diffusion layer DL is p-type, the propagation length L T However, it was found that it could become even smaller.

[0019] Thus, the propagation length L T Factors that may lead to a smaller estimate include the difference in physical properties between SiC and Si, and the fact that when films such as silicide films are formed on a SiC substrate, the interface between the SiC substrate and the film is more prone to deterioration compared to a Si substrate.

[0020] Furthermore, this phenomenon is not limited to SiC substrates; it also occurs when the semiconductor substrate SUB is made of a wide-bandgap semiconductor with a wider bandgap than Si. For example, the same phenomenon occurs when the semiconductor substrate SUB is made of a material containing gallium nitride, gallium oxide, or diamond.

[0021] <Semiconductor devices for evaluation> Figures 4 and 5 show the evaluation semiconductor element 1Q devised by the inventors of the present invention in consideration of the above findings. As shown in Figure 4, the evaluation semiconductor element 1Q comprises at least three evaluation patterns (evaluation pattern TEG1, evaluation pattern TEG2, and evaluation pattern TEG3).

[0022] Figure 5 shows a representative cross-sectional view of evaluation pattern TEG1 among evaluation patterns TEG1, TEG2, and TEG3.

[0023] As shown in Figures 4 and 5, the evaluation pattern TEG1 has a diffusion layer DL formed in a semiconductor substrate SUB, an interlayer insulating film IL formed on the diffusion layer DL, a plurality of contact portions CT1, and a plurality of pad electrodes PAD.

[0024] The semiconductor substrate SUB is made of a wide-bandgap semiconductor with a bandgap wider than that of Si, and consists of materials such as SiC, gallium nitride-containing materials, gallium oxide, or diamond. In the following explanation, the case where the semiconductor substrate SUB is made of SiC will be used as a representative example. The diffusion layer DL is an impurity region formed in the semiconductor substrate SUB and has n-type or p-type conductivity. The interlayer insulating film IL is, for example, a silicon oxide film.

[0025] Multiple pores CH are formed in the interlayer insulating film IL. Multiple contact portions CT1 are formed in the interlayer insulating film IL by embedding a first conductive film inside the multiple pores CH. The multiple contact portions CT1 are electrically connected to the diffusion layer DL. The first conductive film consists of a first barrier metal film and a first metal film formed on the first barrier metal film. The first barrier metal film is, for example, a titanium nitride film. The first metal film is, for example, a tungsten film.

[0026] Multiple pad electrodes PAD are formed on an interlayer insulating film IL and are electrically connected to multiple contact portions CT1. The pad electrodes PAD are provided to bring the terminals of the test device into contact when measuring the electrical resistance between a pair of contact portions CT1.

[0027] Multiple pad electrodes (PADs) consist of a second conductive film. The second conductive film consists of a second barrier metal film and a second metal film formed on the second barrier metal film. The second barrier metal film is, for example, a titanium nitride film. The second metal film is, for example, an aluminum alloy film with copper or silicon added.

[0028] Here, we have illustrated a case where the contact portion CT1 and the pad electrode PAD are composed of separate conductive films, but the contact portion CT1 and the pad electrode PAD may be made of the same second conductive film and integrated together. In that case, the second conductive film formed on the interlayer insulating film IL constitutes the pad electrode PAD, and the second conductive film embedded inside the pore CH constitutes the contact portion CT1.

[0029] Furthermore, a silicide film SI may be formed between each of the multiple contact portions CT1 and the diffusion layer DL. The silicide film SI may be, for example, a nickel silicide film, a cobalt silicide film, or a titanium silicide film.

[0030] Each of the multiple contact portions CT1 has a width W in the Y direction and a width L1 in the X direction. Here, we illustrate the case where the width W of the diffusion layer DL in the Y direction is the same as the width W of the contact portions CT1. The multiple contact portions CT1 are formed such that the distance D between two adjacent contact portions CT1 in the X direction is different. Distance D1 is, for example, 5 μm or more and is smaller than distance D2. Distance D2 is smaller than distance D3.

[0031] The structure of evaluation pattern TEG2 or evaluation pattern TEG3 is the same as that of evaluation pattern TEG1, except that contact portion CT1 is replaced by contact portion CT2 or contact portion CT3, and width L1 is changed to width L2 or width L3. Width L3 is smaller than width L2, and width L2 is smaller than width L1.

[0032] <Method for monitoring propagation length> Hereinafter, with reference to FIGS. 4 and 6, a method for monitoring the propagation length L using the evaluation semiconductor element 1Q will be described. T will be described.

[0033] First, at a pair of contact portions CT1 separated by distances D1, D2, and D3, the electrical resistance of the path from one contact portion CT1 to the other contact portion CT1 through the diffusion layer DL is measured respectively. Next, at a pair of contact portions CT2 separated by distances D1, D2, and D3, the electrical resistance of the path from one contact portion CT2 to the other contact portion CT2 through the diffusion layer DL is measured respectively. Next, at a pair of contact portions CT3 separated by distances D1, D2, and D3, the electrical resistance of the path from one contact portion CT3 to the other contact portion CT3 through the diffusion layer DL is measured respectively.

[0034] FIG. 6 shows an example of the results of measuring the respective electrical resistances. In FIG. 6, cases where there is no change in the electrical resistance of width L1 and the electrical resistance of width L2, and there is a change in the electrical resistance of width L2 and the electrical resistance of width L3 are shown.

[0035] The distances D1, D2, and D3 of evaluation pattern TEG1 are the same as the distances D1, D2, and D3 of evaluation pattern TEG2, and the same as the distances D1, D2, and D3 of evaluation pattern TEG3. Therefore, in evaluation patterns TEG1, TEG2, and TEG3, the spreading resistance R DL is the same. Accordingly, the fact that the electrical resistance changes means that the contact resistance R CL is changing, which means that the width L of the contact portion is smaller than the propagation length L T is smaller.

[0036] In other words, if there is no change in the electrical resistance of width L1 and the electrical resistance of width L2, then the propagation length L T It can be determined that it is smaller than width L2. And if there is a change in the electrical resistance of width L2 and the electrical resistance of width L3, then the propagation length L T It can be determined that it is greater than the width L3. Therefore, "width L3 < propagation length L T From the relationship <width L2>, the propagation length L T We can provide an estimate.

[0037] Furthermore, if there is no change in the electrical resistance of width L1 and width L2, and there is no change in the electrical resistance of width L2 and width L3, the propagation length L T (Propagation length L) is smaller than width L3 T It can be determined that the width L3 is <. Also, if there is a change in the electrical resistance of width L1 and the electrical resistance of width L2, the propagation length L T It is smaller than width L1 and larger than width L2 (width L2 < propagation length L T It can be determined that the width is <L1).

[0038] Thus, according to Embodiment 1, even when the semiconductor substrate SUB is made of a wide-bandgap semiconductor with a wider bandgap than Si, and the sheet resistance of the contact portion CT and the sheet resistance of the diffusion layer DL are different, the propagation length L can be determined by using evaluation patterns TEG1, TEG2, and TEG3 which have different widths L. T We can provide an estimate.

[0039] In Figure 4, three evaluation patterns, such as TEG1, TEG2, and TEG3, are shown as examples, and three widths, such as L1, L2, and L3, are shown as examples. However, there may be four or more types of evaluation patterns and widths L. The more types of evaluation patterns and widths L there are, the more accurately the propagation length L can be measured. T This allows for estimation. Furthermore, while Figure 4 shows three types of distances D, such as D1, D2, and D3, there may be four or more types of distances D.

[0040] <Manufacturing method for semiconductor devices> The propagation length L is shown below using Figures 7 to 19. T The following describes each manufacturing step included in the manufacturing method of a semiconductor device using the monitoring method described above. T The propagation length L determined by the monitoring method T The value can be fed back to each manufacturing process.

[0041] Figure 7 shows a wafer WF, semiconductor chip CHP1, and semiconductor chip CHP2. After each manufacturing process is completed, the wafer WF is divided into individual pieces along the scribe region SR by a dicing process to obtain multiple semiconductor chips CHP1 and multiple semiconductor chips CHP2.

[0042] As examples of the semiconductor device in Embodiment 1, semiconductor chips CHP1 and CHP2 are provided. Semiconductor chip CHP1 is a chip for product shipment. Semiconductor chip CHP2 is an evaluation chip that is not for product shipment. Semiconductor chips CHP1 and CHP2 each have a cell region CR and a scribe region SR that surrounds the cell region CR in a plan view.

[0043] In semiconductor chip CHP1, an evaluation semiconductor element 1Q is provided in the scribe region SR, and a MOSFET 2Q, for example, is provided in the cell region CR. In semiconductor chip CHP2, various test elements, including the evaluation semiconductor element 1Q, are provided in both the scribe region SR and the cell region CR.

[0044] In the manufacturing process described below using Figures 8 to 19, the example shown is when the semiconductor device is a semiconductor chip CHP1. The following description will primarily focus on the structure of the cell region CR, but the structure of the scribe region SR will also be described as necessary. An example of an impurity exhibiting n-type conductivity is nitrogen, while an example of an impurity exhibiting p-type conductivity is aluminum.

[0045] As shown in Figure 8, an n-type semiconductor substrate SUB made of SiC is prepared, having an upper surface TS and a lower surface BS. The semiconductor substrate SUB has an n-type drain region ND and an n-type drift region NV formed on the drain region ND. The impurity concentration in the drain region ND is higher than the impurity concentration in the drift region NV.

[0046] The semiconductor substrate SUB may be a laminate of an n-type SiC substrate and an n-type SiC layer formed on the n-type SiC substrate by epitaxial growth. In this case, the n-type SiC substrate constitutes the drain region ND, and the n-type SiC layer constitutes the drift region NV.

[0047] As shown in Figure 9, first, multiple p-type body regions PB are selectively formed in the semiconductor substrate SUB of the cell region CR using photolithography and ion implantation techniques. Next, n-type source regions NS are selectively formed in the body regions PB using photolithography and ion implantation techniques. Finally, p-type high-concentration diffusion regions PR are selectively formed in the body regions PB using photolithography and ion implantation techniques.

[0048] The impurity concentration in the source region NS is higher than that in the drift region NV. The impurity concentration in the high-concentration diffusion region PR is higher than that in the body region PB. The body region PB is formed to a predetermined depth from the top surface TS of the semiconductor substrate SUB. The source region NS and the high-concentration diffusion region PR are each formed such that their depth from the top surface TS of the semiconductor substrate SUB is shallower than that of the body region PB.

[0049] In the scribe region SR, as shown in Figure 10, a diffusion layer DL is selectively formed in the semiconductor substrate SUB using photolithography and ion implantation techniques. When forming an n-type diffusion layer DL, the diffusion layer DL may be formed using the same manufacturing process as the source region NS. When forming a p-type diffusion layer DL, the diffusion layer DL may be formed using the same manufacturing process as the high-concentration diffusion region PR.

[0050] After the manufacturing process shown in Figures 9 and 10, as shown in Figure 11, first, a gate insulating film GI is formed on the upper surface TS of the semiconductor substrate SUB, for example, by thermal oxidation. The gate insulating film GI is, for example, a silicon oxide film. Next, a conductive film is formed on the gate insulating film GI by a film deposition process, for example, using a CVD method. The conductive film is, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0051] Next, the conductive film is patterned to form multiple gate electrodes GE on the gate insulating film GI of the cell region CR. Each gate electrode GE is formed to span a portion of each of two adjacent body regions PB and a drift region NV located between the two adjacent body regions PB.

[0052] As shown in Figures 12 and 13, first, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB by a film deposition process, for example, using a CVD method, so as to cover multiple gate electrodes GE. Next, a resist material RS is formed on the interlayer insulating film IL. Then, exposure masks MK having various pattern shapes are prepared.

[0053] Next, the resist material RS is exposed using an exposure mask MK to selectively remove a portion of the resist material RS and form a resist pattern RP. Here, we illustrate the case where the resist material RS is positive type and the exposed areas are selectively removed. However, the resist material RS may also be negative type, and the areas that were not exposed may be selectively removed.

[0054] As shown in Figures 14 and 15, multiple pores CH are formed in the interlayer insulating film IL by etching the resist pattern RP using it as a mask. In the cell region CR, the pores CH are formed to reach the source region NS and the high-concentration diffusion region PR. In the scribe region SR, the pores CH are formed to reach the diffusion layer DL. Subsequently, the resist pattern RP is removed by ashing.

[0055] The widths W and L of the multiple holes CH (multiple contact areas CT) are determined by the pattern shape of the exposure mask MK or the exposure amount of the exposure process. For example, the widths L1, L2, and L3 shown in Figures 4 and 5 can be adjusted by changing the aperture pattern of the exposure mask MK or by changing the exposure amount.

[0056] As shown in Figure 16, a silicide film SI is formed at the bottom of multiple pores CH using salicide (Self-Aligned Silicide) technology. First, a metal film is formed inside the multiple pores CH and on the interlayer insulating film IL by a film deposition process using the sputtering method. This metal film is made of, for example, nickel, cobalt, or titanium. Next, the silicon contained in the semiconductor substrate SUB reacts with the metal film by heat treatment. As a result, a silicide film SI is formed on the source region NS, the high-concentration diffusion region PR, and the diffusion layer DL. After that, the unreacted metal film is removed.

[0057] As shown in Figures 17 and 18, first, a first conductive film is formed on the interlayer insulating film IL by a film deposition process using sputtering or CVD so as to fill the interior of the multiple pores CH. The first conductive film is, for example, the first barrier metal film and the first metal film described above. Next, the first conductive film located outside the multiple pores CH is removed by anisotropic etching or polishing using CMP. This forms multiple contact portions CT inside the multiple pores CH.

[0058] The multiple contact areas CT formed in the scribe region SR include contact areas CT1, CT2, and CT3 of evaluation patterns TEG1, TEG2, and TEG3 (see Figures 4 and 5).

[0059] Next, a second conductive film is formed on the interlayer insulating film IL by a film deposition process using sputtering or CVD. The second conductive film is, for example, the second barrier metal film and the second metal film described above. Next, the second conductive film is patterned to form a source electrode SE in the cell region CR and a plurality of pad electrodes PAD in the scribe region SR.

[0060] As shown in Figure 19, a drain electrode DE is formed beneath the lower surface BS of the semiconductor substrate SUB by a film deposition process, for example, using a sputtering method. The drain electrode DE consists of a single layer of metal film, such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a multilayer film formed by appropriately stacking these metal films. The drain electrode DE is formed over the entire lower surface BS of the semiconductor substrate SUB (see Figure 5).

[0061] With the above steps, evaluation semiconductor elements 1Q and MOSFET 2Q are formed on the semiconductor chip CHP1.

[0062] Within the body region PB, the area located below the gate electrode GE via the gate insulating film GI, and situated between the drift region NV and the source region NS, becomes the channel region of MOSFET2Q. As shown by the arrow in Figure 19, the current path of MOSFET2Q is from the drain electrode DE, through the drain region ND, the drift region NV, the channel region, the source region NS, the silicide film SI, and the contact region CT, to the source electrode SE.

[0063] In the cell region CR, the width L of the contact portion CT is equal to the propagation length L. T When it becomes smaller than this, the contact resistance R CL The propagation length L increases, and the on-resistance of MOSFET2Q increases. T The propagation length L determined by the monitoring method T By feeding this value back to each manufacturing process, the increase in the on-resistance of MOSFET2Q can be suppressed.

[0064] For example, in the manufacturing process shown in Figures 9 and 10, the determined propagation length L T Depending on the value of , the dose of ions used to form the source region NS is adjusted (increased), and the diffusion resistance R DL and contact resistor R CL It is also possible to reduce the propagation length L determined in the manufacturing process shown in Figures 12 and 13. T Depending on the value, the exposure amount for the exposure process on the pattern shape of the exposure mask MK or the resist material RS is adjusted, and the determined propagation length L T It is also possible to set the width L of the contact portion CT to be larger than the specified value. By performing at least one of these methods, the increase in the on-resistance of MOSFET2Q can be suppressed, and the performance of the semiconductor device (semiconductor chip CHP1) can be improved.

[0065] Furthermore, without providing feedback to each manufacturing process, the determined propagation length L T This can be used as an indicator. For example, within the requirements of the product specifications, an increase in on-resistance can be tolerated, the width L of the contact section CT can be reduced, and the MOSFET2Q can be miniaturized.

[0066] Although the present invention has been specifically described above based on embodiments, the present invention is not limited to these embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0067] 1Q Evaluation semiconductor devices 2Q MOSFET BS semiconductor substrate bottom surface CH hole CHP1 Semiconductor chip (semiconductor device, chip for product shipment) CHP2 semiconductor chip (semiconductor equipment, evaluation chip) CR cell area CT, CT1, CT2, CT3 Contact Section DE drain electrode DL diffusion layer (impurity region) GE Terminal GI gate insulating film IL interlayer film MK exposure mask ND Drain region (Impurity region) NS source area (impurity area) NV drift region (impurity region) PAD (Pad Electrode) PB body region (impurity region) PR High concentration diffusion region (impurity region) RP Resist Pattern RS Resistant SE source electrode SI silicide membrane SR Scribe Area SUB Semiconductor Substrate TEG1, TEG2, TEG3 evaluation patterns Top surface of TS semiconductor substrate WF wafer

Claims

1. A semiconductor device including an evaluation semiconductor element, The aforementioned evaluation semiconductor device is A diffusion layer formed in a semiconductor substrate, An interlayer insulating film formed on the diffusion layer, A pair of first contact portions, a pair of second contact portions, and a pair of third contact portions are formed in the interlayer insulating film and electrically connected to the diffusion layer, Equipped with, The pair of first contact portions are separated by a first distance in a first direction in a plan view. The pair of second contact portions are separated by a first distance in the first direction. The pair of third contact portions are separated by a first distance in the first direction. The third width of the third contact portion in the first direction is smaller than the second width of the second contact portion in the first direction. A semiconductor device wherein the second width is smaller than the first width of the first contact portion in the first direction.

2. In the semiconductor device described in claim 1, The semiconductor substrate is made of a wide-bandgap semiconductor having a wider bandgap than silicon, and is a semiconductor device.

3. In the semiconductor device described in claim 1, The semiconductor device is made of a semiconductor substrate containing silicon carbide, gallium nitride, gallium oxide, or diamond.

4. In the semiconductor device described in claim 1, The pair of first contact portions, the pair of second contact portions, and the pair of third contact portions are formed by embedding a conductive film inside a plurality of holes formed in the interlayer insulating film. The plurality of holes are formed by etching the interlayer insulating film using the resist pattern as a mask. The resist pattern is formed by exposing the resist material using an exposure mask. A semiconductor device in which the first width, second width, and third width are determined by the pattern shape of the exposure mask.

5. In the semiconductor device described in claim 1, The pair of first contact portions, the pair of second contact portions, and the pair of third contact portions are formed by embedding a conductive film inside a plurality of holes formed in the interlayer insulating film. The plurality of holes are formed by etching the interlayer insulating film using the resist pattern as a mask. The resist pattern is formed by exposing the resist material using an exposure mask. A semiconductor device in which the first width, second width, and third width are determined by the amount of exposure in the exposure process.

6. In the semiconductor device described in claim 1, A semiconductor device in which the first distance is 5 μm or more.

7. In the semiconductor device described in claim 1, The evaluation semiconductor element is a semiconductor device that is formed on the interlayer insulating film and further has a plurality of pad electrodes electrically connected to the pair of first contact portions, the pair of second contact portions, and the pair of third contact portions, respectively.

8. In the semiconductor device described in claim 1, The evaluation semiconductor element further comprises a plurality of first contact portions, a plurality of second contact portions, and a plurality of third contact portions formed in the interlayer insulating film and electrically connected to the diffusion layer, The plurality of first contact portions include the pair of first contact portions, and are formed such that the distance between two adjacent first contact portions in the first direction is different. The plurality of second contact portions include the pair of second contact portions and are formed such that the distance between two adjacent second contact portions in the first direction is different. A semiconductor device in which the plurality of third contact portions include the pair of third contact portions and are formed such that the distance between two adjacent third contact portions in the first direction is different.

9. A method for monitoring propagation length using a semiconductor device as described in claim 1, The first electrical resistance of the path from one of the first contact portions through the diffusion layer to the other first contact portion, the second electrical resistance of the path from one of the second contact portions through the diffusion layer to the other second contact portion, and the third electrical resistance of the path from one of the third contact portions through the diffusion layer to the other third contact portion are measured. If there is a change in the first electrical resistance and the second electrical resistance, the propagation length is determined to be smaller than the first width and larger than the second width. If there is no change in the first electrical resistance and the second electrical resistance, and there is no change in the second electrical resistance and the third electrical resistance, the propagation length is determined to be smaller than the third width. A method for monitoring propagation length, wherein if there is no change in the first electrical resistance and the second electrical resistance, and there is a change in the second electrical resistance and the third electrical resistance, the propagation length is determined to be smaller than the second width and larger than the third width.

10. A method for manufacturing a semiconductor device using the propagation length monitoring method described in claim 9, (a) A step of forming a source region in the semiconductor substrate by ion implantation, (b) A step of forming the interlayer insulating film on the semiconductor substrate, (c) A step of forming a resist material on the interlayer insulating film, (d) A step of forming a resist pattern by performing an exposure treatment on the resist material using an exposure mask, (e) A step of forming holes in the interlayer insulating film that reach the source region by performing an etching process on the interlayer insulating film using the resist pattern as a mask. (f) A step of forming a fourth contact portion in the interlayer insulating film by embedding a conductive film inside the hole, Equipped with, A method for manufacturing a semiconductor device, wherein at least one of the ion dose when forming the source region, the pattern shape of the exposure mask, and the exposure amount of the exposure process is adjusted according to the value of the propagation length determined by the propagation length monitoring method.

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