Semiconductor equipment

Abstract

We provide semiconductor devices that enable miniaturization of semiconductor chips. [Solution] The semiconductor device comprises a semiconductor chip having an amplifier, an input pad of the amplifier provided on its upper surface, and an output pad of the amplifier provided on its upper surface, an input bonding wire whose first end is joined to the input pad, and an output bonding wire whose first end is joined to the output pad, wherein the first input bonding wire is the thickest of the input bonding wires, and the width of the output pad in the region to which at least one of the output bonding wires that is thicker than the first input bonding wire is joined is greater than the widest width of the input pad in the region to which the input bonding wire is joined.

Description

Technical Field

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[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] It is known to thicken the outermost bonding wire among the bonding wires connected to the drain pad of a transistor chip (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Since a large current flows through the outermost bonding wire, thickening the outermost bonding wire can reduce the fusing of the bonding wire. However, when the bonding wire is thickened, the pad size increases and the semiconductor chip becomes larger.

[0005] An object of the present disclosure is to provide a semiconductor device capable of miniaturizing a semiconductor chip.

Means for Solving the Problems

[0006] Embodiments of the present disclosure are semiconductor devices comprising: an amplifier; an input pad of the amplifier provided on its upper surface; an output pad of the amplifier provided on its upper surface; an input bonding wire whose first end is joined to the input pad; and an output bonding wire whose first end is joined to the output pad, wherein the first input bonding wire is the thickest of the input bonding wires, and the width of the output pad in the region to which at least one of the output bonding wires that is thicker than the first input bonding wire is joined is greater than the largest width of the input pad in the region to which the input bonding wire is joined. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide a semiconductor device that can miniaturize semiconductor chips. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a circuit diagram of the amplifier circuit used in the first embodiment. [Figure 2] Figure 2 is a plan view of the semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a cross-sectional view of AA in Figure 2. [Figure 4] Figure 4 is a plan view of the semiconductor chip in the first embodiment. [Figure 5] Figure 5 is a cross-sectional view of AA in Figure 4. [Figure 6] Figure 6 is a cross-sectional view of BB in Figure 4. [Figure 7] Figure 7 is another cross-sectional view of BB in Figure 4. [Figure 8] Figure 8 is a plan view of the area around the semiconductor chip of the semiconductor device according to comparative form 1. [Figure 9] Figure 9 is a plan view of the area around the semiconductor chip of the semiconductor device according to comparative form 2. [Figure 10] Figure 10 is a plan view of the area around the semiconductor chip of the semiconductor device according to the first embodiment. [Figure 11] Figure 11 is a plan view of the area near the semiconductor chip of a semiconductor device according to Modification 1 of the First Embodiment. [Figure 12] Figure 12 is a plan view of the area near the semiconductor chip of a semiconductor device according to a modified example 2 of the first embodiment. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] First, the embodiments of this disclosure will be listed and described.

[0010] (1) Embodiments of the present disclosure are semiconductor devices comprising: an amplifier; an input pad of the amplifier provided on its upper surface; an output pad of the amplifier provided on its upper surface; an input bonding wire whose first end is joined to the input pad; and an output bonding wire whose first end is joined to the output pad, wherein the first input bonding wire is the thickest of the input bonding wires, and the width of the output pad in the region to which at least one of the output bonding wires that is thicker than the first input bonding wire is joined is greater than the widest width of the input pad in the region to which the input bonding wire is joined. This prevents the first output bonding wire from melting and allows for miniaturization of the semiconductor chip. (2) In (1) above, the number of first output bonding wires may be greater than half the number of output bonding wires. This prevents many first output bonding wires from being cut. (3) In (1) above, all of the output bonding wires may be thicker than the first input bonding wire. This prevents the output bonding wire from melting. (4) In any of (1) to (3) above, the width of the output pad may be greater than the largest width in all regions to which the first output bonding wire is bonded. This makes it possible to miniaturize the semiconductor chip. (5) In any of (1) to (4) above, an output terminal electrically connected to the output pad is provided, and at least one of the first output bonding wires may be provided in the output path that electrically connects the output pad and the output terminal. This prevents the output bonding wire provided in the output path from melting. (6) In (5) above, all output bonding wires provided in the output path may be thicker than the first input bonding wires. This prevents the output bonding wires provided in the output path from melting. (7) In (5) or (6) above, the output path includes a second output bonding wire connected in series with at least one of the first output bonding wires, and at least one of the second output bonding wires may be thicker than the first input bonding wire. This prevents the second output bonding wire from melting. (8) In any of the above (7), the semiconductor chip is mounted on a base and a first passive component is mounted on the base, the second end of the first output bonding wire is joined to the first passive component, the first end of the second output bonding wire is joined to the first passive component, and the second end of the second output bonding wire is joined to the output terminal. This prevents the second output bonding wire from melting. (9) In any of (1) to (8) above, the output bonding wire comprises a base on which the semiconductor chip is mounted, a second passive component mounted on the base, an input terminal electrically connected to the input pad, and a second input bonding wire whose first end is joined to the second passive component and whose second end is joined to the input terminal, wherein the second end of the first input bonding wire is joined to the second passive component, and at least one of the output bonding wires may be thicker than any of the second input bonding wires. This prevents the first output bonding wire from melting. (10) In any of (1) to (9) above, the amplifier has a transistor having an input electrode and an output electrode, the input pad is a region of a metal layer electrically connected to the input electrode, outside the active region of the transistor and exposed from a protective film covering the transistor, and the output pad may be a region of a metal layer electrically connected to the output electrode, outside the active region and exposed from the protective film. Thereby, the semiconductor chip can be miniaturized. (11) In any of (1) to (10) above, the upper surface of the semiconductor chip has opposing first and second sides, the plurality of regions where the input bonding wires are joined to the input pads are provided along the first side, the plurality of regions where the output bonding wires are joined to the output pads are provided along the second side, the largest width is the largest width of the input pad in a direction orthogonal to the extending direction of the first side, and the width of the output pad may be the width of the output pad in a direction orthogonal to the extending direction of the second side. Thereby, the semiconductor chip can be miniaturized.

[0011] [Details of Embodiments of the Present Disclosure] A specific example of a semiconductor device according to an embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0012] (First Embodiment) FIG. 1 is a circuit diagram of an amplifier circuit used in the first embodiment. As shown in FIG. 1, the amplifier circuit 108 according to the first embodiment includes an amplifier 50, matching circuits 51 and 52.

[0013] The amplifier 50 has a transistor Q. Transistor Q is, for example, a FET (Field Effect Transistor) and has a source S, a drain D, and a gate G. The source S is electrically connected to a reference potential terminal such as the ground terminal and is short-circuited. The gate G is electrically connected to the input terminal Tin via a matching circuit 51.

[0014] Transistor Q is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0015] The matching circuit 51 matches the impedance seen from the input terminal Tin to the matching circuit 51 with the impedance seen from the matching circuit 51 to the gate G. The amplifier 50 amplifies the high-frequency signal input to the gate G and outputs the amplified high-frequency signal to the drain D. The matching circuit 52 matches the impedance seen from the drain D to the matching circuit 52 with the impedance seen from the matching circuit 52 to the output terminal Tout.

[0016] Matching circuit 51 has inductors L1 and L2 and capacitor C1. Inductors L1 and L2 are connected in series between the input terminal Tin and the gate G. Capacitor C1 is shunt-connected to node N1 between inductors L1 and L2. Matching circuit 52 has inductors L3 and L4 and capacitor C2. Inductors L3 and L4 are connected in series between the drain D and the output terminal Tout. Capacitor C2 is shunt-connected to node N2 between inductors L3 and L4.

[0017] When the amplification circuit 108 is used as a power amplifier for a mobile communication base station, the center frequency of the operating bandwidth is, for example, 0.5 GHz or more and 20 GHz or less.

[0018] Figure 2 is a plan view of the semiconductor device according to the first embodiment 1. Figure 3 is a cross-sectional view of AA in Figure 2. The thickness direction of the base 21 is the Z direction, the direction from the input terminal 24A to the output terminal 24B is the X direction, and the direction perpendicular to the X and Z directions is the Y direction. The semiconductor device 100 of the first embodiment corresponds to the amplification circuit 108 in Figure 1.

[0019] As shown in Figures 2 and 3, the semiconductor device 100 according to the first embodiment includes a package 20, a semiconductor chip 30, and passive components 35A and 35B.

[0020] The package 20 has a base 21, a dielectric layer 22, an input terminal 24A, and an output terminal 24B. At least the +Z plane of the base 21 is conductive. The base 21 may be a metal plate with, for example, a copper layer, a molybdenum layer, and another copper layer laminated together. The base 21 functions as a reference potential terminal to which a reference potential such as ground potential is supplied.

[0021] The semiconductor chip 30 and passive components 35A and 35B are mounted on the base 21, for example, with a conductive bonding layer in between. The dielectric layer 22 is provided on the base 21 so as to sandwich the semiconductor chip 30 and passive components 35A and 35B in the X direction. The dielectric layer 22 is an insulating layer such as ceramics or resin. The dielectric layer 22 may also be a frame surrounding the semiconductor chip 30 and passive components 35A and 35B. A lid that seals the semiconductor chip 30 may be bonded to the frame. The input terminal 24A and output terminal 24B are provided on the dielectric layer 22. The input terminal 24A and output terminal 24B are metal layers such as a copper layer or a gold layer. The input terminal 24A and output terminal 24B correspond to the input terminal Tin and the output terminal Tout, respectively.

[0022] The semiconductor chip 30 includes a semiconductor substrate 31, an input pad 32, an output pad 33, an electrode 34, and a transistor Q. The input pad 32 and the output pad 33 are provided on the upper surface of the semiconductor substrate 31. The electrode 34 is provided on the lower surface of the semiconductor substrate 31. The input pad 32, the output pad 33, and the electrode 34 are electrically connected to the gate G, drain D, and source S of the transistor Q, respectively. The input pad 32 is electrically connected to the input terminal 24A via a passive component 35A. The output pad 33 is electrically connected to the output terminal 24B via a passive component 35B. When the transistor Q is a GaN HEMT, the semiconductor substrate 31 is, for example, a silicon carbide substrate or a sapphire substrate. When the transistor Q is an LDMOS, the semiconductor substrate 31 is, for example, a silicon substrate. The input pad 32, the output pad 33, and the electrode 34 are metal layers such as a gold layer or a copper layer.

[0023] Passive component 35A has a dielectric substrate 36A and electrodes 37A and 38A. Passive component 35B has a dielectric substrate 36B and electrodes 37B and 38B. Electrodes 37A and 37B are provided on the upper surfaces of dielectric substrates 36A and 36B, respectively. Electrodes 38A and 38B are provided on the lower surfaces of dielectric substrates 36A and 36B, respectively. Dielectric substrates 36A and 36B are, for example, alumina substrates or barium titanate substrates. Electrodes 37A, 37B, 38A and 38B are, for example, metal layers such as a gold layer or a copper layer. Dielectric substrate 36A and electrodes 37A and 38A sandwiching dielectric substrate 36A correspond to capacitor C1. Dielectric substrate 36B and electrodes 37B and 38B sandwiching dielectric substrate 36B correspond to capacitor C2. Passive components 35A and 35B may have line patterns in addition to capacitors C1 and C2.

[0024] Bonding wire 41 electrically connects input terminal Tin to electrode 37A. Bonding wire 42 electrically connects electrode 37A to input pad 32. Bonding wire 43 electrically connects output pad 33 to electrode 37B. Bonding wire 44 electrically connects electrode 37B to output terminal 24B. Bonding wires 41 to 44 are thin metal wires, such as gold or aluminum wire. Bonding wires 41 to 44 correspond to inductors L1, L2, L3, and L4, respectively. Bonding wires 43 and 44 are thicker than bonding wires 41 and 42.

[0025] Figure 4 is a plan view of a semiconductor chip in the first embodiment. Figure 5 is a cross-sectional view of AA in Figure 4. Figure 6 is a cross-sectional view of BB in Figure 4. Figure 7 is another cross-sectional view of BB in Figure 4. Figure 4 is a plan view of a part of the semiconductor chip 30. Figures 4 to 7 illustrate the case using a GaN HEMT as an example.

[0026] As shown in Figures 4 to 7, the semiconductor chip 30 has a substrate 10, unit FETs 25, and metal layers 16 and 17. The substrate 10 comprises a substrate 10A and a semiconductor layer 10B provided on the substrate 10A. The region of the semiconductor layer 10B that has been deactivated by ion implantation or the like is the inactive region 11A, and the region that has not been deactivated is the active region 11. A transistor Q is provided in the active region 11. The transistor Q has a plurality of unit FETs 25.

[0027] Transistor Q has multiple source electrodes 12, multiple gate electrodes 13, and multiple drain electrodes 14. The multiple source electrodes 12, multiple gate electrodes 13, and multiple drain electrodes 14 are finger-shaped and extend in the X direction. The multiple source electrodes 12 and multiple drain electrodes 14 are arranged alternately in the Y direction. One source electrode 12 and one drain electrode 14 sandwich one gate electrode 13 in the Y direction.

[0028] The metal layers 16 and 17 sandwich the transistor Q in the X direction. Multiple gate electrodes 13 are connected to the metal layer 16 at their negative ends in the X direction. Multiple drain electrodes 14 are connected to the metal layer 17 at their positive ends in the X direction.

[0029] As shown in Figure 6, the source electrode 12, drain electrode 14, and metal layer 17 each have an ohmic metal layer 54 provided in contact with the substrate 10 and a wiring layer 56 provided in contact with the ohmic metal layer 54. The gate electrode 13 has a gate metal layer 55 provided in contact with the substrate 10. The metal layer 16 has a gate metal layer 55 and a wiring layer 56 provided in contact with the gate metal layer 55.

[0030] As shown in Figure 7, the source electrode 12 and the drain electrode 14 do not necessarily have a wiring layer 56. Also, in Figures 6 and 7, the metal layer 16 does not necessarily have a gate metal layer 55. The metal layer 17 does not necessarily have an ohmic metal layer 54.

[0031] As shown in Figures 5 and 6, a protective film 18 is provided on the substrate 10 so as to cover the unit FET 25, metal layers 16 and 17. The protective film 18 has an opening 18A. The opening 18A exposes the surfaces of the metal layers 16 and 17. The metal layers 16 and 17 exposed through the opening 18A correspond to the input pad 32 and the output pad 33, respectively. The input pad 32 and the output pad are located outside the active region 11.

[0032] As shown in Figure 7, the protective film 18 does not need to cover the tops of the metal layers 16 and 17. The top surfaces of the metal layers 16 and 17 are exposed from the protective film 18. The metal layers 16 and 17 correspond to the input pad 32 and the output pad 33, respectively. As shown in Figures 6 and 7, the width W2 of the output pad 33 in the X direction is greater than the width W1 of the input pad 32 in the X direction.

[0033] As shown in Figures 4 and 5, the via hole 15 penetrates the substrate 10. When viewed from the Z direction, the via hole 15 overlaps with the source electrode 12 and connects to the source electrode 12. A metal layer 19 is provided on the back surface of the substrate 10. A metal layer 19A is provided on the inner surface of the via hole 15. As a result, the metal layer 19 is electrically connected to the source electrode 12 via the via hole 15, and short-circuited. The metal layer 19 corresponds to the electrode 34. The planar shape of the via hole 15 may be elliptical, oblong, rounded rectangle, or circular.

[0034] The source potential (e.g., a reference potential such as ground potential) is supplied from the base 21 to the source electrode 12 via the metal layer 19 and the metal layer 19A in the via hole 15. The gate potential (e.g., a high-frequency signal and gate bias voltage) is supplied from the metal layer 16 to the gate electrode 13. The drain potential (e.g., a drain bias voltage) is supplied from the metal layer 17 to the drain electrode 14. The amplified high-frequency signal in transistor Q is output from the drain electrode 14 to the output pad 33.

[0035] The substrate 10A is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10B has a gallium nitride channel layer provided on the substrate 10A and an aluminum gallium nitride barrier layer provided on the channel layer.

[0036] The ohmic metal layer 54 is, for example, a titanium film and an aluminum film from the substrate 10 side. The gate metal layer 55 is, for example, a nickel film and a gold film from the substrate 10 side. The wiring layer 56 is a metal layer such as a gold layer, a copper layer or an aluminum layer. The protective film 18 is an insulating layer, and is an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer. The protective film 18 may also include an inorganic insulating layer such as a silicon oxide film or a silicon nitride film.

[0037] As shown in Figures 6 and 7, the first end of bonding wire 42 is joined to the input pad 32. The first end of bonding wire 43 is joined to the output pad 33. The joint portion 46 of bonding wire 42 to the input pad 32 is hemispherical and larger than the diameter D1 of bonding wire 42. The joint portion 47 of bonding wire 43 to the output pad 33 is hemispherical and larger than the diameter D2 of bonding wire 43. The region where bonding wire 42 is joined to the input pad 32 is region 46A. The region where bonding wire 43 is joined to the output pad 33 is region 47A. As shown in Figure 4, region 46A is arranged in the Y direction, and region 47A is arranged in the Y direction.

[0038] (Comparison Form 1) Figure 8 is a plan view of the semiconductor device 110 near the semiconductor chip 30 according to comparative form 1. In the semiconductor device 110 of comparative form 1, the diameter D1 of bonding wire 42 and the diameter D2 of bonding wire 43 are equal. The width W1 of input pad 32 in the X direction and the width W2 of output pad 33 in the X direction are equal. The widths W1 and W2 are determined by the diameters D1 and D2. For example, if the diameters D1 and D2 are 25 μm, the widths W1 and W2 will be 90 μm or more. The width W3 of semiconductor chip 30 in the X direction is determined by considering the width of transistor Q in the X direction and the widths W1 and W2.

[0039] In a high-power amplifier circuit 108, the power of the output signal is large, making the bonding wire 43 prone to melting. When the output power increases, the current density within the bonding wire 43 increases. Conductive losses in the bonding wire 43 cause the bonding wire 43 to heat up. If the diameter D2 of the bonding wire 43 is small, heat does not conduct easily within the bonding wire 43. As a result, the temperature of the bonding wire 43 rises in the central part along its length, making the bonding wire 44 prone to melting.

[0040] (Comparison Form 2) Figure 9 is a plan view of the semiconductor device 112 near the semiconductor chip 30 according to comparative form 2. In the semiconductor device 112 of comparative form 2, the diameter D1 of the bonding wire 42 and the diameter D2 of the bonding wire 43 are thicker than in comparative form 1. As a result, even with the same output power, the electrical resistance in the bonding wire 43 is lower than in comparative form 1. For example, if the diameter D2 is doubled, the electrical resistance per unit length becomes 1 / 4. Although the skin effect occurs with high-frequency signals, if the current flows on the surface of the bonding wire 43, if the diameter D2 is doubled, the electrical resistance per unit length becomes 1 / 2. Thus, when the diameter D2 is doubled, the electrical resistance becomes 1 / 4 to 1 / 2, and the voltage drop per unit length and the associated Joule heat also become 1 / 4 to 1 / 2. In addition, when the diameter D2 is doubled, the thermal resistance becomes 1 / 4. As a result, in comparative form 2, the temperature rise of the bonding wire 43 is reduced compared to comparative form 1, preventing the bonding wire 43 from melting. Increasing the diameter D2 increases the spacing D3 of the bonding wires 43 in the Y direction. However, even if the diameter D2 doubles, the spacing D3 is less than or equal to double, and the current flowing through each bonding wire 43 is less than or equal to double. On the other hand, the electrical resistance per unit length becomes 1 / 4 to 1 / 2, and the thermal resistance becomes 1 / 4. Therefore, even considering the increase in spacing D3, the temperature rise of the bonding wire 43 can be reduced in comparative form 2.

[0041] However, if the bonding wires 42 and 43 are made thicker, the width W1 of the input pad 32 in the X direction and the width W2 of the output pad 33 in the X direction will increase. For example, if the diameters D1 and D2 are 50 μm, the widths W1 and W2 will be 160 μm or more. As a result, the width W3 of the semiconductor chip 30 in the X direction will be larger than that of comparative form 1. The manufacturing process of the semiconductor chip 30 is complex, and the manufacturing cost per unit area of ​​the semiconductor chip 30 is high. As a result, the cost of the semiconductor device 112 will increase.

[0042] (Description of the first embodiment) Figure 10 is a plan view of the semiconductor chip 30 vicinity of the semiconductor device 100 according to the first embodiment. As shown in Figure 10, in the semiconductor device 100 of the first embodiment, the diameter D1 of the bonding wire 42 is smaller than the diameter D2 of the bonding wire 43. When the diameter D1 of the bonding wire 42 is made smaller, the inductance and resistance of the source S increase, so the gain decreases slightly, but the decrease in gain is limited. The efficiency and maximum power remain almost unchanged even when the diameter D1 is made smaller.

[0043] By making the bonding wire 43 thicker, the temperature rise of the bonding wire 43 can be reduced compared to comparative form 1, and the melting of the bonding wire 43 can be prevented. By making the bonding wire 42 thinner, the width W1 of the input pad 32 in the X direction can be made smaller than the width W2 of the output pad 33 in the X direction, and the width W3 of the semiconductor chip 30 in the X direction can be made smaller than in comparative form 2. Therefore, the cost of the semiconductor device 100 can be reduced.

[0044] The diameters D1 of the bonding wires 42 are the same, but the diameters D1 may vary unintentionally. Also, the diameters D1 may be intentionally changed. The diameters D2 of the bonding wires 43 are the same, but the diameters D2 may vary unintentionally. Also, the diameters D2 may be intentionally changed. In such cases, the diameter of the thickest bonding wire 42A among the bonding wires 42 is set to D1A. In the semiconductor device 100 of the first embodiment, the diameters D2 of all bonding wires 43 are greater than the diameter D1A.

[0045] (Modification 1 of the first embodiment) Figure 11 is a plan view of the area around the semiconductor chip 30 of the semiconductor device 102 according to Modification 1 of the First Embodiment. As shown in Figure 11, in the semiconductor device 102 of Modification 1 of the First Embodiment, bonding wires 43A and 43B are bonded to the output pad 33. The diameter D2A of bonding wire 43A is larger than the diameter D2B of bonding wire 43B. Diameter D2A is larger than diameter D1A. Diameter D2B may be the same as diameter D1A, smaller than diameter D1A, or larger than diameter D1A. The other configurations are the same as those of the semiconductor device 100 of the First Embodiment, and their description is omitted.

[0046] (Modification 2 of the first embodiment) Figure 12 is a plan view of the area around the semiconductor chip 30 of the semiconductor device 104 according to Modification 2 of the First Embodiment. As shown in Figure 12, the semiconductor device 104 of Modification 2 of the First Embodiment is provided with output pads 33A and 33B. A bonding wire 43A is bonded to output pad 33A. A bonding wire 43B is bonded to output pad 33B. The width W2B of output pad 33B in the X direction is smaller than the width W2A of output pad 33A in the X direction. The width W2B may be the same as the width W1, smaller than the width W1, or larger than the width W1. The other configurations are the same as the semiconductor device 102 of Modification 1 of the First Embodiment, and their description is omitted.

[0047] According to the first embodiment and its modified form, as shown in Figures 11 and 12, the bonding wire 42A (first input bonding wire) is the thickest of the bonding wires 42 (input bonding wires). The bonding wire 43A (first output bonding wire) is thicker than the bonding wire 42A among the bonding wires 43A and 43B (output bonding wires). In this way, by providing a thicker bonding wire 43A compared to comparative embodiment 1, the melting and breaking of the bonding wire 43A can be reduced.

[0048] Furthermore, as shown in Figures 11 and 12, the width W2 (or W2A) of the output pad 33 (or 33A) to which at least one bonding wire 43A is joined is greater than the width W1 of the input pad 32. This allows the width W1 of the input pad 32 to be reduced compared to comparative form 2, thus enabling miniaturization of the semiconductor chip 30.

[0049] If the width of the input pad 32 in the X direction differs from that in the Y direction, then width W1 is the widest width of the input pad 32 in the area where the bonding wire 42 is joined. If the width of the input pad 32 in the X direction differs from that in the Y direction, then width W2 (or W2A) is the width of the output pad 33 or 33A in the X direction in the area where at least one of the bonding wires 43A is joined (corresponding to area 47A in Figure 4).

[0050] The bonding wire 42 may be one or multiple. If the bonding wires 42 are of the same thickness, the thickest bonding wire 42A will correspond to all of the bonding wires 42. The bonding wire 42A may be one or multiple of the bonding wires 42.

[0051] The bonding wire 43 may be one or multiple. At least one of the bonding wires 43 (or 43A and 43B) must be thicker than the bonding wire 42A. From the viewpoint of increasing the number of bonding wires 43A that prevent cutting, the number of bonding wires 43A can be more than half the total number of bonding wires 43A and 43B, can be 7 / 10 or more, and can be 9 / 10 or more.

[0052] From the viewpoint of preventing the bonding wire 43 or 43A from melting, the diameter D2 or D2A of the bonding wire 43 or 43A can be 1.1 times or more, 1.2 times or more, or 1.5 times or more of the diameter D1. From the viewpoint of miniaturizing the semiconductor chip 30, the width W2 or W2A can be 1.1 times or more, 1.2 times or more, or 1.5 times or more of the width W1.

[0053] As shown in Figure 10, all bonding wires 43 are thicker than bonding wire 42A. This prevents all bonding wires 43 from being cut.

[0054] As shown in Figures 10 to 12, in all regions where the bonding wire 43A is joined, the width W2 or W2A of the output pad 33 or 33A is greater than the width W1. This allows for a smaller semiconductor chip 30.

[0055] In Figures 2 and 3, the passive components 35A and 35B are not required. The second end of the bonding wire 42 may be connected to the input terminal 24A. The second end of the bonding wire 43 may be connected to the output terminal 24B.

[0056] The first end of the bonding wire 44 (second output bonding wire) is joined to the electrode 37B of the passive component 35B (first passive component), and the second end of the bonding wire 44 is joined to the output terminal 24B. At least one of the bonding wires 44 may be thicker than the bonding wire 42A. This prevents the bonding wire 44 from melting or breaking.

[0057] From the standpoint of preventing the bonding wires 44 from melting, the number of bonding wires 44 that are thicker than bonding wire 42A can be greater than half the total number of bonding wires 44. All bonding wires 44 can be thicker than bonding wire 42A.

[0058] The first end of the bonding wire 41 (second input bonding wire) is joined to the electrode 37A of the passive component 35A (second passive component), and the second end of the bonding wire 41 is joined to the input terminal 24A. The bonding wire 43A is thicker than the thickest bonding wire 41. This prevents the bonding wire 43 from melting.

[0059] Some of the bonding wires 43 joined to the output pad 33 may be shunt-connected to the output path that electrically connects the output pad 33 and the output terminal 24B. The current flowing through the shunt path is smaller than the current flowing through the output path. Therefore, at least one of the bonding wires 43A is provided in the output path. This prevents the bonding wires 43A provided in the output path from melting.

[0060] All bonding wires 43 provided in the output path are thicker than bonding wire 42A. This prevents the bonding wires 43 provided in the output path from melting or breaking.

[0061] Furthermore, the bonding wire 44 is connected in series with the bonding wire 43A in the output path. In such cases, at least one of the bonding wires 44 is made thicker than the bonding wire 42A. This prevents the bonding wire 44 in the output path from melting.

[0062] As shown in Figures 5 to 7, the input pad 32 is the region of the metal layer 16 connected to the gate electrode 13 (input electrode) that is outside the active region 11 of transistor Q and exposed from the protective film 18 covering transistor Q. The output pad 33 is the region of the metal layer 17 connected to the drain electrode 14 (output electrode) that is outside the active region 11 and exposed from the protective film 18. This allows for a smaller semiconductor chip 30.

[0063] As shown in Figure 4, the semiconductor chip 30 has opposing first and second sides. Multiple regions 46A, to which multiple bonding wires 42 are bonded to the input pad 32, are provided along the first side of the semiconductor chip 30. Multiple regions 47A, to which multiple bonding wires 43 are bonded to the output pad 33, are provided along the second side. In such a structure, a large current flows through the bonding wires 43. Therefore, by making the bonding wires 43 thicker than the bonding wires 42A, the melting of the bonding wires 43 can be prevented. The width W1 of the input pad 32 is the width of the input pad 32 in the direction perpendicular to the first side (i.e., the X direction). The widths W2, W2A, and W2B of the output pads 33, 33A, and 33B are the widths of the output pads 33, 33A, and 33B in the direction perpendicular to the second side (i.e., the X direction). This allows the semiconductor chip 30 to be made smaller.

[0064] The thickness of bonding wires 41 to 44 is the width of bonding wires 41 to 44 in a direction perpendicular to the extension direction of bonding wires 41 to 44 when viewed from the Z direction. If the cross-section of bonding wires 41 to 44 is circular, the thickness of bonding wires 41 to 44 is the diameter of the cross-section of bonding wires 41 to 44.

[0065] When the output power of amplifier 50 is high, bonding wires 43 and 44 are prone to melting. Therefore, inductors L1 and L2 and capacitors C1 and C2 are provided when the maximum output power of amplifier 50 is 5W or more, 50W or more, or 100W or more.

[0066] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications in the sense and scope equivalent to the claims are intended. [Explanation of Symbols]

[0067] 10, 10A circuit board 10B Semiconductor layer 11 Active area 11A Inactive area 12 Source electrodes 13 gates 14 Drain electrode 15 Beer Hall 16, 17, 19 metal layer 18 Protective film 18A aperture 20 packages 21 Base 22 Dielectric layer 24A Input Terminal 24B Output Terminal 25 Unit FET 30 semiconductor chips 31 Semiconductor substrates 32 Input Pads 33, 33A, 33B output pads 34, 37A, 37B, 38A, 38B electrode Bonding wires: 41 (2nd input bonding wire), 42 (input bonding wire), 42A (1st input bonding wire), 43 (output bonding wire), 43A (1st output bonding wire), 43B (output bonding wire), 44 (2nd output bonding wire) 46, 47 joint 46A, 47A area 50 Amplifier 51, 52 matching circuit 54 Ohmic metal layer 55 Gate metal layer 56 wiring layer 100, 102, 104, 110, 112 Semiconductor equipment 108 Amplifier Circuit D1,D1A,D2,D2A,D2B diameter W1, W2, W2A, W2B, W3 width

Claims

1. A semiconductor chip having an amplifier, an input pad for the amplifier provided on its upper surface, and an output pad for the amplifier provided on its upper surface, An input bonding wire, the first end of which is joined to the input pad, An output bonding wire, the first end of which is joined to the output pad, Equipped with, The first input bonding wire is the thickest of the input bonding wires, The width of the output pad in the region where at least one of the output bonding wires, which is thicker than the first input bonding wire, is joined is greater than the widest width of the input pad in the region where the input bonding wire is joined. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the number of first output bonding wires is greater than half the total number of output bonding wires.

3. The semiconductor device according to claim 1, wherein all of the output bonding wires are thicker than the first input bonding wires.

4. The semiconductor device according to any one of claims 1 to 3, wherein in all regions to which the first output bonding wire is bonded, the width of the output pad is greater than the largest width.

5. The output pad is equipped with an output terminal that is electrically connected to the output pad, The semiconductor device according to any one of claims 1 to 3, wherein at least one of the first output bonding wires is provided in an output path that electrically connects the output pad and the output terminal.

6. The semiconductor device according to claim 5, wherein all of the output bonding wires provided in the output path are thicker than the first input bonding wire.

7. The semiconductor device according to claim 5, wherein the output path includes a second output bonding wire connected in series with at least one of the output bonding wires, and at least one of the second output bonding wires is thicker than the first input bonding wire.

8. A base on which the aforementioned semiconductor chip is mounted, The first passive component mounted on the aforementioned base, Equipped with, The second end of the first output bonding wire is joined to the first passive component. The semiconductor device according to claim 7, wherein the first end of the second output bonding wire is joined to the first passive component, and the second end of the second output bonding wire is joined to the output terminal.

9. A base on which the aforementioned semiconductor chip is mounted, The second passive component mounted on the aforementioned base, An input terminal electrically connected to the aforementioned input pad, A second input bonding wire, the first end of which is joined to the second passive component and the second end of which is joined to the input terminal, Equipped with, The second end of the first input bonding wire is joined to the second passive component. The semiconductor device according to any one of claims 1 to 3, wherein at least one of the output bonding wires is thicker than any of the second input bonding wires.

10. The amplifier has a transistor having an input electrode and an output electrode, The input pad is a region of the metal layer electrically connected to the input electrode that is outside the active region of the transistor and exposed from the protective film covering the transistor. The semiconductor device according to any one of claims 1 to 3, wherein the output pad is a region of the metal layer electrically connected to the output electrode that is outside the active region and exposed from the protective film.

11. The upper surface of the semiconductor chip has opposing first and second sides. The plurality of regions to which the input bonding wire is joined to the input pad are provided along the first side, The plurality of regions to which the output bonding wire is joined to the output pad are provided along the second side, The largest width is the largest width of the input pad in a direction perpendicular to the extension direction of the first side. The semiconductor device according to any one of claims 1 to 3, wherein the width of the output pad is the width of the output pad in a direction perpendicular to the extension direction of the second side.

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