Semiconductor memory

Abstract

To provide a semiconductor memory device that operates optimally. [Solution] The semiconductor memory device comprises a plurality of semiconductor layers stacked in the stacking direction and extended in a first direction, a plurality of conductive layers extended in a second direction and connected to the ends of the plurality of semiconductor layers in the first direction, a plurality of via electrodes aligned in the first direction along the sides of the plurality of semiconductor layers in the second direction and having a diameter that increases from a first position to a second position in the stacking direction, and a plurality of charge storage layers provided between the plurality of semiconductor layers and the plurality of via electrodes. Furthermore, at the first timing of the program operation, a first voltage or a second voltage greater than the first voltage is supplied to a plurality of first conductive layers provided in the range from a first position to a third position in the stacking direction, and a third voltage greater than the first voltage and less than the second voltage, or a fourth voltage greater than the third voltage is supplied to a plurality of second conductive layers provided in the range from a second position to a fourth position in the stacking direction, while a program voltage is supplied to one via electrode.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that comprises a plurality of semiconductor layers stacked in the stacking direction and stretched in a first direction intersecting the stacking direction, a plurality of via electrodes aligned in the first direction and stretched in the stacking direction, facing the plurality of semiconductor layers, and a plurality of charge storage layers provided between the plurality of semiconductor layers and the plurality of first via electrodes. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-076886 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that operates optimally. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment comprises: a plurality of semiconductor layers stacked in the stacking direction and stretched in a first direction intersecting the stacking direction; a plurality of conductive layers stacked in the stacking direction corresponding to the plurality of semiconductor layers, stretched in a second direction intersecting the stacking direction and the first direction, and connected to the ends of the plurality of semiconductor layers in the first direction; a plurality of via electrodes aligned in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, stretched in the stacking direction, facing the plurality of semiconductor layers, and having a diameter that increases from a first position to a second position in the stacking direction; and a plurality of charge storage layers provided between the plurality of semiconductor layers and the plurality of via electrodes. In this semiconductor memory device, at the first timing of a program operation to store charge in a portion of multiple charge storage layers, a first voltage or a second voltage greater than the first voltage is supplied to multiple first conductive layers located in the range from a first position in the stacking direction to a third position between the first and second positions, and a third voltage greater than the first voltage and less than the second voltage, or a fourth voltage greater than the third voltage, is supplied to multiple second conductive layers located in the range from a second position in the stacking direction to a fourth position between the second and third positions, while a first program voltage is supplied to one of the multiple via electrodes. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic perspective view showing a part of the configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic circuit diagram showing a portion of the configuration of the memory cell array layer (LMCA). [Figure 3] This is a schematic plan view showing a portion of the configuration of the memory cell array layer (LMCA). [Figure 4] This is a schematic cross-sectional view showing a portion of the configuration of the memory cell array layer (LMCA). [Figure 5] This is a schematic diagram illustrating the threshold voltage of a memory cell (MC) that records 3 bits of data. [Figure 6] This is a flowchart illustrating the overview of the write operation. [Figure 7]This is a schematic circuit diagram intended to illustrate the general operation of the program. [Figure 8] This is a schematic circuit diagram illustrating the verification operation. [Figure 9] This is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the first embodiment. [Figure 10] This is a schematic circuit diagram illustrating the writing operation according to the first embodiment. [Figure 11] This is a schematic waveform diagram illustrating an example of a write operation according to the first embodiment. [Figure 12] This is a schematic waveform diagram illustrating another example of the writing operation according to the first embodiment. [Figure 13] This is a schematic histogram illustrating the effects of the writing operation according to the first embodiment. [Figure 14] This is a schematic histogram illustrating the effects of the writing operation according to the first embodiment. [Figure 15] This is a schematic circuit diagram showing a partial configuration example of the peripheral circuit of a semiconductor memory device according to the first embodiment. [Figure 16] This is a schematic circuit diagram showing a partial configuration example of the peripheral circuit of a semiconductor memory device according to the first embodiment. [Figure 17] This is a schematic waveform diagram illustrating an example of a writing operation according to the second embodiment. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0013] Furthermore, in this specification, the direction along a predetermined plane may be referred to as the first direction, the direction intersecting the first direction along this predetermined plane may be referred to as the second direction, and the direction intersecting this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0015] [First Embodiment] [composition] Figure 1 is a schematic perspective view showing a part of the configuration of a semiconductor memory device according to the first embodiment. The semiconductor memory device according to this embodiment includes a semiconductor substrate Sub and a memory cell array layer L provided above the semiconductor substrate Sub. MCA It is equipped with the following.

[0016] The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B). On the upper surface of the semiconductor substrate Sub is a memory cell array layer L. MCA Peripheral circuits are provided to control the internal configuration.

[0017] Memory cell array layer L MCA It comprises multiple memory layers ML and multiple insulating layers 101 that are alternately stacked in the Z direction. The insulating layers 101 include, for example, silicon oxide (SiO2).

[0018] [Memory cell array layer L MCA [Configuration] Figure 2 shows the memory cell array layer L MCA This is a schematic circuit diagram showing a part of the configuration.

[0019] Memory cell array layer L according to this embodiment MCA This functions as a memory cell array MCA. The memory cell array MCA comprises multiple string units SU. Each string unit SU comprises multiple memory units MU, which correspond to multiple memory layers ML. Each of the multiple memory units MU comprises two memory strings MS. Each of these two memory strings MS comprises multiple memory cells MC (memory transistors) connected in series. One end of these two memory strings MS is connected to the bit line BL via a common drain-side selection transistor STD. The other end of these two memory strings MS is connected to the source line SL via a common source-side selection transistor STS. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may simply be referred to as selection transistors STD and STS.

[0020] A memory cell MC is a field-effect transistor. The memory cell MC comprises a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating layer includes a charge storage layer. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage layer. The memory cell MC stores one or more bits of data. Each gate electrode of multiple memory cell MCs contained within a single memory unit MU is connected to a word line WL. These word lines WL are each commonly connected to all memory units MU in multiple string units SU.

[0021] The selection transistors STD and STS are field-effect transistors. The selection transistors STD and STS include a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. Selection gate lines SGD and SGS are respectively connected to the gate electrodes of the selection transistors STD and STS. The drain-side selection gate line SGD is commonly connected to all the memory units MU in the corresponding string unit SU. The source-side selection gate line SGS is commonly connected to all the memory units MU in the corresponding string unit SU.

[0022] FIG. 3 is a schematic plan view showing a partial configuration of the memory cell array layer L MCA FIG. 4 is a schematic cross-sectional view showing a partial configuration of the memory cell array layer L MCA FIG. 4 shows a view obtained by cutting the structure shown in FIG. 3 along the line A-A' and viewing it along the direction of the arrow.

[0023] The memory cell array layer L MCA comprises bit line regions R arranged in order in the Y direction as shown in FIG. 3 BL , selection transistor regions R SGD , memory cell regions R MC , selection transistor regions R SGS , and source line regions R SL .

[0024] The memory layer ML includes a plurality of semiconductor layers 1,10 arranged in the X direction and extending in the Y direction. These plurality of semiconductor layers 1,10 respectively extend in the Y direction across the selection transistor regions R SGD , memory cell regions R MC , selection transistor regions R SGS , and source line regions R SL and reach the bit line regions R BL . The semiconductor layers are, for example, a plurality of memory cells MC (FIG. 2) connected in series and function as the channel regions of the selection transistors STD and STS connected thereto. The semiconductor layers may include, for example, undoped polycrystalline silicon (Si) or the like.

[0025] An insulating layer 111 is provided between two semiconductor layers 110 aligned in the X direction. The insulating layer 111 may contain, for example, silicon oxide (SiO2). The insulating layer 111 extends in the Z direction, penetrating multiple memory layers ML, as shown in Figure 1, for example.

[0026] Memory cell region R MC In this region, multiple via electrodes 120 are provided, arranged in the Y direction along one side and the other side of the semiconductor layer 110 in the X direction. MC In this configuration, the memory layer ML comprises a plurality of gate insulating layers 130 provided between a plurality of via electrodes 120 and a semiconductor layer 110.

[0027] A portion of the outer surface of the via electrode 120 faces the semiconductor layer 110 via the gate insulating layer 130, and the remaining portion faces the insulating layer 111. In the illustrated example, the outer surface of the via electrode 120 follows a circle concentric with the via electrode 120. Similarly, the contact surface of the gate insulating layer 130 with the semiconductor layer 110 also follows a circle concentric with the via electrode 120.

[0028] The via electrode 120 functions, for example, as the gate electrode of multiple memory cells MC and the word line WL connected thereto. The via electrode 120 may include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W). The via electrode 120 extends in the Z direction, penetrating multiple memory layers ML, as shown in Figure 1, for example.

[0029] As shown in Figure 4, the gate insulating layer 130 includes, for example, a tunnel insulating layer 131 provided on the X-direction side of the semiconductor layer 110, a charge storage layer 132 provided on the X-direction side, and a block insulating layer 133 provided on the X-direction side.

[0030] The tunnel insulating layer 131 may contain, for example, silicon oxide (SiO2).

[0031] The charge storage layer 132 may contain, for example, polycrystalline silicon (Si). Furthermore, this polycrystalline silicon (Si) may contain N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may not contain these impurities.

[0032] The block insulating layer 133 may contain, for example, silicon oxide (SiO2). Alternatively, the block insulating layer 133 may contain aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films (high dielectric constant insulating films).

[0033] Selected transistor region R SGD Figure 3 shows a plurality of via electrodes 140 arranged in the Y direction along one side surface in the X direction of the semiconductor layer 110, and a via wiring 150 provided on the opposite side of the center line CL from these plurality of via electrodes 140. Also, a selected transistor region R SGD In this configuration, the memory layer ML comprises a semiconductor layer 160 connected to one end in the Y direction of a plurality of semiconductor layers 110.

[0034] The center line CL referred to here is the center line of the semiconductor layer 110 in the XY cross-section. The center line CL is a hypothetical straight line extending in the Y direction. The position of the center line CL in the X direction can be defined, for example, by the average value of the central positions in the X direction of multiple via electrodes 120 facing one side surface of the semiconductor layer 110 in the X direction, and the average value of the central positions in the X direction of multiple via electrodes 120 facing the other side surface of the semiconductor layer 110 in the X direction.

[0035] A portion of the outer surface of the via electrode 140 faces the semiconductor layer 110, and the remaining portion faces the insulating layer 111. The surface of the via electrode 140 facing the semiconductor layer 110 is aligned with a circle concentric with the via electrode 140.

[0036] Selected transistor region R SGDThe via electrode 140 inside functions, for example, as the gate electrode of a plurality of drain-side selection transistors STD, and the drain-side selection gate line SGD connected thereto. The via electrode 140 may include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W). The via electrode 140 extends in the Z direction, penetrating a plurality of memory layers ML. In addition, an insulating layer 142 such as silicon oxide (SiO2) or aluminum oxide (Al2O3) is provided on the outer circumferential surface of the via electrode 140.

[0037] The via wiring 150 functions, for example, as contact wiring for supplying holes to the semiconductor layer 110. The via wiring 150 may include, for example, polycrystalline silicon (Si) containing P-type impurities such as boron (B), and may include a semiconductor column formed in a cylindrical or cylindrical shape. This semiconductor column may also be in contact with a plurality of semiconductor layers 110 stacked in the Z direction. The via wiring 150 extends in the Z direction, penetrating a plurality of memory layers ML.

[0038] The semiconductor layer 160 may include, for example, a semiconductor layer such as polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P), and may be in contact with the semiconductor layer 110.

[0039] Bit line region R BL In Figure 3, the memory layer ML includes a conductive layer 170. Also, the bit line region R BL The conductive layer 170 is provided with a plurality of insulating layers 171 arranged in the X direction.

[0040] The conductive layer 170 functions, for example, as a bit line BL (Figure 2). The conductive layer 170 may contain, for example, titanium nitride (TiN). The conductive layer 170 is stretched in the X direction and is electrically connected to a plurality of semiconductor layers 110 via a plurality of semiconductor layers 160.

[0041] The insulating layer 171 may contain, for example, silicon oxide (SiO2). The insulating layer 171 extends in the Z direction, penetrating multiple memory layers ML.

[0042] Selected transistor region R SGS Figure 3 shows a plurality of via electrodes 140 arranged in the Y direction along one side of the semiconductor layer 110 in the X direction, and a via wiring 150 provided on the opposite side of the center line CL from these plurality of via electrodes 140.

[0043] Selected transistor region R SGS The via electrode 140 inside functions, for example, as the gate electrode of multiple source-side selection transistors STS, and the source-side selection gate line SGS connected thereto.

[0044] Source line region R SL A via wiring 180 is provided there.

[0045] The via wiring 180 functions, for example, as a source wire SL. The via wiring 180 may contain, for example, polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P), and may include a semiconductor column formed in a cylindrical or cylindrical shape. This semiconductor column may also be in contact with a plurality of semiconductor layers 110 stacked in the Z direction. The via wiring 180 extends in the Z direction, penetrating a plurality of memory layers ML.

[0046] [Threshold voltage of memory cell MC] Next, with reference to Figure 5, the threshold voltage of the memory cell MC will be explained.

[0047] Figure 5(a) is a schematic histogram illustrating the threshold voltage of a memory cell MC that records 3 bits of data. The horizontal axis shows the voltage of the word line WL, and the vertical axis shows the number of memory cell MCs. Figure 5(b) is a table showing an example of the relationship between the threshold voltage of a memory cell MC that records 3 bits of data and the data recorded.

[0048] In the example shown in Figure 5(a), the threshold voltage of the memory cell MC is controlled to eight different states. The threshold voltage of the memory cell MC controlled to the Er state is the erase verify voltage V VFYErSmaller. The threshold voltage of a memory cell MC controlled to state A is the verify voltage V VFYA Larger verify voltage V VFYB Smaller. The threshold voltage of a B-state controlled memory cell MC is the verify voltage V VFYB Larger verify voltage V VFYC Smaller. Similarly, the threshold voltages of memory cells MC controlled to C state ~ F state are, respectively, the verify voltage V VFYC ~Verify voltage V VFYF Larger verify voltage V VFYD ~Verify voltage V VFYG Smaller. The threshold voltage of a G-state controlled memory cell MC is the verify voltage V VFYG Larger read path voltage V READ Smaller.

[0049] Furthermore, in the example in Figure 5(a), there is a readout voltage V between the threshold distribution corresponding to the Er state and the threshold distribution corresponding to the A state. CGAR This is set. Also, between the threshold distribution corresponding to state A and the threshold distribution corresponding to state B, the read voltage V CGBR The following is set. Similarly, between the threshold distribution corresponding to state B and the threshold distribution corresponding to state C, and between the threshold distribution corresponding to state F and the threshold distribution corresponding to state G, the read voltage V is set. CGCR ~Readout voltage V CGGR It is set.

[0050] For example, the Er state corresponds to the lowest threshold voltage. A memory cell MC in the Er state is a memory cell MC in the erased state. A memory cell MC in the Er state might be assigned the data "111".

[0051] State A corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state described above. For example, the memory cell MC in State A is assigned the data "101".

[0052] Furthermore, the B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the A state described above. For example, the memory cell MC in the B state is assigned the data "001".

[0053] Similarly, in the diagram, states C through G correspond to threshold voltages higher than those corresponding to states B through F. The memory cells MC in these states are assigned data such as "011", "010", "110", "100", and "000".

[0054] In the case of the allocation shown in Figure 5(b), the lower bits of data are read at a single read voltage V CGDR This can be determined by the three read voltages V. CGAR ,V CGCR ,V CGFR This can be determined by the three read voltages V. The data of the higher bits is determined by the three read voltages V. CGBR ,V CGER ,V CGGR This can be determined by [the method used].

[0055] Furthermore, the number of bits of data recorded in the memory cell MC, the number of states, and the data assignment to each state can be changed as appropriate.

[0056] [Overview of writing operations] Next, we will explain the overview of the write operation. The write operation is performed on multiple memory cells (MCs) in the erase state (Er state). When the write operation is performed, these multiple memory cells (MCs) are controlled to one of the states from Er state to G state, depending on the data to be written.

[0057] Figure 6 is a flowchart illustrating the overview of the write operation.

[0058] In step S101, the number of loop iterations is n. W This is set to 1. Loop count n W This variable indicates the number of write loop iterations.

[0059] In step S102, a program operation is executed. The program operation is the selection of the word line WL. S This operation involves supplying a program voltage to the memory cell MC, causing charge to accumulate in the charge storage layer 132, and thereby increasing the threshold voltage of the memory cell MC.

[0060] In step S103, a verification operation is performed. The verification operation is performed on the selected word line WL. S The verify voltage (for example, the verify voltage V explained in Figure 5) VFYA ,V VFYB ,V VFYC ,V VFYD ,V VFYE ,V VFYF ,V VFYG This operation involves supplying one of the following (either) to detect the ON / OFF state of the memory cell MC and to determine whether the threshold voltage of the memory cell MC has reached the target value.

[0061] In step S104, the result of the verification operation is determined. For example, if the number of memory cells (MCs) whose threshold voltage has not reached the target value is greater than a certain number, the verification is determined to be FAIL and the process proceeds to step S105. On the other hand, if the number of memory cells (MCs) whose threshold voltage has not reached the target value is less than a certain number, the verification is determined to be PASS and the process proceeds to step S107.

[0062] In step S105, the number of loop iterations is n. W a predetermined number of times N W Determine whether the condition has been met. If it has not been met, proceed to step S106. If it has been met, proceed to step S108.

[0063] In step S106, the number of loop iterations is n. W Add 1 to it and proceed to step S102. Also, in step S106, for example, the program voltage V PGM A predetermined voltage ΔV is added to it. Therefore, the program voltage V PGM The number of loop iterations is n. W It increases along with the increase of [something].

[0064] In step S107, status data indicating that the write operation was completed successfully is stored in a register, and the write operation is terminated.

[0065] In step S108, status data indicating that the write operation did not complete successfully is stored in a register, and the write operation is terminated.

[0066] [Overview of program operation] Figure 7 is a schematic circuit diagram illustrating the general operation of the program.

[0067] In program operation, multiple memory cells MC connected to a single word line WL within a single string unit SU become selected memory cells MC. Hereafter, such a single word line WL will be referred to as "selected word line WL". S They call this "" and the remaining word lines WL "unselected word lines WL" U It is sometimes called "..."

[0068] In the program operation, for example, an electric field is generated between the control gate electrode and the channel in some of the multiple selective memory cells MC, causing electrons in the channel of the semiconductor layer 110 to tunnel into the charge storage layer 132 (Figure 4), thereby increasing the threshold voltage of these selected memory cells MC.

[0069] Hereafter, among the selected memory cells (MCs), those that increase the threshold voltage will be referred to as "write memory cells (MCs)." Also, the bit line BL connected to the write memory cell MC will be referred to as the bit line BL. W This is called a "selected memory cell MC" if it does not increase the threshold voltage. Furthermore, a bit line BL connected to a prohibited memory cell MC is called a "bit line BL". P It is called that.

[0070] In program operation, for example, bit line BL W Voltage V SRC It supplies bit lines BL. PSupply voltage V DD to it. Voltage V DD is greater than voltage V SRC .

[0071] Also, in the program operation, voltage V SGD is supplied to the drain-side selection gate line SGD corresponding to the string unit SU targeted by the program operation, and voltage V OFF is supplied to the other drain-side selection gate lines SGD.

[0072] Voltage V SGD is greater than voltage V SRC . Also, the voltage difference between voltage V SGD and voltage V SRC is greater than the threshold voltage when the drain-side selection transistor STD functions as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain-side selection transistor STD connected to the bit line BL W , and voltage V SRC is transferred.

[0073] On the other hand, the voltage difference between voltage V SGD and voltage V DD is smaller than the threshold voltage when the drain-side selection transistor STD functions as an NMOS transistor. Therefore, the drain-side selection transistor STD connected to the bit line BL P is in the OFF state.

[0074] Voltage V OFF has a magnitude such that the drain-side selection transistor STD is in the OFF state regardless of the voltage of the bit line BL. Voltage V OFF may have, for example, a negative magnitude.

[0075] Also, in the program operation, voltage V SRC is supplied to the source line SL, and the ground voltage V SS is supplied to the source-side selection gate line SGS. Here, voltage V SRC and the ground voltage V SSThe voltage difference between them is smaller than the threshold voltage when the source-side selection gate line SGS functions as an NMOS transistor. Therefore, the source-side selection transistor STS is in the OFF state.

[0076] Also, in the program operation, the non-selected word line WL U is supplied with a write path voltage V PASS The write path voltage V PASS may be larger than the read path voltage V READ described with reference to FIG. 5, or may be of the same level as the read path voltage V READ The voltage difference between the write path voltage V PASS and the voltage V SRC is larger than the threshold voltage when the memory cell MC functions as an NMOS transistor regardless of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC electrically connected to the bit line BL W , and the voltage V SRC is transferred to the write memory cell MC.

[0077] Also, in the program operation, the selected word line WL S is supplied with a program voltage V PGM The program voltage V PGM is larger than the write path voltage V PASS .

[0078] Here, the voltage V W is supplied to the channel of the semiconductor layer 110 connected to the bit line BL SRC A relatively large electric field is generated between such a semiconductor layer 110 and the selected word line WL S . As a result, electrons in the channel of the semiconductor layer 110 tunnel into the charge storage layer 132 (FIG. 4) through the tunnel insulating layer 131 (FIG. 4). Thereby, the threshold voltage of the write memory cell MC increases.

[0079] Also, the bit line BL PThe channel of the semiconductor layer 110 connected to it is electrically floating, and the potential of this channel is the non-selected word line WL U Capacitive coupling with the write path voltage V PASS It has risen to this extent. Such a semiconductor layer 110 and selected word line WL S Only a smaller electric field than the one described above is generated between them. Therefore, electrons in the channel of the semiconductor layer 110 do not tunnel into the charge storage layer 132 (Figure 4). Consequently, the threshold voltage of the disabled memory cell MC does not increase.

[0080] [Overview of verification process] Figure 8 is a schematic circuit diagram illustrating the overview of the verification operation.

[0081] In program operation, for example, bit line BL W Voltage V DD It supplies bit lines BL. P Voltage V SRC It supplies voltage V to the source line SL. SRC To supply.

[0082] Furthermore, during verification operation, a voltage V is applied to the drain-side selected gate line SGD. SG It supplies voltage V. SG is the voltage V DD ,V SRC It is larger than V. SG and voltage V DD ,V SRC The voltage difference is greater than the threshold voltage required to make the drain-side select transistor STD function as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain-side select transistor STD, and the voltage V DD ,V SRC It will be forwarded.

[0083] Furthermore, during verification operation, a voltage V is applied to the source-side selected gate lines SGS and SGSb. SG This supplies a voltage V. As a result, an electron channel is formed in the channel region of the source-side selection transistor STS, and the voltage VSRC It will be forwarded.

[0084] Furthermore, during verification, the unselected word line WL U Read path voltage V READ It supplies the read path voltage V. READ is the voltage V DD ,V SRC It is larger than that. Also, the read path voltage V READ and voltage V DD ,V SRC The voltage difference is greater than the threshold voltage required to make the memory cell MC function as an NMOS transistor, regardless of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, and the voltage V is applied to the selected memory cell MC. DD ,V SRC It will be forwarded.

[0085] Furthermore, during verification, the selected word line WL S Verify voltage V VFY It supplies the verify voltage V. VFY The verification voltage V is explained with reference to Figure 5. VFYA ,V VFYB ,V VFYC ,V VFYD ,V VFYE ,V VFYF ,V VFYG It is one of the following. Verification voltage V VFY and voltage V SRC The voltage difference is the target value of the threshold voltage of the write memory cell MC. Therefore, a write memory cell MC whose threshold voltage has not reached the target value will be in the ON state. Consequently, the bit line BL connected to such a write memory cell MC will be in the ON state. W Current flows through it. On the other hand, a write memory cell MC whose threshold voltage has reached the target value is in the OFF state. Therefore, the bit line BL connected to such a write memory cell MC is turned OFF. W No current flows through it.

[0086] Furthermore, during the verification operation, the sense amplifier unit SAU (Figure 15), described later, detects whether or not current flows through the bit line BL, thereby detecting the ON / OFF state of the memory cell MC. Hereafter, this type of operation may be referred to as "sense operation".

[0087] [Characteristic differences between memory layer MLs in program operation] Figure 9 is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the first embodiment. When manufacturing the semiconductor memory device according to the first embodiment, via holes are formed at positions corresponding to via electrodes 120 by methods such as RIE (Reactive Ion Etching), and via electrodes 120 are formed in these via holes. Here, when via holes with a large aspect ratio are formed by methods such as RIE, the thickness (diameter in the XY cross-section) of the via electrode 120 may not be constant from the bottom end to the top end. In the illustrated example, the thickness of the via electrode 120 increases from the bottom end to a predetermined height position near the top end. Also, the thickness of the via electrode 120 decreases from this predetermined height position to the top end.

[0088] In such a structure, the lower the memory layer ML is located, the smaller the diameter of the via electrode 120 in the XY cross-section. In the illustrated example, the memory layer ML located below a predetermined height position is defined as the memory layer ML L This is shown as: Memory Layer ML L In this case, electric field lines tend to concentrate between the semiconductor layer 110 and the via electrode 120, and the program voltage V PGM The supply of this material causes a relatively large amount of charge to accumulate in the charge storage layer 132.

[0089] On the other hand, in such a structure, the higher the memory layer ML is located, the larger the diameter of the via electrode 120 in the XY cross-section. In the illustrated example, the memory layer ML located above a predetermined height position is defined as the memory layer ML H This is shown as: Memory Layer ML HIn this case, electric field lines become less likely to concentrate between the semiconductor layer 110 and the via electrode 120, and the program voltage V PGM The supply of this material causes a relatively small amount of charge to accumulate in the charge storage layer 132.

[0090] In this embodiment, in order to mitigate such characteristic differences between memory layers ML during program operation, multiple memory layers ML in the memory cell array MCA are divided into two or more groups according to their position in the Z direction, and the voltage V supplied to the bit line BL during program operation is SRC Adjust for each group. Below are multiple memory layer MLs. L The first group, multiple memory layer ML H Let's explain an example where this is the second group.

[0091] [Writing operation according to the first embodiment] Figure 10 is a schematic circuit diagram illustrating the writing operation according to this embodiment.

[0092] As explained with reference to Figure 7, in program operation, bit line BL W A voltage V is applied to the channel of the semiconductor layer 110 connected to it. SRC Select word line WL S Program voltage V PGM It supplies voltage V SRC and program voltage V PGM The difference between this and the FN tunnel is generated. Here, the voltage V SRC The smaller the value, the better the semiconductor layer 110 - selected word line WL. S The electric field between them becomes larger, and a large amount of charge is accumulated in the charge storage layer 132.

[0093] Therefore, in the first embodiment, as shown in Figure 10, the memory layer ML L The bit line BL inside W The voltage V supplied to it SRC (Hereafter, "Voltage V SRC0 This is called "Memory Layer ML". H The bit line BL inside W The voltage V supplied to it SRC (Hereafter, "Voltage VSRC1 It is called "". ) and is different. Also, voltage V SRC0 to, voltage V SRC1 Make it larger than that.

[0094] Figure 11 is a schematic waveform diagram illustrating an example of a writing operation according to the first embodiment.

[0095] In the example in Figure 11, program operation (step S102 in Figure 6) begins at timing t101. Consequently, the memory layer ML H The bit line BL inside W Voltage V SRC1 It is supplied, and the memory layer ML H The bit line BL inside P Voltage V DD It is supplied. Also, the memory layer ML L The bit line BL inside W Voltage V SRC0 It is supplied, and the memory layer ML L The bit line BL inside P Voltage V DD It will be supplied.

[0096] Next, at timing t102, the selected word line WL S The program voltage V PGM It will be supplied.

[0097] Furthermore, in the example in Figure 11, the verification operation (step S103 in Figure 6) is initiated at timing t103. In the example in Figure 11, first, the state of the write memory cell MC controlled to state A is detected. For example, the selected word line WL S Verify voltage V VFYA It is supplied. Also, the memory layer ML H Among the bit lines BL inside, the bit line BL connected to the write memory cell MC controlled in state A. W Voltage V DD A voltage V is supplied to the other bit lines BL. SRC1 It is supplied. Also, the memory layer ML L Among the bit lines BL inside, the bit line BL connected to the write memory cell MC controlled in state A.W Voltage V DD A voltage V is supplied to the other bit lines BL. SRC0 It will be supplied.

[0098] In this state, a sense operation is performed to determine whether the threshold voltage of the write memory cell MC controlled in state A has reached the target value. At this time, any write memory cell MC whose threshold voltage has reached the target value is set as a disabled memory cell MC.

[0099] Next, at timing t104, the state of the write memory cell MC controlled to the B state is detected. For example, the selected word line WL S Verify voltage V VFYB It is supplied. Also, the memory layer ML H Among the bit lines BL inside, the bit line BL connected to the write memory cell MC controlled by the B state W Voltage V DD A voltage V is supplied to the other bit lines BL. SRC1 It is supplied. Also, the memory layer ML L Among the bit lines BL inside, the bit line BL connected to the write memory cell MC controlled by the B state W Voltage V DD A voltage V is supplied to the other bit lines BL. SRC0 It will be supplied.

[0100] In this state, a sense operation is performed to determine whether the threshold voltage of the write memory cell MC controlled in the B state has reached the target value. At this time, any write memory cell MC whose threshold voltage has reached the target value is set as a disabled memory cell MC.

[0101] Furthermore, in the example in Figure 11, the program operation starts at timing t111. Accordingly, each bit line BL is supplied with the same voltage as the voltage supplied at timing t101. However, the bit line BL connected to the memory cell MC that is set as a prohibited memory cell in the verification operation is supplied with voltage V DD It will be supplied.

[0102] Next, at timing t112, the selected word line WL S The program voltage V PGM The program voltage V is supplied. Here, as explained with reference to Figure 6, in step S106, the program voltage V PGM A predetermined voltage ΔV is added to it. Therefore, the program voltage V at timing t112 is PGM This is the program voltage V at timing t102. PGM It is larger than that.

[0103] In the example shown in Figure 11, the verification operation (step S103 in Figure 6) is initiated at timing t113. At timing t113, the state of the write memory cell MC controlled to state A is detected. At this time, any write memory cell MC whose threshold voltage has reached the target value is set as a forbidden memory cell MC.

[0104] Next, at timing t114, the state of the write memory cell MC controlled to the B state is detected. At this time, any write memory cell MC whose threshold voltage has reached the target value is set as a disabled memory cell MC.

[0105] Next, at timing t115, the state of the write memory cell MC controlled by the C state is detected. At this time, any write memory cell MC whose threshold voltage has reached the target value is set as a forbidden memory cell MC.

[0106] Similarly, in the operation of step S104, as explained with reference to Figure 6, until the verification is determined to be PASS, or in the operation of step S105, the loop count n W a predetermined number of times N W The program and verification operations are repeatedly executed until the target is reached.

[0107] In the example shown in Figure 11, the voltage V supplied to the bit line BL during program operation is shown. SRC In addition, the voltage V supplied to the bit line BL during verification operation SRC Also, voltage V SRC0 ,VSRC1 It is divided into these. However, this operation is merely an example. The voltage V supplied to the bit line BL during verification operation. SRC is the voltage V SRC0 or voltage V SRC1 It would be fine to standardize it to this.

[0108] Figure 12 is a schematic waveform diagram illustrating another example of the write operation according to this embodiment. The write operation illustrated in Figure 12 is performed in substantially the same manner as the write operation illustrated in Figure 11. However, in the example of Figure 12, the voltage V supplied to the bit line BL during the verify operation is different. SRC However, voltage V SRC1 It is standardized.

[0109] [effect] Figures 13 and 14 are schematic histograms illustrating the effects of the writing operation according to this embodiment.

[0110] Figure 13 shows the voltage V during program operation. SRC0 Voltage V SRC1 Set it to the same size, and in this state, select word line WL S When program voltage is supplied to the memory layer ML H Threshold distribution of memory cells MC and memory layer ML L This shows the threshold distribution of the memory cells MC inside. In such cases, as shown in the figure, the memory layer ML L The threshold voltage of the internal write memory cell MC is the memory layer ML H This becomes higher than the threshold voltage of the internal writing memory cell MC. As a result, the variation in the threshold voltage of the memory cell MC increases.

[0111] Figure 14 shows the voltage V during program operation. SRC0 Voltage V SRC1 Set it to be larger than this, and in this state, select word line WL S When program voltage is supplied to the memory layer ML H Threshold distribution of memory cells MC and memory layer ML LThis shows the threshold distribution of the memory cells MC inside. According to this method, as shown in the figure, the memory layer ML L The threshold voltage of the internal write memory cell MC is set in the memory layer ML. H This voltage is approximately the same magnitude as the threshold voltage of the internal write memory cell MC. This makes it possible to suppress variations in the threshold voltage of the memory cell MC.

[0112] [Peripheral circuits] Figure 15 is a schematic circuit diagram showing a partial configuration example of the peripheral circuit of the semiconductor memory device according to this embodiment.

[0113] The semiconductor memory device according to this embodiment includes a plurality of sense amplifier units SAU provided as part of the peripheral circuitry, corresponding to a plurality of bit lines BL. Each sense amplifier unit SAU comprises a sense amplifier SA, a wiring LBUS, and latch circuits SDL, DL0 to DLn (where n is a natural number). A pre-charging transistor 55 is connected to the wiring LBUS. The wiring LBUS is connected to the wiring DBUS via a switch transistor DSW.

[0114] The sense amplifier SA includes a sense transistor 41. In the sense operation described above, the sense transistor 41 discharges the charge of the wiring LBUS in accordance with the current flowing through the bit line BL. The source electrode of the sense transistor 41 is connected to the ground voltage V SS The voltage supply line is connected to the power supply line. The drain electrode is connected to wiring LBUS via switch transistor 42. The gate electrode is connected to bit line BL via sense node SEN, discharge transistor 43, node COM, clamp transistor 44, and voltage-resistant transistor 45. The sense node SEN is connected to signal line CLKSA via capacitor 48.

[0115] Furthermore, the sense amplifier SA includes a voltage transfer circuit. The voltage transfer circuit transmits voltage V to node COM and sense node SEN according to the data latched by the latch circuit SDL. DD A voltage supply line or voltage V suppliedSRC The voltage supply line is selectively connected to the voltage supply line to which the voltage is supplied. The voltage transfer circuit comprises node N1, charging transistor 46, charging transistor 49, charging transistor 47, and discharge transistor 50. Charging transistor 46 is connected between node N1 and sense node SEN. Charging transistor 49 is connected between node N1 and node COM. Charging transistor 47 is connected between node N1 and voltage V DD It is connected between the voltage supply lines to which the voltage V is supplied. Discharge transistor 50 is connected between node N1 and voltage V SRC It is connected between the voltage supply lines to which the voltage is supplied. Furthermore, the gate electrodes of the charging transistor 47 and the discharging transistor 50 are commonly connected to node INV_S of the latch circuit SDL.

[0116] Furthermore, the sense transistor 41, switch transistor 42, discharge transistor 43, clamp transistor 44, charge transistor 46, charge transistor 49, and discharge transistor 50 are, for example, enhancement-type NMOS transistors. The breakdown transistor 45 is, for example, a depletion-type NMOS transistor. The charge transistor 47 is, for example, a PMOS transistor.

[0117] Furthermore, the gate electrode of the switch transistor 42 is connected to the signal line STB. The gate electrode of the discharge transistor 43 is connected to the signal line XXL. The gate electrode of the clamp transistor 44 is connected to the signal line BLC. The gate electrode of the breakdown transistor 45 is connected to the signal line BLS. The gate electrode of the charge transistor 46 is connected to the signal line HLL. The gate electrode of the charge transistor 49 is connected to the signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to a control circuit (not shown).

[0118] The latch circuit SDL comprises nodes LAT_S and INV_S, inverter 51, inverter 52, switch transistor 53, and switch transistor 54. Inverter 51 has an output terminal connected to node LAT_S and an input terminal connected to node INV_S. Inverter 52 has an input terminal connected to node LAT_S and an output terminal connected to node INV_S. Switch transistor 53 is located in the current path between node LAT_S and wiring LBUS. Switch transistor 54 is located in the current path between node INV_S and wiring LBUS. Switch transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of switch transistor 53 is connected to a control circuit (not shown) via signal line STL. The gate electrode of switch transistor 54 is connected to a control circuit (not shown) via signal line STI.

[0119] The latch circuits DL0 to DLn are configured in much the same way as the latch circuit SDL. However, as mentioned above, node INV_S of the latch circuit SDL is in conductivity with the gate electrodes of the charging transistor 47 and the discharging transistor 50 in the sense amplifier SA. The latch circuits DL0 to DLn differ from the latch circuit SDL in this respect.

[0120] The switch transistor DSW is, for example, an NMOS transistor. The switch transistor DSW is connected between wiring LBUS and wiring DBUS. The gate electrode of the switch transistor DSW is connected to a control circuit (not shown) via signal line DBS.

[0121] The signal lines STB, HLL, XXL, BLX, BLC, and BLS are all commonly connected to all sense amplifier units SAU included in the semiconductor memory device. Also, voltage V DD The voltage supply line and voltage V that are supplied SRCThe voltage supply lines that provide the signal are each commonly connected to multiple sense amplifier units SAU included in the semiconductor memory device. Similarly, the signal lines STI and STL of the latch circuit SDL are each commonly connected to all sense amplifier units SAU included in the semiconductor memory device. Likewise, the signal lines TI0 to TIn and TL0 to TLn, corresponding to the signal lines STI and STL in the latch circuits DL0 to DLn, are each commonly connected to all sense amplifier units SAU included in the semiconductor memory device.

[0122] During program operation, the latch circuit SDL corresponding to the above-mentioned write memory cell MC is latched with "L". As a result, the charging transistor 47 is in the OFF state and the discharging transistor 50 is in the ON state, and a voltage V is applied to node N1. SRC This is supplied. Meanwhile, the latch circuit SDL corresponding to the prohibited memory cell MC is latched with "H". As a result, the charging transistor 47 is turned ON and the discharging transistor 50 is turned OFF, and a voltage V is supplied to node N1. DD This is supplied. In this state, by turning on the charging transistor 49, clamping transistor 44, and voltage-resistant transistor 45, the bit line BL W Voltage V SRC It supplies bit line BL L Voltage V DD It is possible to supply it.

[0123] During verification, "H" is latched to the latch circuit SDL corresponding to the write memory cell MC, and "L" is latched to the latch circuit SDL corresponding to the disabled memory cell MC. In this state, the charging transistor 49, clamp transistor 44, and withstand voltage transistor 45 are turned ON, and the bit line BL W Voltage V DD It supplies bit line BL L Voltage V SRC It is possible to supply it.

[0124] Before the sense operation is performed, signal line HLL is set to the "H" state and signal line XXL is set to the "L" state. This turns on the charging transistor 46 and the discharging transistor 43, charging the sense node SEN corresponding to the write memory cell MC. In addition, signal line STB is set to the "L" state and charging transistor 55 is turned on for a certain period of time to charge the wiring LBUS.

[0125] During the sense operation, the signal line XXL,CLKSA is set to the "H" state. This turns on the discharge transistor 43, and the voltage of the sense node SEN increases due to capacitive coupling. If current is flowing through the bit line BL, i.e., if the selective memory cell MC is in the ON state, the charge in the sense node SEN is discharged. On the other hand, if no current is flowing through the bit line BL, i.e., if the selective memory cell MC is in the OFF state, the charge in the sense node SEN is maintained. After a certain period of time, the signal line XXL,CLKSA is set to the "L" state. This turns off the sense transistor 41 if the charge in the sense node SEN has been discharged, and turns on the sense transistor 41 if the charge in the sense node SEN has not been discharged.

[0126] Next, the signal line STB is set to the "H" state. This ensures that the charge on the wiring LBUS is maintained when the sense transistor 41 is in the OFF state, and discharges the charge on the wiring LBUS when the sense transistor 41 is in the ON state. This makes it possible to detect the write memory cell MC when the threshold voltage reaches the target value.

[0127] Figure 16 is a schematic circuit diagram showing a partial configuration example of the peripheral circuit of the semiconductor memory device according to this embodiment.

[0128] The semiconductor memory device according to this embodiment includes voltage generation circuits VG0, VG1, and VG2 as part of its peripheral circuitry. The voltage generation circuits VG0, VG1, and VG2 are boost circuits such as charge pump circuits, or buck circuits such as regulator circuits.

[0129] The output terminal of the voltage generation circuit VG0 is connected to the voltage supply line VS0. The voltage generation circuit VG0 supplies voltage V to the voltage supply line VS0. SRC0 The voltage supply line VS0 supplies the memory layer ML of the multiple sense amplifier units SAU included in the semiconductor memory device. L It is commonly connected to the bit line BL inside. This allows it to connect to the memory layer ML. L Multiple sense amplifier units SAU corresponding to this have a voltage V SRC For example, voltage V SRC0 It will be supplied.

[0130] The output terminal of the voltage generation circuit VG1 is connected to the voltage supply line VS1. The voltage generation circuit VG1 supplies voltage V to the voltage supply line VS1. SRC1 The voltage supply line VS1 supplies the memory layer ML of the multiple sense amplifier units SAU included in the semiconductor memory device. H It is commonly connected to the bit line BL inside. This allows it to connect to the memory layer ML. H Multiple sense amplifier units SAU corresponding to this have a voltage V SRC For example, voltage V SRC1 It will be supplied.

[0131] The output terminal of the voltage generation circuit VG2 is connected to the voltage supply line VS2. The voltage generation circuit VG2 supplies voltage V to the voltage supply line VS2. DD The voltage supply line VS2 is connected in common to all sense amplifier units SAU included in the semiconductor memory device.

[0132] With this configuration, it is possible to perform the writing operation described with reference to Figure 11.

[0133] Furthermore, as explained with reference to Figure 12, for example, the voltage V supplied to the bit line BL during verification operation SRC Voltage V SRC0 or voltage V SRC1 If unified to this, the voltage output from the voltage generation circuits VG0 and VG1 during verification operation should be set to voltage VSRC0 or voltage V SRC1 Alternatively, the voltage supply lines VS0, VS1 and the voltage generation circuits VG0, VG1 can be connected via a multiplexer or similar device.

[0134] [Second Embodiment] Figure 17 is a schematic waveform diagram illustrating an example of a writing operation according to the second embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0135] In the example in Figure 17, the program operation (step S102 in Figure 6) starts at timing t201. In the example in Figure 17, first, the threshold voltage of the write memory cell MC controlled to state A is adjusted. For example, the memory layer ML H Among the bit lines BL inside, the bit line BL connected to the write memory cell MC controlled in state A. W Voltage V SRC1 A voltage V is supplied to the other bit lines BL. DD It is supplied. Also, the memory layer ML L Among the bit lines BL inside, the bit line BL connected to the write memory cell MC controlled in state A. W Voltage V SRC0 A voltage V is supplied to the other bit lines BL. DD It will be supplied.

[0136] Next, at timing t202, the selected word line WL S The program voltage V PGMA It will be supplied.

[0137] Next, at timing t203, the threshold voltage of the write memory cell MC controlled to the B state is adjusted. For example, the memory layer ML H Among the bit lines BL inside, the bit line BL connected to the write memory cell MC controlled by the B state W Voltage V SRC1 A voltage V is supplied to the other bit lines BL. DD It is supplied. Also, the memory layer ML LAmong the bit lines BL inside, the bit line BL connected to the write memory cell MC controlled by the B state W Voltage V SRC0 A voltage V is supplied to the other bit lines BL. DD It will be supplied.

[0138] Next, at timing t204, the selected word line WL S The program voltage V PGMB The program voltage V is supplied. PGMB The program voltage V PGMA It is larger than that.

[0139] Similarly, at timings t205 to t214, the threshold voltage of the write memory cell MC controlled from C state to G state is adjusted. Figure 17 shows the program voltage V corresponding to C state to G state. PGM As such, the program voltage V PGMC ,V PGMD ,V PGME ,V PGMF ,V PGMG This illustrates the program voltage V. PGMC The program voltage V PGMB Larger than. Program voltage V PGMD The program voltage V PGMC Larger than. Program voltage V PGME The program voltage V PGMD Larger than. Program voltage V PGMF The program voltage V PGME Larger than. Program voltage V PGMG The program voltage V PGMF It is larger than that.

[0140] In the example shown in Figure 17, the verification operation (step S103 in Figure 6) is initiated at timing t221. The verification operation according to the second embodiment is basically performed in the same way as the verification operation according to the first embodiment. However, in the verification operation according to the first embodiment, the state of the write memory cell MC corresponding to only a portion of the A state to G state is detected in each verification operation. On the other hand, in the verification operation according to the second embodiment, the state of all write memory cell MC states from A state to G state is detected in each verification operation.

[0141] In the second embodiment, as in the first embodiment, the operation of step S104, described with reference to Figure 6, continues until it is determined that the verification is PASS, or the operation of step S105 continues for a loop count n. W a predetermined number of times N W The program and verification operations are repeatedly executed until the target is reached.

[0142] In the second embodiment, in step S106 of Figure 6, all program voltages V PGMA ,V PGMB ,V PGMC ,V PGMD ,V PGME ,V PGMF ,V PGMG A predetermined voltage ΔV is added to it.

[0143] Furthermore, in the second embodiment as described with reference to Figure 12, for example, the voltage V supplied to the bit line BL during the verification operation SRC Voltage V SRC0 or voltage V SRC1 It would be fine to standardize it to this.

[0144] [Other embodiments] The semiconductor memory devices according to the first and second embodiments have been described above. However, the configurations and operations described above are merely examples, and the specific configurations, methods, etc., can be adjusted as appropriate.

[0145] For example, in the write operation according to the first and second embodiments, multiple memory layers ML in the memory cell array MCA are divided into two groups, and the voltage V supplied to the bit line BL during program operation is SRC This shows an example of adjusting for each of these two groups. However, multiple memory layers ML in the memory cell array MCA may be divided into three or more groups. Also, the voltage V supplied to the bit line BL during program operation. SRC However, these three groups can also be adjusted separately.

[0146] Furthermore, in the first and second embodiments, with reference to Figure 9, an example was shown in which the thickness of the via electrode 120 increases from the lower end to a predetermined height position near the upper end, and then decreases from this predetermined height position to the upper end. However, depending on the manufacturing method, the thickness of the via electrode 120 may increase monotonically from the lower end to the upper end. Also, when the via holes described above are formed in multiple steps, the thickness of the via electrode 120 may increase or decrease approximately periodically from the lower end to the upper end. In addition, for example, if a wafer corresponding to the memory cell array MCA and a wafer corresponding to the peripheral circuit are manufactured separately, the wafer corresponding to the memory cell array MCA is inverted and bonded to the wafer corresponding to the peripheral circuit, and then the substrate is removed from the wafer corresponding to the memory cell array MCA, the shape of the via electrode 120 may be inverted when using the substrate of the wafer corresponding to the peripheral circuit as a reference.

[0147] Even in these cases, multiple memory layers ML in the memory cell array MCA are divided into two or more groups according to their height, and the voltage V supplied to the bit line BL during program operation is SRC It is possible to adjust this for each group. That is, in a group that includes a memory layer ML in which the diameter of the via electrode 120 in the XY cross-section is relatively small, the voltage V supplied to the bit line BL during program operation can be adjusted. SRC It is possible to adjust this to a relatively large value. Also, in groups including memory layer ML in which the diameter of via electrode 120 in the XY cross section is relatively large, the voltage V supplied to bit line BL during program operation SRCIt is possible to adjust this to a relatively small value.

[0148] Furthermore, in the first and second embodiments, the voltage V supplied to the bit line BL in at least one of the program operation and the verify operation DD However, adjustments can be made on a group-by-group basis.

[0149] Furthermore, in the first and second embodiments, an example was described in which the threshold voltage of the memory cell MC is adjusted to eight different states, thereby causing the memory cell MC to store 3 bits of data. However, the memory cell MCA may store 2 bits or less of data, or 4 bits or more of data.

[0150] Furthermore, in the examples of Figures 11, 12, and 17, during the verification operation, the states are detected in order from the write memory cell MC controlled to the state with the lowest threshold voltage among the A state to the G state. However, in the examples of Figures 11, 12, and 17, the states may also be detected in order from the write memory cell MC controlled to the state with the highest threshold voltage among the A state to the G state.

[0151] Furthermore, in the example shown in Figure 17, the program operation adjusts the threshold voltage in order from the write memory cell MC controlled to the state with the lowest threshold voltage among states A to G. However, in the example shown in Figure 17, the threshold voltage may also be adjusted in order from the write memory cell MC controlled to the state with the highest threshold voltage among states A to G.

[0152] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0153] 110... Semiconductor layer, 120... Via electrode, 130... Gate insulating layer, 140... Via electrode, 150... Via wiring, 160... Semiconductor layer, 170... Conductive layer, 180... Via wiring.

Claims

1. A plurality of semiconductor layers stacked in the stacking direction and stretched in a first direction intersecting the stacking direction, A plurality of conductive layers are stacked in the stacking direction corresponding to the plurality of semiconductor layers, are extended in a second direction intersecting the stacking direction and the first direction, and are connected to the ends of the plurality of semiconductor layers in the first direction. A plurality of via electrodes are arranged in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, extended in the stacking direction, facing the plurality of semiconductor layers, and having a diameter that increases from the first position to the second position in the stacking direction, A plurality of charge storage layers are provided between the plurality of semiconductor layers and the plurality of via electrodes. Equipped with, At the first timing of the program operation that accumulates charge in a portion of the plurality of charge storage layers, A first voltage or a second voltage greater than the first voltage is supplied to a plurality of first conductive layers provided in the range from the first position in the stacking direction to the third position between the first position and the second position. With a plurality of second conductive layers provided in the range from the second position in the stacking direction to the fourth position between the second and third positions, a third voltage greater than the first voltage and less than the second voltage, or a fourth voltage greater than the third voltage, is supplied to the plurality of second conductive layers in the range from the second position in the stacking direction to the fourth position between the second and third positions, A first program voltage is supplied to one of the plurality of via electrodes. Semiconductor memory device.

2. At the aforementioned first timing, The first voltage is supplied to one of the plurality of first conductive layers that corresponds to a portion of the plurality of charge storage layers. The second voltage is supplied to the plurality of first conductive layers that do not correspond to the portion of the plurality of charge storage layers. The third voltage is supplied to one of the plurality of second conductive layers that corresponds to the portion of the plurality of charge storage layers. The fourth voltage is supplied to the plurality of second conductive layers that do not correspond to the plurality of charge storage layers. The semiconductor memory device according to claim 1.

3. Some of the aforementioned plurality of charge storage layers include those that are controlled from a first state to a second state. At the aforementioned first timing, The first voltage is supplied to the one of the plurality of first conductive layers that corresponds to the charge storage layer controlled to the second state. Of the plurality of first conductive layers, the second voltage is supplied to all but the one corresponding to the charge storage layer controlled to the second state. The third voltage is supplied to the layer among the plurality of second conductive layers that corresponds to the charge storage layer controlled to the second state. Of the plurality of second conductive layers, the fourth voltage is supplied to all but the one corresponding to the charge storage layer controlled to the second state. The semiconductor memory device according to claim 1.

4. The portion of the plurality of charge storage layers further includes those that are controlled from the first state to the third state, At the second timing of the program operation, The first voltage is supplied to the one of the plurality of first conductive layers that corresponds to the charge storage layer controlled to the third state. Of the plurality of first conductive layers, the second voltage is supplied to all but the one corresponding to the charge storage layer controlled to the third state. The third voltage is supplied to the one of the plurality of second conductive layers that corresponds to the charge storage layer controlled to the third state. With the fourth voltage supplied to all of the plurality of second conductive layers except for the one corresponding to the charge storage layer controlled to the third state, A second program voltage greater than the first program voltage is supplied to one of the plurality of via electrodes. The semiconductor memory device according to claim 3.

5. A plurality of first sense amplifier circuits electrically connected to the plurality of first conductive layers, A first voltage supply line capable of supplying the first voltage to the plurality of first sense amplifier circuits, A second voltage supply line capable of supplying the second voltage to the plurality of first sense amplifier circuits, A plurality of second sense amplifier circuits electrically connected to the plurality of second conductive layers, A third voltage supply line capable of supplying the third voltage to the plurality of second sense amplifier circuits, A fourth voltage supply line capable of supplying the fourth voltage to the plurality of second sense amplifier circuits and The semiconductor memory device according to claim 1, further comprising:

6. A plurality of first latch circuits provided corresponding to the plurality of first sense amplifier circuits, A plurality of second latch circuits provided corresponding to the plurality of second sense amplifier circuits and Furthermore, Each of the plurality of first sense amplifier circuits connects the plurality of first conductive layers to the first voltage supply line or the second voltage supply line in accordance with the data latched by the plurality of first latch circuits. Each of the plurality of second sense amplifier circuits connects the plurality of second conductive layers to the third voltage supply line or the fourth voltage supply line in accordance with the data latched by the plurality of second latch circuits. The semiconductor memory device according to claim 5.

7. A plurality of semiconductor layers stacked in the stacking direction and stretched in a first direction intersecting the stacking direction, A plurality of conductive layers are stacked in the stacking direction corresponding to the plurality of semiconductor layers, are extended in a second direction intersecting the stacking direction and the first direction, and are connected to the ends of the plurality of semiconductor layers in the first direction. A plurality of via electrodes are arranged in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, extended in the stacking direction, facing the plurality of semiconductor layers, and having a diameter that increases from the first position to the second position in the stacking direction, A plurality of charge storage layers are provided between the plurality of semiconductor layers and the plurality of via electrodes, A plurality of first sense amplifier circuits electrically connected to a plurality of first conductive layers, which are provided in a range from the first position in the stacking direction to a third position between the first position and the second position, A first voltage supply line capable of supplying a first voltage to the plurality of first sense amplifier circuits, The plurality of first sense amplifier circuits are provided with a second voltage supply line capable of supplying a second voltage different from the first voltage, A plurality of second sense amplifier circuits electrically connected to a plurality of second conductive layers provided in a range from the second position in the stacking direction to a fourth position between the second position and the third position, The plurality of second sense amplifier circuits are provided with a third voltage supply line capable of supplying a third voltage different from the first voltage and the second voltage, The plurality of second sense amplifier circuits are provided with a fourth voltage supply line capable of supplying a fourth voltage different from the first voltage and the third voltage. A semiconductor memory device equipped with the following features.

8. A plurality of first latch circuits provided corresponding to the plurality of first sense amplifier circuits, A plurality of second latch circuits provided corresponding to the plurality of second sense amplifier circuits and Furthermore, Each of the plurality of first sense amplifier circuits connects the plurality of first conductive layers to the first voltage supply line or the second voltage supply line in accordance with the data latched by the plurality of first latch circuits. Each of the plurality of second sense amplifier circuits connects the plurality of second conductive layers to the third voltage supply line or the fourth voltage supply line in accordance with the data latched by the plurality of second latch circuits. The semiconductor memory device according to claim 7.

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