Connection error detection device, learning device, and inference device

Abstract

To obtain a connection error detection device that can detect potential errors in the description of inter-module connections using a hardware description language in logic circuit design using a hardware description language. [Solution] The connection error detection processing unit 30 acquires circuit information including port information and destination port information contained in the existing design document, and uses the circuit information to learn the connection relationship between the source module and the destination module. Based on the learning results, the connection error detection processing unit 30 infers the destination port information corresponding to the port information contained in the new design document from the port information of the source module contained in the new design document. The connection error detection processing unit 30 compares the destination port information corresponding to the port information in the new design document with the destination port information inferred based on the learning results of the connection relationship between modules, and outputs the comparison result.

Description

Technical Field

[0001] The present disclosure relates to a connection error detection device, a learning device, and an inference device.

Background Art

[0002] Conventionally, as a description method for expressing a logic circuit, there is a description expression using a Hardware Description Language (HDL). In the description of a logic circuit using HDL, it is common to describe in a module structure hierarchically configured in circuit units called modules, and the connection between modules is also expressed by a description using HDL. There is a port as an interface for transmitting and receiving signals between modules. A port for inputting a signal to a module is generally called an input port, and a port for outputting a signal from a module is generally called an output port. The connection from the output port to the input port between modules is also expressed by an HDL description. Note that the description described by HDL may be simply referred to as an HDL description.

[0003] Patent Document 1 describes a method of generating an HDL description of module connection using a database having connection information between modules, referring to the database from HDL reserved words input by a designer, and generating an HDL description of module connection from the database.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the method described in Patent Document 1 cannot handle connections between modules that do not exist in the database, and it is not possible to generate an HDL description of inter-module connections from reserved HDL words entered by the designer.

[0006] Furthermore, in the design of logic circuits, the created HDL description is checked for syntax errors and errors in the rules of the HDL description using verification tools. In addition, formal verification and functional verification using simulation are performed.

[0007] On the other hand, tools that check for syntax errors and rule errors in HDL descriptions cannot detect functional errors in HDL descriptions. Furthermore, in order to verify the validity of connections between modules through formal and functional verification, the verifier must create expected values ​​to verify the validity of connections between modules, which can lead to omissions, and omissions can also occur due to the creation of incorrect expected values.

[0008] This disclosure has been made in view of the above, and aims to provide a connection error detection device that can detect potentially erroneous locations in the description of inter-module connections using a hardware description language in logic circuit design using a hardware description language. [Means for solving the problem]

[0009] To solve the aforementioned problems and achieve the objectives, the connection error detection device according to this disclosure includes a connection error detection processing unit that detects potentially erroneous locations in the information on connections between modules included in a design document, which is described in a hardware description language. The connection error detection processing unit obtains circuit information, including port information of the source module included in the existing design document and destination port information of the destination module included in the existing design document that corresponds to the port information of the source module in the existing design document, from the existing design document in which the logic circuit design has been completed and the description of the inter-module connection identification information, which is information on connections between modules included in the existing design document, described in a hardware description language. Using the circuit information, the unit learns the connection relationship between the source module and the destination module. Based on the learning result of the connection relationship between modules, the connection error detection processing unit infers destination port information of the destination module included in the newly created design document that corresponds to the port information of the source module included in the new design document, from the port information of the source module included in the new design document. The connection error detection processing unit compares the destination port information corresponding to the port information in the new design document with the destination port information inferred based on the learning result of the connection relationship between modules and outputs the comparison result. [Effects of the Invention]

[0010] According to this disclosure, in logic circuit design using a hardware description language, it is possible to detect potentially erroneous locations in the description of inter-module connections using the hardware description language. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows the configuration of the connection error detection device according to Embodiment 1. [Figure 2] Diagram showing the configuration of the learning device according to Embodiment 1. [Figure 3]This figure shows an example of port information acquired in the learning device according to Embodiment 1. [Figure 4] This figure shows an example of connection destination port information acquired in the learning device according to Embodiment 1. [Figure 5] Flowchart showing the processing procedure of the learning process by the learning device according to Embodiment 1 [Figure 6] This figure shows the configuration of the neural network used in the learning device according to Embodiment 1. [Figure 7] Diagram showing the configuration of the inference device according to Embodiment 1. [Figure 8] Flowchart showing the processing procedure of inference processing by the inference device according to Embodiment 1 [Figure 9] This figure shows an example of connection destination port comparison result information output from the inference device according to Embodiment 1. [Figure 10] This diagram shows the configuration in which each function of the control unit according to Embodiment 1 is implemented in hardware. [Figure 11] This diagram shows the configuration in which each function of the control unit according to Embodiment 1 is implemented in software. [Modes for carrying out the invention]

[0012] The connection error detection device, learning device, and inference device according to the embodiment will be described in detail below with reference to the drawings.

[0013] Embodiment 1. FIG. 1 is a diagram showing the configuration of the connection error detection device according to Embodiment 1. The connection error detection device 1 according to Embodiment 1 extracts and outputs a location where there may be an error in the information on module connections described by HDL from the logic circuit description of a design document including HDL descriptions in the logic circuit design using HDL. The design document is created in the logic circuit design process when developing a system, is a document written about "how to make the system", is an electronic document created as digital information, and is an electronic file. The design document includes HDL descriptions and descriptions other than the HDL descriptions. The HDL description is specifically a source code. The design document specifically includes a source code and design materials for creating the source code. The design materials for creating the source code are materials created using tools such as Word (registered trademark) and Excel (registered trademark).

[0014] The connection error detection device 1 includes an input / output unit 10, a storage unit 20, a connection error detection processing unit 30, a control unit 40, and a display unit 50. Information can be exchanged between the respective components of the connection error detection device 1 described above.

[0015] The input / output unit 10 performs input / output of information with devices outside the connection error detection device 1. The input / output unit 10 has a function as a communication unit that communicates with devices outside the connection error detection device 1 via a network (not shown) such as the Internet or a dedicated line (not shown) to exchange information. Note that the input / output unit 10 may exchange information by other methods.

[0016] The storage unit 20 stores various types of information used for controlling the connection error detection device 1.

[0017] The connection error detection processing unit 30 detects and outputs a location where there may be an error in the information on the module connections described in HDL from the logical circuit description of the design document including the HDL description. That is, the connection error detection processing unit 30 obtains circuit information including the port information of the source module included in the existing design document and the destination port information of the destination module included in the existing design document, which is the destination port information corresponding to the port information of the source module included in the existing design document, from the existing design document in which the logical circuit design is completed and the description in HDL of the module connection specific information, which is the information on the connections between the modules described in HDL and included in the existing design document, and learns the connection relationship between the source module and the destination module using the circuit information. The connection error detection processing unit 30 infers the destination port information of the destination module included in the newly created new design document, which is the destination port information corresponding to the port information of the source module included in the new design document, based on the learning result of the connection relationship between the modules. Then, the connection error detection processing unit 30 compares the destination port information corresponding to the port information in the new design document with the destination port information inferred based on the learning result of the connection relationship between the modules and outputs the comparison result. <0,000,096><0,000,097><0,000,098>The connection error detection processing unit 30 includes a machine learning device 31 having a learning device 32 and an inference device 33. Details of the machine learning device 31 will be described later. <0,000,099><0,000,100><0,000,101>The control unit 40 controls the entire connection error detection device 1. The control unit 40 receives information from a device outside the connection error detection device 1 via the input / output unit 10, transmits the information to the connection error detection processing unit 30, and stores the information in the storage unit 20. <0,000,102><0,000,103><0,000,104>Next, the learning device 32 and inference device 33 of the machine learning device 31 will be described. The machine learning device 31 comprises a learning device 32 and an inference device 33, and learns the destination ports through machine learning and detects potentially erroneous locations in the inter-module connection information of the HDL description from the logic circuit description of the design document.

[0021] Figure 2 shows the configuration of the learning device according to Embodiment 1. The learning device 32 learns the connection destination port based on the learning data. The learning device 32 includes a circuit information acquisition unit 321, a model generation unit 322, and a learned model storage unit 34. The learned model storage unit 34 may be located outside the learning device 32, or it may be provided in the storage unit 20 of the connection error detection device 1. The circuit information acquisition unit 321 is the first circuit information acquisition unit in the connection error detection device 1.

[0022] The circuit information acquisition unit 321 acquires an existing design document, which is an existing design document in which the logic circuit design has been completed, and an HDL description of inter-module connection identification information, which is information on the connections between modules included in the existing design document and is written in HDL. From the existing design document and the HDL description of inter-module connection identification information, it extracts circuit information including the port information of the source module included in the existing design document and the destination port information of the destination module included in the existing design document, which corresponds to the port information of the source module, and outputs this as training data to the model generation unit 322. Here, the training data is data that associates the port information and the destination port information with each other. Note that the port information of a module may be simply called port information. Also, the destination port information of a module may be simply called destination port information.

[0023] Port information refers to the port information of the first module, which is the source module when two modules described in the design document are connected, and is the source port information in the connection of the ports of the two modules described in the design document.

[0024] The destination port information refers to the port information of the second module, which is the destination module when two modules described in the design document are connected; it refers to the destination port information in the connection of the ports of the two modules described in the design document; and it refers to the port information of the second module that is connected to the port of the first module. Note that in the design document, the source module may be connected to multiple destination modules. In other words, in the design document, the source port and destination port may be connected in a one-to-one relationship, or in a one-to-many relationship.

[0025] The inter-module connection identification information is information that can identify the connections between modules contained in the existing design document. Furthermore, the destination port information corresponding to the port information extracted by the circuit information acquisition unit 321 is destination port information that appropriately corresponds to the port information contained in the existing design document. The existing design document is a design document in which the logic circuit design has been completed, and the information on inter-module connections is appropriately described in HDL, and there are no errors in the inter-module connections described in HDL.

[0026] The circuit information acquisition unit 321 acquires circuit information, specifically the existing design document and the HDL description of the module connection identification information, from an external device of the connection error detection device 1. Specifically, first, the input / output unit 10 communicates with the external device of the connection error detection device 1 to acquire the existing design document and the HDL description of the module connection identification information from the external device. Next, the control unit 40 stores the existing design document and the HDL description of the module connection identification information acquired by the input / output unit 10 in the storage unit 20. Then, the circuit information acquisition unit 321 acquires the existing design document and the HDL description of the module connection identification information from the storage unit 20. A machine learning device 31 may also be provided in the logic circuit design device. The circuit information acquisition unit 321 generates training data by associating the extracted port information with the destination port information corresponding to that port information.

[0027] In other words, the circuit information acquisition unit 321 has the function of a data acquisition unit that acquires circuit information for generating learning data, and the function of a learning data generation unit that extracts port information and connection destination port information corresponding to said port information from the circuit information and generates learning data.

[0028] Figure 3 shows an example of port information acquired by the learning device according to Embodiment 1. In Figure 3, the port information is presented in a data table format in which the port information is stored in a data table. Figure 4 shows an example of destination port information acquired by the learning device according to Embodiment 1. In Figure 4, the destination port information is presented in a data table format in which the destination port information is stored in a data table.

[0029] In the port information shown in Figure 3, the port information for the first module described in the design document is grouped into a set, with the "port name," "input / output type," "function name," "interface classification," and "module name" linked to a management number, "No." Figure 3 shows three sets of port information classified by the management numbers "No1," "No2," and "No3."

[0030] In the connection port information shown in Figure 4, the port information for the second module described in the design document is associated with a management number "No." and consists of "Connection Port Name," "Input / Output Type," "Function Name," "Interface Classification," and "Module Name" as one set. Figure 4 shows three sets of port information corresponding to the management numbers "No1," "No2," and "No3."

[0031] The port information shown in Figure 3 and the destination port information shown in Figure 4 are associated with each other by a management number. That is, the destination port information labeled "No. 1" in the destination port information shown in Figure 4 corresponds to the destination port information labeled "No. 1" in the port information shown in Figure 3. Similarly, the destination port information labeled "No. 2" in the destination port information shown in Figure 4 corresponds to the destination port information labeled "No. 2" in the port information shown in Figure 3.

[0032] Note that the port information shown in Figure 3 and the destination port information shown in Figure 4 are examples only. The port information and destination port information may be information related to the correlation between ports, or information related to the correlation between modules. An example of information related to the correlation between modules is a block diagram between modules or a wiring diagram between modules.

[0033] The model generation unit 322 learns destination port information based on training data created from a combination of the port information of the source module and the destination port information of the destination module output from the circuit information acquisition unit 321. In other words, the model generation unit 322 has the function of a learning unit that generates a trained model 35 for inferring appropriate destination port information corresponding to the port information, using the port information of the HDL description extracted from the existing design document and the destination port information of the HDL description corresponding to the port information. Here, the training data is data that associates the port information and destination port information output from the circuit information acquisition unit 321 with each other.

[0034] More specifically, the model generation unit 322 learns the connection relationships between modules, which are the connection relationships between the port information and the corresponding destination port information, based on training data created from the combination of port information and destination port information output from the circuit information acquisition unit 321.

[0035] The trained model storage unit 34 stores the trained model 35 output from the model generation unit 322.

[0036] Next, the processing procedure of the learning device 32 will be explained using Figure 5. Figure 5 is a flowchart showing the processing procedure of the learning device according to Embodiment 1.

[0037] In step S110, the circuit information acquisition unit 321 acquires training data. Specifically, the circuit information acquisition unit 321 acquires module port information and destination port information corresponding to the port information as training data. The circuit information acquisition unit 321 acquires the existing design document, which is circuit information, and the HDL description of the inter-module connection identification information, which is information on connections between modules included in the existing design document and described in HDL. From the existing design document and the HDL description of the inter-module connection identification information, the circuit information acquisition unit 321 extracts the port information included in the existing design document and the destination port information corresponding to the port information, and acquires them as training data. The circuit information acquisition unit 321 outputs the training data to the model generation unit 322.

[0038] In the above, it was assumed that the existing design document and the HDL description of the inter-module connection identification information would be acquired simultaneously. However, it is sufficient if the existing design document and the HDL description of the inter-module connection identification information can be input in association with each other, and the data for the existing design document and the HDL description of the inter-module connection identification information may be acquired at different times. In other words, the circuit information acquisition unit 321 may acquire the existing design document and the HDL description of the inter-module connection identification information at any time, as long as the port information and the corresponding destination port information are extracted and associated.

[0039] In step S120, the model generation unit 322 performs a learning process according to the learning data, which is a combination of port information and corresponding destination port information obtained by the circuit information acquisition unit 321. The model generation unit 322 learns the destination ports using so-called supervised learning according to the learning data and generates a trained model 35.

[0040] In step S130, the trained model storage unit 34 stores the trained model 35. That is, the model generation unit 322 causes the generated trained model 35 to be stored in the trained model storage unit 34.

[0041] The model generation unit 322 can use any known learning algorithm, such as supervised learning, unsupervised learning, or reinforcement learning. As an example, we will describe the case where the model generation unit 322 performs supervised learning using a neural network.

[0042] The model generation unit 322 learns destination port information, for example, by supervised learning according to a neural network model. Here, supervised learning is a method in which a learning device is given pairs of input and result (label) data, learns features in that training data, and infers the result from the input.

[0043] A neural network consists of an input layer made up of multiple neurons, a hidden layer (intermediate layer) also made up of multiple neurons, and an output layer also made up of multiple neurons. The hidden layer can be one or more layers.

[0044] Figure 6 shows the configuration of the neural network used in the learning device according to Embodiment 1. For example, in a three-layer neural network as shown in Figure 6, when multiple data are input to input layers X1 to X3, these values ​​are multiplied by weights w11 to w16 and input to hidden layers Y1 to Y2, and the result is further multiplied by weights w21 to w26 and output from output layers Z1 to Z3. This output result varies depending on the values ​​of weights w11 to w16 and weights w21 to w26.

[0045] In Embodiment 1, the neural network learns the destination port information through so-called supervised learning, according to training data (dataset) created based on the combination of port information acquired by the circuit information acquisition unit 321 and the destination port information corresponding to said port information.

[0046] In other words, the neural network learns by inputting port information into input layers X1 to X3 and adjusting the weights w11 to w16 and w21 to w26 so that the output from output layers Z1 to Z3 approaches the destination port information corresponding to the input port information.

[0047] The model generation unit 322 generates and outputs a trained model 35 by performing the training described above.

[0048] Figure 7 shows the configuration of the inference device according to Embodiment 1. The inference device 33 comprises a circuit information acquisition unit 331, an inference unit 332, and a comparison unit 333. The circuit information acquisition unit 331 is the second circuit information acquisition unit in the connection error detection device 1. The inference unit 332 is connected to the learned model storage unit 34.

[0049] The circuit information acquisition unit 331 acquires a newly created design document, which is a newly created design document, and an HDL description of module connection identification information, which is information about the connections between modules included in the new design document and is written in HDL. From the new design document and the HDL description of module connection identification information, it extracts and acquires circuit information that includes the port information of the source module included in the new design document and the destination port information of the destination module included in the new design document, which corresponds to the port information of the source module.

[0050] A new design document is a design document that has been newly created and whose logic circuit design is not yet complete. It contains information about connections between modules in HDL description and is a design document that is subject to error detection for errors in the HDL description of connections between modules.

[0051] The circuit information acquisition unit 331 acquires the new design document and the HDL description of the inter-module connection identification information from an external device of the connection error detection device 1. Specifically, first the input / output unit 10 communicates with the external device of the connection error detection device 1 to acquire the new design document and the HDL description of the inter-module connection identification information from the external device. Next, the control unit 40 stores the new design document and the HDL description of the inter-module connection identification information acquired by the input / output unit 10 in the storage unit 20. Then, the circuit information acquisition unit 331 acquires the new design document and the HDL description of the inter-module connection identification information from the storage unit 20. Note that the inference device 33 may be provided in the logic circuit design device.

[0052] The circuit information acquisition unit 331 transmits the port information extracted from the new design document and the HDL description of the inter-module connection identification information to the inference unit 332 as inference data. The circuit information acquisition unit 331 also transmits the destination port information extracted from the new design document and the HDL description of the inter-module connection identification information to the comparison unit 333.

[0053] The inference unit 332 outputs destination port information using the trained model 35. The inference unit 332 reads the trained model 35 from the trained model storage unit 34. The inference unit 332 inputs the port information, which is inference data output from the circuit information acquisition unit 331, into the trained model 35. As a result, the inference unit 332 infers the destination port information. In other words, the inference unit 332 can output destination port information corresponding to the inference data port information, which is the inference result inferred from the port information, by inputting the port information, which is inference data for inferring destination port information, acquired by the circuit information acquisition unit 331, into the trained model 35 for inferring destination port information.

[0054] The comparison unit 333 compares the first destination port information, which is the destination port information output from the circuit information acquisition unit 331, with the second destination port information, which is the destination port information output from the inference unit 332, and outputs the comparison result. In other words, the comparison unit 333 compares the first destination port information extracted from the new design document with the second destination port information, which is the inference result inferred using the trained model 35 in the comparison unit 333, and outputs the comparison result.

[0055] Next, using Figure 8, the processing procedure for the inference process to obtain destination port information in the inference device 33 will be described. Figure 8 is a flowchart showing the processing procedure for the inference process by the inference device according to Embodiment 1.

[0056] In step S210, the circuit information acquisition unit 331 acquires port information, which is inference data, and destination port information corresponding to the port information. Specifically, the circuit information acquisition unit 331 acquires a new design document, which is circuit information, and an HDL description of inter-module connection identification information, which is information on connections between modules included in the new design document and is written in HDL. From the new design document and the HDL description of inter-module connection identification information, the unit extracts and acquires the port information of the modules included in the new design document and destination port information corresponding to the port information.

[0057] In step S220, the inference unit 332 inputs the port information, which is inference data acquired by the circuit information acquisition unit 331, into the trained model 35 stored in the trained model storage unit 34, and obtains the destination port information corresponding to the input port information as an inference result obtained by the trained model 35.

[0058] In step S230, the inference unit 332 outputs the destination port information, which is the inference result obtained by the trained model 35, as text data to the comparison unit 333.

[0059] The inference results obtained by the trained model 35 are inference data acquired by the circuit information acquisition unit 331, and are destination port information corresponding to the port information extracted in step S210 from the new design document and the HDL description of the inter-module connection identification information.

[0060] In step S240, the comparison unit 333 compares the destination port information, which is the inference result input from the inference unit 332, with the destination port information input from the circuit information acquisition unit 331. That is, the comparison unit 333 compares the first destination port information, which is the destination port information input from the circuit information acquisition unit 331, with the second destination port information, which is the inference result input from the inference unit 332.

[0061] In step S250, the comparison unit 333 outputs the comparison result information between the first destination port information and the second destination port information to the display unit 50 and the storage unit 20. The display unit 50 receives the comparison result information transmitted from the comparison unit 333 and displays the comparison result information between the first destination port information and the second destination port information based on the comparison result information. The storage unit 20 receives the comparison result information transmitted from the comparison unit 333 and stores the comparison result information. The comparison unit 333 may also transmit the comparison result information to a logic circuit design device (not shown).

[0062] The comparison unit 333 may output the comparison result information as text data. Alternatively, the comparison unit 333 may output the comparison result information as data table format information in which the comparison result information is stored in a data table.

[0063] The comparison results may be presented as a numerical representation of the difference between the two compared destination port information, for example, expressed as a percentage from 0% to 100%, or as an extracted representation of the difference between the two compared destination port information.

[0064] Figure 9 shows an example of destination port comparison result information output from the inference device according to Embodiment 1. In Figure 9, the destination port comparison result information, which is the comparison result of the two destination port information that has been compared, is summarized and shown in data table format. The destination port comparison result information is information output from the comparison unit 333 that shows the comparison result between the first destination port information and the second destination port information.

[0065] In the port information shown in Figure 9, the "port name," "first destination port information," "second destination port information," and "matching degree," extracted from the first destination port information output from the circuit information acquisition unit 331, are linked to a management number, "No," to form one set. Figure 9 shows the comparison results of three sets classified by the management numbers "No1," "No2," and "No3."

[0066] The "degree of agreement" is the degree of agreement between the destination port information, which is the inference result input from the inference unit 332, and the destination port information, which is input from the circuit information acquisition unit 331, and is shown as a numerical value.

[0067] In Figure 9, the comparison information for management number "No. 3" shows that the "Function Name" in the first destination port information is "Read Signal," while the "Function Name" in the second destination port information is "Write Signal," allowing us to confirm the difference between the first and second destination port information. Furthermore, in Figure 9, the comparison information for management number "No. 3" shows a "Severity of Match" of "40%," confirming that the first and second destination port information do not match.

[0068] Therefore, the comparison unit 333 can extract potentially erroneous locations in the HDL description of inter-module connections in a new document based on the destination port information obtained by inputting the port information, which is inference data, into the trained model 35, and present them to the user, the designer.

[0069] By viewing the comparison results between the first and second connection destination port information displayed on the display unit 50, the user can easily and reliably confirm connection errors between modules. This allows the user to review the logic circuit description in the new design document and correct the logic circuit description in the new design document.

[0070] The learning device 32 and the inference device 33 are used to learn and infer destination port information, but the learning device 32 and the inference device 33 may be separate devices from the connection error detection device 1, for example, connected to the connection error detection device 1 via a network such as the Internet. Also, at least one of the learning device 32 and the inference device 33 may be connected to the connection error detection device 1 via a network, for example. Furthermore, at least one of the learning device 32 and the inference device 33 may reside on a cloud server. Also, at least one of the learning device 32 and the inference device 33 may be built into the connection error detection device 1.

[0071] Furthermore, although Embodiment 1 was described as outputting destination port information using a trained model 35 learned by the model generation unit 322 of the connection error detection device 1, it is also possible to obtain a trained model from another external device such as another connection error detection device 1 and output destination port information based on this trained model.

[0072] Furthermore, while Embodiment 1 described a case where supervised learning is applied to the learning algorithm used by the model generation unit 322, it is not limited to this. In addition to supervised learning, reinforcement learning, unsupervised learning, or semi-supervised learning can also be applied to the learning algorithm.

[0073] Furthermore, the model generation unit 322 may learn destination port information according to training data created for multiple HDL descriptions. The model generation unit 322 may acquire training data from multiple existing design documents and HDL descriptions of inter-module connection identification information used in the same large-scale integrated circuit (LSI), or it may learn destination port information using training data collected from existing design documents and HDL descriptions of inter-module connection identification information used in different LSIs. It is also possible to add or remove HDL descriptions of inter-module connection identification information from which training data is collected. In addition, a learning device that has learned destination port information for a certain logic circuit may be applied to an HDL description of another inter-module connection identification information, and the destination port information for that other HDL description of inter-module connection identification information may be relearned and updated.

[0074] Furthermore, the learning algorithm used in the model generation unit 322 can be deep learning, which learns to extract the features themselves, or machine learning can be performed according to other known methods, such as support vector machines.

[0075] According to the connection error detection device 1 of the above-described embodiment 1, the device includes a connection error detection processing unit that detects potentially erroneous locations in the information on connections between modules included in a design document, which is described in a hardware description language. The connection error detection processing unit obtains circuit information from an existing design document in which the logic circuit design has been completed and a description of inter-module connection identification information, which is information on connections between modules included in the existing design document and is described in a hardware description language, which includes port information of the source module included in the existing design document and destination port information of the destination module included in the existing design document that corresponds to the port information of the source module in the existing design document. The device learns the connection relationship between the source module and the destination module using the circuit information. Based on the learning result of the connection relationship between modules, the device infers destination port information of the destination module included in the newly created design document, which corresponds to the port information of the source module included in the newly created design document, from the port information of the source module included in the newly created design document. The device then compares the destination port information corresponding to the port information in the newly created design document with the destination port information inferred based on the learning result of the connection relationship between modules and outputs the comparison result.

[0076] Furthermore, according to the connection error detection device 1 of the above-described embodiment 1, a learning device is realized that includes a first circuit information acquisition unit that acquires learning data from an existing design document in which logic circuit design has been completed and a description in a hardware description language of inter-module connection identification information which is information on connections between modules included in the existing design document and is described in a hardware description language, and which includes port information of the source module included in the existing design document and destination port information of the destination module included in the existing design document that corresponds to the port information, and a model generation unit that generates a trained model for inferring destination port information corresponding to the port information from the port information using the learning data.

[0077] Furthermore, according to the connection error detection device 1 of the above-described embodiment 1, an inference device is realized that includes a second circuit information acquisition unit that acquires port information of a source module included in a new design document and destination port information of a destination module included in a new design document, which corresponds to the port information, from a newly created new design document and a description in hardware description language of inter-module connection identification information, which is information on connections between modules included in the new design document and is described in hardware description language; and an inference unit that infers destination port information corresponding to the port information from the port information acquired by the second circuit information acquisition unit using a trained model for inferring destination port information corresponding to the port information from the port information.

[0078] The connection error detection device 1 according to the above-described embodiment 1 has a learning device 32 that acquires training data including port information of the source module and destination port information of the destination module from an existing design document and an HDL description of inter-module connection identification information, and generates a trained model for inferring destination port information corresponding to the port information from the port information using the training data.The connection error detection device 1 then has an inference device that acquires port information of the source module included in the new design document and first destination port information of the destination module included in the new design document from a new design document and an HDL description of inter-module connection identification information, and uses the trained model for inferring destination port information corresponding to the port information to infer second destination port information from the port information, compares the first destination port information and the second destination port information and outputs the comparison result.

[0079] The connection error detection device 1, having this configuration, can use machine learning to extract and output potentially erroneous locations in the inter-module connections of the HDL description in a newly created design document. As a result, the connection error detection device 1 can easily check for errors in the HDL description of inter-module connections in logic circuit design using a hardware description language, thereby reducing the burden on the designer.

[0080] Furthermore, the connection error detection device 1 can automatically detect errors in the inter-module connections of the HDL description before performing formal verification (formal verification) and simulation verification (functional verification), thereby reducing the occurrence of rework due to the discovery of defects in later processes. In addition, the connection error detection device 1 can mechanically and automatically detect errors in the inter-module connections of the HDL description without human intervention, thereby reducing the man-hours required for logic circuit design.

[0081] Therefore, the connection error detection device 1 according to Embodiment 1 has the effect of being able to detect potentially error-prone locations in the description of inter-module connections using a hardware description language in logic circuit design using a hardware description language.

[0082] Next, the hardware configuration of the control unit 80 according to Embodiment 1 will be described. The control unit 80 according to Embodiment 1 corresponds to the connection error detection processing unit 30 and the control unit 40 of the connection error detection device 1 according to Embodiment 1, respectively. Each function of the control unit 80 according to Embodiment 1 is realized by a processing circuit. The processing circuit may be dedicated hardware, or it may be a processing unit that executes a program stored in a memory device.

[0083] When the processing circuit is dedicated hardware, the processing circuit may be a single circuit, a complex circuit, a programmed processor, a parallel programmed processor, an application-specific integrated circuit, a field-programmable gate array, or a combination thereof. Figure 10 shows a configuration in which each function of the control unit 80 according to Embodiment 1 is realized in hardware. The processing circuit 81 incorporates a logic circuit 81a that realizes the functions of the control unit 80.

[0084] If the processing circuit 81 is a processing unit, the functions of the control unit 80 are realized by software, firmware, or a combination of software and firmware.

[0085] Figure 11 shows a configuration in which each function of the control unit 80 according to Embodiment 1 is implemented by software. The processing circuit 81 includes a processor 811 that executes program 81b, a random access memory 812 used by the processor 811 as a work area, and a storage device 813 that stores program 81b. The processor 811 loads program 81b stored in the storage device 813 onto the random access memory 812 and executes it, thereby realizing the functions of the control unit 80. The software or firmware is written in a programming language and stored in the storage device 813. The processor 811 can be a central processing unit, but is not limited to that. The storage device 813 can be a semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), or EEPROM (Electrically Erasable Programmable Read Only Memory). The semiconductor memory may be non-volatile memory or volatile memory. Furthermore, the storage device 813 can be a magnetic disk, flexible disk, optical disk, compact disk, minidisc, or DVD (Digital Versatile Disc) in addition to semiconductor memory. The processor 811 may output data such as calculation results to the storage device 813 for storage, or it may store such data in an auxiliary storage device (not shown) via the random access memory 812. By integrating the processor 811, random access memory 812, and storage device 813 onto a single chip, the functions of the control unit 80 can be realized by a microcomputer.

[0086] The processing circuit 81 realizes the functions of the control unit 80 by reading and executing the program 81b stored in the memory device 813. The program 81b can also be described as instructing the computer to execute the procedures and methods for realizing the functions of the control unit 80.

[0087] Furthermore, the processing circuit 81 may implement some of the functions of the control unit 80 using dedicated hardware, and some of the functions of the control unit 80 using software or firmware.

[0088] Thus, the processing circuit 81 can realize each of the above-mentioned functions through hardware, software, firmware, or a combination thereof.

[0089] The configurations shown in the above embodiments are merely examples, and can be combined with other known technologies. It is also possible to omit or modify parts of the configuration without departing from the gist of the invention. [Explanation of symbols]

[0090] 1 Connection error detection device, 10 Input / Output unit, 20 Storage unit, 30 Connection error detection processing unit, 31 Machine learning device, 32 Learning device, 33 Inference device, 34 Trained model storage unit, 35 Trained model, 40, 80 Control unit, 50 Display unit, 81 Processing circuit, 81a Logic circuit, 81b Program, 321, 331 Circuit information acquisition unit, 322 Model generation unit, 332 Inference unit, 333 Comparison unit, 811 Processor, 812 Random access memory, 813 Storage device.

Claims

1. It includes a connection error detection processing unit that detects potentially erroneous locations in the connection information between modules included in the design document, which is described using a hardware description language. The aforementioned connection error detection processing unit, From an existing design document in which the logic circuit design has been completed, and a description in a hardware description language of module connection identification information which is information on connections between modules included in the existing design document and is described in a hardware description language, circuit information is obtained that includes port information of the source module included in the existing design document and destination port information of the destination module included in the existing design document which corresponds to the port information of the source module in the existing design document, and the connection relationship between the source module and the destination module is learned using the circuit information, Based on the learning results of the connection relationships between the modules, the destination port information of the destination module included in the newly created design document is inferred from the port information of the source module included in the newly created design document, and the destination port information corresponding to said port information is inferred. The process involves comparing the destination port information corresponding to the port information in the aforementioned new design document with the destination port information inferred based on the learning results of the connection relationships between the modules, and outputting the comparison result. A connection error detection device characterized by the following.

2. A first circuit information acquisition unit acquires learning data from the existing design document and the description of the inter-module connection identification information in a hardware description language, including the port information of the source module in the existing design document and the destination port information of the destination module in the existing design document corresponding to the port information, A model generation unit generates a trained model for inferring destination port information corresponding to port information from port information in the new design document using the aforementioned training data, The learning device has the following features: The connection error detection device according to claim 1, characterized by the following:

3. A second circuit information acquisition unit acquires, from the aforementioned new design document and the description of the inter-module connection identification information in hardware description language, the port information of the source module included in the new design document and the destination port information of the destination module included in the new design document, which corresponds to the port information, first destination port information. An inference unit that uses a trained model for inferring destination port information corresponding to the port information from the port information in the aforementioned new design document, infers a second destination port information, which is destination port information corresponding to the port information, from the port information acquired by the second circuit information acquisition unit, The inference device is equipped with the following features: A connection error detection device according to claim 1 or 2, characterized by the above.

4. The system includes a comparison unit that compares the first destination port information acquired by the second circuit information acquisition unit with the second destination port information inferred by the inference unit and outputs a comparison result. The connection error detection device according to claim 3, characterized by the following:

5. A first circuit information acquisition unit acquires learning data from an existing design document in which the logic circuit design has been completed, and a description in a hardware description language of inter-module connection identification information which is information on connections between modules included in the existing design document and is described in a hardware description language, the learning data includes port information of the source module included in the existing design document and destination port information of the destination module included in the existing design document which corresponds to the port information, A model generation unit generates a trained model for inferring destination port information corresponding to the port information from the port information using the aforementioned training data, A learning device characterized by being equipped with the following features.

6. A second circuit information acquisition unit acquires, from a newly created new design document and a description in a hardware description language of inter-module connection identification information, which is information about the connections between modules included in the new design document and is described in a hardware description language, the port information of the source module included in the new design document and the destination port information of the destination module included in the new design document that corresponds to the port information, An inference unit that infers the destination port information corresponding to the port information from the port information acquired by the second circuit information acquisition unit, using a trained model for inferring the destination port information corresponding to the port information from the port information, An inference device characterized by comprising:

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