Semiconductor memory device and method for storing data in a semiconductor memory device

Abstract

To provide a semiconductor memory device that requires a short time to store data, and a method for storing data in a semiconductor memory device. [Solution] The circuit in the semiconductor memory device shifts the threshold voltage of each of the second plurality of memory cells among the first plurality of memory cells by a uniform amount. The circuit then identifies which of the two or more voltage ranges, separated by a read level of 1 or more, the threshold voltage of each of the second plurality of memory cells is in. For the third plurality of memory cells among the second plurality of memory cells, the circuit selects a plurality of memory cells that are included in one group and applies a single program pulse to the first word line with a voltage corresponding to the voltage range of one group, performing this operation for each group of memory cells that share a common voltage range among the two or more voltage ranges.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a data storage method for a semiconductor memory device.

Background Art

[0002] As a semiconductor memory device, a NAND type flash memory capable of storing a plurality of bits of data per memory cell is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor memory device and a data storage method for a semiconductor memory device with a short data storage time.

Means for Solving the Problems

[0005] A semiconductor memory device according to one embodiment comprises a first plurality of memory cells and a circuit. The gate of each of the first plurality of memory cells is connected to a first word line. The circuit performs a first operation to set the threshold voltage of each of the first plurality of memory cells to a first state corresponding to data among a plurality of first states. In the first operation, the circuit operates as follows: The circuit shifts the threshold voltage of each of the second plurality of memory cells among the first plurality of memory cells by a uniform amount by applying a program pulse of a first voltage to the first word line. Then, after applying the program pulse of the first voltage, the circuit determines which of the two or more voltage ranges separated by one or more read levels the threshold voltage of each of the second plurality of memory cells is in by performing a read operation on each of the second plurality of memory cells using one or more different read levels. The circuit then sets the threshold voltage of the third plurality of memory cells to the second state by selecting multiple memory cells included in one group and applying a single program pulse to the first word line with a voltage corresponding to the voltage range of one group, for each group of memory cells that share a common voltage range among two or more voltage ranges. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing an example configuration of a memory system according to the first embodiment. [Figure 2] A diagram showing an example of the configuration of a memory chip according to the first embodiment. [Figure 3] A diagram showing the circuit configuration of a block according to the first embodiment. [Figure 4] A diagram illustrating an example of data coding according to the first embodiment. [Figure 5] A diagram showing the potential change of each wire during program operation according to the first embodiment. [Figure 6]A circuit diagram showing the state of the NAND string during program operation according to the first embodiment. [Figure 7] This figure shows the potential change of each wire when a single lead-level voltage is applied according to the first embodiment. [Figure 8] This is a diagram illustrating the two-stage light operation according to the first embodiment. [Figure 9] This is a schematic diagram illustrating the first light operation according to the first embodiment. [Figure 10] A schematic diagram illustrating the voltage of the program pulse applied to the selected word line in the first write operation according to the first embodiment. [Figure 11] A diagram illustrating the Pass Write method according to the first embodiment. [Figure 12] A diagram illustrating the Foggy&Fine method according to the first embodiment. [Figure 13] A flowchart illustrating an example of write operation in the memory chip CP according to the first embodiment. [Figure 14] A diagram showing the potential change of each wire during QPW operation according to the second embodiment. [Figure 15] A schematic diagram illustrating the voltage of the program pulse applied to the selected word line in the first write operation according to the second embodiment. [Modes for carrying out the invention]

[0007] The semiconductor memory device and the data storage method for the semiconductor memory device according to the embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0008] (First Embodiment) Figure 1 shows an example of the configuration of a memory system according to the first embodiment.

[0009] As shown in FIG. 1, the memory system 1 is connectable to a host device 300. The host device 300 may be, for example, a server, a personal computer, or a mobile information processing device. The memory system 1 functions as an external storage device of the host device 300. The host device 300 can issue various requests to the memory system 1. The various requests include write requests and read requests.

[0010] The memory system 1 includes a NAND flash memory 100 and a controller 200. The NAND flash memory 100 includes one or more memory chips CP. Each memory chip CP is an example of a semiconductor memory device.

[0011] One or more channels are connected to the controller 200, and the controller 200 and one or more memory chips CP are interconnected via one or more channels.

[0012] Here, the memory system 1 includes memory chips CP0-0, CP0-1, CP0-2, CP0-3, CP1-0, CP1-1, CP1-2, CP1-3 as one or more memory chips CP, and includes channels ch^0, ch^1 as one or more channels. The memory chips CP0-0, CP0-1, CP0-2, CP0-3 are connected to the controller 200 via the channel ch^0. The memory chips CP1-0, CP1-1, CP1-2, CP1-3 are connected to the controller 200 via the channel ch^1. Note that the number of memory chips CP included in the memory system 1 is not limited to 8. The number of channels connected to the controller 200 is not limited to 2. Also, the connection relationship between the controller 200 and one or more memory chips CP is not limited to the above-described relationship.

[0013] Each memory chip CP includes a plurality of memory cell transistors and can store data in a non-volatile manner.

[0014] The controller 200 includes a host interface circuit 201, a RAM (Random Access Memory) 202, a CPU (Central Processing Unit) 203, a buffer memory 204, a memory interface circuit 205, and an ECC (Error-Correcting Code) circuit 206.

[0015] The controller 200 can be configured as, for example, a SoC (System-On-a-Chip). The controller 200 may be composed of a plurality of chips. Instead of the CPU 203, the controller 200 may include an FPGA (field-programmable gate array) or an ASIC (application specific integrated circuit). That is, the controller 200 can be configured by software, hardware, or a combination thereof. The RAM 202 may be disposed outside the controller 200.

[0016] The host interface circuit 201 is connected to the host device 300 via a bus compliant with, for example, the SATA (Serial Advanced Technology Attachment) standard, the SAS (Serial Attached SCSI) standard, or the PCI (Peripheral Components Interconnect) Express (TM) and the like. The host interface circuit 201 controls the communication between the controller 200 and the host device 300. Note that the standard to which the bus connecting the host interface circuit 201 and the host device 300 complies is not limited to these.

[0017] The memory interface circuit 205 is connected to eight memory chips CP via two channels and controls the communication between the controller 200 and each memory chip CP.

[0018] The CPU 203 controls the operation of the controller 200.

[0019] RAM 202 is used as a workspace for the CPU 203. Buffer memory 204 temporarily stores data sent to and received from the memory chip CP. RAM 202 and buffer memory 204 may be composed of, for example, DRAM (dynamic random access memory), SRAM (static random access memory), or a combination thereof. However, the types of memory constituting RAM 202 and buffer memory 204 are not limited to these.

[0020] The ECC circuit 206 performs error correction coding on data written to the NAND flash memory 100. The ECC circuit 206 also performs error correction on data read from the NAND flash memory 100.

[0021] The ECC circuit 206 may be included in the memory interface circuit 205. Some or all of the functions of the ECC circuit 206 may be implemented by the CPU 203.

[0022] Figure 2 shows an example of the configuration of a memory chip CP according to the first embodiment. Note that the multiple memory chips CP constituting the NAND flash memory 100 have a common configuration.

[0023] The memory chip CP comprises a NAND I / O interface 11, a control circuit 12, a NAND memory cell array 13, a sense amplifier circuit 14, and a word line driver 15. The sense amplifier circuit 14 includes a data latch circuit 16. The control circuit 12, the sense amplifier circuit 14, and the word line driver 15 constitute an access circuit 30. The access circuit 30 is an example of a circuit.

[0024] The NAND I / O interface 11 receives various signals from the controller 200. These signals include commands, addresses, or data.

[0025] The control circuit 12 controls the operation of the memory chip CP in response to signals received by the NAND I / O interface 11. The control circuit 12 controls the word line driver 15 and the sense amplifier circuit 14 to perform write operations, read operations, erase operations, etc. A write operation is an operation to store data in the NAND memory cell array 13. A read operation is an operation to retrieve data stored in the NAND memory cell array 13 from the NAND memory cell array 13. An erase operation is an operation to erase data stored in the NAND memory cell array 13 from the NAND memory cell array 13.

[0026] When a write command is input, the control circuit 12 controls the sense amplifier circuit 14 and the word line driver 15 to store the data input in conjunction with the write command at a specified address on the NAND memory cell array 13. Furthermore, when a read command is input, the control circuit 12 controls the sense amplifier circuit 14 and the word line driver 15 to retrieve data from a specified address on the NAND memory cell array 13.

[0027] For example, the control circuit 12 controls the voltages applied to multiple word lines WL by the word line driver 15 and the voltages applied to multiple bit lines BL by the sense amplifier circuit 14 (bit line voltages) in order to store data in the memory cell transistor MT included in the NAND memory cell array 13.

[0028] The sense amplifier circuit 14 is configured to independently apply voltage (or current) to multiple bit lines BL and to independently detect the voltage (or current) of multiple bit lines BL.

[0029] Furthermore, the sense amplifier circuit 14 uses the data latch circuit 16 when the light is in operation. Details on how to use the data latch circuit 16 will be described later.

[0030] The word line driver 15 is configured to be able to apply voltage independently to multiple word lines and selected gate lines.

[0031] The NAND memory cell array 13 includes multiple block blocks (BLKs). A block block is a subarray that serves as the unit for erase operations. In other words, data written to one block block is erased all at once.

[0032] Figure 3 shows the circuit configuration of a block BLK according to the first embodiment. Each block BLK has the same configuration. A block BLK has, for example, four string units SU0 to SU3. Each string unit SU contains multiple NAND strings 114.

[0033] Each NAND string 114 contains, for example, 64 memory cell transistors MT (MT0 to MT63) and selection transistors ST1 and ST2. Each memory cell transistor MT has a control gate and a charge storage layer to non-volatilely retain data. The 64 memory cell transistors MT (MT0 to MT63) are connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. The memory cell transistors MT may be of the MONOS (Metal Oxide Nitride Oxide Silicon) type with an insulating film in the charge storage layer, or of the FG (Floating Gate) type with a conductive film in the charge storage layer. Furthermore, the number of memory cell transistors MT in the NAND string 114 is not limited to 64.

[0034] The gates of the selection transistor ST1 in each of the string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. In contrast, the gates of the selection transistor ST2 in each of the string units SU0 to SU3 are connected in common to, for example, the selection gate line SGS. The gates of the selection transistor ST2 in each of the string units SU0 to SU3 may be connected to different selection gate lines SGS0 to SGS3 (not shown) for each string unit SU. The control gates of the memory cell transistors MT0 to MT13 within the same block BLK are connected in common to the word lines WL0 to WL13, respectively.

[0035] The drain of the selection transistor ST1 of each NAND string 114 within the string unit SU is connected to a different bit line BL (BL0 to BL(L-1), where L is a natural number greater than or equal to 2). Furthermore, the bit line BL connects one NAND string 114 within each string unit SU to multiple blocks BLK. Additionally, the source of each selection transistor ST2 is connected to the source line SL.

[0036] In other words, a string unit SU is a collection of NAND strings 114 connected to different bit lines BL and the same selected gate line SGD. A block BLK is a collection of multiple string units SU that share a common word line WL. The NAND memory cell array 13 is a collection of multiple block BLK that share a common bit line BL.

[0037] As mentioned above, the data erasure operation on the NAND memory cell array 13 is performed in units of block BLK.

[0038] Furthermore, write operations to and read operations from the NAND memory cell array 13 are performed collectively on the memory cell transistor MT connected to a word line WL in a single string unit SU. Hereinafter, a group of memory cell transistors MT on which write and read operations are performed collectively will be called a memory cell group MCG. The collection of storage areas for 1 bit of data stored in each memory cell transistor MT included in a single memory cell group MCG will be called a page.

[0039] Hereafter, the memory cell transistor MT will be simply referred to as the memory cell.

[0040] Each memory cell can store n bits (n≧1) of data. When each memory cell stores n bits of data, the storage capacity per memory cell group (MCG) is equal to the size of n pages. The mode where n is 1 is called SLC (Single Level Cell) mode. The mode where n is 2 is called MLC (Multi Level Cell) mode. The mode where n is 3 is called TLC (Triple Level Cell) mode. The mode where n is 4 is called QLC (Quad Level Cell) mode.

[0041] The threshold voltage of each memory cell is controlled by the access circuit 30 to stay within a certain range. The controllable range of the threshold voltage is divided into a range of 2 to the power of n, and a different n-bit value is assigned to each range.

[0042] In the first embodiment, a mode in which n is 2 or greater is adopted. Hereafter, an example of a mode in which n is 2 or greater will be described in which the memory cell is used in TLC mode. Note that the first embodiment is not limited to systems in which the memory cell is used in TLC mode, but is applicable to systems in which the memory cell is used in any mode in which n is 2 or greater.

[0043] Figure 4 is a diagram illustrating an example of data coding according to the first embodiment.

[0044] As mentioned above, in TLC mode, 3 bits of data are stored per memory cell. The bits that make up the 3 bits of data stored in the memory cell are referred to as the upper bit, middle bit, and lower bit, according to their order. Of the three pages that a memory cell group MSG has, the page where the upper bits are stored is referred to as the upper page, the page where the middle bits are stored is referred to as the middle page, and the page where the lower bits are stored is referred to as the lower page.

[0045] According to the TLC mode, the range of possible threshold voltages is divided into eight ranges. These eight ranges, in order from lowest to highest threshold voltage, are called the “Er” state, “A” state, “B” state, “C” state, “D” state, “E” state, “F” state, and “G” state. The threshold voltage of each memory cell is controlled by the access circuit 30 so that it belongs to one of the “Er” state, “A” state, “B” state, “C” state, “D” state, “E” state, “F” state, and “G state.” As a result, when the number of memory cells is plotted against the threshold voltage, the memory cells ideally form a distribution of eight non-overlapping lobes, each belonging to a different state, as shown in the lower part of Figure 4. Hereafter, the distribution of memory cells for each state may simply be referred to as the state distribution.

[0046] The eight states correspond to 3 bits of data. The upper table in Figure 4 shows an example of the correspondence between states and 3 bits of data, i.e., data coding. In this example, the “Er” state corresponds to “111”, the “A” state corresponds to “110”, the “B” state corresponds to “100”, the “C” state corresponds to “000”, the “D” state corresponds to “010”, the “E” state corresponds to “011”, the “F” state corresponds to “001”, and the “G” state corresponds to “101”. Note that when the 3 bits of data are written as “abc”, “a” is the upper bit, “b” is the middle bit, and “c” is the lower bit. In this way, each memory cell can store data corresponding to the state to which its threshold voltage belongs. Note that the correspondence between states and data shown in Figure 4 is an example of data coding. Data coding is not limited to the example shown in this figure.

[0047] The threshold voltage is reduced to the "Er" state by the erase operation. The threshold voltage is then maintained in the "Er" state or increased to one of the "A", "B", "C", "D", "E", "F", and "G" states by the write operation.

[0048] In write operation, a programmed operation is performed that increases the threshold voltage by injecting electrons into the charge storage film (or maintains the threshold voltage by prohibiting injection). Below, the operation that increases the threshold voltage is referred to as the "0 program," and the bit line BL targeted by the "0" program is given "0" data. On the other hand, the operation that maintains the threshold voltage is referred to as the "1 program," and the bit line BL targeted by the "1" program is given "1" data.

[0049] Figure 5 shows the potential change of each wire during program operation according to the first embodiment. As shown in this figure, first the sense amplifier circuit 14 transfers program data to each bit line BL. A ground voltage Vss (e.g., 0V) is applied as an "L" level to the bit line BL to which "0" data is given. A write-protect voltage Vinhibit (e.g., 2.5V) is applied as an "H" level to the bit line BL to which "1" data is given.

[0050] The word line driver 15 also selects one of the blocks BLK and then selects one of the string units SU. Then, it applies, for example, 5V to the select gate line SGD of the selected string unit SU to turn on the select transistor ST1. On the other hand, it applies a voltage Vss to the select gate line SGS to turn off the select transistor ST2.

[0051] Furthermore, the word line driver 15 applies a voltage Vss to the non-selected string unit SU in the selection block BLK and to the select gate lines SGD and SGS of the non-selected string unit SU in the non-selected block BLK, thereby turning off the selection transistors ST1 and ST2.

[0052] Furthermore, the source line SL is set to, for example, 1V (a higher potential than the select gate line SGS).

[0053] Subsequently, the word line driver 15 sets the potential of the select gate line SGD in the select string unit SU in the select block BLK to, for example, 2.5V. This potential is such that the select transistor ST1 corresponding to the bit line BL given "0" data (0V) is turned on, but the select transistor ST1 corresponding to the bit line BL given "1" data (2.5V) is cut off.

[0054] The word line driver 15 selects one of the word lines WL in the selection block BLK, applies a voltage Vpgm to the selected word line, and applies a voltage Vpass_pgm to the other unselected word lines. The voltage Vpgm is a high voltage for injecting electrons into the charge storage film by tunneling, and Vpgm > Vpass_pgm. Figure 6 shows the state of the string unit SU at this time. Figure 6 is a circuit diagram showing the state of the NAND string 114 during program operation according to the first embodiment.

[0055] Figure 6 illustrates two NAND strings corresponding to the bit line BL programmed with "0" and the bit line BL programmed with "1". It also shows the state when word line WL3 is selected. In this figure, it is assumed that eight memory cells (MT0 to MT7) are connected to one NAND string 114.

[0056] As shown in Figure 6, the voltage Vpgm is applied to the selected word line WL3, and the voltage Vpass_pgm is applied to the unselected word lines WL0~WL2 and WL4~WL7.

[0057] Then, in the NAND string corresponding to the bit line BL targeted by the "0" program, the selection transistor ST1 is turned ON. As a result, the channel potential Vch of the memory cell MT3 connected to the selection word line WL3 becomes 0V. In other words, the potential difference between the gate and the channel increases, and as a result, electrons are injected into the charge storage film, raising the threshold of the memory cell MT3.

[0058] In the NAND string corresponding to the bit line BL targeted by the “1” program, the selection transistor ST1 is cut off. As a result, the channel of memory cell MT3 connected to the selection word line WL3 becomes electrically floating, and the channel potential Vch is raised to near voltage Vpgm due to capacitive coupling with the word line WL, etc. That is, the potential difference between the gate and the channel becomes small, and as a result, electrons are not injected into the charge storage film, and the threshold of memory cell MT3 is maintained.

[0059] Hereafter, a memory cell whose threshold voltage has been set to a certain state by program operation will sometimes be referred to as a memory cell belonging to that state. Also, the operation of providing "0" data to the bit line BL connected to a memory cell in order to program it with "0" will be referred to as selecting that memory cell.

[0060] Let's return to the explanation in Figure 4. A read level, which is a determination voltage used to determine data, is set between two adjacent states. For example, as illustrated in Figure 4, a read level VA is set between the "Er" state and the "A" state, a read level VB is set between the "A" state and the "B" state, a read level VC is set between the "B" state and the "C" state, a read level VD is set between the "C" state and the "D" state, a read level VE is set between the "D" state and the "E" state, a read level VF is set between the "E" state and the "F" state, and a read level VG is set between the "F" state and the "G" state.

[0061] During a read operation, the access circuit 30 sequentially applies voltages of multiple read levels to the selected word line and determines for each memory cell whether it is in a conductive state (in other words, on state) or a non-conductive state (in other words, off state) when the voltage of each read level is applied. Then, the access circuit 30 uses the determination result obtained for each read level used to determine the data associated with the state to which the memory cell belongs through logical operations. In other words, data is acquired based on a comparison between the threshold voltage of each memory cell and the read level.

[0062] Figure 7 shows the potential change of each wire when a single lead level voltage according to the first embodiment is applied.

[0063] The word line driver 15 selects the programmed block BLK and string unit SU, and applies, for example, 5V to the select gate line SGS in the selected block BLK and the select gate line SGD in the selected string unit SU. As a result, both the select transistor ST1 and the select transistor ST2 are turned on in the NAND string 114 contained in the selected string unit SU.

[0064] On the other hand, a voltage Vss is applied to the select gate line SGS in the unselected block BLK and to the select gate line SGD in the unselected string unit SU in the selected block BLK, thereby turning off the select transistors ST1 and / or ST2. As a result, in the NAND string included in the unselected string unit SU, at least the select transistor ST1 is turned off. In addition, in the NAND string 114 included in the unselected block BLK, both the select transistors ST1 and ST2 are turned off.

[0065] Furthermore, the word line driver 15 selects one of the word lines WL in the selection block BLK, applies a read-level voltage to the selected word line as voltage Vread, and applies voltage Vpass_read to the other unselected word lines. Voltage Vpass_read is the voltage required to turn on the memory cells MT connected to the unselected word lines regardless of their threshold voltages, and Vpass_read > Vread.

[0066] Then, the sense amplifier circuit 14 charges each bit line BL to voltage Vbl. Voltage Vbl is greater than the source line voltage Vsl, so Vbl > Vsl. As a result, in the NAND string contained in the selected string unit SU, current flows (or does not flow) from the bit line BL side to the source line SL side, depending on the threshold voltage of the memory cell MT connected to the selected word line. Based on whether or not this current flows, the sense amplifier circuit 14 determines whether each memory cell connected to the selected word line is in a conducting or non-conducting state.

[0067] During a read operation, the access circuit 30 determines the data stored in the memory cell by performing the operations shown in Figure 7 for each of the multiple read levels.

[0068] The threshold voltage of a memory cell can fluctuate due to various factors, including mutual interference between memory cells connected to adjacent bit lines. Therefore, a portion of the high-voltage or low-voltage side of the threshold voltage distribution for each state may fall outside the range between the two read levels corresponding to the boundary of that state.

[0069] If a portion of the high-voltage or low-voltage side of the threshold voltage distribution of a given state falls outside the range between two read levels corresponding to the boundary of that state, then during a read operation, incorrect data, i.e., an error, is read from the memory cell whose threshold voltage falls outside that range. The incorrect data is sent to the controller 200 and corrected by the ECC circuit 206 provided by the controller 200.

[0070] However, there is a limit to the number of error bits that can be corrected by the ECC circuit 206. Therefore, it is desirable to set the threshold voltage of each memory cell so that it does not exceed the range corresponding to the target state as much as possible during write operation.

[0071] To keep the threshold voltage of each memory cell as close as possible to the range corresponding to the target state, the memory chip CP performs the write operation in multiple stages. In the first embodiment, the memory chip CP performs a two-stage write operation. The first stage of the two-stage write operation is referred to as the first write operation. The second stage of the two-stage write operation is referred to as the second write operation.

[0072] In the first write operation, all bits of data (for example, 3 bits in the case of TLC) are coarsely written to the memory cell. That is, the threshold voltage of the memory cell is coarsely set according to the data of all bits. Subsequently, in the second write operation, all bits of data are precisely rewritten to that memory cell. That is, the threshold voltage of the memory cell is precisely set according to the data of all bits.

[0073] Figure 8 is a diagram illustrating the two-stage write operation according to the first embodiment. Figure 8 shows three graphs illustrating the change in the threshold voltage distribution of memory cells constituting one memory cell group MCG. In each graph, the horizontal axis represents voltage, and the vertical axis represents the number of memory cells. Here, the range from one voltage VX to another VY is denoted as the range VX-VY.

[0074] In the block blackout after the erase operation, the threshold voltage of all memory cells is in state "Er".

[0075] A first write operation is performed on the memory cell group MCG in the state after the erase operation. In the first write operation, the threshold voltage of each memory cell is roughly set to be as close as possible to the target state among the eight states "Er" to "G".

[0076] More specifically, ranges are provided that are slightly lower in voltage than the range VA-VB (VAf-VBf), slightly lower in voltage than the range VB-VC (VBf-VCf), slightly lower in voltage than the range VC-VC (VCf-VDf), slightly lower in voltage than the range VD-VC (VDf-VEf), slightly lower in voltage than the range VE-VC (VEf-VFf), slightly lower in voltage than the range VF-VG (VFf-VGf), and ranges greater than voltage BGf. Then, the threshold voltage of a memory cell whose target state is state "Er" is maintained, the threshold voltage of a memory cell whose target state is state "A" is set within the range VAf-VBf, the threshold voltage of a memory cell whose target state is state "B" is set within the range VBf-VCf, the threshold voltage of a memory cell whose target state is state "C" is set within the range VCf-VDf, the threshold voltage of a memory cell whose target state is state "D" is set within the range VDf-VEf, the threshold voltage of a memory cell whose target state is state "E" is set within the range VEf-VFf, the threshold voltage of a memory cell whose target state is state "F" is set within the range VFf-VGf, and the threshold voltage of a memory cell whose target state is state "G" is set to a voltage slightly greater than voltage VGf.

[0077] As a result, after the first light operation, lobe-shaped distributions are formed in each of the following ranges: range less than voltage VAf, range VAf-VBf, range VBf-VCf, range VCF-VDf, range VDf-VEf, range VFf-VFf, range VFf-VGf, and range greater than voltage BGf. The range less than voltage VAf is denoted as state "Erf", the range VAf-VBf as state "Af", the range VBf-VCf as state "Bf", the range VCf-VDf as state "Cf", the range VDf-VEf as state "Df", the range VEf-VFf as state "Ef", the range VFf-VGf as state "Ff", and the range greater than voltage BGf as state "Gf".

[0078] The states "Erf", "Af", "Bf", "Cf", "Df", "Ef", "Ff", and "Gf", which are the target states for the first write operation, are referred to as intermediate target states. The states "Er", "A", "B", "C", "D", "E", "F", and "G", which are the target states for the second write operation, are referred to as final target states. In the first write operation, the threshold voltage of a memory cell whose intermediate target state is state "Erf" is maintained at the same voltage. Therefore, state "Erf" is equivalent to state "Er".

[0079] In the first write operation, the threshold voltage of each memory cell is set more coarsely compared to the second write operation. Therefore, the threshold voltage distributions of states "Af", "Bf", "Cf", "Df", "Ef", "Ff", and "Gf" may fall outside their corresponding ranges.

[0080] In the second write operation, program operations and read operations to verify whether the threshold voltage of the memory cell has reached the final target state are repeated alternately. The read operation to verify whether the threshold voltage of the memory cell has reached the final target state is also called the verify operation. In the verify operation, for example, the operation described in Figure 7 is performed. In the program operation, regardless of what the final target state is, all memory cells whose threshold voltage has not yet reached the final target state are selected and a program pulse is applied to the word line WL. Furthermore, the voltage Vpgm of the program pulse is controlled so that the amount of threshold voltage shift per application of the program pulse is fine. This makes it possible to control the lobe-shaped distribution for each final target state so that it does not extend beyond the boundary of the final target state as much as possible. Therefore, the voltage width of the threshold voltage distribution for each state excluding the state "Erf" among all final target states (for example, Vw2 in Figure 8) is made narrower than the voltage width of the threshold voltage distribution for each state excluding the state "Er" among all intermediate target states (for example, Vw1 in Figure 8).

[0081] The following describes technologies that are comparable to the first embodiment. Technologies that are comparable to the first embodiment will be referred to as comparative examples.

[0082] In the comparative example, the program operation and verify operation are repeatedly performed in the first write operation, similar to the second write operation. The program pulse voltage Vpgm is controlled so that the threshold voltage shift per program operation is larger than the shift in the second write operation. As a result, the threshold voltage of each memory cell is set more coarsely to the intermediate target state compared to the second write operation.

[0083] Furthermore, in the comparative example, during program operation, regardless of the intermediate target state, all memory cells whose threshold voltage has not yet reached the intermediate target state are selected and a program pulse is applied to the word line WL. Therefore, memory cells whose intermediate target state is state "Gf" require a large number of program operations.

[0084] Thus, according to the comparative example, a verification operation is required for each program operation, and the number of necessary program operations is large. Therefore, according to the comparative example, the first write operation takes a lot of time.

[0085] In the first embodiment, in order to shorten the time required for the first write operation, the voltage of the program pulse is varied for each memory cell in the first write operation, according to the characteristics of the memory cell and the intermediate target state (which can also be called the final target).

[0086] Figure 9 is a schematic diagram illustrating the first light operation according to the first embodiment.

[0087] First, the access circuit 30 selects all memory cells in the memory cell group MCG targeted for write operation whose final target state is one of states "A" to "G" (in other words, all memory cells whose intermediate target state is one of states "Af" to "Gf"), and executes a program operation that applies a predetermined voltage Vpgm_init to the word line once. As a result, as shown in part (A) of Figure 9, the threshold voltage of all memory cells whose final target state is one of states "A" to "G" is shifted by a uniform amount to the higher voltage side. Consequently, the distribution of all memory cells whose final target state is one of states "A" to "G" forms a distribution D_int that is slightly shifted to the higher voltage side from the distribution of state "Er".

[0088] Next, the access circuit 30 divides the memory cells included in the distribution D_int into two or more subgroups according to the threshold voltage by performing a read operation using a read level of 1 or higher.

[0089] For example, in the example shown in part (B) of Figure 9, voltages Vgr1 and Vgr2 are used as read levels. Based on the results of read operations for each read level using voltages Vgr1 and Vgr2 respectively, the access circuit 30 identifies whether the threshold voltage of each memory cell included in distribution D_int is in a voltage range where the threshold voltage is less than voltage Vgr1, a voltage range from voltage Vgr1 to voltage Vgr2, or a voltage range where the threshold voltage is greater than voltage Vgr2. The access circuit 30 then classifies memory cells in the voltage range where the threshold voltage is less than voltage Vgr1 into subgroup Gr1, memory cells in the voltage range from voltage Vgr1 to voltage Vgr2 into subgroup Gr2, and memory cells in the voltage range where the threshold voltage is greater than voltage Vgr2 into subgroup Gr3.

[0090] In detail, the access circuit 30 selects all memory cells whose final target state is one of states "A" to "G", and performs a read operation using voltage Vgr1 as the read level, and a read operation using voltage Vgr2 as the read level. The access circuit 30 classifies memory cells that are determined to be conductive in the read operation using voltage Vgr1 as the read level into subgroup Gr1. The access circuit 30 classifies memory cells that are determined to be non-conductive in the read operation using voltage Vgr1 as the read level, and that are determined to be conductive in the read operation using voltage Vgr2 as the read level, into subgroup Gr2. The access circuit 30 classifies memory cells that are determined to be non-conductive in the read operation using voltage Vgr2 as the read level into subgroup Gr3. In this way, the memory cells are grouped into groups based on the voltage ranges that share a common threshold value among two or more voltage ranges separated by one or more read levels.

[0091] Hereafter, a read operation that groups data using one or more read levels as read levels will be referred to as a group read operation.

[0092] Through a group read operation, each memory cell included in the distribution D_int is classified into one of three subgroups Gr1 to Gr3, each with a different threshold voltage. The sense amplifier circuit 14 performs the determination of whether a memory cell is conducting or not, and the classification based on the determination result. The sense amplifier circuit 14 stores the classification result in the data latch circuit 16.

[0093] In the example shown in Figure 9, two voltages, Vgr1 and Vgr2, were used as read levels in the group read operation. The number of voltages used as read levels in the group read operation is not limited to two. When the number of voltages used as read levels is R (where R is an integer greater than or equal to 1), each of all memory cells whose final target state is one of states "A" to "G" is classified by the group read operation into (R+1) subgroups corresponding to (R+1) voltage ranges separated by R read levels.

[0094] There is a correlation between the program pulse voltage Vpgm and the threshold voltage displacement. The higher the program pulse voltage Vpgm, the greater the threshold voltage displacement. The lower the program pulse voltage Vpgm, the smaller the threshold voltage displacement.

[0095] Therefore, for multiple memory cells with the same intermediate target state, the access circuit 30 applies one program pulse to the selection word line for each subgroup, using a voltage Vpgm corresponding to the voltage range. For example, the access circuit 30 uses one program pulse of a certain voltage for a subgroup of memory cells whose threshold voltage is in the first voltage range. Then, for a subgroup whose threshold voltage is in the second voltage range, which is higher than the first voltage range, the access circuit 30 uses one program pulse of a lower voltage than the program pulse used for the subgroup of memory cells whose threshold voltage is in the first voltage range.

[0096] More specifically, the access circuit 30 selects a memory cell for each combination of target state and subgroup, and performs a programmed operation on the selected memory cell using a programmed pulse with a voltage corresponding to the combination of target state and subgroup.

[0097] For example, as shown in part (C) of Figure 9, the access circuit 30 selects a memory cell belonging to subgroup Gr1 of memory cells whose final target state is state "A" (in other words, memory cells whose intermediate target state is state "Af"), and applies a program pulse of voltage Vpgm_Gr1 to the selection word line. The access circuit 30 selects a memory cell belonging to subgroup Gr2 of memory cells whose final target state is state "A" (in other words, memory cells whose intermediate target state is state "Af"), and applies a program pulse of voltage Vpgm_Gr2 to the selection word line. The access circuit 30 selects a memory cell belonging to subgroup Gr3 of memory cells whose final target state is state "A" (in other words, memory cells whose intermediate target state is state "Af"), and applies a program pulse of voltage Vpgm_Gr3 to the selection word line.

[0098] Voltage Vpgm_Gr1 is the voltage that can set the threshold voltage of a memory cell belonging to subgroup Gr1 to state "Af" with the application of a single program pulse. Voltage Vpgm_Gr2 is the voltage that can set the threshold voltage of a memory cell belonging to subgroup Gr2 to state "Af" with the application of a single program pulse. Voltage Vpgm_Gr3 is the voltage that can set the threshold voltage of a memory cell belonging to subgroup Gr3 to state "Af" with the application of a single program pulse. Voltage Vpgm_Gr2 is lower than voltage Vpgm_Gr1, and voltage Vpgm_Gr3 is lower than voltage Vpgm_Gr2.

[0099] In this way, among the memory cells included in the distribution D_int, memory cells with lower threshold voltages use program pulses with higher voltages, which makes it possible to narrow the voltage width of the threshold voltage distribution of the intermediate target state compared to the voltage width of the distribution D_int.

[0100] The access circuit 30 also individually selects memory cells for each subgroup, similar to the memory cell with an intermediate target state of state "Af", for each of the memory cells with an intermediate target state of state "Bf", state "Cf", state "Df", state "Ef", state "Ff", and state "Gf", and applies a program pulse to the selected word line.

[0101] Hereafter, a combination of a certain state "S" (where S is one of A to G) and a subgroup Grx (where x is one of 1 to 3) will be denoted as the combination (S, Grx).

[0102] Figure 10 is a schematic diagram illustrating the voltage of the program pulse applied to the selected word line in the first write operation according to the first embodiment. In this figure, the horizontal axis represents time and the vertical axis represents voltage.

[0103] In the example shown in Figure 10, all memory cells of combination (Af, Gr1), all memory cells of combination (Af, Gr2), all memory cells of combination (Af, Gr3), all memory cells of combination (Bf, Gr1), all memory cells of combination (Bf, Gr2), all memory cells of combination (Bf, Gr3), all memory cells of combination (Cf, Gr1), all memory cells of combination (Cf, Gr2), all memory cells of combination (Cf, Gr3), all memory cells of combination (Df, Gr1), all memory cells of combination (Df, Gr2), and all memory cells of combination (Df, Gr3) The following are selected in this order: Morisel, all memory cells of combination (Ef, Gr1), all memory cells of combination (Ef, Gr2), all memory cells of combination (Ef, Gr3), all memory cells of combination (Ff, Gr1), all memory cells of combination (Ff, Gr2), all memory cells of combination (Ff, Gr3), all memory cells of combination (Gf, Gr1), all memory cells of combination (Gf, Gr2), and combination (Gf, Gr3). For each combination of target state and subgroup, one program pulse with a voltage corresponding to the combination of target state and subgroup is applied.

[0104] Thus, according to the first embodiment, in the first write operation, after the application of one program pulse of voltage Vpgm, program pulses are applied for a number of combinations of target states and subgroups, excluding state "Er". Furthermore, the verify operation can be eliminated. Therefore, the time required for the first write operation can be reduced compared to the comparative example in which the program operation and verify operation are repeatedly performed. As the time required for the first write operation is reduced, the time required for the write operation (i.e., the first write operation and the second write operation) is also reduced.

[0105] Note that the order in which the combinations of intermediate target states and subgroups are selected is not limited to the order shown in Figure 10.

[0106] When write operations are performed on multiple memory cell groups (MCGs) contained within a single block (BLK), the order in which the first write operations and second write operations are performed on the multiple memory cell groups (MCGs) can be set in various ways. Known write schemes that define the order in which the first and second write operations are performed on multiple memory cell groups (MCGs) include the Pass Write scheme and the Foggy & Fine scheme. In the first embodiment, either write scheme is applicable.

[0107] Figure 11 is a diagram illustrating the Pass Write method according to the first embodiment.

[0108] According to the Pass Write method, the first and second operations are performed on the memory cell group MCG of string unit SU0 connected to word line WL0, consisting of a first write operation and a second write operation following the first write operation. Next, the third and fourth operations are performed on the memory cell group MCG of string unit SU1 connected to word line WL0, consisting of a first write operation and a second write operation following the first write operation. Next, the fifth and sixth operations are performed on the memory cell group MCG of string unit SU2 connected to word line WL0, consisting of a first write operation and a second write operation following the first write operation. Next, the seventh and eighth operations are performed on the memory cell group MCG of string unit SU3 connected to word line WL0, consisting of a first write operation and a second write operation following the first write operation.

[0109] Once the first and second write operations for the memory cell group MCG of all string units SU connected to word line WL0 are completed, the ninth and tenth operations are performed on the memory cell group MCG of string unit SU0 connected to word line WL1, consisting of the first write operation and the second write operation following the first write operation. Next, the eleventh and twelfth operations are performed on the memory cell group MCG of string unit SU1 connected to word line WL1, consisting of the first write operation and the second write operation following the first write operation. Next, the thirteenth and fourteenth operations are performed on the memory cell group MCG of string unit SU2 connected to word line WL1, consisting of the first write operation and the second write operation following the first write operation. Next, the fifteenth and sixteenth operations are performed on the memory cell group MCG of string unit SU3 connected to word line WL1, consisting of the first write operation and the second write operation following the first write operation.

[0110] Thus, according to the Pass Write method, a first write operation and a second write operation are performed on a memory cell group MCG connected to a certain word line WLm. Subsequently, a first write operation and a second write operation are performed on a memory cell group MCG connected to word line WLm+1, which is adjacent to word line WLm.

[0111] Figure 12 is a diagram illustrating the Foggy&Fine method according to the first embodiment. In the Foggy&Fine method, the first light operation is also called the Foggy program, and the second light operation is called the Fine program.

[0112] According to the Foggy&Fine method, the first to fourth operations are performed on the memory cell group MCG connected to word line WL0. Next, the fifth to eighth operations are performed on the memory cell group MCG connected to word line WL1.

[0113] Next, as the 9th through 12th operations, a second write operation is performed on the memory cell group MCG connected to word line WL0. The operations are then repeated in the same order. That is, after the first write operation is performed on the memory cell group MCG connected to word line WLm, the first write operation is performed on the memory cell group MCG connected to word line WLm+1 before the second write operation is performed on the memory cell group MCG connected to word line WLm.

[0114] Figure 13 is a flowchart illustrating an example of write operation in a memory chip CP according to the first embodiment. Here, we describe the write operation for one memory cell group MCG. In the explanation of Figure 13, this one memory cell group MCG will be referred to as the target memory cell group MCG.

[0115] First, the access circuit 30 performs a first write operation consisting of steps S101 to S107. In the first write operation, the access circuit 30 performs a program operation using the program voltage Vpgm_init (step S101). The access circuit 30 selects all memory cells from the target memory cell group MCG except for the memory cell whose final target state is state "Er," that is, memory cells whose final target state is any of states "A" to "G," and applies a program pulse of voltage Vpgm_init to the word line WL to which the target memory cell group MCG is connected.

[0116] Next, the access circuit 30 performs a group read operation (step S102). Following the example shown in Figures 9 and 10, the access circuit 30 performs a read operation using voltages Vgr1 and Vgr2 as read levels, respectively. Based on the results of the read operation using voltages Vgr1 and Vgr2 as read levels, the sense amplifier circuit 14 classifies each memory cell whose final target state is one of states "A" to "G" into one of three subgroups: subgroup Gr1, where the threshold voltage of the memory cell is in a voltage range less than voltage Vgr1; subgroup Gr2, where the threshold voltage of the memory cell is in a voltage range from voltage Vgr1 to voltage Vgr2; and subgroup Gr3, where the threshold voltage of the memory cell is in a voltage range greater than voltage Vgr2.

[0117] The sense amplifier circuit 14 stores the result of the group read operation, i.e., the classification result, in the data latch circuit 16 (step S103).

[0118] Next, the access circuit 30 selects one of several combinations of intermediate target states and subgroups (step S104). The combination selected in step S104 is denoted as combination (S_sel, Gr_sel). In step S104, all intermediate target states except state "Erf" can be selected.

[0119] The access circuit 30 performs a program operation for all memory cells of the combination (S_sel, Gr_sel) using a program voltage corresponding to the combination (S_sel, Gr_sel) (step S105). The access circuit 30 selects all memory cells (S_sel, Gr_sel) of the combination (S_sel, Gr_sel) from the target memory cell group MCG and applies a single program pulse of the program voltage corresponding to the combination (S_sel, Gr_sel) to the word line WL to which the target memory cell group MCG is connected.

[0120] If there are still unselected combinations among the multiple combinations of intermediate target states and subgroups (step S106: Yes), the access circuit 30 selects one of the unselected combinations (step S107). Then, the combination newly selected in step S107 is set as the combination (S_sel, Gr_sel), and the process in step S105 is executed.

[0121] If there are no combinations of intermediate target states and subgroups that have not yet been selected (step S106: No), the first write operation is completed, and the access circuit 30 performs the second write operation (step S108). Then, the write operation for the target memory cell group MCG is completed.

[0122] In the above explanation, the target memory cell group MCG is an example of a first plurality of memory cells. States "Erf" to "Gf" are an example of a plurality of first states. Multiple memory cells within the target memory cell group MCG whose intermediate target state is one of states "Af" to "Gf" are an example of a second plurality of memory cells. A certain intermediate target state among states "Af" to "Gf" is an example of a second state. State "Erf" is an example of a third state. States "Af" to "Gf" are an example of a plurality of fourth states. The first write operation to the target memory cell group MCG is an example of a first operation. The second write operation to the target memory cell group MCG is an example of a second operation. The word line connected to the target memory cell group MCG is an example of a first word line. The word line adjacent to the word line connected to the target memory cell group MCG is an example of a second word line. The memory cell group MCG connected to the word line adjacent to the word line connected to the target memory cell group MCG is an example of a seventh plurality of memory cells. A first write operation to a memory cell group MCG connected to a word line adjacent to a word line connected to a target memory cell group MCG is an example of a third operation. The voltage Vpgm_init is an example of a first voltage. One or more read levels used in a group read operation (e.g., voltages Vgr1, Vgr2 shown in Figure 9) are examples of one or more read levels.

[0123] As described above, according to the first embodiment, in the first write operation, the access circuit 30 applies a program pulse of voltage Vpgm_init to the selected word line, thereby shifting the threshold voltage of all memory cells in the target memory cell group MCG whose intermediate target state is state "Af" to state "Gf" by a uniform amount (see, for example, part (A) of Figure 9 and step S101 of Figure 13). After applying the program pulse of voltage Vpgm_init, the access circuit 30 performs a read operation using a read level of 1 or higher, i.e., a group read operation, for all memory cells in the target memory cell group MCG whose intermediate target state is state "Af" to state "Gf". By performing the group read operation, the access circuit 30 identifies which of the two or more voltage ranges separated by a read level of 1 or higher the threshold voltage of each of the intermediate target states in the target memory cell group MCG is in (see, for example, part (B) of Figure 9 and steps S102 and S103 of Figure 13). The access circuit 30 selects a subgroup of memory cells from among all memory cells in the target memory cell group MCG whose intermediate target state is state "Af" to state "Gf", and whose threshold voltage is in a common voltage range among two or more voltage ranges divided into one or more read levels. The access circuit 30 then applies a program pulse of a voltage corresponding to that voltage range to the selected word line and performs the operation to set the threshold voltage of each memory cell in that subgroup to the intermediate target state, for each subgroup.

[0124] Therefore, the time required for the first light operation is reduced compared to the comparative example. As a result of the reduction in the time required for the first light operation, the time required for the light operation (i.e., the first light operation and the second light operation) is reduced.

[0125] Furthermore, according to the first embodiment, when the access circuit 30 selects multiple memory cells included in a subgroup corresponding to a certain voltage range (referred to as the first voltage range), it applies a single program pulse to the selection word line with a voltage corresponding to the first voltage range. When the access circuit 30 selects multiple memory cells included in a subgroup corresponding to another voltage range higher than the first voltage range (referred to as the second voltage range), it applies a single program pulse to the selection word line with a voltage lower than the voltage of the program pulse when the first voltage range was selected.

[0126] Therefore, it is possible to make the threshold voltage range of the target state distribution narrower than the threshold voltage range of distribution D_init without repeatedly executing program operations and verification operations. Since the verification operation for each program operation can be eliminated, the time required for the first write operation is shortened compared to the comparative example.

[0127] Furthermore, according to the first embodiment, in the first write operation, the access circuit 30 selects all memory cells for each combination of an intermediate target state of the threshold voltage and a voltage range of the threshold voltage, and applies a single program pulse of the voltage corresponding to that combination to the selected word line, thereby setting the threshold voltage of all memory cells for each combination to the intermediate target state.

[0128] Therefore, the access circuit 30 can set the threshold voltage of each memory cell included in the target memory cell group MCG to an intermediate target state.

[0129] In the explanation above, memory cells whose intermediate target state is any state other than state "Erf" (the lowest voltage state among states "Erf" to "Gf") were targeted for program operation using the voltage Vprg_init program pulse. Since the threshold voltage shift caused by the voltage Vprg_init program pulse is small, all memory cells included in the target memory cell group MCG may be targeted for program operation using the voltage Vprg_init program pulse regardless of the intermediate target state.

[0130] Furthermore, according to the first embodiment, when the Pass Write method is applied, the access circuit 30 performs a first write operation and a second write operation on a certain memory cell group MCG, and then performs a first write operation on a memory cell group MCG adjacent to that memory cell group MCG.

[0131] Furthermore, according to the first embodiment, when the Foggy&Fine method is applied, the access circuit 30 performs a first write operation on a certain memory cell group MCG (referred to as the first memory cell group MCG), and then performs a first write operation on another memory cell group MCG adjacent to the first memory cell group MCG (referred to as the second memory cell group MCG). After performing a first write operation on the second memory cell group MCG, the access circuit 30 performs a second write operation on the first memory cell group MCG.

[0132] (Second embodiment) In the program operation described in the first embodiment, as already explained, an "L" level (e.g., ground voltage Vss, 0V) is applied to the bit line BL corresponding to the memory cell whose threshold voltage is to be increased (given "0" data), and an "H" level (e.g., 2.5V) is applied to the bit line BL corresponding to the memory cell whose threshold voltage is not to be increased (given "1" data). In this case, only two types of control can be performed on the multiple memory cells included in the memory cell group MCG: increasing or maintaining the threshold voltage.

[0133] In contrast, in the second embodiment, the access circuit 30 is configured to perform QPW (Quick Pass Write) operation as a programmed operation.

[0134] Figure 14 shows the potential change of each wire during QPW operation according to the second embodiment.

[0135] In QPW operation, as shown in Figure 14, a voltage higher than the "L" level (ground voltage Vss, e.g., 0V) and lower than the "H" level (write-protect voltage Vinhibit, e.g., 2.5V) is applied to the bit line BL corresponding to the memory cell whose threshold voltage is to be increased by a small range. In other words, the charge level of the bit line BL is increased compared to the bit line BL corresponding to the memory cell whose threshold voltage is to be increased (where "0" data is assigned). As a result, the channel potential Vch in the target memory cell rises above the "L" level (ground voltage Vss, e.g., 0V). Therefore, the injection of electrons into the charge storage film by the program voltage Vpgm applied to the selected word line is mitigated by the amount of this increase in channel voltage Vch. Thus, in QPW operation, three types of control can be performed on multiple memory cells included in the memory cell group MCG: increasing the threshold voltage, maintaining the threshold voltage, or increasing the threshold voltage by a small range. In the following, the voltage applied to the bit line BL for this QPW operation will be referred to as the QPW voltage Vbl_qpw.

[0136] The access circuit 30 simultaneously selects all memory cells of a first combination and all memory cells of a second combination different from the first combination, from among multiple combinations of intermediate target states of threshold voltage and a certain voltage range of threshold voltage, and applies a single program pulse of a predetermined voltage to the selected word line. Here, the access circuit 30 performs a QPW operation on one of the memory cells of the first combination and all memory cells of the second combination, and performs the normal program operation described in the first embodiment on the other. In other words, the access circuit 30 applies a QPW voltage Vbl_qpw to each bit line connected to one of the memory cells of the first combination and all memory cells of the second combination, and applies a ground voltage Vss (e.g., 0V) to each bit line connected to the other of the memory cells of the first combination and all memory cells of the second combination, and applies a single program pulse of a predetermined voltage to the selected word line. This makes it possible to set the threshold voltages of the memory cells of the two different combinations to the intermediate target state with a single program pulse.

[0137] Figure 15 is a schematic diagram illustrating the voltage of the program pulse applied to the selected word line in the first write operation according to the second embodiment.

[0138] In the example shown in Figure 15, a program operation using one program pulse is simultaneously executed for all memory cells in combination (Af, Gr1) and all memory cells in combination (Bf, Gr1), a program operation using one program pulse is simultaneously executed for all memory cells in combination (Af, Gr2) and all memory cells in combination (Bf, Gr2), and a program operation using one program pulse is simultaneously executed for all memory cells in combination (Af, Gr3) and all memory cells in combination (Bf, Gr3). Here, the program operation for each memory cell in combination (Bf, Gr1), the program operation for each memory cell in combination (Bf, Gr2), and the program operation for each memory cell in combination (Bf, Gr3) are normal program operations. The program operation for each memory cell in combination (Af, Gr1), the program operation for each memory cell in combination (Af, Gr2), and the program operation for each memory cell in combination (Af, Gr3) are QPW operations.

[0139] A program operation using one program pulse is simultaneously executed for all memory cells in combination (Cf, Gr1) and all memory cells in combination (Df, Gr1), a program operation using one program pulse is simultaneously executed for all memory cells in combination (Cf, Gr2) and all memory cells in combination (Df, Gr2), and a program operation using one program pulse is simultaneously executed for all memory cells in combination (Cf, Gr3) and all memory cells in combination (Df, Gr3). Here, the program operation for each memory cell in combination (Df, Gr1), the program operation for each memory cell in combination (Df, Gr2), and the program operation for each memory cell in combination (Df, Gr3) are normal program operations. The program operation for each memory cell in combination (Cf, Gr1), the program operation for each memory cell in combination (Cf, Gr2), and the program operation for each memory cell in combination (Cf, Gr3) are QPW operations.

[0140] A program operation using one program pulse is simultaneously executed for all memory cells in combination (Ef, Gr1) and all memory cells in combination (Ff, Gr1), a program operation using one program pulse is simultaneously executed for all memory cells in combination (Ef, Gr2) and all memory cells in combination (Ff, Gr2), and a program operation using one program pulse is simultaneously executed for all memory cells in combination (Ef, Gr3) and all memory cells in combination (Ff, Gr3). Here, the program operation for each memory cell in combination (Ff, Gr1), the program operation for each memory cell in combination (Ff, Gr2), and the program operation for each memory cell in combination (Ff, Gr3) are normal program operations. The program operation for each memory cell in combination (Ef, Gr1), the program operation for each memory cell in combination (Ef, Gr2), and the program operation for each memory cell in combination (Ef, Gr3) are QPW operations.

[0141] Thus, according to the second embodiment, by applying a single program pulse to the selected word line with different voltages applied to the bit lines connected to each combination of memory cells, it is possible to simultaneously set the threshold voltages of two different combinations of memory cells to the intermediate target state. As a result, the number of program operations required for the first write operation is further reduced, and the time required for the write operation is further shortened.

[0142] In the first and second embodiments, the memory chip CP is configured to perform write operations in two parts: a first write operation and a second write operation. In the first write operation, a program operation is performed for each combination of target state and subgroup. The program operation technique for each combination of target state and subgroup described in the first and second embodiments can be applied regardless of the number of stages in which the write operation is divided. Furthermore, the program operation technique for each combination of target state and subgroup described in the first and second embodiments can be applied to any stage.

[0143] According to the first and second embodiments, the semiconductor memory device includes a first plurality of memory cells, each of which gates is connected to a first word line, and a circuit that performs a first operation to set the threshold voltage of each of the first plurality of memory cells to a first state corresponding to data among a plurality of first states. In the first operation, the circuit shifts the threshold voltage of each of the second plurality of memory cells among the first plurality of memory cells by a uniform amount by applying a program pulse of a first voltage to the first word line. Then, after applying the program pulse of the first voltage, the circuit determines which of the two or more voltage ranges separated by one or more read levels the threshold voltage of each of the second plurality of memory cells is in by performing a read operation on each of the second plurality of memory cells using one or more different read levels. The circuit then sets the threshold voltage of the third plurality of memory cells to the second state by selecting multiple memory cells included in a group and applying a single program pulse of a voltage corresponding to the voltage range corresponding to that group to the first word line, for each group of memory cells that share a common voltage range among two or more voltage ranges.

[0144] Therefore, it is possible to obtain a semiconductor memory device with a short time required for writing operations, that is, a short time required for storing data.

[0145] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0146] 1 Memory system, 11 NAND I / O interface, 12 Control circuit, 13 NAND memory cell array, 14 Sense amplifier circuit, 15 Word line driver, 16 Data latch circuit, 30 Access circuit, 100 NAND flash memory, 114 NAND string, 200 Controller, 201 Host interface circuit, 202 RAM, 203 CPU, 204 Buffer memory, 205 Memory interface circuit, 206 ECC circuit, 300 Host device.

Claims

1. A plurality of first memory cells, each with a gate connected to a first word line, A circuit that performs a first operation to set the threshold voltage of each of the first plurality of memory cells to a first state corresponding to the data among a plurality of first states, Equipped with, The first operation is, By applying a program pulse of a first voltage to the first word line, the threshold voltage of each of the second plurality of memory cells among the first plurality of memory cells is shifted by a uniform amount. After applying the program pulse of the first voltage, a read operation is performed on each of the second plurality of memory cells using one or more different read levels to determine which of the two or more voltage ranges separated by the one or more read levels the threshold voltage of each of the second plurality of memory cells is in. For a third plurality of memory cells whose threshold voltage setting destination is a second state which is one of the plurality of first states, the threshold voltage of the third plurality of memory cells is set to the second state by performing the operation of selecting a plurality of memory cells included in one group and applying a single program pulse of a voltage corresponding to the voltage range corresponding to one group to the first word line, for each group of memory cells whose threshold voltages share a common voltage range among the two or more voltage ranges, and including, Semiconductor memory device.

2. The aforementioned circuit is When a plurality of memory cells included in a group corresponding to a first voltage range among the two or more voltage ranges is selected from the third plurality of memory cells, a single program pulse of the second voltage is applied to the first word line. If a plurality of memory cells are selected from the third plurality of memory cells that are included in a group corresponding to a second voltage range that is higher in voltage than the first voltage range among the two or more voltage ranges, a single program pulse of a third voltage lower than the second voltage is applied to the first word line. The semiconductor memory device according to claim 1.

3. In the first operation, the circuit, for each combination of the state to which the threshold voltage is set and the voltage range in which the threshold voltage is set, Selecting a fourth plurality of memory cells from the second plurality of memory cells that correspond to the combination, and applying a single program pulse of voltage corresponding to the combination to the first word line, thereby setting the threshold voltage of each of the fourth plurality of memory cells to the target state. The semiconductor memory device according to claim 1.

4. The first plurality of memory cells are each connected to a different bit line, In the first operation, the circuit Select a fifth plurality of memory cells from the second plurality of memory cells that have a first combination of a threshold voltage setting state and a voltage range in which the threshold voltage is located, and a sixth plurality of memory cells from the second plurality of memory cells that have a second combination different from the first combination, apply a fourth voltage to the bit lines connected to each of the fifth plurality of memory cells, and apply a fifth voltage different from the fourth voltage to the bit lines connected to the sixth plurality of memory cells, and then apply a program pulse once to the first word line to set the threshold voltages of the fifth plurality of memory cells and the sixth plurality of memory cells to the setting state. The semiconductor memory device according to claim 1.

5. The plurality of first states include a third state on the lowest voltage side and a plurality of fourth states different from the third state, and each of the second plurality of memory cells has a threshold voltage setting target state that is one of the plurality of fourth states. The semiconductor memory device according to claim 1.

6. After the first operation, the circuit performs a second operation to set each of the first plurality of memory cells to a fourth state corresponding to the data among a plurality of fourth states, each having a threshold voltage distribution width narrower than the threshold voltage distribution width of one of the plurality of first states. A semiconductor memory device according to any one of claims 1 to 5.

7. The system further comprises a seventh plurality of memory cells, each of which gates is connected to a second word line adjacent to the first word line. After performing the first and second operations, the circuit performs a third operation in which it sets the threshold voltage of each of the seven plurality of memory cells to the first state corresponding to the data among the plurality of first states. The semiconductor memory device according to claim 6.

8. The system further comprises a seventh plurality of memory cells, each of which gates is connected to a second word line adjacent to the first word line. The aforementioned circuit is After performing the first operation, a third operation is performed to set the threshold voltage of each of the seven plurality of memory cells to the first state corresponding to the data among the plurality of first states. After performing the third operation, perform the second operation. The semiconductor memory device according to claim 6.

9. Performing a first operation in which each gate is connected to a first word line, the threshold voltage of each of the first multiple memory cells is set to the first state corresponding to the data among the multiple first states. Includes, The first operation is, By applying a program pulse of a first voltage to the first word line, the threshold voltage of each of the second plurality of memory cells among the first plurality of memory cells is shifted by a uniform amount. After applying the program pulse of the first voltage, a read operation is performed on each of the second plurality of memory cells using one or more different read levels to determine which of the two or more voltage ranges separated by the one or more read levels the threshold voltage of each of the second plurality of memory cells is in. For a third plurality of memory cells whose threshold voltage setting destination is a second state which is one of the plurality of first states, the threshold voltage of the third plurality of memory cells is set to the second state by performing the operation of selecting a plurality of memory cells included in one group and applying a single program pulse of a voltage corresponding to the voltage range corresponding to one group to the first word line, for each group of memory cells whose threshold voltages share a common voltage range among the two or more voltage ranges, and including, A method for storing data in a semiconductor memory device.

10. In selecting a plurality of memory cells from the third plurality of memory cells that are included in a group corresponding to a first voltage range among the two or more voltage ranges, a single program pulse of the second voltage is applied to the first word line, In selecting a plurality of memory cells from the third plurality of memory cells that are included in a group corresponding to a second voltage range that is higher in voltage than the first voltage range among the two or more voltage ranges, a single program pulse of a third voltage lower than the second voltage is applied to the first word line. The data storage method according to claim 9, including the method described in claim 9.

11. The first operation described above is performed for each combination of the state to which the threshold voltage is set and the voltage range in which the threshold voltage is set. Selecting a fourth plurality of memory cells from the second plurality of memory cells in the aforementioned combination and applying a single program pulse of voltage corresponding to the combination to the first word line, thereby setting the threshold voltage of each of the fourth plurality of memory cells to the specified state. The data storage method according to claim 9, including the method described in claim 9.

12. The first plurality of memory cells are each connected to a different bit line, The first operation is, Select a fifth plurality of memory cells from the second plurality of memory cells that have a first combination of a threshold voltage setting state and a voltage range in which the threshold voltage is located, and a sixth plurality of memory cells from the second plurality of memory cells that have a second combination different from the first combination, apply a fourth voltage to the bit lines connected to each of the fifth plurality of memory cells, and apply a fifth voltage different from the fourth voltage to the bit lines connected to the sixth plurality of memory cells, and then apply a program pulse once to the first word line to set the threshold voltages of the fifth plurality of memory cells and the sixth plurality of memory cells to the setting state. The data storage method according to claim 9, including the method described in claim 9.

13. The plurality of first states include a third state on the lowest voltage side and a plurality of fourth states different from the third state, and each of the second plurality of memory cells has a threshold voltage setting target state that is one of the plurality of fourth states. The data storage method according to claim 9.

14. After the first operation, a second operation is performed to set each of the first plurality of memory cells to a fourth state corresponding to the data among a plurality of fourth states, each having a threshold voltage distribution width narrower than the threshold voltage distribution width of one of the plurality of first states. A data storage method according to any one of claims 9 to 13, further comprising the above.

15. After performing the first and second operations, a third operation is performed in which each gate is connected to a second word line adjacent to the first word line, and the threshold voltage of each of the seven plurality of memory cells is set to the first state corresponding to the data among the plurality of first states. The data storage method according to claim 14, further comprising:

16. After performing the first operation, a third operation is performed in which each gate is connected to a second word line adjacent to the first word line, and the threshold voltage of each of the seven plurality of memory cells is set to the first state corresponding to the data among the plurality of first states. After performing the third operation, the second operation is performed, The data storage method according to claim 14, including the method described in claim 14.

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