memory devices

Abstract

To improve the performance of memory devices. [Solution] The memory device of the embodiment includes a first bit line, a first selection transistor, a second bit line, a string, a word line, a sense amplifier, and a driver circuit. One end of the first selection transistor is connected to the first bit line. The second bit line is connected to the other end of the first selection transistor. The string includes a second selection transistor connected to the second bit line and a memory cell transistor. The word line is connected to the memory cell transistor. The sense amplifier is connected to the first bit line. The driver circuit is connected to either the first bit line or the second bit line. When the memory cell transistor is set to program-disabled during a write operation, the sense amplifier applies a first voltage to the first bit line, and the driver circuit applies a second voltage higher than the first voltage to the second bit line.

Description

Technical Field

[0001] The embodiments relate to a memory device.

Background Art

[0002] A NAND type flash memory capable of storing data non-volatilely is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the performance of the memory device.

Means for Solving the Problems

[0005] [ The memory device of the embodiment includes a first bit line, a first selection transistor, a second bit line, a string, a word line, a sense amplifier, and a driver circuit. One end of the first selection transistor is connected to the first bit line. The second bit line is connected to the other end of the first selection transistor. The string includes a second selection transistor connected to the second bit line and a memory cell transistor. The word line is connected to the memory cell transistor. The sense amplifier is connected to the first bit line. The driver circuit is connected to the first bit line or the second bit line. When the memory cell transistor is set to program inhibit in a write operation, the sense amplifier applies a first voltage to the first bit line, and the driver circuit applies a second voltage higher than the first voltage to the second bit line.

Brief Description of the Drawings

[0006] [Figure 1]A block diagram showing an example of the overall configuration of a memory system equipped with a memory device according to the first embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the first embodiment. [Figure 3] A circuit diagram showing an example of the circuit configuration of a data register and sense amplifier module included in a memory device according to the first embodiment. [Figure 4] A circuit diagram showing an example of the circuit configuration of the bit line portion of a memory device according to the first embodiment. [Figure 5] A perspective view showing an overview of the structure of the memory device according to the first embodiment. [Figure 6] A plan view showing an example of a planar layout of a memory cell array included in a memory device according to the first embodiment. [Figure 7] A cross-sectional view showing an example of the cross-sectional structure of a NAND string provided in a memory device according to the first embodiment. [Figure 8] A cross-sectional view showing an example of the cross-sectional structure of a memory cell transistor included in the memory device according to the first embodiment. [Figure 9] A cross-sectional view showing an example of the cross-sectional structure of a selection transistor in a memory device according to the first embodiment. [Figure 10] A cross-sectional view showing an example of the cross-sectional structure of the source wires of a memory device according to the first embodiment. [Figure 11] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array provided in a memory device according to the first embodiment. [Figure 12] A cross-sectional view showing an example of the cross-sectional structure of a local bit line in a memory device according to the first embodiment. [Figure 13] A diagram showing an example of the threshold voltage distribution of a memory cell transistor MT in a memory device according to the first embodiment. [Figure 14] This figure shows an example of the operation of a NAND string connected to the bit line to be programmed during the charging phase of a write operation of a memory device according to the first embodiment. [Figure 15]This figure shows an example of the operation of a NAND string connected to the bit line to be programmed during the programming of a write operation of a memory device according to the first embodiment. [Figure 16] This figure shows an example of the operation of a NAND string connected to a program-protected bit line during the charging phase of a write operation of a memory device according to the first embodiment. [Figure 17] This figure shows an example of the operation of a NAND string connected to a program-prohibited bit line during the programming of a write operation of a memory device according to the first embodiment. [Figure 18] This figure shows a specific example of the operation of the NAND string during a write operation in the second comparative example. [Figure 19] A diagram showing a specific example of the operation of a NAND string during a write operation in the first embodiment. [Figure 20] A circuit diagram showing an example of the circuit configuration of a memory device according to the second embodiment. [Figure 21] A plan view showing an example of a planar layout of a memory cell array included in a memory device according to the second embodiment. [Figure 22] This figure shows an example of the operation of a NAND string connected to the bit line to be programmed during the charging phase of a write operation of a memory device according to the second embodiment. [Figure 23] This figure shows an example of the operation of a NAND string connected to the bit line to be programmed during the programming of a write operation of a memory device according to the second embodiment. [Figure 24] This figure shows an example of the operation of a NAND string connected to a program-prohibited bit line during the charging phase of a write operation of a memory device according to the second embodiment. [Figure 25] This figure shows an example of the operation of a NAND string connected to a program-prohibited bit line during the programming of a write operation of a memory device according to the second embodiment. [Figure 26] A circuit diagram showing an example of the circuit configuration of a memory device according to the third embodiment. [Figure 27]Cross-sectional view showing an example of the cross-sectional structure of the staircase region of the memory cell array included in the memory device according to the third embodiment. [Figure 28] Diagram showing an example of the operation of the NAND string connected to the bit line to be programmed during the programming of the write operation of the memory device according to the third embodiment. [Figure 29] Diagram showing an example of the operation of the NAND string connected to the bit line where programming is prohibited during the programming of the write operation of the memory device according to the third embodiment. [Figure 30] Circuit diagram showing an example of the circuit configuration of the memory device according to the fourth embodiment. [Figure 31] Circuit diagram showing an example of the circuit configuration of the operation selection circuit included in the memory device according to the fourth embodiment. [Figure 32] Diagram showing an example of the operation of the NAND string connected to the bit line to be programmed during the programming of the write operation of the memory device according to the fourth embodiment. [Figure 33] Diagram showing an example of the operation of the NAND string connected to the bit line where programming is prohibited during the programming of the write operation of the memory device according to the fourth embodiment.

Embodiments for Carrying Out the Invention

[0007] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions and proportions in each drawing are not necessarily the same as those in reality. The illustration of the components is omitted where appropriate. Hatching added to the plan view is not necessarily related to the material or characteristics of the components. In this specification, components having substantially the same function and configuration are assigned the same reference numeral. Numbers and letters added to reference numerals are used to distinguish similar elements that are referred to by the same reference numeral. In this specification, one of the sources or drains of a transistor is referred to as "end (of the current path)," and the other of the source or drain is referred to as "other end (of the current path)." The configuration (source or drain) assigned to the one end and the other end may differ for each transistor.

[0008] <1> First Embodiment The memory device 1 according to the first embodiment is a type of HCF (Horizontal Channel Flash) having a structure in which the channel extends in a direction parallel to the substrate. In the memory device 1 according to the first embodiment, a circuit capable of applying a higher voltage than that of the sense amplifier is connected in the middle of the bit line BL, thereby extending the control range of the bit line BL voltage during writing operations. Details of the memory device 1 according to the first embodiment will be described below.

[0009] <1-1> Composition First, the configuration of the memory device 1 according to the first embodiment will be described.

[0010] <1-1-1> Overall configuration of memory device 1 Figure 1 is a block diagram showing an example of the overall configuration of a memory system comprising a memory device 1 according to the first embodiment. As shown in Figure 1, the memory device 1 is controlled by an external memory controller 2. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, a data register 17, and a sense amplifier module 18.

[0011] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where "n" is an integer of 1 or more). A block BLK is a collection of multiple memory cells. A block BLK corresponds, for example, to a unit of data erasure. A block BLK includes multiple pages. A page corresponds to a unit in which data reading and writing are performed. Although not shown in the diagram, the memory cell array 10 is provided with multiple bit lines BL0 to BLm (where "m" is an integer of 1 or more) and multiple word lines WL. Each memory cell is associated, for example, with one bit line BL and one word line WL.

[0012] The input / output circuit 11 is an interface circuit that controls the transmission and reception of input / output signals to and from the memory controller 2. These input / output signals include, for example, data DAT, status information, address information, and commands. The input / output circuit 11 can input and output data DAT to and from the sense amplifier module 18 and the memory controller 2, respectively. The input / output circuit 11 can output status information transferred from the register circuit 13 to the memory controller 2. The input / output circuit 11 can output address information and commands transferred from the memory controller 2 to the register circuit 13.

[0013] The logic controller 12 controls the input / output circuit 11 and the sequencer 14 based on the control signals input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the memory device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signal it has received is a command or address information. The logic controller 12 commands the input / output circuit 11 to input or output the input / output signal.

[0014] The register circuit 13 temporarily stores status information, address information, and commands. The status information is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11. The address information includes block addresses, page addresses, column addresses, etc. The commands include instructions for various operations of the memory device 1.

[0015] The sequencer 14 controls the overall operation of the memory device 1. Based on the commands and address information stored in the register circuit 13, the sequencer 14 performs read operations, write operations, erase operations, etc. The sequencer 14 may also be called a controller or control circuit.

[0016] The driver circuit 15 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 15 then supplies the generated voltages to the raw decoder module 16, sense amplifier module 18, etc.

[0017] The row decoder module 16 is a circuit used for selecting the block BLK to be operated on and for transferring voltage to wiring such as word lines WL. The row decoder module 16 includes multiple row decoders RD0 to RDn. Row decoders RD0 to RDn are each associated with blocks BLK0 to BLKn and are used for selecting blocks BLK. Each row decoder RD transfers the voltage generated by the driver circuit 15 to various wirings provided in the memory cell array 10.

[0018] The data register 17 can temporarily store data DAT. The data register 17 is used when inputting and outputting data DAT, for example, between the input / output circuit 11 and the sense amplifier module 18. The data register 17 may also be called a data latch, page register, or cache memory.

[0019] The sense amplifier module 18 is a circuit used to supply voltage to each bit line BL and to read data. The sense amplifier module 18 includes multiple sense amplifier units SAU0 to SAUm. Each sense amplifier unit SAU0 to SAUm is associated with multiple bit lines BL0 to BLm. Each sense amplifier unit SAU can determine the data read from the selected memory cell transistor MT based on the voltage of the associated bit line BL.

[0020] The combination of memory device 1 and memory controller 2 may constitute a single semiconductor device. For example, an SD card is one such semiconductor device. TM Examples include memory cards and SSDs (solid state drives).

[0021] <1-1-2> Circuit configuration of memory device 1 Next, an example of the circuit configuration of the memory device 1 according to the first embodiment will be described.

[0022] (1: Circuit configuration of memory cell array 10) Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array 10 provided in a memory device 1 according to the first embodiment. Figure 2 shows one of several block BLKs included in the memory cell array 10. As shown in Figure 2, a block BLK is connected to a plurality of bit lines BL0 to BLm, a plurality of word lines WL0 to WL(N-1) (where N is an integer of 2 or more), selection gate lines SGD0 to SGD3, selection gate lines SGS0 to SGS3, and a source line SL. The selection gate lines SGD0 to SGD3 and SGS0 to SGS3 and the word lines WL0 to WL(N-1) (where N is an integer of 2 or more) are provided for each block BLK. The bit lines BL0 to BLm are shared by multiple block BLKs. The source line SL is shared by multiple block BLKs, for example.

[0023] Block BLK includes, for example, four string units SU0 to SU3. Each string unit SU contains multiple NAND strings NS. Each of the multiple NAND strings NS is associated with a bit line BL0 to BLm. Each NAND string NS is connected between the associated bit line BL and the source line SL.

[0024] Each NAND string NS includes, for example, N memory cell transistors MT0 to MT(N-1) and selection transistors STD and STS. Each memory cell transistor MT is a memory cell having a control gate and a charge storage layer (floating gate) that non-volatilely retains (stores) data. The threshold voltage of the memory cell transistor MT can be changed based on the amount of charge injected into the charge storage layer, etc. The selection transistors STD and STS are used for selecting the string unit SU, respectively.

[0025] In each NAND string NS, the selection transistor STD, memory cell transistors MT(N-1) to MT0, and selection transistor STS are connected in series in this order. Specifically, one end of the selection transistor STD is connected to the associated bit line BL. The other end of the selection transistor STD is connected to one end of the memory cell transistor MT(N-1). The memory cell transistors MT0 to MT(N-1) are connected in series between the selection transistor STD and STS. One end of the selection transistor STS is connected to the other end of the memory cell transistor MT0. The other end of the selection transistor STS is connected to the source line SL.

[0026] The selection gate lines SGD0 to SGD3 are associated with string units SU0 to SU3, respectively. Each selection gate line SGD is connected to the gate of each of the multiple selection transistors STD contained in the associated string unit SU. The selection gate lines SGS0 to SGS3 are associated with string units SU0 to SU3, respectively. The selection gate line SGS is connected to the gate of each of the multiple selection transistors STS contained in the associated block BLK. The word lines WL0 to WL(N-1) are connected to the control gates of each of the multiple memory cell transistors MT0 to MT(N-1) contained in the associated block BLK.

[0027] In addition, in the memory cell array 10, the number of string units SU included in each block BLK, and the number of selection transistors STD and STS included in each NAND string NS, can be designed to any number.

[0028] In this specification, a set of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is referred to as a cell unit CU. Furthermore, a set of 1-bit data stored in each of the multiple memory cell transistors MT contained within a cell unit CU is referred to as page data. That is, a "page" corresponds to a set of multiple memory cell transistors MT connected to a common word line WL within the same block BLK. A cell unit CU can store two or more pages of data, depending on the number of bits of data stored in each memory cell transistor MT. In other words, the memory controller 2 can manage the storage area of ​​the memory device 1 in units of cell unit CUs, each composed of multiple memory cell transistors MT capable of storing multiple bits of data.

[0029] (2: Circuit configuration of data register 17 and sense amplifier module 18) Figure 3 is a circuit diagram showing an example of the circuit configuration of a data register 17 and a sense amplifier module 18 provided in a memory device 1 according to the first embodiment. As shown in Figure 3, the data register 17 includes a plurality of latch circuits XDL0 to XDLm. Each sense amplifier unit SAU included in the sense amplifier module 18 includes, for example, a bit line connection section BLHU, a sense amplifier section SA, buses DBUS and LBUS, latch circuits SDL, ADL, BDL, CDL and DDL, and a transistor TR.

[0030] Each latch circuit XDL can temporarily hold (store) data. Latch circuits XDL0 to XDLm are associated with sense amplifier units SAU0 to SAUm, respectively. Each latch circuit XDL is configured to send and receive data to and from its associated sense amplifier unit SAU via the bus DBUS. Each latch circuit XDL is also used for input and output of data DAT between the sense amplifier module 18 and the input / output circuit 11. Each latch circuit XDL may be shared by multiple sense amplifier units SAU.

[0031] The bit line junction BLHU is a protection circuit that prevents, for example, the high voltage applied to the channel of the NAND string NS during an erase operation from being applied to the sense amplifier section SA. The bit line junction BLHU includes, for example, a high-voltage transistor. The voltage rating of the high-voltage transistor is higher than that of the transistor used in the sense amplifier section SA.

[0032] The sense amplifier section SA is a circuit used for determining data based on the voltage of the bit line BL and for applying voltage to the bit line BL. Each sense amplifier section SA is connected to the associated bit line BL via the bit line connection section BLHU. When the control signal STB is asserted during a read operation, the sense amplifier section SA determines whether the data read from the selected memory cell transistor MT is "0" bit data or "1" bit data based on the voltage of the associated bit line BL.

[0033] Each of the latch circuits SDL, ADL, BDL, CDL, and DDL can temporarily hold (store) data. The latch circuits SDL, ADL, BDL, CDL, and DDL, as well as the sense amplifier unit SA, are configured to send and receive data via the bus LBUS. During data writing, the sense amplifier unit SAU controls the bit line BL according to the data stored in the latch circuit SDL. For example, when the writing operation is complete, the latch circuit SDL stores data indicating that the writing of data to the memory cell transistor MT is complete. The other latch circuits are used, for example, to temporarily store the data of each bit when individual memory cell transistors MT store two or more bits of data. The number of latch circuits can be set arbitrarily. The number of latch circuits is set, for example, according to the amount of data (number of bits) that the memory cell transistor MT can store.

[0034] The transistor TR controls the transfer of signals between the associated buses DBUS and LBUS. One end and the other end of the transistor TR of each sense amplifier unit SAU are connected to the associated buses DBUS and LBUS, respectively. The control signal DSW is input to the gate of the transistor TR of each sense amplifier unit. The control signals STB and DSW are generated, for example, by the sequencer 14.

[0035] (3: Detailed circuit configuration of the bit line section) In the memory device 1 according to the first embodiment, the sense amplifier unit SAU and the block BLK are connected via multiple types of wiring that function as bit lines BL. In other words, the bit lines BL are divided and used as multiple wires. The divided bit lines BL are configured to branch as appropriate, for example, via selection transistors. In addition, a circuit capable of applying a higher voltage than that of the sense amplifier section SA is connected in the middle of the bit lines BL. The configuration including these circuits will be referred to as the bit line section and described below.

[0036] Figure 4 is a circuit diagram showing an example of the circuit configuration of the bit line section of the memory device 1 according to the first embodiment. Figure 4 shows a bit line BL associated with one sense amplifier unit SAU, and elements and wiring used to control the bit line BL. As shown in Figure 4, one bit line BL is divided into, for example, a global bit line GBL, a local bit line LBIY, and local bit lines LBIX0 to LBIXn. Local bit lines LBIY and LBIX may also be referred to as local block wiring LBI.

[0037] The number of global bit lines (GBL) corresponds to the number of bit lines (BL). For example, the number of local bit lines (LBIY) corresponds to the number of global bit lines (GBL). The number of local bit lines (LBIX) corresponds to the number of block lines (BLK) connected to the associated local bit lines (LBIY). In this example, multiple block lines (BLK0 to BLKn) are associated with local bit lines (LBIY). Each local bit line (LBIX) is connected to the respective NAND string NS of the string units SU0 to SU3 of the associated block line (BLK). Note that the number of local bit lines (LBIY) connected to a global bit line (GBL) may be two or more. The number of local bit lines (LBIX) (block lines) connected to a local bit line (LBIY) may be two or more.

[0038] The memory device 1 according to the first embodiment further includes a driver wiring DRL and selection transistors BST and DST for each block BLK. The driver wiring DRL is connected, for example, to a driver circuit 15 and is used to transfer a voltage higher than that of the sense amplifier section SA. The selection transistor BST is a transistor used for selecting block BLK. The selection transistor DST is a transistor used to transfer the voltage of the driver wiring DRL to the local bit line LBIX. The combination of the driver wiring DRL and the selection transistor DST may be referred to as a driver circuit.

[0039] Specifically, blocks BLK0 to BLKn each contain selection transistors BST0 to BSTn. Blocks BLK0 to BLKn also each contain selection transistors DST0 to DSTn. The gates of selection transistors BST0 to BSTn are connected to selection lines BS0 to BSn, respectively. The gates of selection transistors DST0 to DSTn are connected to selection lines DS0 to DSn, respectively. Selection line BS can be controlled independently for each block BLK. For example, selection line BS can be controlled independently for each local bit line LBIX. The voltages applied to selection lines BS and DS are generated by the driver circuit 15 based on the control of the sequencer 14, for example.

[0040] One end and the other end of the selection transistor BST0 of block BLK0 are connected to local bit lines LBIY and LBIX0, respectively. One end and the other end of the selection transistor DST0 of block BLK0 are connected to local bit line LBIX0 and driver wiring DRL, respectively. One end and the other end of the selection transistor BST1 of block BLK1 are connected to local bit lines LBIY and LBIX1, respectively. One end and the other end of the selection transistor DST1 of block BLK1 are connected to local bit line LBIX1 and driver wiring DRL, respectively. Similarly, the local bit line LBIX of each block BLK is connected to local bit line LBIY via the corresponding selection transistor BST and to driver wiring DRL via the corresponding selection transistor DST.

[0041] <1-1-3> Structure of memory device 1 Next, the structure of the memory device 1 according to the first embodiment will be described.

[0042] The drawings referenced below use a three-dimensional Cartesian coordinate system. The Z direction corresponds to the vertical direction relative to the surface of the reference semiconductor substrate. "Up and down" is defined based on the direction along the Z direction. The positive direction (up) corresponds to the direction away from the reference semiconductor substrate. The XY plane (cross section) corresponds to the plane (cross section) parallel to the X and Y directions, respectively. The YZ cross section corresponds to the cross section parallel to the Y and Z directions, respectively. The XZ cross section corresponds to the cross section parallel to the X and Z directions, respectively.

[0043] (1: Overview of the structure of the memory cell array 10) Figure 5 is a perspective view showing an overview of the structure of the memory device 1 according to the first embodiment. Figure 5 shows an overview of the HCF (Horizontal Channel Flash) in the memory device 1 according to the first embodiment. As shown in Figure 5, the memory device 1 includes, for example, a substrate 20, a plurality of conductive layers 21, a plurality of conductive members 22, a plurality of conductive members 23, a plurality of semiconductor layers 24, a plurality of contacts 25, a plurality of conductive layers 26, and a plurality of pillars 30. Note that in Figure 5, one contact 25 and one conductive layer 26 are shown in detail.

[0044] Multiple conductive layers 21 are arranged in the Z direction. Adjacent conductive layers 21 in the Z direction are insulated from each other. Each conductive layer 21 has, for example, a portion that extends in the X direction and a portion that does not overlap with the conductive layer 21 above it (hereinafter referred to as the terrace portion). As a result, multiple conductive layers 21 have a stepped arrangement. Hereafter, the region in which multiple conductive layers 21 are provided will be referred to as the stepped region SR.

[0045] Multiple conductive members 22 are provided at the same height (layer) as multiple conductive layers 21. Adjacent conductive members 22 in the Z direction are insulated from each other. Each conductive member 22 has, for example, a portion that extends in the Y direction. Each conductive member 22 is electrically connected to the conductive layer 21 provided at the same height (layer). The conductive members 22 are used as local bit lines LBIY.

[0046] Multiple conductive members 23 are provided at the same height (layer) as multiple conductive layers 21. Adjacent conductive members 23 in the Z direction are insulated from each other. Each conductive member 23 has, for example, a portion that extends in the X direction. Each conductive member 23 is electrically connected to a conductive member 22 provided at the same height (layer). The conductive member 22 is used as a local bit line LBIX. The number of conductive members 23 provided at the same height corresponds to the number of block BLKs connected to the conductive member 22 (local bit line LBIY). The conductive members 23 provided at the same height are arranged in the Y direction. In addition, conductive members 23 may be electrically connected to the conductive member 22 from both sides in the X direction. In this case, block BLKs may be evenly distributed on both sides of the conductive member 22 in the X direction.

[0047] Multiple semiconductor layers 24 are provided at the same height (layer) as multiple conductive layers 21. Adjacent semiconductor layers 24 in the Z direction are insulated from each other. Each semiconductor layer 24 has, for example, a portion extended in the Y direction. Each semiconductor layer 24 is connected to a conductive member 23 provided at the same height (layer). The semiconductor layers 24 are used as channels CH of the NAND string NS. The number of semiconductor layers 24 provided at the same height in each block BLK corresponds to the number of string units SU included in one block BLK. The semiconductor layers 24 provided at the same height (layer) are aligned in the X direction. Furthermore, each conductive member 23 may be electrically connected to semiconductor layers 24 from both sides in the Y direction.

[0048] Each contact 25 is a conductor extending in the Z direction. Multiple contacts 25 are associated with multiple conductive layers 21. Each contact 25 is provided on a terrace portion of the associated conductive layer 21.

[0049] Multiple conductive layers 26 are provided above multiple conductive layers 21. Each conductive layer 26 has, for example, a portion that extends in the Y direction. Multiple conductive layers 26 are arranged, for example, in the X direction (not shown). Multiple conductive layers 26 are associated with each of the multiple conductive layers 21. Each conductive layer 26 is connected to the terrace portion of the associated conductive layer 21 via a contact 25. Conductive layers 26 are used as global bit lines (GBL).

[0050] Each pillar 30 is a conductor extending in the Z direction. Multiple pillars 30 are provided adjacent to multiple semiconductor layers 24 aligned in the Z direction for each string unit SU. The pillars 30 are used as word lines WL. The portion where the pillars 30 and the semiconductor layer 24 are adjacent (intersect) functions as a memory cell transistor MT.

[0051] (2: Planar layout of memory cell array 10) Figure 6 is a plan view showing an example of the planar layout of a memory cell array 10 provided in a memory device 1 according to the first embodiment. Figure 6 shows an extracted layer of the memory cell array 10 on which conductive members 22 (local bit lines LBIY) are provided. As shown in Figure 6, the memory cell array 10 further comprises, for example, a conductive layer 27. The conductive layer 27 has, for example, a portion extended in the Y direction and is used as a driver wiring DRL.

[0052] A selection transistor BST is provided between the conductive member 22 (local bit line LBIY) and each conductive member 23 (local bit line LBIX). Multiple selection transistors BST associated with the same block BLK overlap in the Z direction (not shown). A selection transistor DST is provided between each conductive member 23 (local bit line LBIX) and the conductive layer 27 (driver wiring DRL). In this example, four semiconductor layers 24 are connected to the conductive member 23 (local bit line LBIX) of each block BLK. The four semiconductor layers 24 connected to the conductive member 23 of each block BLK correspond to the NAND strings NS of string units SU0 to SU3, respectively.

[0053] Note that the structure and arrangement of the selection transistor DST and the conductive layer 27 are not limited to the configuration shown in Figure 6. Other elements may be added if it is possible to achieve operation similar to the writing operation described later. For example, the illustrated selection transistor DST may be configured and controlled in the same way as the selection transistor BST, and transistors to which the operation of the selection transistor DST described later is applied may be inserted in the current path between the conductive layer 27 of each layer and the driver circuit 15. The arrangement of other components of the memory cell array 10 may also be changed as appropriate.

[0054] (3: Cross-sectional structure of NAND string NS) Figure 7 is a cross-sectional view showing an example of the cross-sectional structure of a NAND string NS provided in the memory device 1 according to the first embodiment. Figure 7 shows the XY cross-section of one NAND string NS. As shown in Figure 7, the memory cell array 10 further includes, for example, an insulating member 28 and pillars 40, 43, 50, 53 and pillar 60.

[0055] The insulating member 28 is, for example, an insulator provided in a portion of the height (layer) where the semiconductor layer 24 is provided, where conductive members 22 and 23, etc., are not provided. The insulating member 28 is provided, for example, between adjacent semiconductor layers 24 (not shown) in the X direction, and separates and insulates adjacent NAND strings NS.

[0056] Multiple pillars 30 are arranged, for example, in the Y direction and alternately on both sides of the semiconductor layer 24 in the X direction. In other words, the multiple pillars 30 are arranged in a staggered pattern so as to sandwich the semiconductor layer 24. Each pillar 30 is positioned between the semiconductor layer 24 and the insulating member 28. The pillars 30 and the semiconductor layer 24 are insulated via insulating film 31, conductive film 32, and insulating film 33. The pillars 30, along with insulating film 31, conductive film 32, and insulating film 33, and the semiconductor layer 24 in the vicinity of the pillars 30, function as memory cell transistors MT. Insulating film 31 functions as a tunnel insulating film. Conductive film 32 functions as a charge storage layer (floating gate). Insulating film 33 functions as a block insulating film.

[0057] Each pillar 40 is a conductor extended in the Z direction and used as a selection gate line SGD. Each pillar 40 is positioned between the conductive member 23 (local bit line LBIX) side of the semiconductor layer 24 and the insulating member 28. The pillar 40 and the semiconductor layer 24 are insulated via insulating films 41 and 42. The pillar 40, insulating films 41 and 42, and the semiconductor layer 24 near the pillar 40 function as a selection transistor STD. The insulating films 41 and 42 function as gate insulating films. Each NAND string NS only needs to have one or more sets of pillar 40 and insulating films 41 and 42. Multiple sets of pillar 40 and insulating films 41 and 42 may be aligned in the Y direction, or they may be aligned in the Y direction and alternately arranged on both sides of the semiconductor layer 24 in the X direction. Pillar 43 is a semiconductor extended in the Z direction. For pillar 43, for example, silicon doped with P-type impurities such as boron (B) is used. Pillar 43 is positioned near the selection transistor STD and is in contact with the semiconductor layer 24. Pillar 43 is used as the body contact BC of the selection transistor STD.

[0058] Each pillar 50 is a conductor extended in the Z direction and is used as a select gate line SGS. Each pillar 50 is positioned between the source line SL side portion of the semiconductor layer 24 and the insulating member 28. The pillar 50 and the semiconductor layer 24 are insulated via insulating films 51 and 52. The pillar 50, insulating films 51 and 52, and the semiconductor layer 24 near the pillar 50 function as a select transistor STS. Each NAND string NS only needs to have one or more sets of pillar 50 and insulating films 51 and 52. Multiple sets of pillar 50 and insulating films 51 and 52 may be aligned in the Y direction, or they may be aligned in the Y direction and alternately arranged on both sides of the semiconductor layer 24 in the X direction. Pillar 53 is a semiconductor extended in the Z direction. For example, silicon doped with P-type impurities such as boron (B) can be used as pillar 53. Pillar 53 is positioned near the selection transistor STS and is in contact with the semiconductor layer 24. Pillar 53 is used as a body contact BC for the selection transistor STS.

[0059] The pillar 60 is a conductor extended in the Z direction and is used as the source line SL. The pillar 60 is positioned between the end of the semiconductor layer 24 opposite to the conductive member 23 (local bit line LBIX) and the insulating member 28. The pillar 60 and the semiconductor layer 24 are electrically connected. For example, silicon doped with N-type impurities such as phosphorus (P) is used as the pillar 60.

[0060] Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell transistor MT in a memory device 1 according to the first embodiment. Figure 8 shows an XZ cross-section including two adjacent memory cell transistors MT in the Z direction. As shown in Figure 8, the memory cell array 10 further includes, for example, a plurality of insulating layers 70. The plurality of insulating layers 70 are arranged side by side in the Z direction. Each insulating layer 70 separates and insulates adjacent wiring layers (layers including conductive layers 21 and conductive members 22 and 23) in the Z direction. Pillars 30 (word lines WL) are provided penetrating the plurality of insulating layers 70 arranged in the Z direction. Insulating films 31 are provided on the sides of the pillars 30. The insulating films 42 of each memory cell transistor MT are provided continuously between adjacent memory cell transistors MT in the Z direction. At the same height (layer) as the semiconductor layer 24, steps may be formed in the pillars 30 and insulating films 31 in the portions of each wiring layer adjacent to the semiconductor layer 24. The conductive film 32 and insulating film 33 of each memory cell transistor MT are separated between adjacent memory cell transistors MT in the Z direction.

[0061] Figure 9 is a cross-sectional view showing an example of the cross-sectional structure of a selection transistor STD provided in the memory device 1 according to the first embodiment. As shown in Figure 9, the pillar 40 (selection gate line SGD) is provided penetrating a plurality of insulating layers 70 aligned in the Z direction. An insulating film 41 is provided on the side surface of the pillar 40. The insulating film 41 of each selection transistor STD is provided continuously between adjacent selection transistor STDs in the Z direction. At the same height (layer) as the semiconductor layer 24, a step may be formed in the portion of the pillar 40 and insulating film 41 adjacent to the semiconductor layer 24 in each wiring layer. The insulating film 42 of each selection transistor STD is separated between adjacent selection transistor STDs in the Z direction. The cross-sectional structure of the selection transistor STS is similar to, for example, the cross-sectional structure of the selection transistor STD, but with pillar 50, insulating film 51, and insulating film 52, respectively.

[0062] Figure 10 is a cross-sectional view showing an example of the cross-sectional structure of a source wire SL in a memory device 1 according to the first embodiment. As shown in Figure 10, the pillar 60 (source wire SL) is provided penetrating a plurality of insulating layers 70 aligned in the Z direction. The side surface of the pillar 60 is connected to a plurality of semiconductor layers 24 stacked in the Z direction.

[0063] (4: Cross-sectional structure of memory cell array 10) Figure 11 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array 10 provided in a memory device 1 according to the first embodiment. Figure 11 shows an XY cross-section of the region of the memory cell array 10 that includes local bit lines LBIX and LBIY. As shown in Figure 11, the memory cell array 10 further includes, for example, insulating members 80 and 82, semiconductor layers 81 and 83, and pillars 40a and 43a.

[0064] The insulating member 80 is a columnar member extending in the Z direction. Multiple insulating members 80 are arranged in the memory cell array 10 along the X direction. Each insulating member 80 is surrounded by a conductive member 23 (local bit line LBIX). The conductive member 23 is formed, for example, by creating multiple holes corresponding to the multiple insulating members 80 and penetrating the multiple insulating layers 70, then removing a portion of the semiconductor layer 24 of each wiring layer through the multiple holes, and embedding a conductor in the space where the semiconductor layer 24 was removed. The conductive members 23 provided around two adjacent insulating members 80 are electrically connected. Therefore, the conductive member 23 may have a portion along the outer circumference of each insulating member 80. Also, the conductive member 23 may have a boundary between two adjacent insulating members 80.

[0065] The semiconductor layer 81 is provided between the conductive member 23 and the semiconductor layer 24. The semiconductor layer 81 contains silicon doped with, for example, an N-type impurity such as phosphorus (P). In each wiring layer within the block BLK, the conductive member 23 and the NAND string NS of each string unit SU are electrically connected via the semiconductor layer 81.

[0066] The insulating member 82 is a columnar member extending in the Z direction. Multiple insulating members 82 are arranged in the memory cell array 10 along the Y direction. Each insulating member 82 is surrounded by a conductive member 22 (local bit line LBIY). The conductive member 22 is formed, for example, by creating multiple holes corresponding to the multiple insulating members 82 and penetrating multiple insulating layers 70, then removing a portion of the semiconductor layer 24 of each wiring layer through the multiple holes, and embedding a conductor in the space where the semiconductor layer 24 was removed. Conductive members 22 provided around two adjacent insulating members 82 are electrically connected. Therefore, the conductive member 22 may have a portion along the outer circumference of each insulating member 82. Also, the conductive member 22 may have a boundary between two adjacent insulating members 82.

[0067] The semiconductor layer 83 is provided between the conductive member 22 and the semiconductor layer 24. The semiconductor layer 83 contains silicon doped with, for example, an N-type impurity such as phosphorus (P). In each wiring layer within the block BLK, the conductive member 22 and the conductive member 23 (local bit line LBIX) are electrically connected via the semiconductor layers 83 and 24.

[0068] Each pillar 40a is a conductor extended in the Z direction and used as a selection line BS. Each pillar 40a is, for example, placed between the semiconductor layer 24 between the conductive members 22 and 23 and the insulating member 28. A gate insulating film is provided between each pillar 40a and the semiconductor layer 24, for example, similar to a selection transistor STD. The pillar 40a, the gate insulating film, and the semiconductor layer 24 near the pillar 40a function as a selection transistor BST. Each block BLK only needs to have one or more sets of pillar 40a and gate insulating film for each wiring layer. Multiple sets of pillar 40a and gate insulating film may be aligned in the Y direction, or they may be aligned in the Y direction and alternately arranged on both sides of the semiconductor layer 24 in the X direction. Pillar 43a is a semiconductor extended in the Z direction. For example, silicon doped with P-type impurities such as boron (B) is used as pillar 43a. Pillar 43a is positioned near the selection transistor BST and is in contact with the semiconductor layer 24. Pillar 43a is used as the body contact BC of the selection transistor BST.

[0069] In this example, after the laminated structure of the semiconductor layer 24 and the insulating layer 70 is formed, and before the conductive members 22 and 23 are formed, multiple holes HL are formed that penetrate multiple insulating layers 70. Subsequently, a portion of the semiconductor layer 24 of each wiring layer is removed through the multiple holes HL, and the insulating member 28 is embedded. Therefore, each of the conductive members 22 and 23 may have a portion along the outer circumference of each hole HL.

[0070] In memory device 1, two adjacent string units SU may be arranged symmetrically in the X direction. In this case, the body contact BC (pillar 43) of the selection transistor STD may be shared by two adjacent string units SU. In this case, one body contact BC is provided for every two string units SU.

[0071] Figure 12 is a cross-sectional view showing an example of the cross-sectional structure of a local bit line LBIX provided in a memory device 1 according to the first embodiment. Figure 12 shows a YZ cross-section including two adjacent local bit line LBIX in the Z direction. As shown in Figure 12, the insulating member 80 is provided penetrating a plurality of insulating layers 70 aligned in the Z direction. The side surface of the insulating member 80 is in contact with the conductive member 23 (local bit line LBIX) of each wiring layer. In each wiring layer, the conductive member 23 is connected to the semiconductor layer 24 via a semiconductor layer 81. Two adjacent conductive members 23 in the Z direction are separated and insulated from each other via an insulating layer 70.

[0072] <1-1-4> Threshold voltage distribution of memory cell transistor MT Figure 13 shows an example of the threshold voltage distribution of memory cell transistors MT in the memory device 1 according to the first embodiment. In the graph shown in Figure 13, the horizontal axis represents the threshold voltage (Vth) of the memory cell transistors MT, and the vertical axis represents the number of memory cell transistors MT (NMTs). The first comparative example shown shows the threshold voltage of the memory cell transistors MT when predetermined data is written to a 3D-NAND having a structure in which the channel extends in a direction perpendicular to the substrate. As shown in Figure 13, in an HCF (Horizontal Channel Flash) such as the memory device 1 according to the first embodiment, the writing characteristics differ from position to position when predetermined data is written to the NAND string NS. Therefore, variations in the threshold voltage of the memory cell transistors MT may occur depending on their position.

[0073] For example, in memory device 1, pillars 30 (word lines WL), etc., may have a tapered or bowed shape. That is, the diameter of pillars 30, etc., may differ depending on the height from the bottom. In program operation using the same program voltage, the increase in threshold voltage is smaller when the diameter of the word line WL is large, and larger when the diameter of the word line WL is small. For this reason, the threshold voltage distribution of the memory cell transistor MT in memory device 1 according to the first embodiment is a combination of states S1 to S5, for example, when predetermined data is written. For example, when the channel is formed perpendicular to the substrate, as in the first comparative example, variations in the threshold distribution according to the diameter of the pillar can be suppressed. For this reason, memory device 1 is required to suppress variations in the threshold voltage of the memory cell transistor MT according to the diameter of the pillar 30.

[0074] <1-2> Writing operation Next, the write operation of the memory device 1 according to the first embodiment will be described. In the write operation, the memory device 1 repeatedly executes a combination of a program operation that increases the threshold voltage of the memory cell transistor MT and a verify read operation. Based on the result of the verify read operation, the memory device 1 can check whether the threshold voltage of the memory cell transistor MT to be written has reached the target state. Then, based on the result of the verify read operation, the memory device 1 sets the bit line BL to be programmed or disabled in a subsequent program operation.

[0075] During program operation, before applying the program voltage to the memory cell transistor MT to be written, a charging process is performed on the bit line BL. During the charging process, the selection transistor STD connected to the programmable bit line BL is controlled to the ON state. At this time, the channel voltage of the NAND string NS connected to the programmable bit line BL is based on the voltage applied to the bit line BL. On the other hand, during the charging process, the selection transistor STD connected to the program-protected bit line BL is controlled to the OFF state. At this time, the channel voltage of the NAND string NS connected to the program-protected bit line BL is boosted based on the voltage applied to each word line WL.

[0076] Furthermore, during the write operation, a low-level voltage is applied to each of the selection transistors BST, STD, and STS of the unselected block BLK. The selection line BS is shared by each selection transistor BST within the block BLK. Therefore, in a selected block BLK, the same voltage is applied to both the selection transistor BST connected to the programmable bit line BL and the selection transistor BST connected to the program-protected bit line BL. On the other hand, in a selected block BLK, different voltages may be applied to the selection transistor DST connected to the programmable bit line BL and the selection transistor DST connected to the program-protected bit line BL.

[0077] <1-2-1> Programmed bit line BL The following describes an example of the operation of each component associated with the bit line BL to be programmed during the writing operation of the memory device 1 according to the first embodiment. In the following description of the first embodiment, it is assumed that the voltage applied to the global bit line GBL is applied to the selection transistor BST via the local bit line LBIY.

[0078] (1: When charging) Figure 14 shows an example of the operation of the NAND string NS connected to the programmable bit line BL (programmable BL) during the charging phase of the write operation of the memory device 1 according to the first embodiment. As shown in Figure 14, during charging, the sequencer 14 applies voltage VSGD to the selection transistor STD (selection gate line SGD), voltage VSGS to the selection transistor STS (selection gate line SGS), voltage VBS to the selection transistor BST (selection line BS), voltage VDSL to the selection transistor DST (selection line DS), and voltage VINH to the driver wiring DRL. The sense amplifier unit SAU (sense amplifier section SA) applies voltage VBL to the global bit line GBL.

[0079] Voltages VSGD and VSGS are voltages corresponding to high levels. Voltage VSGD is higher than voltage VBS. Voltage VBS is higher than voltage VBL. On the programmable bit line BL, the sense amplifier unit SAU can control voltage VBL, for example, to a voltage corresponding to the position of memory cell transistor MT or the data to be written. Voltage VDSL is a voltage corresponding to a low level. Voltage VINH is higher than voltage VBS.

[0080] When voltage VDSL is applied to the selection transistor DST, it turns off. Therefore, the voltage VINH applied to the driver wiring DRL is not transferred to the local bit line LBIX via the selection transistor DST. When voltage VBS is applied to the selection transistor BST, it turns on. As a result, the voltage VBL applied to the global bit line GBL is transferred to the local bit line LBIX via the selection transistor BST. Then, the selection transistor STD turns on based on the voltage difference between the voltage VSGD applied to the gate and the local bit line LBIX. As a result, the channel voltage VCH of the NAND string NS is the voltage based on voltage VBL.

[0081] Subsequently, the program path voltage VPASS is applied to each memory cell transistor MT (word line WL) in the NAND string NS. The program path voltage VPASS is higher than the voltage VSGD. At this time, in the NAND string NS connected to the bit line BL to be programmed, the selection transistor STD is in the ON state, so the channel voltage is maintained at the voltage based on the voltage VBL.

[0082] (2: Programming time) Figure 15 shows an example of the operation of a NAND string NS connected to the bit line BL (write target BL) to be programmed during the programming of a write operation of the memory device 1 according to the first embodiment. As shown in Figure 15, the sequencer 14 applies a program voltage VPGM to the memory cell transistor MT (word line WL) to be written during programming. The program voltage VPGM is a higher voltage than the program path voltage VPASS. When the program voltage VPGM is applied, electrons are injected into the charge storage layer of the memory cell transistor MT based on the voltage difference between the control gate and the channel CH. Therefore, the amount of rise in the threshold voltage of the memory cell transistor MT can be controlled by adjusting the channel voltage VCH of the NAND string NS within a range where the selection transistor STD does not turn off. The program voltage VPGM is stepped up, for example, each time the program operation is repeated.

[0083] <1-2-2> Program-prohibited bit line BL Below, we will describe an example of the operation of each configuration associated with a program-prohibited bit line BL in the write operation of the memory device 1 according to the first embodiment, mainly highlighting the differences from the case of a programmable bit line BL described in Figures 14 and 15.

[0084] (1: When charging) Figure 16 shows an example of the operation of a NAND string NS connected to the program-protected bit line BL (program-protected BL) during the charging phase of a write operation of the memory device 1 according to the first embodiment. As shown in Figure 16, the sequencer 14 applies a voltage VDSH to the selection transistor DST (selection line DS) during charging. The sense amplifier unit SAU (sense amplifier section SA) applies a voltage VBLH to the global bit line GBL, for example. Voltage VDSH is a voltage corresponding to a high level. Voltage VBLH is a voltage that is higher than voltage VBL and lower than voltage VBS.

[0085] When the voltage VDSH is applied, the selection transistor DST turns ON. As a result, the voltage VINH applied to the driver wiring DRL is transferred to the local bit line LBIX via the selection transistor DST. This causes the voltage on the local bit line LBIX to become higher than the voltage VBS, and the selection transistor BST turns OFF. Also, the selection transistor STD turns OFF as the voltage on the local bit line LBIX rises. This causes the channel CH of the NAND string NS to become floating. Subsequently, when the program path voltage VPASS is applied to each memory cell transistor MT (word line WL) of the NAND string NS, the channel voltage VCH is boosted.

[0086] In the program-disabled bit line BL of the first embodiment, the voltage applied by the sense amplifier unit SAU to the global bit line GBL can be changed within a range that allows the selection transistor BST to remain in the off state. The sequencer 14 may apply a low-level voltage to the selection transistor BST (selection line BS) during the period when the local bit line LBIX is being charged via the selection transistor DST. In this case, the sequencer 14 applies the voltage VBS to the selection transistor BST after the charging of the local bit line LBIX is complete.

[0087] (2: Programming time) Figure 17 shows an example of the operation of a NAND string NS connected to a program-protected bit line BL (program-protected BL) during the programming of a write operation of the memory device 1 according to the first embodiment. As shown in Figure 17, during programming, a program voltage VPGM is applied to the memory cell transistor MT (word line WL) to be written to. When the program voltage VPGM is applied, the channel voltage VCH of the NAND string NS connected to the program-protected bit line BL is boosted, thereby suppressing the injection of electrons into the charge storage layer to be written to.

[0088] <1-3> Effects of the First Embodiment The memory device 1 according to the first embodiment described above can improve the reliability of the memory device 1. The effects of the first embodiment will be explained in detail below using a second comparative example. The second comparative example corresponds to the case in which the selection transistor DST and driver wiring DRL are omitted from the memory device 1 according to the first embodiment.

[0089] Figure 18 shows a specific example of the operation of the NAND string NS during a write operation in the second comparative example. Figures 18(A) and (B) show specific examples of the voltages of the global bit line GBL, selection transistor BST (selection line BS), local bit line LBIX, selection transistor STD (selection gate line SGD), and channel CH, respectively, when the device is programmed and when it is disabled. In the second comparative example, the maximum output voltage of the sense amplifier unit SAU is set to 2.2V. Also, during the write operation, in the selected block BLK, the voltage VBS is controlled to ~3V and the voltage VSGD is controlled to ~2.2V.

[0090] As shown in Figure 18(A), the sense amplifier unit SAU can control the voltage of the global bit line GBL, which corresponds to the programmable bit line BL, within the range of 0 to 0.6V. This range corresponds to the voltage range in which the selection transistor STD, with a voltage of ~2.2V applied to its gate, remains ON and the voltage of the global bit line GBL can be transferred to the channel CH. The voltage of the local bit line LBIX, which corresponds to the programmable bit line BL, is 0 to 0.6V based on the voltage of the global bit line GBL, and the channel voltage VCH is similarly 0 to 0.6V.

[0091] Furthermore, as shown in Figure 18(B), the sense amplifier unit SAU applies a voltage of 2.2V to the global bit line GBL, which corresponds to the program-protected bit line BL. This voltage corresponds to the voltage at which the selection transistor STD can be turned off. Specifically, the voltage of the local bit line LBIX, which corresponds to the program-protected bit line BL, becomes approximately 2.2V based on the voltage of the global bit line GBL. As the voltage of the local bit line LBIX and the voltage of the selection gate line SGD become approximately the same, the selection transistor STD is turned off. As a result of the selection transistor STD being turned off, the channel voltage VCH is boosted, for example, to approximately 4V.

[0092] Thus, in the second comparative example, the select transistor STD is controlled to the off state based on the voltage VBLH applied to the program-prohibited bit line BL during the write operation and the voltage VSGD applied to the select gate line SGD. For this reason, the voltage of the select gate line SGD cannot be raised above the maximum output voltage of the sense amplifier unit SAU. Also, due to the potential (voltage) loss in the select transistor STD, the transfer potential (voltage) is limited to ~0.6V.

[0093] Figure 19 shows a specific example of the operation of the NAND string NS during a write operation in the first embodiment. Figures 19(A) and (B) show specific examples of the voltages of the global bit line GBL, selection transistor BST (selection line BS), local bit line LBIX, selection transistor DST (selection line DS), selection transistor STD (selection gate line SGD), and channel CH, respectively, when the device is programmed and when it is disabled. In this example, the maximum output voltage of the sense amplifier unit SAU is set to 2.2V, similar to the second comparative example. During the write operation, the voltage VBS is controlled to ~3V in the selected block BLK, and the voltage VSGD is controlled to ~4V, which is higher than in the second comparative example.

[0094] As shown in Figure 19(A), in the memory device 1 according to the first embodiment, the selection transistor DST associated with the programmable bit line BL is controlled to be in the off state. Furthermore, the sense amplifier unit SAU of the first embodiment can control the voltage of the global bit line GBL corresponding to the programmable bit line BL over a wider range of 0 to 1.5V than in the second comparative example. This range corresponds to the voltage range in which the selection transistor STD, with a voltage of ~4V applied to its gate, remains in the ON state and the voltage of the global bit line GBL can be transferred to the channel CH. In this example, the voltage of the local bit line LBIX corresponding to the programmable bit line BL is 0 to 1.5V based on the voltage of the global bit line GBL, and the channel voltage VCH is similarly 0 to 1.5V.

[0095] Furthermore, as shown in Figure 19(B), in the memory device 1 according to the first embodiment, the selection transistor DST associated with the program-protected bit line BL is controlled to be ON. As a result, the voltage VINH (e.g., ~4V) of the driver wiring DRL is transferred to the local bit line LBIX via the selection transistor DST. The voltage of the local bit line LBIX corresponding to the program-protected bit line BL then becomes ~4V based on the voltage of the driver wiring DRL. As a result, the voltage of the local bit line LBIX and the voltage of the selection gate line SGD become approximately the same, and the selection transistor STD is turned OFF. Consequently, because the selection transistor STD is turned OFF, the channel voltage VCH is boosted, rising to, for example, ~6V. In this example, the sense amplifier unit SAU of the first embodiment applies a voltage of, for example, 2.2V to the global bit line GBL corresponding to the program-protected bit line BL. The voltage applied to the global bit line GBL corresponding to the program-protected bit line BL is not particularly limited.

[0096] Thus, in the first embodiment, when programming is disabled during a write operation, the selection transistor STD is controlled to the off state based on the voltage VINH applied via the selection transistor DST and the voltage VSGD applied to the selection gate line SGD. Therefore, the memory device 1 according to the first embodiment can raise the voltage of the selection gate line SGD to above the maximum output voltage of the sense amplifier unit SAU. Consequently, potential (voltage) loss in the selection transistor STD is suppressed, and the transfer potential (voltage) can be extended to ~1.5V. In other words, even when the maximum output voltage of the sense amplifier unit SAU is the same as in the second comparative example, the memory device 1 according to the first embodiment can control the voltage applied to the bit line BL to be programmed over a wider range than in the second comparative example.

[0097] As a result, the memory device 1 according to the first embodiment can expand the operating voltage range of the voltage VBL applied by the sense amplifier unit SAU to the bit line BL to be programmed during writing operations, thereby increasing the variations in operation.

[0098] For example, the memory device 1 according to the first embodiment can reduce differences in writing characteristics by changing the voltage applied to the bit line BL to be programmed according to the position of the memory cell transistor MT. As a result, the memory device 1 according to the first embodiment can suppress the difference in the amount of threshold voltage rise according to the position of the memory cell transistor MT, and can narrow the threshold voltage distribution of the memory cell transistor MT compared to the second comparative example. Furthermore, as the threshold voltage distribution narrows, the memory device 1 can suppress the occurrence of read errors. In addition, the memory device 1 according to the first embodiment can write multiple levels of data simultaneously by changing the voltage applied to the bit line BL to be programmed according to the data to be written. In this case, the memory device 1 can improve the speed of the writing operation.

[0099] As described above, the memory device 1 according to the first embodiment can improve the performance of the memory device 1.

[0100] <2> Second Embodiment The memory device 1A according to the second embodiment is configured to achieve the same operation as the first embodiment when multiple local bit lines LBIY are connected to one global bit line GBL. The differences between the memory device 1A according to the second embodiment and the first embodiment are described below.

[0101] <2-1> Composition First, the configuration of the memory device 1A according to the second embodiment will be described.

[0102] <2-1-1> Circuit configuration of memory device 1A Figure 20 is a circuit diagram showing an example of the circuit configuration of a memory device 1A according to the second embodiment. As shown in Figure 20, the memory cell array 10 of the memory device 1A is provided with two local bit lines LBIYa and LBIYb for one global bit line GBL, and includes selection transistors ASTa and ASTb. Hereinafter, the reference code of the configuration associated with the local bit line LBIYa is appended with "a", and the reference code of the configuration associated with the local bit line LBIYb is appended with "b".

[0103] The local bit line LBIYa is connected to the global bit line GBL via the selection transistor ASTa and the conductive layer 21. That is, one end and the other end of the selection transistor ASTa are connected to the local bit line LBIYa and the global bit line GBL, respectively. The local bit line LBIYb is connected to the global bit line GBL via the selection transistor ASTb and the conductive layer 21. That is, one end and the other end of the selection transistor ASTb are connected to the local bit line LBIYb and the global bit line GBL, respectively. The selection transistors ASTa and ASTb are connected to the selection lines ASa and ASb, respectively. The voltages applied to each of the selection lines ASa and ASb are generated by the driver circuit 15, for example, based on the control of the sequencer 14.

[0104] At least one block BLKa is connected to the local bit line LBIYa. The local bit line LBIXa of each block BLKa is connected to the local bit line LBIYa via the selection transistor BSTA. The selection transistor BSTA is connected to the selection line BSa. Four NAND strings NS, corresponding to string units SU0 to SU3, are connected between the local bit line LBIXa and the source line SL. The driver wire DRLa is connected to the local bit line LBIYa via the selection transistor DSTA. The gate of the selection transistor DSTA is connected to the selection line DSa.

[0105] At least one block BLKb is connected to the local bit line LBIYb. The local bit line LBIXb of each block BLKb is connected to the local bit line LBIYb via the selection transistor BSTb. The selection transistor BSTb is connected to the selection line BSb. Four NAND strings NS, corresponding to string units SU0 to SU3, are connected between the local bit line LBIXb and the source line SL. The driver wire DRLb is connected to the local bit line LBIYb via the selection transistor DSTb. The gate of the selection transistor DSTb is connected to the selection line DSb.

[0106] As described above, the memory device 1A according to the second embodiment is provided with a selection transistor AST for selecting a plurality of local bit lines LBIY connected to a single global bit line GBL. In the memory device 1A, unlike the first embodiment, the selection transistor DST is connected to the local bit line LBIY instead of the local bit line LBIX. The number of local bit lines LBIY connected to the global bit line GBL may be three or more. The voltages applied to the driver wirings DRLa and DRLb may be controlled independently or collectively.

[0107] <2-1-2> Structure of memory device 1A Figure 21 is a plan view showing an example of a planar layout of a memory cell array 10 provided in a memory device 1A according to the second embodiment. Figure 21 shows an extracted layer of the memory cell array 10 where conductive members 22a (local bit lines LBIYa) and 22b (local bit lines LBIYb) are provided. As shown in Figure 21, the memory cell array 10 of the second embodiment further comprises conductive layers 27a and 27b. Conductive layers 27a and 27b are used as driver wiring DRLa and DRLb, respectively.

[0108] A selection transistor BSTA is provided between each conductive member 23a (local bit line LBIXa) from conductive member 22a (local bit line LBIYa). A selection transistor DSTA is provided between conductive member 23a (local bit line LBIXa) and conductive layer 27a (driver wiring DRLa). A selection transistor BSTb is provided between conductive member 22b (local bit line LBIYb) and conductive member 23b (local bit line LBIXb). A selection transistor DSTb is provided between conductive member 23b (local bit line LBIXb) and conductive layer 27b (driver wiring DRLb).

[0109] The structure and arrangement of the selection transistors DSt and DSTb and the conductive layers 27a and 27b are not limited to the configuration shown in Figure 21. Other elements may be added if it is possible to achieve the same operation as the writing operation described later. The arrangement of other components of the memory cell array 10A can also be changed as appropriate. Other components of the memory device 1A according to the second embodiment are the same as those of the memory device 1 according to the first embodiment.

[0110] <2-2> Writing operation Next, the write operation of the memory device 1A according to the second embodiment will be explained using the case where block BLKa is selected and block BLKb is not selected as an example.

[0111] <2-2-1> Programmed bit line BL The following describes an example of the operation of each configuration associated with the programmable bit line BL in the writing operation of the memory device 1A according to the second embodiment, mainly highlighting the differences from the writing operation of the memory device 1 according to the first embodiment.

[0112] (1: When charging) Figure 22 shows an example of the operation of the NAND string NS connected to the programmable bit line BL (programmable BL) during the charging phase of the write operation of the memory device 1 according to the second embodiment. As shown in Figure 22, during charging, the sequencer 14 applies voltage VBSH to the selection transistor BSTA (selection line BSa), voltage VDSL to the selection transistor DSTa (selection line DS), voltage VASH to the selection transistor ASTa (selection line ASa), voltage VASL to the selection transistor ASTb (selection line ASb), and voltage VINH to the driver wiring DRLa. The sense amplifier unit SAU applies voltage VBL to the global bit line GBL. Voltage VASL is a voltage corresponding to a low level. Voltage VASH corresponds to a high level and is a higher voltage than voltage VBL. Voltage VBSH is, for example, a higher voltage than voltage VASH.

[0113] When the voltage VASL is applied, the selection transistor ASTb is turned off. When the voltage VASH is applied, the selection transistor ASTa is turned on. When the voltage VDSL is applied, the selection transistor DSTA is turned off. Therefore, the voltage VINH applied to the driver wiring DRLa is not transferred to the local bit line LBIXa via the selection transistor DSTA. When the voltage VBSH is applied, the selection transistor BSTA is turned on. As a result, the voltage VBL applied to the global bit line GBL is transferred to the local bit line LBIXa via the selection transistors ASTa and BSTA. Then, the selection transistor STD is turned on based on the voltage difference between the voltage VSGD applied to the gate and the local bit line LBIXa. As a result, the channel voltage VCH of the NAND string NS is the voltage based on the voltage VBL.

[0114] (2: Programming time) Figure 23 shows an example of the operation of a NAND string NS connected to the bit line BL (programmed BL) to be programmed during the programming of a write operation of the memory device 1A according to the second embodiment. As shown in Figure 23, the sequencer 14 applies a program voltage VPGM to the memory cell transistor MT (word line WL) to be written during programming. When the program voltage VPGM is applied, electrons are injected into the charge storage layer of the memory cell transistor MT based on the voltage difference between the control gate and the channel CH. Therefore, the amount of rise in the threshold voltage of the memory cell transistor MT can be controlled, similar to the first embodiment, by adjusting the channel voltage VCH of the NAND string NS within a range in which the selection transistor STD does not turn off.

[0115] <2-2-2> Program-prohibited bit line BL Below, we will explain, in the writing operation of the memory device 1A according to the second embodiment, an example of the operation of each configuration associated with the program-prohibited bit line BL, mainly highlighting the differences from the programmable bit line BL described in Figures 22 and 23.

[0116] (1: When charging) Figure 24 shows an example of the operation of a NAND string NS connected to the program-protected bit line BL (program-protected BL) during the charging phase of a write operation of the memory device 1 according to the second embodiment. As shown in Figure 24, the sequencer 14 applies a voltage VDSH to the selection transistor DSTa (selection line DSa) during programming. The sense amplifier unit SAU applies a voltage VBLH to the global bit line GBL, for example. In the second embodiment, the voltage VBLH is higher than the voltage VBL and lower than the voltages VASH and VBSH, respectively.

[0117] When the voltage VDSH is applied to the selection transistor DSTa, it turns ON. As a result, the voltage VINH applied to the driver wiring DRLa is transferred to the local bit line LBIYa via the selection transistor DSTa. This causes the voltage on the local bit line LBIYa to become higher than the voltage VASH, and the selection transistor ASTa turns OFF. Also, when the voltage VBSH is applied to the selection transistor BSTA, it turns ON. As a result, the voltage on the local bit line LBIYa is transferred to the local bit line LBIXa via the selection transistor BSTA. Then, the selection transistor STD turns OFF as the voltage on the local bit line LBIXa rises. This causes the channel CH of the NAND string NS to become floating. Subsequently, when the program path voltage VPASS is applied to each memory cell transistor MT (word line WL) of the NAND string NS, the channel voltage VCH is boosted.

[0118] In the program-disabled bit line BL of the second embodiment, the voltage applied by the sense amplifier unit SAU to the global bit line GBL can be appropriately changed within the range in which the selection transistor ASTa is in the off state.

[0119] (2: Programming time) Figure 25 shows an example of the operation of a NAND string NS connected to a write-protected bit line BL (write-protected BL) during programming of a write operation of the memory device 1 according to the second embodiment. As shown in Figure 25, during programming, a program voltage VPGM is applied to the memory cell transistor MT (word line WL) to be written to. When the program voltage VPGM is applied, the channel voltage VCH of the NAND string NS connected to the program-protected bit line BL is boosted, and as with the first embodiment, electron injection into the charge storage layer to be written is suppressed.

[0120] Other operations of the memory device 1A according to the second embodiment are the same as those of the memory device 1 according to the first embodiment.

[0121] <2-3> Effects of the second embodiment The memory device 1A according to the second embodiment can achieve the same effects as the first embodiment. Note that the positions of the selection transistors DSt and DSTb described in the second embodiment may be changed as in the first embodiment. Specifically, the selection transistors DSt and DSTb may be connected to local bit lines LBIXa and LBIXb, respectively. Even in this case, the same effects as the first embodiment can be achieved by controlling the selection transistors DSt and DSTb in the same way as in the first embodiment.

[0122] <3> Third Embodiment The memory device 1B according to the third embodiment achieves the same effects as the first embodiment by utilizing a circuit formed in the stepped region SR. The differences between the memory device 1B according to the third embodiment and the first and second embodiments are described below.

[0123] <3-1> Composition Next, the configuration of the memory device 1B according to the third embodiment will be described.

[0124] <3-1-1> Circuit configuration of memory device 1B Figure 26 is a circuit diagram showing an example of the circuit configuration of the memory device 1B according to the third embodiment. As shown in Figure 26, the memory device 1B according to the third embodiment has a configuration in which a selection transistor OST and DSTc and a control bit line CBL are added for each global bit line GBL compared to the memory device 1 according to the first embodiment.

[0125] The selection transistors OST and DSTc are located in the step region SR. OST and DSTc are n-channel and p-channel transistors, respectively. One end and the other end of the selection transistor OST are connected to the global bit line GBL and the local bit line LBIY, respectively. One end and the other end of the selection transistor DSTc are connected to the driver wiring DRL and the local bit line LBIY, respectively. A control bit line CBL is connected to the gates of both the selection transistors OST and DSTc. Each control bit line CBL can be controlled independently, for example, by the sequencer 14.

[0126] <3-1-2> Structure of memory device 1B Figure 27 is a cross-sectional view showing an example of the cross-sectional structure of the stepped region SR of the memory cell array 10 of the memory device 1B according to the third embodiment. As shown in Figure 27, the memory cell array 10 includes, for example, a conductive layer 90, semiconductor layers 91 and 92, conductive layers 93, 94 and 95, and contacts C1 to C4 in the stepped region SR.

[0127] The conductive layer 90 is provided above the conductive layer 21. The conductive layer 90 is connected to the conductive layer 21 via contact C1. Semiconductor layers 91 and 92 are provided on the wiring layer above the conductive layer 90. Conductive layers 93 and 94 are provided on the wiring layer above the semiconductor layer 91. A conductive layer 95 is provided on the wiring layer above the conductive layers 93 and 94.

[0128] The semiconductor layer 91 contains P-type impurities. The semiconductor layer 91 also contains diffusion regions DIF1 and DIF2 of N-type impurities. A gate electrode GE1 is provided between diffusion regions DIF1 and DIF2, and on the semiconductor layer 91, via a gate insulating film OX1. The semiconductor layer 91, the gate insulating film OX1, and the gate electrode GE1 function as a selection transistor (OST). Diffusion region DIF1 of the semiconductor layer 91 is connected to the conductor layer 90 via contact C2. Diffusion region DIF2 of the semiconductor layer 91 is connected to the conductor layer 93 via contact C3. The conductor layer 93 functions as a global bit line (GBL).

[0129] The semiconductor layer 92 contains N-type impurities. The semiconductor layer 92 also contains diffusion regions DIF3 and DIF4 of P-type impurities. A gate electrode GE2 is provided between diffusion regions DIF3 and DIF4, and on the semiconductor layer 92, via a gate insulating film OX2. The semiconductor layer 92, the gate insulating film OX2, and the gate electrode GE2 function as a selection transistor DSTc. Diffusion region DIF3 of the semiconductor layer 92 is connected to the conductor layer 90 via contact C2. Diffusion region DIF4 of the semiconductor layer 92 is connected to the conductor layer 94 via contact C3. The conductor layer 94 functions as a driver wiring (DRL).

[0130] The conductive layer 95 is connected to the gate electrode GE1 of the selection transistor OST and the gate electrode GE2 of the selection transistor DSTc, respectively, via two contacts C4. The conductive layer 95 functions as a control bit line CBL.

[0131] The other configurations of the memory device 1B according to the third embodiment are the same as those of the memory device 1 according to the first embodiment.

[0132] <3-2> Writing operation Next, the writing operation of the memory device 1B according to the third embodiment will be described.

[0133] <3-2-1> Programmed bit line BL Figure 28 shows an example of the operation of the NAND string NS connected to the bit line BL (programmed BL) to be programmed during the writing operation of the memory device 1B according to the third embodiment. As shown in Figure 28, during charging, the sequencer 14 applies voltage VSGD to the selection transistor STD (selection gate line SGD), voltage VSGS to the selection transistor STS (selection gate line SGS), voltage VBS to the selection transistor BST (selection line BS), voltage VDSL to the selection transistor DST (selection line DS), voltage VINH to the driver wiring DRL, and a high-level voltage ("H") to the control bit line CBL. The sense amplifier unit SAU (sense amplifier section SA) applies voltage VBL to the global bit line GBL.

[0134] When a high-level voltage is applied, the selection transistors OST and DSTc become ON and OFF, respectively. As a result, the voltage VBL applied to the global bit line GBL is transferred to the local bit line LBIY, and the local bit line LBIY is charged. On the other hand, the voltage VINH applied to the driver wiring DRL is not transferred to the local bit line LBIY via the selection transistor DSTc. Then, the selection transistor BST, to which the voltage VBSH is applied, becomes ON. As a result, the voltage of the local bit line LBIY is transferred to the local bit line LBIX via the selection transistor BST. Then, the selection transistor STD becomes ON based on the voltage difference between the voltage VSGD applied to its gate and the local bit line LBIX. As a result, the channel voltage VCH of the NAND string NS becomes the voltage based on the voltage VBL.

[0135] Subsequently, the program path voltage VPASS is applied to each memory cell transistor MT (word line WL) of the NAND string NS. At this time, in the NAND string NS connected to the bit line BL to be programmed, the selection transistor STD is in the ON state, so the channel voltage is maintained at the voltage based on voltage VBL.

[0136] During programming, when the program voltage VPGM is applied to the memory cell transistor MT (word line WL) to be written, electrons are injected into the charge storage layer of the memory cell transistor MT based on the voltage difference between the control gate and the channel CH. Therefore, the amount of rise in the threshold voltage of the memory cell transistor MT can be controlled, similar to the first embodiment, by adjusting the channel voltage VCH of the NAND string NS within a range where the selection transistor STD does not turn off.

[0137] <3-2-2> Program-prohibited bit line BL Figure 29 shows an example of the operation of a NAND string NS connected to the program-protected bit line BL (program-protected BL) during the programming of a write operation of the memory device 1B according to the third embodiment. As shown in Figure 29, the sequencer 14 applies a low-level voltage ("L") to the control bit line CBL during charging. In addition, the sense amplifier unit SAU (sense amplifier section SA) applies a voltage VBLH to the global bit line GBL, for example.

[0138] When a low-level voltage is applied to the selection transistors OST and DSTc, they become OFF and ON, respectively. As a result, the voltage VINH applied to the driver wiring DRL is transferred to the local bit line LBIY, and the local bit line LBIY is charged. On the other hand, the voltage VBLH applied to the global bit line GBL is not transferred to the local bit line LBIY via the selection transistor OST. Then, the selection transistor BST, to which the voltage VBSH is applied, becomes ON. As a result, the voltage of the local bit line LBIY is transferred to the local bit line LBIX via the selection transistor BST. Then, the selection transistor STD becomes OFF as the voltage of the local bit line LBIX rises. As a result, the channel CH of the NAND string NS becomes floating. Subsequently, when the program path voltage VPASS is applied to each memory cell transistor MT (word line WL) of the NAND string NS, the channel voltage VCH is boosted.

[0139] During programming, when the program voltage VPGM is applied to the memory cell transistor MT (word line WL) to be written, electrons are injected into the charge storage layer of the memory cell transistor MT based on the voltage difference between the control gate and the channel CH. Therefore, the amount of rise in the threshold voltage of the memory cell transistor MT can be controlled, similar to the first embodiment, by adjusting the channel voltage VCH of the NAND string NS within a range where the selection transistor STD does not turn off.

[0140] During programming, when the program voltage VPGM is applied to the memory cell transistor MT (word line WL) to be written, the channel voltage VCH of the NAND string NS connected to the program-prohibited bit line BL is boosted. Therefore, as in the first embodiment, electron injection into the charge storage layer to be written is suppressed.

[0141] Other operations of the memory device 1B according to the third embodiment are the same as those of the memory device 1 according to the first embodiment.

[0142] <3-3> Effects of the Third Embodiment The memory device 1B according to the third embodiment can achieve the same effects as the first embodiment. Furthermore, the memory device 1B according to the third embodiment can reduce the number of elements used to control the bit line BL compared to the first embodiment. As a result, the memory device 1B according to the third embodiment can reduce the circuit area compared to the first embodiment, thereby reducing the manufacturing cost of the memory device 1.

[0143] <4> Fourth Embodiment The memory device 1C according to the fourth embodiment controls the circuit formed in the step region SR in the memory device 1B according to the third embodiment based on the voltage of the global bit line GBL. The differences between the memory device 1C according to the fourth embodiment and the memory device 1B according to the third embodiment are described below.

[0144] <4-1> Composition First, the configuration of the memory device 1C according to the fourth embodiment will be described.

[0145] <4-1-1> Circuit configuration of memory device 1C Figure 30 is a circuit diagram showing an example of the circuit configuration of the memory device 1C according to the fourth embodiment. As shown in Figure 30, the memory device 1C according to the fourth embodiment has a configuration in which an operation selection circuit 19 is added for each global bit line GBL compared to the memory device 1B according to the third embodiment. The operation selection circuit 19 has an input terminal IN connected to the global bit line GBL and an output terminal OUT connected to the control bit line CBL. The operation selection circuit 19 is configured to control the voltage of the output terminal OUT to a low level or a high level based on the voltage of the associated global bit line GBL.

[0146] <4-1-2> Configuration of the operation selection circuit 19 Figure 31 is a circuit diagram showing an example of the circuit configuration of the operation selection circuit 19 provided in the memory device 1C according to the fourth embodiment. As shown in Figure 31, the operation selection circuit 19 includes transistors NM and PM. Transistors NM and PM are n-channel transistors and p-channel transistors, respectively. A ground voltage VSS is applied to one end of transistor NM as a voltage corresponding to a low level, for example. A power supply voltage VDD is applied to one end of transistor PM as a voltage corresponding to a high level, for example. The other ends of transistors NM and PM are connected to the output terminal OUT. The gates of transistors NM and PM are connected to the input terminal IN.

[0147] The operation selection circuit 19 outputs a high-level voltage (e.g., power supply voltage VDD) to the output terminal OUT when the voltage at the input terminal IN is less than a predetermined voltage, with transistors NM and PM in the off and on states, respectively. Furthermore, when the voltage at the input terminal IN is greater than or equal to the predetermined voltage, the operation selection circuit 19 outputs a low-level voltage (e.g., ground voltage VSS) to the output terminal OUT when transistors NM and PM are in the on and off states, respectively.

[0148] The operation selection circuit 19 may have any other circuit configuration as long as it can achieve the same operation. The operation selection circuit 19 may also be configured to output a high-level voltage (e.g., power supply voltage VDD) to the output terminal OUT when the voltage at the input terminal IN is equal to a predetermined threshold. The other configurations of the memory device 1C according to the fourth embodiment are the same as those of the memory device 1B according to the third embodiment.

[0149] <4-2> Writing operation Next, the writing operation of the memory device 1C according to the fourth embodiment will be described.

[0150] <4-2-1> Programmed bit line BL Figure 32 shows an example of the operation of a NAND string NS connected to the bit line BL (programmed BL) to be programmed during the programming of the write operation of the memory device 1C according to the fourth embodiment. As shown in Figure 32, the sense amplifier unit SAU (sense amplifier section SA) applies a voltage VBL to the bit line BL to be programmed. The voltage VBL is lower than a predetermined threshold TH set in the operation selection circuit 19. Therefore, the operation selection circuit 19 applies a high-level voltage to the control bit line CBL based on the fact that the voltage at the input terminal IN is VBL. Then, the selection transistors OST and DSTc to which the high-level voltage is applied become ON and OFF, respectively. Other operations such as the NAND string NS connected to the bit line BL to be programmed are the same as the operations described with reference to Figure 28 in the third embodiment.

[0151] <4-2-2> Program-prohibited bit line BL Figure 33 shows an example of the operation of a NAND string NS connected to a program-protected bit line BL (program-protected BL) during the programming of a write operation of the memory device 1C according to the fourth embodiment. As shown in Figure 33, the sense amplifier unit SAU (sense amplifier section SA) applies a voltage VBLH to the bit line BL to be programmed. The voltage VBLH is higher than a predetermined threshold TH set in the operation selection circuit 19. Therefore, the operation selection circuit 19 applies a low-level voltage to the control bit line CBL based on the fact that the voltage at the input terminal IN is VBLH. Then, the selection transistors OST and DSTc to which the low-level voltage is applied become the off state and the on state, respectively. Other operations such as the NAND string NS connected to the program-protected bit line BL are the same as the operations described using Figure 29 in the third embodiment.

[0152] Other operations of the memory device 1C according to the fourth embodiment are the same as those of the memory device 1B according to the third embodiment.

[0153] <4-3> Effects of the fourth embodiment The memory device 1C according to the fourth embodiment can achieve the same effects as the third embodiment. Furthermore, the memory device 1C according to the fourth embodiment can reduce the area required for the control bit line CBL and the circuit area used to control the control bit line CBL compared to the third embodiment. As a result, the memory device 1C according to the fourth embodiment can reduce the circuit area compared to the third embodiment, thereby reducing the manufacturing cost of the memory device 1C.

[0154] <5> Variations, etc. The concepts described in the above embodiments can be combined as appropriate. For example, the configuration described in the second embodiment, in which multiple local bit lines LBIY are connected to one global bit line GBL via a selection transistor AST, may be combined with any of the first, third, and fourth embodiments. In the above embodiments, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 can each be modified as appropriate. The number of wiring layers and contacts of the memory device 1 can be modified as appropriate depending on the circuit design. Each pillar and each contact may have a tapered shape, an inverse tapered shape, or a bowed shape. Each wiring in the multilayer wiring may include a metal oxide film around a conductor such as tungsten. Conductor layers that are alternately stacked with insulating layers in the multilayer wiring may be considered to include such a metal oxide film.

[0155] In the above embodiment, the high-level voltage is the voltage at which an n-channel transistor with that voltage applied to its gate turns on, and a p-channel transistor with that voltage applied to its gate turns off. The low-level voltage is the voltage at which an n-channel transistor with that voltage applied to its gate turns off, and a p-channel transistor with that voltage applied to its gate turns on. The high-level and low-level voltages may each be referred to as logic levels. In this specification, the application of a voltage to a word line WL corresponds to the driver circuit 15 applying a voltage to the word line WL via the row decoder module 16. Similarly, the application of a voltage to other wiring corresponds to the driver circuit 15 applying a voltage via the row decoder module 16. The voltage of each wiring may be estimated based on the voltage of the signal line connecting the driver circuit 15 and the row decoder module 16.

[0156] In this specification, “connection” means that an electrical connection is made, and does not exclude, for example, the interposition of another element. “Electrically connected” may be via an insulator, as long as it is possible to operate in the same manner as an electrically connected connection. “Region” may be considered as a configuration included by the substrate 20. For example, if the substrate 20 is specified to include a stepped region SR, the stepped region SR is associated with the region above the substrate 20. “Height” corresponds to, for example, the distance in the Z direction between the configuration to be measured and the substrate 20. A configuration other than the substrate 20 may be used as the reference for “height”. “Top view” corresponds to, for example, viewing the surface of the substrate 20 from the vertical direction of the substrate 20. “Conductivity type” corresponds to P-type or N-type.

[0157] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0158] 1,1A,1B,1C...Memory device, 2...Memory controller, 10...Memory cell array, 11...Input / output circuit, 12...Logic controller, 13...Register circuit, 14...Sequencer, 15...Driver circuit, 16...Raw decoder module, 17...Data register, 18...Sense amplifier module, 19...Operation selection circuit, 20...Substrate, 21,26,27,27a,27b,90,93,94,95...Conductive layer, 22,22a,22b,23,23a,23b...Conductive material, 24,81,83,91,92...Semiconductor layer, 25,C1~C4...Contact, 28,80,82...Insulating material, 30,40,40a,43,43a,50,53,60...P Rah, 31, 33, 41, 42, 51, 52…Insulating film, 32…Conductive film, 70…Insulating layer, DIF1, DIF2, DIF3, DIF4…Diffusion region, GE1, GE2…Gate electrode, OX1, OX2…Gate insulating film, RD…Raw decoder, SAU…Sense amplifier unit, BLK…Block, SU…String unit, NS…NAND string, BL…Bit line, CBL…Control bit line, WL…Word line, SGD, SGS…Selection gate line, DRL…Driver wiring, MT…Memory cell transistor, STD, STS, BST, DST…Selection transistor, BS, DS…Selection line, LBIX, LBIY…Local bit line, GBL…Global bit line

Claims

1. The first bit line and, A first selection transistor, one end of which is connected to the first bit line, The second bit line connected to the other end of the first selection transistor, A string including a second selection transistor connected to the second bit line and a memory cell transistor, The word line connected to the memory cell transistor, A sense amplifier connected to the first bit line, A driver circuit connected to the first bit line or the second bit line, During a write operation, if the memory cell transistor is set to program-disabled, the sense amplifier applies a first voltage to the first bit line, and the driver circuit applies a second voltage higher than the first voltage to the second bit line. Memory device.

2. In the writing operation, the driver circuit applies the second voltage to the second bit line for a first time period, and then stops applying the second voltage to the second bit line. The memory device according to claim 1.

3. During a write operation, when the memory cell transistor is set as the target for programming, the sense amplifier applies a third voltage lower than the first voltage to the first bit line. The memory device according to claim 1.

4. A third bit line connected between the sense amplifier and the first bit line, The system further comprises a third selection transistor, the first and second of which are connected to the third bit line and the first bit line, respectively. The driver circuit is connected to the first bit line. The memory device according to claim 1.

5. A third bit line connected between the sense amplifier and the first bit line, A third select transistor of first conductivity type, with one end and the other end connected to the third bit line and the first bit line, respectively. The system further comprises a fourth bit line connected to the gate of the third selection transistor, The driver circuit includes a fourth selection transistor having one end connected to the first bit line, the other end to which the second voltage is applied, and the gate connected to the fourth bit line, and having a second conductivity type different from the first conductivity type. The memory device according to claim 1.

6. The system further comprises a sequencer that performs the aforementioned writing operation, The sequencer, in the write operation, applies a voltage of a first logic level to the fourth bit line when the memory cell transistor is set to program-disabled, and applies a voltage of a second logic level different from the first logic level to the fourth bit line when the memory cell transistor is set to program. The memory device according to claim 5.

7. It further includes an operation selection circuit, The operation selection circuit, in the write operation, applies a voltage of a first logic level to the fourth bit line when the output voltage of the sense amplifier is less than a first voltage, and applies a voltage of a second logic level different from the first logic level to the fourth bit line when the output voltage is equal to or greater than the first voltage. The memory device according to claim 5.

8. It further comprises a first conductive layer, a first contact, and a second contact. The third selection transistor includes a first semiconductor layer of a third conductivity type, a first gate insulating film on the first semiconductor layer, and a first gate electrode on the first gate insulating film. The fourth selection transistor is provided at the same height as the first semiconductor layer and includes a second semiconductor layer having a fourth conductivity type different from the third conductivity type, a second gate insulating film on the second semiconductor layer, and a second gate electrode on the second gate insulating film. The first conductive layer is provided above the first semiconductor layer. The first contact connects the first conductive layer and the first gate electrode. The second contact connects the first conductive layer and the second gate electrode. The memory device according to claim 5.

9. Further equipped with a circuit board, The string includes a third semiconductor layer that extends in a first direction parallel to the surface of the substrate and has a portion that functions as a channel for the memory cell transistor. The memory device according to claim 1.

10. The present invention further comprises a first pillar extending in a second direction intersecting the first direction and functioning as the word line, wherein the portion where the first pillar and the third semiconductor layer intersect functions as the memory cell transistor. The memory device according to claim 9.

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