Semiconductor memory

Abstract

To improve processing power. [Solution] According to the embodiment, the semiconductor memory device includes a plurality of memory strings NS, each containing a plurality of memory cells MC stacked spaced apart in a first direction and arranged side by side in a second direction with current paths connected in series; a word line WL connected to the plurality of first memory cells stacked spaced apart in the first direction; and a plurality of bit lines BL. The plurality of memory cells are capable of storing data corresponding to any of a plurality of states. In program operation, the plurality of states are classified into a plurality of groups (groups A to D), and the row decoder applies a plurality of pulse voltages to the word line, each corresponding to a plurality of groups. In program verification operation, the row decoder applies a plurality of verify voltages to the word line, each corresponding to a plurality of states.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device.

Background Art

[0002] As a semiconductor memory device, a three-dimensional stacked NAND flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In one embodiment of the present invention, a semiconductor memory device capable of improving processing capabilities is provided.

Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment includes a plurality of memory strings, each containing a plurality of memory cells stacked spaced apart in a first direction and arranged side by side in a second direction intersecting the first direction, with current paths connected in series; a word line extending in the first direction and connected to the gates of a plurality of first memory cells stacked spaced apart in the first direction; a plurality of bit lines connected to each of the plurality of memory strings; a row decoder connected to the word line; a sense amplifier connected to the plurality of bit lines; and a controller configured to execute a write operation by repeatedly performing a program loop including a program operation and a program verify operation. Each of the plurality of memory cells is capable of storing data corresponding to any one of a plurality of states. In the program operation of the plurality of first memory cells, the plurality of states are classified into a plurality of groups, and the row decoder applies a plurality of pulse voltages to the word line, each corresponding to the plurality of groups. In the program verify operation of the plurality of first memory cells, the row decoder applies a plurality of verify voltages to the word line, each corresponding to the plurality of states. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing the overall configuration of the semiconductor memory device according to the first embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 3] A perspective view showing a three-dimensional example of the circuit configuration of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 4] A plan view showing an example of a planar layout of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 5] A cross-sectional view along line IV-IV in Figure 4, showing an example of the cross-sectional structure of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 6]A cross-sectional view along the VV line in Figure 5, showing an example of the cross-sectional structure of a memory cell transistor included in a semiconductor memory device according to the first embodiment. [Figure 7] A cross-sectional view along the line VI-VI in Figure 4, showing an example of the cross-sectional structure of a memory cell array included in a semiconductor memory device according to the first embodiment. [Figure 8] A cross-sectional view along line VII-VII in Figure 7, showing an example of the cross-sectional structure of a selection transistor included in a semiconductor memory device according to the first embodiment. [Figure 9] This figure shows the threshold voltage distribution and data allocation when the memory cell transistor included in the semiconductor memory device according to the first embodiment is a TLC. [Figure 10] This figure shows an example of the change in the threshold voltage distribution of a memory cell transistor due to multi-pulse writing operation. [Figure 11] A diagram showing an example of state grouping when the memory cell transistor included in the semiconductor memory device according to the first embodiment is a TLC. [Figure 12] A timing chart showing an example of the voltage of each wire during multi-pulse writing operation in a semiconductor memory device according to the first embodiment. [Figure 13] A flowchart showing an example of the flow of a multi-pulse write operation in a semiconductor memory device according to the first embodiment. [Figure 14] This figure shows a modified example of state grouping when the memory cell transistor included in the semiconductor memory device according to the first embodiment is a TLC. [Figure 15] A timing chart showing an example of the voltage of the selected word line during multi-pulse writing operation in a semiconductor memory device according to the second embodiment. [Figure 16] A figure showing an example of the pulse voltage application conditions in a multi-pulse write operation in a semiconductor memory device according to the second embodiment. [Figure 17] A figure showing the transition of the threshold voltage distribution for each group during multi-pulse writing operation in a semiconductor memory device according to the second embodiment. [Figure 18]A diagram showing an example of grouping states when the memory cell transistor included in the semiconductor memory device according to the third embodiment is TLC. [Figure 19] A timing chart showing an example of the voltage of each wiring in the multi-pulse write operation in the semiconductor memory device according to the third embodiment. [Figure 20] A diagram showing the transition of the threshold voltage distribution for each state in the multi-pulse write operation in the semiconductor memory device according to the third embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given common reference numerals. When distinguishing between a plurality of components having the same reference numeral, a suffix is added to the common reference numeral for distinction. When no distinction is particularly required for a plurality of components, only the common reference numeral is assigned to the plurality of components, and no suffix is added. Here, the suffix is not limited to subscripts or superscripts, and includes, for example, lowercase alphabets added to the end of the reference numeral, and indexes indicating arrays.

[0008] 1. First Embodiment The semiconductor memory device 1 according to the first embodiment will be described. The semiconductor memory device 1 is a NAND-type flash memory capable of storing data non-volatilely. Note that the semiconductor memory device 1 is not limited to a NAND-type flash memory. The semiconductor memory device 1 may be another non-volatile memory.

[0009] 1.1 Configuration 1.1.1 Overall Configuration of the Semiconductor Memory Device First, referring to FIG. 1, an example of the overall configuration of the semiconductor memory device 1 will be described. FIG. 1 is a block diagram showing the overall configuration of the semiconductor memory device 1. Note that in FIG. 1, a part of the connection of each component is shown by an arrow line, but the connection between components is not limited to this.

[0010] As shown in FIG. 1, the semiconductor memory device 1 is configured to be controllable by an external memory controller 2. For example, the semiconductor memory device 1 transmits and receives signals DQ, timing signals DQS and DQSn to and from the memory controller 2. The signal DQ is, for example, data DAT, an address ADD, or a command CMD. The timing signals DQS and DQSn are timing signals used when inputting and outputting data DAT. The timing signal DQSn is an inverted signal of the timing signal DQS.

[0011] In addition, the semiconductor memory device 1 receives various control signals from the memory controller 2. Then, the semiconductor memory device 1 transmits a ready / busy signal RBn to the memory controller 2. The ready / busy signal RBn is a signal indicating whether the semiconductor memory device 1 is in a state where it cannot receive a command CMD from the memory controller 2 (busy state) or a state where it can (ready state).

[0012] The semiconductor memory device 1 includes an input / output circuit 10, a logic control circuit 11, an address register 12, a command register 13, a sequencer 14, a ready / busy circuit 15, a voltage generation circuit 16, a memory cell array 17, a row decoder 18, a sense amplifier 19, a data register 20, and a column decoder 21.

[0013] The input / output circuit 10 is a circuit that inputs and outputs the signal DQ. The input / output circuit 10 is connected to the memory controller 2. Also, the input / output circuit 10 is connected to the logic control circuit 11, the address register 12, the command register 13, and the data register 20.

[0014] If the input signal DQ is address ADD, the input / output circuit 10 sends address ADD to the address register 12. If the input signal DQ is command CMD, the input / output circuit 10 sends command CMD to the command register 13. If the input signal DQ is data DAT, the input / output circuit 10 receives the input signal DQ based on the timing signals DQS and DQSn. Then, the input / output circuit 10 sends data DAT to the data register 20. The input / output circuit 10 also outputs data DAT, along with the timing signals DQS and DQSn, to the memory controller 2.

[0015] The logic control circuit 11 is a circuit that performs logic control based on control signals. The logic control circuit 11 is connected to the memory controller 2. The logic control circuit 11 is also connected to the input / output circuit 10 and the sequencer 14. The logic control circuit 11 receives multiple control signals from the memory controller 2. Based on the received control signals, the logic control circuit 11 controls the input / output circuit 10 and the sequencer 14.

[0016] The address register 12 is a register that temporarily stores the address ADD. The address register 12 is connected to the input / output circuit 10, the row decoder 18, and the column decoder 21. The address ADD includes the row address RA and the column address CA. The row address RA is the address for selecting wiring (word lines and selection gate lines) arranged in the row direction in the memory cell array 17. The column address CA is the address for selecting wiring (bit lines) arranged in the column direction in the memory cell array 17. For example, the row address RA includes the block address and the page address. The block address is the address that specifies one of the multiple block BLKs included in the memory cell array 17. The page address is the address that specifies one of the multiple word lines connected to the block BLK. The address register 12 transfers the row address RA to the row decoder 18. The address register 12 also transfers the column address CA to the column decoder 21.

[0017] Command register 13 is a register that temporarily stores command CMD. Command register 13 is connected to the input / output circuit 10 and the sequencer 14. Command register 13 transfers command CMD to the sequencer 14.

[0018] The sequencer 14 is a controller that controls the semiconductor memory device 1. The sequencer 14 controls the overall operation of the semiconductor memory device 1. For example, the sequencer 14 controls the ready / busy circuit 15, the voltage generation circuit 16, the row decoder 18, the sense amplifier 19, the data register 20, and the column decoder 21. For example, the sequencer 14 executes write operations, read operations, erase operations, etc., based on the command CMD.

[0019] Furthermore, the sequencer 14 manages the grouping of the write states of the memory cell transistor MC, which will be described later.

[0020] The ready / busy circuit 15 is a circuit that transmits a ready / busy signal RBn to the memory controller 2 based on the control of the sequencer 14.

[0021] The voltage generation circuit 16 generates various voltages used for writing, reading, and erasing operations based on the control of the sequencer 14. The voltage generation circuit 16 supplies the generated voltages to the memory cell array 17, the row decoder 18, and the sense amplifier 19, etc. For example, in a writing operation, the voltage generation circuit generates multiple pulse voltages with different voltages and supplies the generated pulse voltages to the row decoder 18.

[0022] The memory cell array 17 is a collection of multiple memory cell transistors (also simply referred to as "memory cells") arranged in three dimensions. The memory cell array 17 includes multiple blocks BLK. In the example shown in Figure 1, the memory cell array 17 includes four blocks BLK0, BLK1, BLK2, and BLK3. A block BLK is a collection of multiple memory cell transistors from which data is erased collectively, for example. In other words, a block BLK is a data erasure unit. Each block BLK includes multiple string units SU. In the example shown in Figure 1, each block BLK includes four string units SU0 to SU3. Each string unit SU includes multiple NAND strings NS. The number of block BLKs and the number of string units SU within each block BLK are arbitrary. Details of the configuration of the memory cell array 17 will be described later.

[0023] The row decoder 18 is a decoding circuit for row address RA. Based on the decoding result, the row decoder 18 selects one of the block BLKs in the memory cell array 17. The row decoder 18 applies a voltage to the row-direction wiring (word line and selection gate line) of the selected block BLK.

[0024] The sense amplifier 19 is a circuit that performs writing and reading of data DAT. The sense amplifier 19 is connected to the memory cell array 17 and the data register 20. During a read operation, the sense amplifier 19 reads the data DAT from the memory cell array 17 via column-direction wiring (bit lines). During a write operation, the sense amplifier 19 supplies a voltage to the memory cell array 17 based on the written data DAT and the threshold voltage of the memory cell transistors.

[0025] The data register 20 is a register that temporarily stores data DAT. The data register 20 is connected to the sense amplifier 19 and the column decoder 21. The data register 20 includes multiple latch circuits. Each latch circuit temporarily stores write data or read data.

[0026] The column decoder 21 is a circuit that decodes the column address CA. The column decoder 21 receives the column address CA from the address register 12. Based on the decoding result of the column address CA, the column decoder 21 selects a latch circuit in the data register 20.

[0027] 1.1.2 Circuit configuration of memory cell array Next, an example of the circuit configuration of the memory cell array 17 will be described with reference to Figures 2 and 3. Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 17. Figure 3 is a three-dimensional perspective view showing an example of the circuit configuration of the memory cell array 17. Note that the example shown in Figure 2 shows the circuit configuration of one block BLK. The example shown in Figure 3 shows the circuit configuration of string units SU0 and SU1.

[0028] In this embodiment, multiple NAND strings NS within the string unit SU are stacked on top of the substrate. Hereinafter, the plane parallel to the surface of the substrate will be referred to as the XY plane. The directions that intersect each other within the XY plane will be referred to as the X direction and the Y direction. The direction from the substrate toward the memory cell array 17 will be referred to as the Z direction. In the Z direction, the direction from the substrate toward the memory cell array 17 will be defined as the upward direction, and the direction from the memory cell array 17 toward the substrate will be defined as the downward direction.

[0029] As shown in Figure 2, each string unit SU contains multiple NAND strings NS.

[0030] The NAND string NS includes multiple memory cell transistors MC and selection transistors ST1 and ST2. In the example shown in Figure 2, the NAND string NS includes eight memory cell transistors MC0 to MC7. The number of memory cell transistors MC included in the NAND string NS is arbitrary.

[0031] A memory cell transistor (MC) is a memory element that stores data non-volatilely. The MC includes a control gate and a charge storage film. The MC may be of the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or the FG (Floating Gate) type. The MONOS type uses an insulator for the charge storage film. The FG type uses a conductor for the charge storage film. The following description will focus on the case where the memory cell transistor (MC) is of the FG type.

[0032] The selection transistors ST1 and ST2 are switching elements. They are used to select the string unit SU during various operations. The number of selection transistors ST1 and ST2 in the NAND string NS is arbitrary; it is sufficient to have at least one ST1 and one ST2 in the NAND string NS.

[0033] The current paths of the selection transistor ST2, memory cell transistors MC0~MC7, and selection transistor ST1 within the NAND string NS are connected in series. The drain of selection transistor ST1 is connected to the bit line BL. The source of selection transistor ST2 is connected to the source line SL.

[0034] The control gates of memory cell transistors MC0 to MC7 within the same block BLK are connected in common to word lines WL0 to WL7. More specifically, for example, block BLK contains four string units SU0 to SU3, and each string unit SU contains multiple memory cell transistors MC0. The control gates of multiple memory cell transistors MC0 within block BLK are connected in common to a single word line WL0. The same applies to memory cell transistors MC1 to MC7.

[0035] The gates of multiple selection transistors ST1 within a string unit SU are connected in common to a single selection gate line SGD. More specifically, the gates of multiple selection transistors ST1 within a string unit SU0 are connected in common to selection gate line SGD0. The gates of multiple selection transistors ST1 within a string unit SU1 are connected in common to selection gate line SGD1. The gates of multiple selection transistors ST1 within a string unit SU2 are connected in common to selection gate line SGD2. The gates of multiple selection transistors ST1 within a string unit SU3 are connected in common to selection gate line SGD3.

[0036] The gates of multiple selection transistors ST2 within block BLK are connected in common to the selection gate line SGS. Note that, similar to the selection gate line SGD, a different selection gate line SGS may be provided for each string unit SU.

[0037] Word lines WL0 to WL7, selection gate lines SGD0 to SGD3, and selection gate line SGS are connected to the row decoder 18, respectively.

[0038] Each bit line BL is commonly connected to one NAND string NS within each string unit SU of each block BLK. The set of NAND strings NS connected to one bit line BL is also referred to as a layer unit LU. For example, multiple NAND strings NS within a layer unit LU are arranged in the same layer. Multiple NAND strings NS connected to one bit line BL are assigned the same column address CA. Each bit line BL is connected to a sense amplifier 19.

[0039] Source lines SL are shared, for example, between multiple block lines BLK.

[0040] A collection of multiple memory cell transistors MC connected to a common word line WL within a single string unit SU is denoted, for example, as a "cell unit CU". Write and read operations are performed on a cell unit CU basis. A page is a unit of data that is written to (or read out of) a cell unit CU in a batch. For example, if a memory cell transistor MC stores 1 bit of data, the storage capacity of the cell unit CU is 1 page. That is, the cell unit CU stores 1 page of data. A cell unit CU may have a storage capacity of 2 pages or more, based on the number of bits of data stored by the memory cell transistor MC. A memory cell transistor MC may be an SLC (Single Level Cell) that stores 1 bit of data, or an MLC (Multi Level Cell) that stores 2 bits of data. Alternatively, a memory cell transistor MC may be a TLC (Triple Level Cell) that stores 3 bits of data, a QLC (Quad Level Cell) that stores 4 bits of data, or a PLC (Penta Level Cell) that stores 5 bits of data. In this embodiment, the case where the memory cell transistor MC is a TLC will be described below.

[0041] As shown in Figure 3, multiple NAND strings NS in each string unit SU are stacked spaced apart in the Z direction. The memory cell transistors MC0 to MC7, as well as the selection transistors ST1 and ST2 within the NAND strings NS, are arranged on the XY plane. The gates of the multiple memory cell transistors MC stacked spaced apart in the Z direction within each string unit SU are commonly connected to a single word line WL extending in the Z direction. More specifically, for example, within string unit SU0, the gates of the multiple memory cell transistors MC0 stacked spaced apart in the Z direction are commonly connected to the word line WL0. The gates of the memory cell transistors MC1 to MC7 are similarly connected.

[0042] Multiple memory cell transistors MC contained within the cell unit CU are spaced apart in the Z direction. Therefore, during write and read operations, multiple memory cell transistors MC located spaced apart in the Z direction within the string unit SU are selected collectively.

[0043] The drains of multiple selection transistors ST1 within a string unit SU are each connected to different bit lines BL. For example, multiple bit lines BL are stacked spaced apart in the Z direction. The drains of selection transistors ST1 located on the same layer of each string unit SU are connected to a single bit line BL in common. More specifically, for example, the drain of the selection transistor ST1 corresponding to the NAND string NS located on the bottom layer of each string unit SU is connected to bit line BL0. The drain of the selection transistor ST1 corresponding to the NAND string NS located on the m-th layer (where m is an integer greater than or equal to 1) of each string unit SU is connected to bit line BLm.

[0044] 1.1.3 Structure of a memory cell array Next, we will describe an example of the structure of the memory cell array 17.

[0045] 1.1.3.1 Plan Layout First, an example of a planar layout of the memory cell array 17 will be described with reference to Figure 4. Figure 4 is a plan view showing an example of a planar layout of the memory cell array 17. In Figure 4, the plan view of a layer (block BLK) with approximately equal height from the substrate (i.e., position in the Z direction) is shown. The portion shown in Figure 4 corresponds to one layer unit LU in the circuit diagram shown in Figure 2.

[0046] As shown in Figure 4, within the same layer, the memory cell array 17 includes multiple conductive pillars CGP and SGP, multiple memory structures MS, multiple insulators INS, and semiconductor CPS.

[0047] The insulator INS is an insulator that extends in the Y direction. The insulator INS includes, for example, silicon oxide. The example shown in Figure 4 illustrates a case where five insulator INS are arranged apart from each other in the X direction.

[0048] A semiconductor CPS is a semiconductor that extends in the XY plane. A semiconductor CPS includes, for example, polysilicon. The semiconductor CPS has a linear portion located between two adjacent insulators (INS) in the X direction and extending in the Y direction. Furthermore, the semiconductor CPS has two ends that sandwich five insulators (INS) in the Y direction. The two ends of the semiconductor CPS are connected via the linear portion.

[0049] Each of the multiple conductive pillars CGP and SGP extends in the Z direction so as to intersect with the insulator INS and the semiconductor CPS. Each of the multiple conductive pillars CGP and SGP is provided at the boundary between the insulator INS and the semiconductor CPS in the region where two adjacent insulators INS face each other. That is, each of the multiple conductive pillars CGP and SGP has a side facing the semiconductor CPS without intervening with the insulator INS in a plan view from the Z direction, and a side facing the insulator INS without intervening with the semiconductor CPS. The multiple conductive pillars CGP and SGP are aligned in the Y direction at the boundary between the insulator INS and the linear portion of the semiconductor CPS. In the example shown in Figure 4, a case is shown where four conductive pillars CGP are arranged so as to be sandwiched in the Y direction by two conductive pillars SGP. The portion where each of the multiple conductive pillars CGP and SGP faces the semiconductor CPS functions as a transistor.

[0050] The memory structure MS is provided between the semiconductor CPS and the conductive pillar CGP and includes a charge storage film. The memory structure MS is not provided between the insulator INS and the conductive pillar CGP. For example, the memory structure MS has a fan shape in a plan view from the Z direction. The portion where each of the multiple conductive pillar CGPs contacts the semiconductor CPS via the memory structure MS functions as a memory cell transistor MC. The memory structure MS is not provided between the semiconductor CPS and the conductive pillar SGP. Therefore, the portion where each of the multiple conductive pillar SGPs contacts the semiconductor CPS functions as a selection transistor ST1 or ST2, rather than a memory cell transistor MC. The eight sets of conductive pillar CGPs and memory structure MS, along with the four conductive pillar SGPs, provided at the boundary between one linear portion of the semiconductor CPS and the insulator INS provided at one end of the linear portion, and the boundary between the linear portion and the insulator INS provided at the other end of the linear portion, function as one NAND string NS. In Figure 4, the four NAND strings NS, formed by five insulators INS and semiconductor CPS, correspond to string units SU0 to SU3, respectively.

[0051] The linear portion of the semiconductor CPS functions as the channel of the NAND string NS. One end of the semiconductor CPS functions as the bit line BL. The other end of the semiconductor CPS functions as the source line SL.

[0052] 1.1.3.2 Cross-sectional structure of conductive pillar CGP Next, the cross-sectional structure of the conductive pillar CGP will be described with reference to Figures 5 and 6. Figure 5 is a cross-sectional view along line IV-IV in Figure 4, showing an example of the cross-sectional structure of the memory cell array 17 according to the embodiment. Figure 5 mainly shows the cross-sectional structure of one conductive pillar CGP. Figure 6 is a cross-sectional view along line VV in Figure 5, showing an example of the cross-sectional structure of the memory cell transistor MC. More specifically, Figure 6 shows the cross-sectional structure of the conductive pillar CGP in a layer parallel to the XY plane and including the semiconductor layer 122.

[0053] As shown in Figure 5, the memory cell array 17 includes a substrate 120, insulating layers 121 and 123, a semiconductor layer 122, an insulator 137, a conductive pillar CGP, and a memory structure MS. The insulator 137 corresponds to the insulator INS.

[0054] The substrate 120 is, for example, a p-type semiconductor. An insulating layer 121 is provided on the upper surface of the substrate 120. The substrate 120 and the insulating layer 121 may include circuits not shown. The circuits included in the substrate 120 and the insulating layer 121 correspond to, for example, a low decoder 18 or a sense amplifier 19.

[0055] On the upper surface of the insulating layer 121, multiple semiconductor layers 122 and multiple insulating layers 123 are stacked alternately, one layer at a time. In the example shown in Figure 5, six semiconductor layers 122 and six insulating layers 123 are stacked alternately, one layer at a time. In other words, multiple semiconductor layers 122 are provided on the substrate 120, spaced apart in the Z direction. The number of stacked semiconductor layers 122 corresponds, for example, to the number of bit lines BL.

[0056] The semiconductor layer 122 corresponds to the semiconductor CPS and has a portion extending in the Y direction (the linear portion of the semiconductor CPS). The portion of the semiconductor layer 122 extending in the Y direction shown in Figure 5 functions as a channel in the NAND string NS. The insulator layers 121 and 123 include, for example, silicon oxide. The semiconductor layer 122 includes, for example, polysilicon.

[0057] The insulator 137 has a portion that extends in the XY plane within the same layer as the semiconductor layer 122, and this portion corresponds to the insulator INS. The insulator 137 may have columnar portions extending in the Z direction in a plurality of insulators INS that are spaced apart in the Z direction.

[0058] The conductive pillar CGP extends in the Z direction so as to intersect with multiple semiconductor layers 122 and insulating layers 123. The lower end of the conductive pillar CGP reaches the insulating layer 121. The upper end of the conductive pillar CGP aligns, for example, with the upper end of the top insulating layer 123. The conductive pillar CGP functions as a word line WL by being electrically connected to the row decoder 18.

[0059] Within the same layer as the semiconductor layer 122, a portion of the side surface of the conductive pillar CGP is in contact with the insulator 137. The portion of the side surface of the conductive pillar CGP in the same layer as the semiconductor layer 122 that is not in contact with the insulator 137 is in contact with the memory structure MS. The conductive pillar CGP includes a conductive film 130 and an insulating film 131. The memory structure MS includes an insulating film 132, a charge storage film 133, and an insulating film 134.

[0060] The conductive film 130 extends in the Z direction. For example, the upper end of the conductive film 130 aligns with, for example, the upper end of the top insulating layer 123. The lower end of the conductive film 130 is located below the bottom semiconductor layer 122. The conductive film 130 contains, for example, tungsten. The conductive film 130 functions as a wiring (word line WL) connected to the gate of the memory cell transistor MC.

[0061] The insulating film 131 covers the sides and bottom of the conductive film 130. The insulating film 131 includes, for example, silicon oxide. The insulating film 131 may also have a laminated structure containing silicon oxide and aluminum oxide or hafnium silicate.

[0062] The insulating film 132 is provided between the semiconductor layer 122 and the insulating film 131, in the same layer as the semiconductor layer 122. The charge storage film 133 is provided between the semiconductor layer 122 and the insulating film 132, in the same layer as the semiconductor layer 122. The insulating film 134 is provided between the semiconductor layer 122 and the charge storage film 133, in the same layer as the semiconductor layer 122. The side surface of the insulating film 134 is in contact with the semiconductor layer 122. The insulating film 132 includes, for example, hafnium silicate. The insulating film 134 includes, for example, silicon oxide. The charge storage film 133 includes a material having the function of storing charge. Specifically, the charge storage film 133 may include, for example, a conductor such as silicon or a metal. The charge storage film 133 may also include, for example, an insulator such as silicon nitride. If the charge storage film 133 contains a conductor such as silicon or a metal, the memory cell transistor MC functions as an FG-type memory cell transistor MC. If the charge storage film 133 contains an insulator such as silicon nitride, the memory cell transistor MC functions as a MONOS-type memory cell transistor MC.

[0063] A conductive pillar CGP can function as multiple memory cell transistors MC connected to the same word line WL. In other words, a conductive pillar CGP can function as a single cell unit CU. Therefore, the multiple memory cell transistors MC within the cell unit CU are spaced apart in the Z direction.

[0064] Next, with reference to Figure 6, an example of the cross-sectional structure of a memory cell transistor (MC) will be described.

[0065] As shown in Figure 6, in a cross-section including the semiconductor layer 122, the conductive film 130 is provided, for example, in the central part of the conductive pillar CGP. The insulating film 131 surrounds the side surface of the conductive film 130. The insulating film 132 surrounds the portion of the side surface of the insulating film 131 that is not in contact with the insulator INS (insulator 137). The charge storage film 133 surrounds the side surface of the insulating film 132. The insulating film 134 surrounds the side surface of the charge storage film 133. The semiconductor layer 122 surrounds the side surface of the insulating film 134. Thus, the insulating film 132, the charge storage film 133, and the insulating film 134 are provided only between the conductive pillar CGP and the semiconductor layer 122, and not between the conductive pillar CGP and the insulator INS.

[0066] The conductive film 130 is used as wiring (word line WL) connected to the gate of the memory cell transistor MC. The insulating films 131 and 132 are used as block insulating films of the memory cell transistor MC. The insulating film 134 is used as a tunnel insulating film of the memory cell transistor MC.

[0067] 1.1.3.3 Cross-sectional structure of conductive pillar SGP Next, an example of the cross-sectional structure of a conductive pillar SGP will be described with reference to Figures 7 and 8. Figure 7 is a cross-sectional view along the line VI-VI in Figure 4, showing an example of the cross-sectional structure of a memory cell array 17. Figure 7 mainly shows the cross-sectional structure of one conductive pillar SGP in contact with the same insulator INS. Figure 8 is a cross-sectional view along the line VII-VII in Figure 7, showing an example of the cross-sectional structure of a selection transistor ST1. More specifically, Figure 8 shows the cross-sectional structure of a conductive pillar SGP in a layer parallel to the XY plane and containing the semiconductor layer 122.

[0068] As shown in Figure 7, the memory cell array 17 further includes conductive pillar SGPs. The structure other than the conductive pillar SGPs is equivalent to the structure shown in Figure 5, and therefore its explanation is omitted.

[0069] The conductive pillar SGP extends in the Z direction so as to intersect with multiple semiconductor layers 122 and insulating layers 123. The lower end of the conductive pillar SGP reaches the insulating layer 121. The upper end of the conductive pillar SGP aligns, for example, with the upper end of the top insulating layer 123. By being electrically connected to the low decoder 18, it functions as a selected gate line SGD.

[0070] Within the same layer as the semiconductor layer 122, a portion of the side surface of the conductive pillar SGP is in contact with the insulator INS (insulator 137). The portion of the side surface of the conductive pillar SGP in the same layer as the semiconductor layer 122 that is not in contact with the insulator INS is in contact with the semiconductor layer 122. The conductive pillar SGP includes a conductive film 140 and an insulating film 141.

[0071] The conductive film 140 extends in the Z direction. The upper end of the conductive film 140 aligns, for example, with the upper end of the uppermost insulating layer 123. The lower end of the conductive film 140 is located below the lowermost semiconductor layer 122. The conductive film 140 contains, for example, tungsten.

[0072] The insulating film 141 covers the sides and bottom of the conductive film 140. The insulating film 141 includes, for example, silicon oxide. The insulating film 141 may also have a laminated structure containing silicon oxide and aluminum oxide or hafnium silicate.

[0073] Next, an example of the cross-sectional structure of the selection transistor ST1 will be described with reference to Figure 8.

[0074] In a cross-section including the semiconductor layer 122, the conductive film 140 is provided, for example, in the central part of the conductive pillar SGP. The insulating film 141 surrounds the sides of the conductive film 140. The semiconductor layer 122 surrounds a portion of the sides of the insulating film 141. The portion of the sides of the insulating film 141 not surrounded by the semiconductor layer 122 is surrounded by the insulator 137.

[0075] The conductor film 140 is used as a wiring (selection gate line SGD) connected to the gate of the selection transistor ST1. The insulator film 141 is used as a block insulating film of the selection transistor ST1. Thus, the conductive pillar SGP can function as a plurality of selection transistors ST1 connected to the same selection gate line SGD.

[0076] In addition, in FIGS. 7 and 8, the cross-sectional structure of the conductive pillar SGP corresponding to the selection gate line SGD has been described. However, the conductive pillar SGP corresponding to the selection gate line SGS also has the same cross-sectional structure as the conductive pillar SGP corresponding to the selection gate line SGD.

[0077] 1.2 Threshold Voltage Distribution of Memory Cell Next, referring to FIG. 9, an example of the threshold voltage distribution of the memory cell transistor MC will be described. FIG. 9 is a diagram showing the threshold voltage distribution and data assignment when the memory cell transistor MC is a TLC.

[0078] As shown in FIG. 9, when the memory cell transistor MC is a TLC that stores 3-bit data, the distribution of its threshold voltage is divided into eight. These eight threshold voltage distributions (threshold voltage ranges) are denoted as S0 state to S7 state in order from the one with the lowest threshold voltage.

[0079] The voltages V0 to V7 are verification voltages used for each program verification operation in the S0 state to S7 state during the write operation. The voltage VREAD is the voltage applied to the non-selected word line WL during the read operation. When the voltage VREAD is applied to the gate of the memory cell transistor MC, it is turned on regardless of the stored data. The relationship between the voltages V0 to V7 and the voltage VREAD is V0 < V1 < V2 < V3 < V4 < V5 < V6 < V7 < VREAD. Note that the verification voltage V0 may be omitted.

[0080] State S0 corresponds to the erase state of the memory cell transistor MC. States S1 to S7 correspond to the state in which charge has been injected into the charge storage layer of the memory cell transistor MC and data has been written. The threshold voltage of the memory cell transistor MC in state S0 is greater than or equal to voltage V0 and less than voltage V1. The threshold voltages of the memory cell transistor MC in states S1 to S6 are greater than or equal to voltage V1 and less than voltage V2 to greater than or equal to voltage V6 and less than voltage V7, respectively. The threshold voltage of the memory cell transistor MC in state S7 is greater than or equal to voltage V7 and less than voltage VREAD.

[0081] The verification voltage setting and the read voltage setting for each state may be the same or different. For simplicity, the following explanation will focus on the case where the verification voltage and read voltage have the same setting.

[0082] Hereinafter, read operations using voltages V0 to V7 will be referred to as read operations R0 to R7, respectively. Read operation R0 determines whether the threshold voltage of the memory cell transistor MC is less than voltage V0. Read operation R1 determines whether the threshold voltage of the memory cell transistor MC is less than voltage V1. Read operation R2 determines whether the threshold voltage of the memory cell transistor MC is less than voltage V2. Read operation R3 determines whether the threshold voltage of the memory cell transistor MC is less than voltage V3. The same applies to subsequent operations.

[0083] As described above, the threshold voltage of each memory cell transistor (MC) belongs to one of eight threshold voltage distributions. This allows each memory cell transistor (MC) to take on eight different states. By assigning these states to binary data "000" to "111", each memory cell transistor (MC) can store 3 bits of data. Hereafter, the 3 bits of data will be referred to as the "Lower bit," "Middle bit," and "Upper bit," respectively, from the least significant bit. Furthermore, the set of Lower bits stored by memory cell transistors (MC) contained in the same cell unit (CU) will be referred to as "Lower page data," the set of Middle bits as "Middle page data," and the set of Upper bits as "Upper page data."

[0084] In the example shown in Figure 9, the memory cell transistor MC included in each state is assigned data consisting of "Upper bit / Middle bit / Lower bit" as follows.

[0085] S0 State: “111” Data S1 State: “110” Data S2 State: “100” Data S3 State: “000” Data S4 State: “010” Data S5 State: “011” Data S6 State: “001” Data S7 State: “101” Data When reading data assigned in this manner, read operations R0 to R7 are executed. The Lower bit is determined by read operations R1 and R5. The Middle bit is determined by read operations R2, R4, and R6. The Upper bit is determined by read operations R3 and R7. The values ​​of the Lower, Middle, and Upper bits are determined by two, three, and two read operations, respectively. Hereafter, this data assignment will be referred to as the "2-3-2 code". Note that the assignment of data to states S0 to S7 is not limited to the 2-3-2 code.

[0086] 1.3 Writing Operation Next, we will explain the writing operation. The writing operation broadly includes program operation and program verification operation.

[0087] Program operation is the process of increasing the threshold voltage by injecting electrons into the charge storage layer (or maintaining the threshold voltage by hardly injecting any electrons into the charge storage layer). Hereafter, memory cell transistors MC that increase the threshold voltage will also be referred to as "programmable memory cell transistors MC". Conversely, memory cell transistors MC that do not increase the threshold voltage will also be referred to as "program-inhibited memory cell transistors MC".

[0088] The program verification operation is performed after the program operation, by reading the data and determining whether the threshold voltage of the memory cell transistor (MC) has reached the target level. Hereinafter, if the threshold voltage of the memory cell transistor (MC) has reached the target level, it will be referred to as "verification passed," and if it has not reached the target level, it will be referred to as "verification failed." More specifically, for example, in the program verification operation, if the number of fail bits in the read data is greater than or equal to a preset reference value, it is determined that "verification failed." If verification fails, the threshold voltage of the memory cell transistor (MC) is raised to the target level by repeating the combination of program operation and program verification operation (hereinafter referred to as the "program loop"). A memory cell transistor (MC) whose threshold voltage has reached the target level is prohibited from being programmed in the subsequent program loop. In other words, a memory cell transistor (MC) that has completed its program is prohibited from being programmed.

[0089] Hereafter, the memory cell transistor MC targeted for writing will also be referred to as the "selected memory cell transistor MC." Similarly, the word line WL connected to the selected memory cell transistor MC will also be referred to as the "selected word line WL." For example, the program voltage applied to the selected word line WL during program operation is stepped up with each iteration of the program loop. The threshold voltage of the selected memory cell transistor MC increases in proportion to the step-up amount.

[0090] 1.3.1 Multi-pulse writing operation Next, the multi-pulse writing operation will be explained with reference to Figure 10. Figure 10 shows an example of the change in the threshold voltage distribution of a memory cell transistor (MC) due to the multi-pulse writing operation.

[0091] Multi-pulse writing is a writing operation in which, in a single program operation, multiple pulse voltages (program voltages) corresponding to multiple target levels (states) are successively applied to the selected word line WL. In this case, "successive" includes the interval between pulse voltages. The voltage values ​​of the multiple pulse voltages differ depending on the target level (state). The memory cell transistor MC is set to a writeable state for the corresponding pulse voltage and to a program-inhibited state for other pulse voltages by voltage control on the bit line BL. By using pulse voltages corresponding to the target levels, the threshold voltage of the memory cell transistor MC rises to a voltage value corresponding to the target level.

[0092] As shown in the upper part of Figure 10, for example, the threshold voltage distribution of multiple memory cell transistors MC before the start of a write operation is distributed in the S0 state.

[0093] As shown in the middle section of Figure 10, during a single program operation, a different pulse voltage is applied to the selected word line WL for each target level. In the example shown in Figure 10, eight pulse voltages are applied, each corresponding to states S0 through S7. As a result, the threshold voltage of the memory cell transistor MC is divided into eight distributions, each corresponding to states S0 through S7. For example, after the first program operation, the threshold voltage distribution of each state has a relatively wide tail and overlaps with the tails of the threshold voltage distributions of adjacent states. For example, the threshold voltage distribution of state S1 overlaps with the threshold voltage distributions of states S0 and S2, and a portion of them.

[0094] After the program execution, the program verification operation is performed. In multi-pulse writing operations, program verification operations corresponding to each target level are performed sequentially. In the example shown in Figure 10, read operations R0 to R7 are performed sequentially using voltages V0 to V7 corresponding to states S0 to S7, respectively. In multi-pulse programming, where programming is performed in parallel for all states, the program verification operation is also performed sequentially for all states.

[0095] If verification fails, the program loop then repeats.

[0096] As shown in the lower part of Figure 10, for example, the second program operation is executed in the same way as the first program operation. That is, multiple pulse voltages (program voltages) corresponding to multiple target levels (states) are applied to the selected word line WL. Note that in the second program operation, the pulse voltages are step-up.

[0097] After the program execution, a program verification operation is performed. If the verification passes, the multi-pulse write operation is terminated.

[0098] 1.3.2 Grouping of States Next, an example of state grouping in multi-pulse writing operation will be described with reference to Figure 11. Figure 11 shows an example of state grouping when the memory cell transistor MC is TLC. Note that although the example shown in Figure 11 shows the case where the memory cell transistor MC is TLC, it is not limited to this. For example, the memory cell transistor MC may be QLC or PLC.

[0099] As shown in Figure 11, when the memory cell transistor MC is TLC, its threshold voltage distribution is divided into states S0 to S7. In this embodiment, when performing a write operation, one or more adjacent states with corresponding threshold voltage distributions are grouped together. In the example shown in Figure 11, states S0 and S1 are classified into group A, states S2 and S3 into group B, states S4 and S5 into group C, and states S6 and S7 into group D. The number of groups is arbitrary; the number of groups must be less than the number of states. Furthermore, the grouping combinations are not limited to the example shown in Figure 11.

[0100] 1.3.3 Voltage of Each Wiring in Multi-Pulse Writing Operation Next, referring to FIG. 12, an example of the voltage of each wiring in the multi-pulse writing operation will be described. FIG. 12 is a timing chart showing an example of the voltage of each wiring in the multi-pulse writing operation. FIG. 12 shows the voltages of the selected word line and the bit line BL. In the example shown in FIG. 12, for the sake of simplifying the explanation, the voltage of the bit line BL in the program verification operation is omitted.

[0101] As shown in FIG. 12, in the period from time t0 to t1, the first program operation PG1 is executed. The row decoder 18 continuously applies the pulse voltage Vp_A corresponding to group A, the pulse voltage Vp_B corresponding to group B, the pulse voltage Vp_C corresponding to group C, and the pulse voltage Vp_D corresponding to group D to the selected word line WL. For example, during the period when the pulse voltage Vp_A is applied, group A is the selected group, during the period when the pulse voltage Vp_B is applied, group B is the selected group, during the period when the pulse voltage Vp_C is applied, group C is the selected group, and during the period when the pulse voltage Vp_D is applied, group D is the selected group. For example, the pulse voltages Vp_A, Vp_B, Vp_C, and Vp_D are in the relationship of Vp_A < Vp_B < Vp_C < Vp_D. Note that the order of applying the pulse voltages is arbitrary. For example, the row decoder 18 may apply the pulse voltages Vp_D, Vp_C, Vp_B, and Vp_A to the selected word line WL in this order.

[0102] The sense amplifier 19 applies voltage VSS to bit line BL_A corresponding to group A while pulse voltage Vp_A is applied to the selection word line WL. In the NAND string NS corresponding to group A, the selection transistor ST1 is turned ON. As a result, the threshold voltage of the selection memory cell transistor MC for group A rises in proportion to the voltage difference between voltage Vp_A and voltage VSS. The sense amplifier 19 also applies voltage VBL to bit line BL_B corresponding to group B, bit line BL_C corresponding to group C, and bit line BL_D corresponding to group D. Voltage VBL is a positive voltage that cuts off the selection transistor ST1. In the NAND strings NS corresponding to groups B, C, and D, the selection transistor ST1 is cut off. As a result, the NAND strings NS corresponding to groups B, C, and D are placed in a floating state. The selection memory cell transistor MC corresponding to groups B, C, and D is inhibited from programming by channel boosting.

[0103] The sense amplifier 19 applies voltage VSS to bit line BL_B while pulse voltage Vp_B is applied to the selection word line WL. The sense amplifier 19 also applies voltage VBL to bit lines BL_A, BL_C, and BL_D. As a result, the threshold voltage of the group B selection memory cell transistor MC increases in proportion to the voltage difference between voltage Vp_B and voltage VSS. The increase in the threshold voltage of the group B selection memory cell transistor MC is greater than the increase in the threshold voltage of the group A selection memory cell transistor MC. Furthermore, the selection memory cell transistors MC corresponding to groups A, C, and D are disabled from programming.

[0104] The sense amplifier 19 applies voltage VSS to bit line BL_C while a pulse voltage Vp_C is applied to the selection word line WL. The sense amplifier 19 also applies voltage VBL to bit lines BL_A, BL_B, and BL_D. As a result, the threshold voltage of the selection memory cell transistor MC in group C increases in proportion to the voltage difference between voltage Vp_C and voltage VSS. The increase in the threshold voltage of the selection memory cell transistor MC in group C is greater than the increase in the threshold voltage of the selection memory cell transistor MC in group B. Furthermore, the selection memory cell transistors MC corresponding to groups A, B, and D are disabled from programming.

[0105] The sense amplifier 19 applies voltage VSS to bit line BL_D while pulse voltage Vp_D is applied to the selection word line WL. The sense amplifier 19 also applies voltage VBL to bit lines BL_A, BL_B, and BL_C. As a result, the threshold voltage of the selection memory cell transistor MC in group D increases in proportion to the voltage difference between voltage Vp_D and voltage VSS. The increase in the threshold voltage of the selection memory cell transistor MC in group D is greater than the increase in the threshold voltage of the selection memory cell transistor MC in group C. Furthermore, the selection memory cell transistors MC corresponding to groups A, B, and C are disabled from programming.

[0106] During the period from time t1 to t2, the program verification operation PV is performed. The row decoder 18 sequentially applies voltages V0 to V7 to the selected word line WL. That is, read operations R0 to R7 are performed sequentially. The order in which voltages V0 to V7 are applied is arbitrary. When the threshold voltage reaches the target level (the program is complete), the selected memory cell transistor MC is inhibited from being programmed in the subsequent program loop.

[0107] During the period from time t2 to t3, the second program operation PG2 is executed. The row decoder 18 continuously applies step-up voltages of pulse voltages Vp_A, Vp_B, Vp_C, and Vp_D to the selected word line WL. The step-up voltage ΔVp added to each pulse voltage is the same. That is, the step-up width of each pulse voltage is the same. The step-up voltage ΔVp is a positive voltage. More specifically, the row decoder 18 continuously applies the step-up pulse voltages Vp_A+ΔVp, Vp_B+ΔVp, Vp_C+ΔVp, and Vp_D+ΔVp to the selected word line WL. In the example shown in Figure 12, the same step-up voltage ΔVp is added to pulse voltages Vp_A, Vp_B, Vp_C, and Vp_D, but the step-up voltage may be different for each pulse voltage.

[0108] During the period when a pulse voltage Vp_A + ΔVp is applied to the selected word line WL, the sense amplifier 19 applies voltage VSS to the bit line BL_A corresponding to the selected memory cell transistor MC to be programmed, and voltage VBL to the bit line BL_A corresponding to the selected memory cell transistor MC that is inhibited from being programmed. The sense amplifier 19 also applies voltage VBL to bit lines BL_B, BL_C, and BL_D.

[0109] During the period when a pulse voltage Vp_B + ΔVp is applied to the selected word line WL, the sense amplifier 19 applies voltage VSS to the bit line BL_B corresponding to the selected memory cell transistor MC to be programmed, and voltage VBL to the bit line BL_B corresponding to the selected memory cell transistor MC that is inhibited from being programmed. The sense amplifier 19 also applies voltage VBL to bit lines BL_A, BL_C, and BL_D.

[0110] During the period when a pulse voltage Vp_C + ΔVp is applied to the selected word line WL, the sense amplifier 19 applies voltage VSS to the bit line BL_C corresponding to the selected memory cell transistor MC to be programmed, and voltage VBL to the bit line BL_C corresponding to the selected memory cell transistor MC that is inhibited from being programmed. The sense amplifier 19 also applies voltage VBL to bit lines BL_A, BL_B, and BL_D.

[0111] During the period when a pulse voltage Vp_D + ΔVp is applied to the selected word line WL, the sense amplifier 19 applies voltage VSS to the bit line BL_D corresponding to the selected memory cell transistor MC to be programmed, and voltage VBL to the bit line BL_D corresponding to the selected memory cell transistor MC that is inhibited from being programmed. The sense amplifier 19 also applies voltage VBL to bit lines BL_A, BL_B, and BL_C.

[0112] During the period from time t3 to t4, the program verification operation PV is performed in the same manner as during the period from time t1 to t2.

[0113] During the period from time t4 to t5, the third program operation PG3 is executed. The row decoder 18 continuously applies step-up voltages of pulse voltages Vp_A+ΔVp, Vp_B+ΔVp, Vp_C+ΔVp, and Vp_D+ΔVp to the selected word line WL. More specifically, the row decoder 18 continuously applies pulse voltages Vp_A+2ΔVp, Vp_B+2ΔVp, Vp_C+2ΔVp, and Vp_D+2ΔVp to the selected word line WL. Note that the step-up voltage in the third program operation PG3 may be a voltage smaller than the voltage ΔVp.

[0114] The sense amplifier 19 applies voltage to each bit line BL, similar to the second programmed operation of PG2.

[0115] During the period from time t5 to t6, the program verification operation PV is performed, similar to the period from time t1 to t2. If the verification passes, the multi-pulse write operation is terminated.

[0116] 1.3.4 Flow of Multi-Pulse Writing Operation Next, we will explain an example of the flow of a multi-pulse write operation with reference to Figure 13. Figure 13 is a flowchart showing an example of the flow of a multi-pulse write operation.

[0117] As shown in Figure 13, when the sequencer 14 receives a write command for multi-pulse writing from the memory controller 2, it starts program operation (STP1).

[0118] During program operation, the row decoder 18 applies multiple pulse voltages corresponding to each group to the selection word line WL (STP2). More specifically, for example, if multiple states are grouped into groups A to D, the row decoder 18 first applies a pulse voltage for group A to the selection word line WL. At this time, the threshold voltage of the selected memory cell transistor MC for group A that is programmed is increased. Next, the row decoder 18 applies a pulse voltage for group B to the selection word line WL. At this time, the threshold voltage of the selected memory cell transistor MC for group B that is programmed is increased. Next, the row decoder 18 applies a pulse voltage for group C to the selection word line WL. At this time, the threshold voltage of the selected memory cell transistor MC for group C that is programmed is increased. Next, the row decoder 18 applies a pulse voltage for group D to the selection word line WL. At this time, the threshold voltage of the selected memory cell transistor MC for group D that is programmed is increased.

[0119] Sequencer 14 terminates program execution (STP3).

[0120] Next, the sequencer 14 performs a program verification operation for all states (STP4). For example, if the memory cell transistor MC is TLC, the sequencer 14 sequentially performs read operations R0 to R7 corresponding to the verify voltages V0 to V7.

[0121] If verification passes (STP5_Yes), the sequencer 14 terminates the multi-pulse write operation.

[0122] If verification fails (STP5_No), the sequencer 14 checks whether the number of program loop iterations has reached a preset number.

[0123] If the number of program loop iterations reaches the set number (STP6_Yes), the sequencer 14 terminates the multi-pulse write operation. For example, the sequencer 14 notifies the memory controller 2 that the write operation failed.

[0124] If the number of program loop iterations has not reached the set number (STP6_No), the PLC 14 steps up each pulse voltage (STP7). The PLC 14 then proceeds to step STP1 and executes the next program loop.

[0125] 1.4 Variations of State Grouping Next, with reference to Figure 14, a modified example of state grouping in a write operation is shown. Figure 14 shows a modified example of state grouping when the memory cell transistor MC is TLC.

[0126] When the memory cell transistor MC is TLC, its threshold voltage distribution can be divided into S0 to S7 states. For example, the S0 state is more susceptible to read disturbance than the other states. That is, the threshold voltage of the memory cell transistor MC in the S0 state is more likely to rise due to read disturbance than that of the memory cell transistor MC in the other states. For this reason, a margin for the rise in threshold voltage may be provided between the S0 state and the S1 state. In such a case, as shown in Figure 14, the S0 state may be designated as Group A, the S1, S2, and S3 states as Group B, the S4 and S5 states as Group C, and the S6 and S7 states as Group D.

[0127] 1.5 Effects of this embodiment The semiconductor memory device 1 according to this embodiment can improve processing capabilities. This effect will be described in detail below. For example, if multiple memory cell transistors MC within a cell unit CU are stacked spaced apart in the Z direction, the effects of interference between adjacent cells in the upper and lower layers are significant during writing operations. For instance, multi-pulse writing operations, which apply multiple pulse voltages corresponding to each state to the selected word line WL during program operation, are effective in reducing inter-cell interference effects because writing to all states is performed in parallel. However, the processing time for the writing operation increases with the number of pulses. In contrast, with the configuration according to this embodiment, the semiconductor memory device 1 can form the channels (semiconductor CPS) of the NAND string NS on an XY plane parallel to the substrate. Furthermore, the semiconductor memory device 1 can form a cell unit CU including a plurality of memory cell transistors MC, which are stacked spaced apart in the Z direction and whose gates are commonly connected to the word line WL. The semiconductor memory device 1 can also perform a multi-pulse write operation in which a plurality of adjacent states are grouped together and a plurality of pulse voltages corresponding to each group are continuously applied to the selected word line WL. As a result, the semiconductor memory device 1 can reduce the number of pulses in a single program operation. The semiconductor memory device 1 can suppress the increase in processing time for the write operation. Therefore, the semiconductor memory device 1 can improve its processing capability. 2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, a multi-pulse writing operation different from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0128] 2.1 Multi-pulse writing operation An example of multi-pulse writing operation will be described with reference to Figures 15 to 17. Figure 15 is a timing chart showing an example of the voltage of the selected word line WL in multi-pulse writing operation. Figure 16 is a diagram showing an example of the pulse voltage application conditions in multi-pulse writing operation. Figure 16 shows the threshold voltage distribution for each group after the first program operation PG1. Figure 17 is a diagram showing the transition of the threshold voltage distribution for each group in multi-pulse writing operation. In the example shown in Figures 15 to 17, three groups (group A, group B, and group C) are shown. Each group contains one or more adjacent states.

[0129] In the multi-pulse writing operation of this embodiment, the difference in threshold voltages between groups is set to be the same as the potential difference of the step-up voltage ΔVp. The pulse voltage is stepped up by voltage ΔVp. The sequencer 14 predicts the pulse voltage required for the next program operation based on the result of the program verification operation PV. Then, the sequencer reconfigures the groups (changes the configuration). More specifically, the sequencer 14 divides the threshold voltage distribution of each group into multiple sections according to the conditions of the next required pulse voltage. In the next (second) program operation PG, sections where the same pulse voltage conditions are used for multiple groups are written together. That is, in the second and subsequent program operations, the groups are grouped according to the sections with the same pulse voltage conditions.

[0130] As shown in Figure 15, the first program operation PG1 is executed during the period t0 to t1. The pulse voltage corresponding to each group is stepped up by a voltage ΔVp. For example, if the initial value of the pulse voltage is voltage Vp0, the pulse voltage of each group can be expressed as voltage Vp0 + nΔVp (where n is a non-negative integer). Here, for group A, n=0. For group B, n=1. For group C, n=2. More specifically, the row decoder 18 continuously applies the pulse voltage Vp0 corresponding to group A, the pulse voltage Vp0 + ΔVp corresponding to group B, and the pulse voltage Vp0 + 2ΔVp corresponding to group C to the selected word line WL.

[0131] During the period from time t1 to t2, the program verification operation PV is performed.

[0132] As shown in Figures 16 and 17, after the first program operation PG1, the threshold voltage distributions of the multiple memory cell transistors MC are divided into groups A, B, and C. For example, the threshold voltage distributions increase in the order of group A, group B, and group C. Note that the threshold voltage distributions of adjacent groups may partially overlap.

[0133] Voltages VV1 to VV5 are verification voltages. The relationship of voltages VV1 to VV5 is VV1 < VV2 < VV3 < VV4 < VV5. Also, for example, the voltage difference between voltage VV2 and voltage VV1, the voltage difference between voltage VV3 and voltage VV2, the voltage difference between voltage VV4 and voltage VV3, and the potential difference between voltage VV5 and voltage VV4 are voltage ΔVp. That is, the relationship of voltages VV1 to VV5 and voltage ΔVp is VV2 - VV1 = VV3 - VV2 = VV4 - VV3 = VV5 - VV4 = ΔVp. For example, the verification voltages VV1 to VV5 are in a relationship where the difference ΔVp between the pulse voltage Vp0 used in the program operation of the first program loop and the pulse voltage Vp0 + ΔVp used in the program operation of the second program loop is varied by a multiple. For example, voltage VV3 is the verification voltage VA of the threshold voltage distribution of group A. Voltage VV4 is the verification voltage VB of the threshold voltage distribution of group B. Voltage VV5 is the verification voltage VC of the threshold voltage distribution of group C.

[0134] Based on the result of the program verification operation PV, the sequencer 14 divides the threshold voltage distribution of each group into a plurality of sections corresponding to the verification voltages. And for each section, the condition CD of the pulse voltage in the next program operation is set.

[0135] For example, in group A, since the memory cell transistors MC in the section higher than voltage VV3 (voltage VA) have reached the target level, they are prohibited from programming in the second program operation PG2. For the memory cell transistors MC in the section higher than voltage VV2 and lower than or equal to voltage VV3, the condition CD1 of the pulse voltage is set. For the memory cell transistors MC in the section higher than voltage VV1 and lower than or equal to voltage VV2, the condition CD2 of the pulse voltage is set. For the memory cell transistors MC in the section lower than or equal to voltage VV1, the condition CD3 of the pulse voltage is set.

[0136] For example, in group B, memory cell transistors MC in the voltage range higher than VV4 (voltage VB) have reached the target level and are therefore disabled during the second program operation PG2. For memory cell transistors MC in the voltage range higher than VV3 and lower than or equal to VV4, pulse voltage condition CD2 is set. For memory cell transistors MC in the voltage range higher than VV2 and lower than or equal to VV3, pulse voltage condition CD3 is set. For memory cell transistors MC in the voltage range lower than or equal to VV2, pulse voltage condition CD4 is set.

[0137] For example, in group C, memory cell transistors MC in the category with a voltage higher than VV5 (voltage VC) have reached the target level and are therefore disabled during the second program operation PG2. For memory cell transistors MC in the category with a voltage higher than VV4 and less than or equal to VV5, pulse voltage condition CD3 is set. For memory cell transistors MC in the category with a voltage higher than VV3 and less than or equal to VV4, pulse voltage condition CD4 is set. For memory cell transistors MC in the category with a voltage of VV3 or less, pulse voltage condition CD5 is set.

[0138] As shown in Figure 15, n=1 is set as condition CD1. The pulse voltage for condition CD1 is voltage Vp0 + ΔVp. The pulse voltage Vp0 + ΔVp for condition CD1 is the voltage obtained by stepping up the voltage Vp0 corresponding to group A in the first program operation PG1 by voltage ΔVp. In the second program operation PG2, the threshold voltage of the memory cell transistor MC classified under condition CD1 of group A is increased based on the pulse voltage Vp0 + ΔVp.

[0139] Condition CD2 is set to n=2. The pulse voltage for condition CD2 is voltage Vp0+2ΔVp. The pulse voltage Vp0+2ΔVp for condition CD2 is the same as the voltage obtained by stepping up the voltage Vp0 corresponding to group A in the first program operation PG1 by 2ΔVp, and also the same as the voltage obtained by stepping up the pulse voltage Vp0+ΔVp corresponding to group B in the first program operation PG1 by ΔVp. In the second program operation PG2, the threshold voltages of the memory cell transistors MC, which are divided into groups A and B according to condition CD2, are increased based on the pulse voltage Vp0+2ΔVp.

[0140] Condition CD3 is set to n=3. The pulse voltage for condition CD3 is Vp0+3ΔVp. The pulse voltage Vp0+3ΔVp for condition CD3 is the same as the voltage Vp0 corresponding to group A in the first program operation PG1, which is stepped up by 3ΔVp, and the same as the pulse voltage Vp0+ΔVp corresponding to group B in the first program operation PG1, which is stepped up by 2ΔVp. Also, the pulse voltage Vp0+3ΔVp for condition CD3 is the same as the voltage Vp0+2ΔVp corresponding to group C in the first program operation PG1, which is stepped up by ΔVp. In the second program operation PG2, the threshold voltages of the memory cell transistors MC, which are divided into groups A, B, and C according to condition CD3, are increased based on the pulse voltage Vp0+3ΔVp.

[0141] Condition CD4 is set to n=4. The pulse voltage for condition CD4 is Vp0+4ΔVp. The pulse voltage Vp0+4ΔVp for condition CD4 is the same as the voltage obtained by stepping up the voltage Vp0+ΔVp corresponding to group B in the first program operation PG1 by 3ΔVp, and also the same as the voltage obtained by stepping up the pulse voltage Vp0+2ΔVp corresponding to group C in the first program operation PG1 by 2ΔVp. In the second program operation PG2, the threshold voltages of the memory cell transistors MC classified under condition CD4 for groups B and C are increased based on the pulse voltage Vp0+4ΔVp.

[0142] Condition CD5 is set to n=5. The pulse voltage for condition CD5 is Vp0+5ΔVp. The pulse voltage Vp0+5ΔVp for condition CD5 is obtained by stepping up the voltage Vp0+2ΔVp corresponding to group C in the first program operation PG1 by 3ΔVp. In the second program operation PG2, the threshold voltage of the memory cell transistor MC, which is classified as condition CD5 in group C, is increased based on the pulse voltage Vp0+5ΔVp.

[0143] As shown in Figure 15, the second program operation PG2 is executed during the period t2 to t3. Based on the results of the program verification operation PV, the sequencer 14 regroups the pulse voltages applied in the second program operation PG2 according to conditions CD1 to CD5 (this can also be described as reassigning or changing the group configuration). More specifically, the sequencer 14 groups multiple memory cell transistors MC to which condition CD1 of group A is applied into one group, multiple memory cell transistors MC to which conditions CD2 of groups A and B are applied into one group, multiple memory cell transistors MC to which condition CD3 of groups A, B, and C are applied into one group, multiple memory cell transistors MC to which condition CD4 of groups B and C is applied into one group, and multiple memory cell transistors MC to which condition CD5 of group C is applied into one group. The row decoder 18 applies multiple pulse voltages corresponding to conditions CD1 to CD5 to the selected word line WL.

[0144] As shown in Figure 17, the second program operation PG2 narrows the width of the threshold voltage distribution for each group. For example, the threshold voltage of most memory cell transistors MC is considered to have reached the target level.

[0145] As shown in Figure 15, the program verification operation PV is performed during the period from time t3 to t4. The memory cell transistor MC to be programmed, whose threshold voltage has reached the target level, is disabled from programming in the third program operation PG3.

[0146] During the period from time t4 to t5, the third program operation PG3 is executed. The row decoder 18 applies multiple pulse voltages corresponding to conditions CD1 to CD5 to the selected word line WL. For example, in the third program operation PG3, the step-up voltage is reduced because the lower end of the threshold voltage distribution for each group has risen to near the target level. For example, the step-up voltage is set to voltage ΔVp'. Voltage ΔVp' is a positive voltage smaller than voltage ΔVp. More specifically, the pulse voltage for condition CD1 is set to voltage Vp0 + ΔVp + ΔVp'. The pulse voltage for condition CD2 is set to voltage Vp0 + 2ΔVp + ΔVp'. The pulse voltage for condition CD3 is set to voltage Vp0 + 3ΔVp + ΔVp'. The pulse voltage for condition CD4 is set to voltage Vp0 + 4ΔVp + ΔVp'. The pulse voltage for condition CD5 is set to voltage Vp0 + 5ΔVp + ΔVp'. Furthermore, the sequencer 14 may perform grouping again based on the results of the program verification operation PV.

[0147] During the period from time t5 to t6, the program verification operation PV is performed. If the verification passes, the multi-pulse write operation is terminated.

[0148] 2.2 Effects according to this embodiment With the configuration according to this embodiment, the semiconductor memory device 1 can obtain the same effects as in the first embodiment. Furthermore, with the configuration according to this embodiment, the semiconductor memory device 1 can be set so that the difference in threshold voltages between groups and the potential difference of the step-up voltage ΔVp are the same. Based on the results of the program verification operation PV, the semiconductor memory device 1 can predict the pulse voltage required for the next program operation. In the next program operation, the semiconductor memory device 1 can change the group configuration for each section in which the same pulse voltage condition is used. This suppresses the application of pulse voltages with the same voltage value and reduces the number of pulses in the multi-pulse write operation. Therefore, the semiconductor memory device 1 can improve its processing capacity. 3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, a multi-pulse writing operation different from that of the first and second embodiments will be described. The following description will focus on the differences from the first and second embodiments.

[0149] 3.1 Grouping of States First, an example of state grouping in a write operation will be explained with reference to Figure 18. Figure 18 shows an example of state grouping when the memory cell transistor MC is TLC. Note that although the example shown in Figure 18 shows the case where the memory cell transistor MC is TLC, the memory cell transistor MC may also be QLC or PLC.

[0150] As shown in Figure 18, for example, Group A includes the S0 state and the S1 state. The potential difference between the threshold voltage distribution of the S0 state and the threshold voltage distribution of the S1 state is, for example, ΔVt. That is, voltages V0, V1, and ΔVt are related by V1-V0=ΔVt. Group B includes the S2 state and the S3 state. Similar to Group A, the potential difference between the threshold voltage distribution of the S2 state and the threshold voltage distribution of the S3 state is ΔVt. That is, voltages V2, V3, and ΔVt are related by V3-V2=ΔVt. Group C includes the S4 state and the S5 state. Similar to Group A, the potential difference between the threshold voltage distribution of the S4 state and the threshold voltage distribution of the S5 state is ΔVt. That is, voltages V4, V5, and ΔVt are related by V5-V4=ΔVt. Group D includes the S6 state and the S7 state. Similar to group A, the potential difference between the threshold voltage distribution of state S6 and the threshold voltage distribution of state S7 is ΔVt. That is, voltages V6, V7, and ΔVt are related by the relationship V7-V6=ΔVt.

[0151] 3.2 Multi-pulse writing operation An example of multi-pulse writing operation will be described with reference to Figures 19 and 20. Figure 19 is a timing chart showing an example of the voltage of each wire during writing operation. Figure 19 shows the voltage of the selected word line and bit line BL. Note that in the example shown in Figure 19, the voltage of bit line BL during program verification operation is omitted for simplicity of explanation. Figure 20 is a diagram showing the transition of the threshold voltage distribution for each state during multi-pulse writing operation.

[0152] As shown in Figure 19, the voltage applied to the selection word line WL during the period t0 to t6 is the same as in the description using Figure 12 of the first embodiment. In this embodiment, different voltages are applied to the bit lines BL corresponding to different states included in the same group during program operation.

[0153] During the period from time t0 to t1, the sense amplifier 19 applies a voltage ΔVt to the bit line BL_A corresponding to the S0 state of group A while a pulse voltage Vp_A is applied to the selection word line WL. The voltage ΔVt is higher than the voltage VSS and lower than the voltage VBL. The sense amplifier 19 also applies a voltage VSS to the bit line BL_A corresponding to the S1 state of group A. In the NAND string NS corresponding to group A, the selection transistor ST1 is turned ON. As a result, the threshold voltage of the selection memory cell transistor MC corresponding to the S0 state of group A rises in proportion to the voltage difference between the voltage Vp_A and the voltage ΔVt. The threshold voltage of the selection memory cell transistor MC corresponding to the S1 state of group A rises in proportion to the voltage difference between the voltage Vp_A and the voltage VSS. As shown in Figure 20, the amount of increase in the threshold voltage of the selection memory cell transistor MC corresponding to the S1 state is greater by a voltage ΔVt than the amount of increase in the threshold voltage of the selection memory cell transistor MC corresponding to the S0 state. As shown in Figure 19, the sense amplifier 19 applies voltage VBL to the bit lines BL_B, BL_C, and BL_D. The select memory cell transistors MC corresponding to groups B, C, and D are disabled from programming.

[0154] The sense amplifier 19 applies voltage ΔVt to the bit line BL_B corresponding to the S2 state of group B while the pulse voltage Vp_B is applied to the selection word line WL. The sense amplifier 19 also applies voltage VSS to the bit line BL_B corresponding to the S3 state of group B. In the NAND string NS corresponding to group B, the selection transistor ST1 is turned ON. As a result, the threshold voltage of the selection memory cell transistor MC corresponding to the S2 state of group B rises in proportion to the voltage difference between voltage Vp_B and voltage ΔVt. The threshold voltage of the selection memory cell transistor MC corresponding to the S3 state of group B rises in proportion to the voltage difference between voltage Vp_B and voltage VSS. As shown in Figure 20, the amount of increase in the threshold voltage of the selection memory cell transistor MC corresponding to the S3 state is greater by voltage ΔVt than the amount of increase in the threshold voltage of the selection memory cell transistor MC corresponding to the S2 state. As shown in Figure 19, the sense amplifier 19 applies voltage VBL to the bit lines BL_A, BL_C, and BL_D. The select memory cell transistors MC corresponding to groups A, C, and D are disabled from programming.

[0155] The sense amplifier 19 applies a voltage ΔVt to the bit line BL_C corresponding to the S4 state of group C while a pulse voltage Vp_C is applied to the selection word line WL. The sense amplifier 19 also applies a voltage VSS to the bit line BL_C corresponding to the S5 state of group C. In the NAND string NS corresponding to group C, the selection transistor ST1 is turned ON. As a result, the threshold voltage of the selection memory cell transistor MC corresponding to the S4 state of group C rises in proportion to the voltage difference between voltage Vp_C and voltage ΔVt. The threshold voltage of the selection memory cell transistor MC corresponding to the S5 state of group C rises in proportion to the voltage difference between voltage Vp_C and voltage VSS. As shown in Figure 20, the amount of increase in the threshold voltage of the selection memory cell transistor MC corresponding to the S5 state is greater by voltage ΔVt than the amount of increase in the threshold voltage of the selection memory cell transistor MC corresponding to the S4 state. As shown in Figure 19, the sense amplifier 19 applies a voltage VBL to the bit lines BL_A, BL_B, and BL_D. The select memory cell transistors MC corresponding to groups A, B, and D are disabled from programming.

[0156] The sense amplifier 19 applies a voltage ΔVt to the bit line BL_D corresponding to the S6 state of group D while the pulse voltage Vp_D is applied to the selection word line WL. The sense amplifier 19 also applies a voltage VSS to the bit line BL_D corresponding to the S7 state of group D. In the NAND string NS corresponding to group D, the selection transistor ST1 is turned ON. As a result, the threshold voltage of the selection memory cell transistor MC corresponding to the S6 state of group D rises in proportion to the voltage difference between voltage Vp_D and voltage ΔVt. The threshold voltage of the selection memory cell transistor MC corresponding to the S7 state of group D rises in proportion to the voltage difference between voltage Vp_D and voltage VSS. As shown in Figure 20, the amount of increase in the threshold voltage of the selection memory cell transistor MC corresponding to the S7 state is greater by voltage ΔVt than the amount of increase in the threshold voltage of the selection memory cell transistor MC corresponding to the S6 state. As shown in Figure 19, the sense amplifier 19 applies a voltage VBL to the bit lines BL_A, BL_B, and BL_C. The select memory cell transistors (MC) corresponding to groups A, B, and C are disabled from programming.

[0157] During the period from time t1 to t2, the program verification operation PV is executed, similar to the explanation using Figure 12.

[0158] During the period from time t2 to t3, the second program operation PG2 is executed. While the pulse voltage Vp_A + ΔVp is applied to the selected word line WL, the sense amplifier 19 applies voltage ΔVt to the bit line BL_A corresponding to the selected memory cell transistor MC of the S0 state, voltage VSS to the bit line BL_A corresponding to the selected memory cell transistor MC of the S1 state, and voltage VBL to the bit line BL_A corresponding to the selected memory cell transistor MC of the Inhibit state. As shown in Figure 20, the width of the threshold voltage distribution for the S0 and S1 states becomes smaller than after the first program operation PG1. Also, as shown in Figure 19, the sense amplifier 19 applies voltage VBL to the bit lines BL_B, BL_C, and BL_D.

[0159] During the period when the pulse voltage Vp_B + ΔVp is applied to the selected word line WL, the sense amplifier 19 applies voltage ΔVt to the bit line BL_B corresponding to the selected memory cell transistor MC that is the target of programming in state S2, voltage VSS to the bit line BL_B corresponding to the selected memory cell transistor MC that is the target of programming in state S3, and voltage VBL to the bit line BL_B corresponding to the selected memory cell transistor MC that is inhibited. As shown in Figure 20, the width of the threshold voltage distribution in states S2 and S3 becomes smaller than after the first program operation PG1. Also, as shown in Figure 19, the sense amplifier 19 applies voltage VBL to bit lines BL_A, BL_C, and BL_D.

[0160] During the period when the pulse voltage Vp_C + ΔVp is applied to the selected word line WL, the sense amplifier 19 applies voltage ΔVt to the bit line BL_C corresponding to the selected memory cell transistor MC that is the target of programming in state S4, voltage VSS to the bit line BL_C corresponding to the selected memory cell transistor MC that is the target of programming in state S5, and voltage VBL to the bit line BL_C corresponding to the selected memory cell transistor MC that is inhibited. As shown in Figure 20, the width of the threshold voltage distribution in states S4 and S5 becomes smaller than after the first program operation PG1. Also, as shown in Figure 19, the sense amplifier 19 applies voltage VBL to bit lines BL_A, BL_B, and BL_D.

[0161] During the period when the pulse voltage Vp_D + ΔVp is applied to the selected word line WL, the sense amplifier 19 applies voltage ΔVt to the bit line BL_D corresponding to the selected memory cell transistor MC that is the target of programming in state S6, voltage VSS to the bit line BL_D corresponding to the selected memory cell transistor MC that is the target of programming in state S7, and voltage VBL to the bit line BL_D corresponding to the selected memory cell transistor MC that is inhibited. As shown in Figure 20, the width of the threshold voltage distribution in states S6 and S7 becomes smaller than after the first program operation PG1. Also, as shown in Figure 19, the sense amplifier 19 applies voltage VBL to bit lines BL_A, BL_B, and BL_C.

[0162] During the period from time t3 to t4, the program verification operation PV is performed in the same manner as during the period from time t1 to t2.

[0163] During the period from time t4 to t5, the third program operation PG3 is executed. The sense amplifier 19 applies a voltage to each bit line BL, similar to the second program operation PG2. As shown in Figure 20, the width of the threshold voltage distribution for states S0 to S7 becomes smaller than after the second program operation PG2.

[0164] As shown in Figure 19, during the period from time t5 to t6, the program verification operation PV is performed in the same manner as during the period from time t1 to t2. If the verification passes, the multi-pulse write operation is terminated.

[0165] 3.3 Effects according to this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained. Furthermore, with the configuration according to this embodiment, the semiconductor memory device 1 can apply different voltages to the bit lines BL corresponding to multiple states included in the same group. More specifically, the semiconductor memory device 1 can set the voltage of the bit line BL corresponding to a state with a low threshold voltage distribution higher than the voltage of the bit line BL corresponding to a state with a high threshold voltage distribution. This makes the increase in the threshold voltage of the memory cell transistor MC included in a state with a low threshold voltage distribution smaller than the increase in the threshold voltage of the memory cell transistor MC included in a state with a high threshold voltage distribution. This allows multiple adjacent states to be written with the same pulse voltage. The number of pulses in multi-pulse writing operation can be reduced. Therefore, the semiconductor memory device 1 can improve its processing capability. In this embodiment, the case where one group includes two states was described, but one group may include three or more states. Also, in this embodiment, the case where the third embodiment is applied to the first embodiment, that is, the case where different voltages are applied to bit lines BL corresponding to different states of the same group in the first embodiment was described, but the second and third embodiments may be combined.

[0166] 4. Variations, etc. The semiconductor memory device according to the above embodiment includes a plurality of memory strings (NS) containing a plurality of memory cells (MCs) stacked spaced apart in a first direction (Z direction), each arranged in a row in a second direction (Y direction) intersecting the first direction, and having current paths connected in series; a word line (WL) extending in the first direction and connected to the gates of the plurality of first memory cells stacked spaced apart in the first direction; a plurality of bit lines (BL) connected to each of the plurality of memory strings; a row decoder (18) connected to the word line; a sense amplifier (19) connected to the plurality of bit lines; and a controller (14) configured to execute a write operation by repeatedly performing a program loop including a program operation (PG) and a program verify operation (PV). Each of the plurality of memory cells is capable of storing data corresponding to any one of a plurality of states (S0 to S7). In the program operation of the plurality of first memory cells, the plurality of states are classified into a plurality of groups (group A to group D), and the row decoder applies a plurality of pulse voltages (Vp_A to Vp_D) corresponding to each of the plurality of groups to the word line. In the program verification operation of multiple first memory cells, the row decoder applies multiple verification voltages (V0 to V7) to the word line, each corresponding to a different state.

[0167] With the configuration according to the above embodiment, the semiconductor memory device can improve its processing capabilities.

[0168] Furthermore, various modifications are applicable, not limited to the embodiments described above.

[0169] In the above embodiment, "connection" includes a state in which something else, such as a transistor or resistor, is interposed between the two parties for an indirect connection.

[0170] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0171] 1...Semiconductor memory device, 2...Memory controller, 10...Input / output circuit, 11...Logic control circuit, 12...Address register, 13...Command register, 14...Programmable logic controller, 15...Ready / busy circuit, 16...Voltage generation circuit, 17...Memory cell array, 18...Raw decoder, 19...Sense amplifier, 20...Data register, 21...Column decoder, 120...Substrate, 121, 123...Insulating layer, 122...Semiconductor layer, 130, 140...Conductive film, 131, 132, 134, 141...Insulating film, 133...Charge storage film, 137...Insulator

Claims

1. A plurality of memory strings, each containing a plurality of memory cells stacked spaced apart in a first direction, arranged side by side in a second direction intersecting the first direction, and having current paths connected in series, A word line extending in the first direction and connected to the gates of a plurality of first memory cells stacked spaced apart in the first direction, Multiple bit lines connected to each of the aforementioned multiple memory strings, A row decoder connected to the aforementioned word line, A sense amplifier connected to the aforementioned plurality of bit lines, A controller configured to perform a write operation by repeatedly running a program loop that includes program operation and program verification operation. Equipped with, Each of the aforementioned plurality of memory cells is capable of storing data corresponding to one of the plurality of states, In the program operation of the plurality of first memory cells, the plurality of states are classified into a plurality of groups, and the row decoder applies a plurality of pulse voltages to the word line, each corresponding to the plurality of groups. In the program verification operation of the plurality of first memory cells, the row decoder applies a plurality of verification voltages to the word line, each corresponding to one of the plurality of states. Semiconductor memory device.

2. Each of the aforementioned plurality of groups includes one or more states among the plurality of states whose threshold voltage distributions are adjacent, and each of the plurality of states is included in any one of the plurality of groups. The semiconductor memory device according to claim 1.

3. In the program operation described above, the row decoder continuously applies the plurality of pulse voltages corresponding to each of the plurality of groups to the word line. The semiconductor memory device according to claim 2.

4. The aforementioned plurality of states include a first state and a second state, The plurality of groups includes a first group including the first state and a second group including the second state, The plurality of first memory cells include second and third memory cells for writing data corresponding to the first state, and a fourth memory cell for writing data corresponding to the second state. In the program operation of the plurality of first memory cells, when the second memory cell and the fourth memory cell are being programmed and the third memory cell is in a programmed state, the threshold voltage of the second memory cell is raised during a first period in which a first pulse voltage corresponding to the first group of the plurality of pulse voltages is applied to the word line, and the threshold voltage of the fourth memory cell is raised during a second period in which a second pulse voltage corresponding to the second group of the plurality of pulse voltages is applied to the word line. The semiconductor memory device according to claim 1.

5. The plurality of bit lines include a first bit line connected to the second memory cell, a second bit line connected to the third memory cell, and a third bit line connected to the fourth memory cell. The sense amplifier applies a first voltage to the first bit line during the first period, and applies a second voltage higher than the first voltage to the second bit line and the third bit line. The semiconductor memory device according to claim 4.

6. Based on the results of the program verification operation in the first program loop, the controller performs a reassignment of the multiple groups in the program operation of the second program loop. The semiconductor memory device according to claim 1.

7. The controller, in the first program loop, after the program operation, performs the program verification operation on the word line using a potential that is multiple times the difference between the pulse voltage used in the program operation of the first program loop and the pulse voltage scheduled to be used in the program operation of the second program loop, and in the program operation of the second program loop, changes the configuration of the multiple groups so that multiple second memory cells among the multiple first memory cells, whose pulse voltages used to raise the threshold voltage are the same, are included in the same group. The semiconductor memory device according to claim 1.

8. The controller, in the first program loop, after the program operation, performs the program verification operation on the word line using a potential that is multiple times the difference between the pulse voltage used in the program operation of the first program loop and the pulse voltage scheduled to be used in the program operation of the second program loop, and in the program operation of the second program loop, changes the configuration of the plurality of groups such that the second memory cell and the third memory cell, among the plurality of first memory cells, which have different conditions for the pulse voltage used to raise the threshold voltage, belong to different groups. The semiconductor memory device according to claim 1.

9. The difference between the pulse voltage used in the program operation of the first program loop and the pulse voltage used in the program operation of the second program loop is equal to the difference in threshold voltages between two adjacent states among the plurality of states whose threshold voltage distributions are adjacent. The semiconductor memory device according to any one of claims 6 to 8.

10. The plurality of states include a first state, a second state having a higher threshold voltage than the first state, and a third state having a higher threshold voltage than the second state. The plurality of groups includes a first group including the first state and the second state, and a second group including the third state, The plurality of first memory cells include a second memory cell and a third memory cell for writing data corresponding to the first state, a fourth memory cell and a fifth memory cell for writing data corresponding to the second state, and a sixth memory cell for writing data corresponding to the third state. The plurality of bit lines include a first bit line connected to the second memory cell, a second bit line connected to the third memory cell, a third bit line connected to the fourth memory cell, a fourth bit line connected to the fifth memory cell, and a fifth bit line connected to the sixth memory cell. In the program operation of the plurality of first memory cells, when the second memory cell, the fourth memory cell, and the sixth memory cell are subject to programming and the third memory cell and the fifth memory cell are in a program completed state, during the first period in which a first pulse voltage corresponding to the first group of the plurality of pulse voltages is applied to the word line, the sense amplifier applies a third voltage to the first bit line, applies a first voltage lower than the third voltage to the third bit line, and applies a second voltage higher than the third voltage to the second bit line, the fourth bit line, and the fifth bit line. The semiconductor memory device according to claim 1.

11. The third voltage is equal to the difference between the threshold voltage of the first state and the threshold voltage of the second state. The semiconductor memory device according to claim 10.

12. During the first period, the second memory cell and the fourth memory cell are subject to programming, while the third memory cell, the fifth memory cell, and the sixth memory cell are prohibited from being programmed. The semiconductor memory device according to claim 10.

13. Each of the plurality of pulse voltages is stepped up each time the program loop is repeated. The semiconductor memory device according to claim 1.

14. The step-up width of each of the aforementioned multiple pulse voltages is the same. The semiconductor memory device according to claim 13.

15. The number of the aforementioned groups is less than the number of the aforementioned states. The semiconductor memory device according to claim 1.

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