Semiconductor memory

Abstract

Applying high voltage to memory cells that are not intended for writing without increasing the voltage of the sense amplifier module. [Solution] The semiconductor memory device of the embodiment comprises a laminate in which a plurality of first insulating layers and a plurality of second insulating layers are alternately stacked; a plurality of channel layers provided in each of the plurality of first insulating layers and extending in a first direction along the plurality of first insulating layers; word lines extending within the laminate in the stacking direction of the laminate and intersecting the plurality of channel layers; a plurality of bit lines connected to each of the plurality of channel layers; and boost circuits provided in each of the plurality of first insulating layers and connected to each of the plurality of bit lines.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor memory devices. [Background technology]

[0002] In a semiconductor memory device having multiple memory cells connected to a common word line, a low-level voltage is supplied to the memory cell to be written to via the bit line, while a high-level voltage is applied to the memory cells not to be written to via the bit line. This allows data to be written to the memory cell to be written to, while data to be written to the memory cell not to be written to is suppressed.

[0003] The high-level voltage applied to memory cells not intended for writing is, for example, the power supply voltage. In this case, a higher voltage level can more reliably suppress writing, so there is a demand to further increase the voltage applied to memory cells not intended for writing. However, in this case, it is necessary to increase the voltage of the sense amplifier module that supplies voltage to the bit lines, which leads to an increase in the chip area of ​​the semiconductor memory device. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-146819 [Overview of the project] [Problems that the invention aims to solve]

[0005] One embodiment aims to provide a semiconductor memory device that can apply a high voltage to memory cells that are not to be written to without increasing the voltage of the sense amplifier module. [Means for solving the problem]

[0006] The semiconductor memory device of the embodiment comprises a laminate in which a plurality of first insulating layers and a plurality of second insulating layers are alternately stacked; a plurality of channel layers provided in each of the plurality of first insulating layers and extending in a first direction along the plurality of first insulating layers; word lines extending within the laminate in the stacking direction of the laminate and intersecting the plurality of channel layers; a plurality of bit lines connected to each of the plurality of channel layers; and boost circuits provided in each of the plurality of first insulating layers and connected to each of the plurality of bit lines. [Brief explanation of the drawing]

[0007] [Figure 1] Block diagram of a semiconductor memory device according to an embodiment. [Figure 2] A schematic circuit diagram showing an example of the block configuration of a semiconductor memory device according to an embodiment. [Figure 3] A circuit diagram showing an example of the configuration of a sense amplifier circuit and a latch circuit included in a semiconductor memory device according to an embodiment. [Figure 4] A schematic diagram illustrating the writing operation of a semiconductor memory device according to an embodiment. [Figure 5] A circuit diagram showing an example of the configuration of a boost circuit included in a semiconductor memory device according to an embodiment. [Figure 6] A schematic diagram illustrating the operation of a boost circuit in a semiconductor memory device according to an embodiment. [Figure 7] A schematic diagram showing an example of the configuration of a part of a semiconductor memory device according to the embodiment. [Figure 8] A plan view showing an example of the configuration of a part of a semiconductor memory device according to the embodiment. [Figure 9] A perspective cross-sectional view showing an example of a configuration including a block region of a semiconductor memory device according to an embodiment. [Figure 10] A schematic diagram showing an example of the configuration of the hookup region in a semiconductor memory device according to the embodiment. [Figure 11] A schematic diagram showing an example of the components of a boost circuit for a semiconductor memory device according to an embodiment. [Figure 12]A plan view showing an example of the physical configuration of a boost circuit included in a semiconductor memory device according to an embodiment. [Figure 13] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 14] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 15] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 16] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 17] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 18] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 19] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 20] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 21] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 22] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 23] A schematic diagram illustrating, in order, some of the steps of the method for manufacturing a semiconductor memory device according to an embodiment. [Figure 24] A circuit diagram showing an example of the configuration of a boost circuit included in a semiconductor memory device according to a modified embodiment. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially identical.

[0009] [Circuit configuration of semiconductor memory devices] First, an example of the circuit configuration of the semiconductor memory device 1 of the embodiment will be explained using Figures 1 to 6.

[0010] (Overall configuration of semiconductor memory device) Figure 1 is a block diagram of a semiconductor memory device 1 according to an embodiment. As shown in Figure 1, the semiconductor memory device 1 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, a command register 350, a sequencer 360, a ready / busy circuit 370, a voltage generation circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0011] The input / output circuit 310 controls the input and output of signal DQ to an external device, such as a memory controller (not shown), which controls the semiconductor memory device 1. The input / output circuit 310 includes an input circuit and an output circuit (not shown).

[0012] The input circuit sends data DAT, such as the write data WDT, received from an external device to the data register 540, sends address ADD to the address register 340, and sends command CMD to the command register 350.

[0013] The output circuit transmits status information STS received from status register 330, data DAT such as read data RDT received from data register 540, and address ADD received from address register 340 to an external device.

[0014] The logic control circuit 320 receives signals from an external device, such as the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn. The logic control circuit 320 also controls the input / output circuit 310 and the sequencer 360 according to the received signals.

[0015] The status register 330 temporarily holds status information STA during, for example, data write, read, and erase operations, and notifies an external device whether the operation has been completed successfully.

[0016] The address register 340 temporarily holds the address ADD received from an external device via the input / output circuit 310. The address register 340 also transfers the row address RA to the row decoder 520 and the column address CA to the column decoder 550.

[0017] The command register 350 temporarily stores the command CMD received from an external device via the input / output circuit 310 and transfers it to the sequencer 360.

[0018] The sequencer 360 controls the operation of the entire semiconductor memory device 1. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generation circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550, etc., in response to the command CMD held in the command register 350, and performs write operations, read operations, erase operations, etc.

[0019] The ready / busy circuit 370 transmits a ready / busy signal R / Bn to an external device depending on the operating status of the sequencer 360.

[0020] The voltage generation circuit 380 generates the voltages necessary for write, read, and erase operations in response to the control of the sequencer 360, and supplies the generated voltages to, for example, the memory cell array 510, the row decoder 520, and the sense amplifier module 530. The row decoder 520 and the sense amplifier module 530 apply the voltage supplied from the voltage generation circuit 380 to the memory cells in the memory cell array 510.

[0021] The memory cell array 510 includes multiple blocks BLK (BLK0 to BLKn), where n is an integer greater than or equal to 1. A block BLK is a collection of multiple memory cells associated with bit lines and word lines, and serves, for example, as a data erasure unit. The memory cells are configured, for example, as transistors, and hold non-volatile data.

[0022] By incorporating such memory cells, the semiconductor memory device 1 is configured as, for example, a NAND-type non-volatile memory.

[0023] The row decoder 520 decodes the row address RA. Based on the decoding result, the row decoder 520 selects one of the blocks BLK. The row decoder 520 also applies the required voltage to the block BLK.

[0024] During a read operation, the sense amplifier module 530 senses the data read from the memory cell array 510. The sense amplifier module 530 also transmits the read data RDT to the data register 540. During a write operation, the sense amplifier module 530 transmits the write data WDT to the memory cell array 510.

[0025] The data register 540 includes multiple latch circuits. The latch circuits hold the write data WDT and the read data RDT. For example, during a write operation, the data register 540 temporarily holds the write data WDT received from the input / output circuit 310 and transmits it to the sense amplifier module 530. Similarly, during a read operation, the data register 540 temporarily holds the read data RDT received from the sense amplifier module 530 and transmits it to the input / output circuit 310.

[0026] The column decoder 550 decodes the column address CA during operations such as write, read, and erase, and selects a latch circuit in the data register 540 according to the decoding result.

[0027] The group of circuits arranged around the memory cell array 510 is also called the peripheral circuit. The peripheral circuit includes at least a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550. The peripheral circuit may also include a status register 330, an address register 340, a command register 350, and a sequencer 360, and may further include an input / output circuit 310, a logic control circuit 320, a ready / busy circuit 370, and a voltage generation circuit 380.

[0028] Thus, the semiconductor memory device 1 comprises a memory cell array 510 containing multiple memory cells and peripheral circuits for operating the multiple memory cells.

[0029] (Block circuit configuration) Figure 2 is a schematic circuit diagram showing an example of the configuration of a block BLK in the semiconductor memory device 1 according to the embodiment. The semiconductor memory device 1 of the embodiment is configured as, for example, a three-dimensional non-volatile memory, as will be described in detail later. In Figure 2, the configuration of memory cells MC and the like included in the block BLK is shown in three dimensions accordingly.

[0030] The memory cell array 510 comprises multiple block BLKs as described above. Each of the multiple block BLKs comprises multiple string units SUs. Within a single block BLK, the multiple string units SUs are aligned with each other in the X direction.

[0031] Furthermore, as will be described later, the semiconductor memory device 1 of the embodiment has a stacked structure in which multiple layers are stacked in the Z direction, and each of the multiple string units SU comprises multiple memory units MU provided corresponding to each of these layers. Each of the multiple memory units MU comprises two memory strings MS.

[0032] One end of each of these two memory strings MS is connected to peripheral circuits such as the sense amplifier module 530 via common bit lines LBIx, LBIy, LBIstr, etc. The other ends of each of these two memory strings MS are connected to peripheral circuits via a common source line SL.

[0033] Multiple bit lines LBIx corresponding to a single block BLK extend along the X direction to positions corresponding to multiple memory units MU provided on one side of the block BLK in the Y direction, corresponding to each of the aforementioned layers. Multiple bit lines LBIy corresponding to these bit lines LBIx and connected to each of them extend along the Y direction to positions in the Z direction corresponding to these bit lines LBIx on one side of the corresponding block BLK in the X direction.

[0034] Furthermore, each of these bit lines LBIy is equipped with a boost circuit BST, which will be described in detail later.

[0035] Multiple bit lines LBIy correspond to a single block BLK, and multiple bit lines LBIstr connected to each of these bit lines LBIy extend along the X direction to the Z direction position corresponding to these bit lines LBIy on the other side of the corresponding block BLK in the Y direction.

[0036] Each of these bit lines LBIstr, corresponding to a single block BLK, has extensions that do not overlap with each other in the Z direction. By connecting the Z-direction-extending contacts described later to these non-overlapping Z-direction-extending portions, these bit lines LBIstr can be electrically drawn to the upper layers of multiple layers and connected to the sense amplifier module 530.

[0037] These bit lines, LBIx, LBIy, and LBIstr, are also called local bit lines, as they are located on the block BLK side in the connection between multiple memory cells MC and the sense amplifier module 530. These local bit lines are connected to the global bit lines, which will be described later and are located on the sense amplifier module 530 side, thereby electrically connecting the multiple memory cells MC and the sense amplifier module 530.

[0038] The memory string MS comprises multiple memory cells MC and selection transistors STD and STS connected in series between the bit line LBIx and the source line SL. The selection transistor STD, the multiple memory cells MC, and the selection transistor STS extend in this order along the Y direction. In this case, the selection transistor STD connected to the bit line LBIx is the drain-side selection transistor, and the selection transistor STS connected to the source line SL is the source-side selection transistor.

[0039] A memory cell MC is, for example, a field-effect transistor (FET) that includes a charge storage layer in its gate insulating layer. The threshold voltage of the memory cell MC changes depending on the amount of charge in the charge storage layer. By providing one or more threshold voltages, the memory cell MC may be able to store one bit or more bits of data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to a single memory string MS. These word lines WL are each commonly connected to all memory units MU in a single block BLK.

[0040] More specifically, among the multiple memory cells MC contained in multiple memory units MU that overlap each other in the Z direction, multiple memory cells MC that are located in the same position within the memory string MS, that is, between the selection transistors STD and STS, are connected in common by a word line WL that extends in the Z direction through the block BLK. In addition, within individual string units SU aligned in the X direction, multiple word lines WL that are connected to multiple memory cells MC that are located in the same position within the memory string MS and each extend in the Z direction are bundled together, for example, on the Z-outward side of the block BLK and extend in the X direction.

[0041] The selection transistors STD and STS are, for example, field-effect transistors. The gate electrodes of the selection transistors STD and STS are connected to selection gate lines SGD and SGS, respectively. The two selection gate lines SGD, which are drain-side selection gate lines corresponding to the two memory strings MS contained in one memory unit MU, are each commonly connected to all memory units MU in one string unit SU. The two selection gate lines SGS, which are source-side selection gate lines corresponding to the two memory strings MS contained in one memory unit MU, are each commonly connected to all memory units MU in one string unit SU.

[0042] More specifically, multiple selection transistors STD contained within multiple memory units MU that overlap each other in the Z direction are commonly connected to a selection gate line SGD that extends in the Z direction through the block BLK. Additionally, multiple selection transistors STS contained within multiple memory units MU that overlap each other in the Z direction are commonly connected to a selection gate line SGS that extends in the Z direction through the block BLK.

[0043] One end of the word line WL and one end of the selection gate lines SGD and SGS are connected to peripheral circuits such as the low decoder 520, respectively.

[0044] Furthermore, the selection transistor STD included in one memory string MS, the multiple memory cells MC, and the selection transistor STS share a channel. That is, the channel included in one memory string MS also extends along the Y direction to positions corresponding to the multiple layers provided by the semiconductor memory device 1 of this embodiment.

[0045] (Circuit configuration and operation of the sense amplifier module) Figure 3 is a circuit diagram showing an example of the configuration of the sense amplifier circuit SA and latch circuits SDL, ADL, BDL, and XDL provided in the semiconductor memory device 1 according to the embodiment. The sense amplifier module 530 described above is composed of a plurality of sense amplifier circuits SA provided for each bit line BL.

[0046] The bit line BL shown in Figure 3 corresponds to a global bit line that connects the aforementioned bit line LBIstr, which is part of the local bit lines, to the sense amplifier circuit SA. It is connected to the corresponding sense amplifier SA via the bit line connection section BLHU.

[0047] In the example shown in Figure 3, each bit line BLstr is connected to a bit line BL in a one-to-one relationship, but multiple bit lines BLstr may be connected to a single bit line BL. To miniaturize the semiconductor memory device 1, multiple bit lines BL are arranged at a narrow pitch. By connecting bit lines BLstr to bit lines BL in a many-to-one relationship, the number of bit lines BL can be reduced and the pitch can be loosened. Since the boost circuit BST also functions as a switch circuit, even in this case, it is possible to select a bit line BLstr to connect to the memory unit MU to be operated from among the multiple bit lines BLstr connected to a single bit line BL and electrically connect it to the sense amplifier circuit SA.

[0048] Each sense amplifier circuit SA, for example during a read operation, senses the data read to the corresponding bit line BL and determines whether the read data is "0" or "1".

[0049] Furthermore, the aforementioned data register 540 (see Figure 1) includes multiple latch circuits SDL, ADL, BDL, and XDL, each corresponding to a multiple sense amplifier circuit SA. These latch circuits SDL, ADL, BDL, and XDL are also provided for each bit line BL. The sense amplifier circuits SA and the latch circuits SDL, ADL, BDL, and XDL are each connected to the bus LBUS, and can send and receive data from each other via the bus LBUS.

[0050] These latch circuits, SDL, ADL, BDL, and XDL, temporarily hold data associated with their corresponding bit lines, BL. The number of latch circuits SDL, ADL, and BDL is designed based, for example, on the number of data bits that one memory cell MC can hold.

[0051] The latch circuit XDL is connected to the input / output circuit 310 (see Figure 1) of the semiconductor memory device 1 and is used for data input and output between the sense amplifier circuit SA and the input / output circuit 310. The latch circuit XDL can also be used, for example, as a cache memory for the semiconductor memory device 1. For example, even if the latch circuits SDL, ADL, and BDL are in use, the semiconductor memory device 1 can accept data from the outside if the latch circuit XDL is free.

[0052] Figure 3 shows one sense amplifier circuit SA within the sense amplifier module 530 and one latch circuit SDL, ADL, BDL, and XDL within the data register 540.

[0053] As shown in Figure 3, the sense amplifier circuit SA is a transistor TR 30 ~TR 37 and capacitor CA, and the bit line connection BLHU is transistor TR 38 ,TR 39 It includes.

[0054] Transistor T 30 This is a low-voltage P-channel MOS (Metal-Oxide-Semiconductor) FET.31 ~TR 37 Each of them is a low-voltage N-channel MOSFET. Transistor TR 38 ,TR 39 Each of them is a high-voltage N-channel MOSFET.

[0055] Low-voltage CMOS transistors including low-voltage P-channel MOSFETs and low-voltage N-channel MOSFETs are transistors to which a relatively low voltage is applied, and are also called low-voltage (LV: Low Voltage, VLV: Very Low Voltage) MOS transistors.

[0056] High-voltage CMOS transistors including high-voltage N-channel MOSFETs are transistors to which a relatively high voltage is applied, and are also called high-voltage (HV: High Voltage) MOS transistors.

[0057] The source of transistor TR 30 is connected to the power line. The drain of transistor TR 30 is connected to node ND1. The gate of transistor TR 30 is connected to node INV. Node INV is a node included in, for example, latch circuit SDL. The drain of transistor TR 31 is connected to node ND1. The source of transistor TR 31 is connected to node ND2. A control signal BLX is input to the gate of transistor TR 31 .

[0058] The drain of transistor TR 32 is connected to node ND1. The source of transistor TR 32 is connected to node SEN. A control signal HLL is input to the gate of transistor TR 32 . The drain of transistor TR 33 is connected to node SEN. The source of transistor TR 33 is connected to node ND2. A control signal XXL is input to the gate of transistor TR 33 .

[0059] Transistor (TR) 34 The drain of the transistor TR is connected to node ND2. 34 The gate of the transistor TR receives the control signal BLC. 35 The drain of the transistor TR is connected to node ND2. 35 The source is connected to node SRC. Transistor TR 35 The gate is connected, for example, to node INV in the latch circuit SDL.

[0060] Transistor (TR) 36 The source is grounded. Transistor TR 36 The gate of the transistor TR is connected to node SEN. 37 The drain of the transistor TR is connected to the bus LBUS. 37 The source is the transistor TR 36 The drain of the transistor TR is wrapped. 37 The control signal STB is input to the gate.

[0061] One electrode of capacitor CA is connected to node SEN. The other electrode of capacitor CA is connected to the clock signal CLK.

[0062] Transistor (TR) 38 The drain is transistor TR 34 It is connected to the source. Transistor TR 38 The source is connected to the bit line BL. Transistor TR 38 The gate of the transistor TR receives the control signal BLS. 39 The drain of the transistor TR is connected to node BLBIAS. 39 The source is connected to the bit line BL. Transistor TR 39 The control signal BIAS is input to the gate.

[0063] In the sense amplifier circuit SA, bit line connection section BLHU, and latch circuits SDL, ADL, BDL, XDL having the above configuration, the transistor TR 30 A power supply voltage, for example, VDD, is applied to the power line connected to the source. The power supply voltage VDD is, for example, the maximum voltage that the sense amplifier module 530 can output. A reference voltage VSS is applied to node SRC. The reference voltage VSS is, for example, 0V.

[0064] For example, the erase voltage VERA is applied to node BLBIAS. In node INV, which is included in the latch circuit SDL, the voltage changes based on the data held by the latch circuit SDL.

[0065] Each of the control signals BLX, HLL, XXL, BLC, STB, BLS, BIAS, and clock CLK is generated, for example, by the sequencer 360 (see Figure 1). In the read operation, the sense amplifier unit SA determines the data read to the bit line BL based on the timing when, for example, the control signal STB is activated.

[0066] Next, we will briefly explain the operation of the sense amplifier circuit SA with the above configuration.

[0067] As an example of writing data to a memory cell MC, when charge is injected into the memory cell MC to raise the threshold, the node INV of the latch circuit SDL stores an "H" level ("0" data). This causes the transistor TR 35 When this is turned on, a reference voltage VSS is applied to the bit line BL connected to the memory cell MC to be written to.

[0068] Another example of writing data to a memory cell MC is when no charge is injected into the memory cell MC and the threshold is not changed; in this case, the node INV of the latch circuit SDL stores an "L" level ("1" data). This causes the transistor TR 30 When the switch is turned on, the power supply voltage VDD is applied to the bit line BL connected to the memory cell MC to be written.

[0069] During readout, node INV is set to the "L" level, and transistor TR 30 When it is turned on, the bit line BL is precharged. Also, transistor TR 32 The device is also turned on, and node SEN is charged to the predetermined potential.

[0070] Subsequently, the transistor TR 35 When the transistor TR is turned off, the signal XXL is set to "H" level. 36 This is turned on. As a result, if the corresponding memory cell MC is turned on, the potential of node SEN decreases, and transistor TR 36 The transistor TR is turned off. On the other hand, if the corresponding memory cell MC is turned off, the potential of node SEN remains at the "H" level, and the transistor TR 36 It will be turned on.

[0071] Furthermore, the signal STB controls the transistor TR 37 When it is turned on, the transistor TR 36 The potential corresponding to the on / off state is read to the bus LBUS and held in one of the latch circuits SDL, ADL, BDL, or XDL.

[0072] Note that the circuit configurations of the sense amplifier circuit SA and latch circuits SDL, ADL, BDL, and XDL shown in Figure 3 are just examples, and the sense amplifier circuit SA and latch circuits SDL, ADL, BDL, and XDL can take various other configurations.

[0073] Here, within a single string unit SU, the write operation to the memory cell MC is performed for each word line WL. Therefore, among the multiple memory cell MCs connected to the common word line WL, for example, the bit line BL connected to the memory cell MC to which "0" data is to be written is applied as described above, while the bit line BL connected to the memory string MS containing memory cell MCs that are not to be written to is applied, thereby suppressing the writing of data to these memory cell MCs that are not to be written to. Details of this operation will be explained using Figure 4.

[0074] Figure 4 is a schematic diagram showing the writing operation of the semiconductor memory device 1 according to the embodiment.

[0075] Figure 4 shows the memory string MS contained within a single string unit SU. However, to avoid making the diagram too complex, only one of the two memory string MS contained within the memory unit MU of the string unit SU is shown in each figure.

[0076] Furthermore, in the example in Figure 4, the memory cell MC to be written is the third memory cell MC from the left side of the page, located in the center between the selection transistors STD and STS at both ends of the memory string MS, which is connected to the second bit line BL from the upper layer.

[0077] As shown in Figure 4, during a write operation, a reference voltage VSS is applied to the memory string MS containing the memory cell MC to be written, via the bit lines LBIstr, LBIy, LBIx, etc., from the bit line BL. In addition, a write suppression voltage VDDbst is applied to the other memory string MS via the bit lines LBIstr, LBIy, LBIx, etc., from the bit line BL. The write suppression voltage VDDbst has a voltage value obtained by boosting the power supply voltage VDD supplied from the bit line BL by the boost circuit BST (see Figure 2) provided on the corresponding bit line LBIy.

[0078] Furthermore, during the write operation, voltages Vsgd and Vsgs are applied to the selection transistors STD and STS within the string unit SU containing the memory cell MC to be written, from the selection gate lines SGD and SGS to which they are connected. Voltage Vsgd is the voltage at which the selection transistor STD turns on when the voltage applied from the bit line BL is approximately the reference voltage VSS. Voltage Vsgs is the voltage at which the selection transistor STS turns off regardless of the threshold voltage of the selection transistor STS. Therefore, the selection transistor STS belonging to the memory string MS within the string unit SU remains off throughout the process, and as long as the channel potential of each memory string MS is low, all the selection transistors STD belonging to the memory string MS within the string unit SU are turned on.

[0079] Subsequently, when the write suppression voltage VDDbst, which is higher than the reference voltage VSS, rises in the channel potential of memory string MS containing memory cells MC that are not to be written to, the selection transistor STD belonging to these memory string MS is cut off. On the other hand, the channel potential of memory string MS containing memory cells MC that are to be written to is suppressed to approximately the reference voltage VSS, so the selection transistor STD remains ON.

[0080] Furthermore, during the write operation, a program voltage Vpgm is applied to the word line WL connected to the memory cell MC to be written. The program voltage Vpgm is a voltage that allows charge to be stored in the charge storage layer of the memory cell MC. In addition, a transfer voltage Vpass is applied to the word lines WL connected to other memory cell MCs. The transfer voltage Vpss is the voltage at which the memory cell MC turns on, regardless of the threshold voltage of the memory cell MC.

[0081] As a result, in the memory cell MC being written to, the potential difference between the channel potential and the program voltage Vpgm applied from the word line WL causes charge (electrons) to be injected from the channel into the charge storage layer, shifting the threshold voltage in the positive direction. This writes, for example, "0" data to the memory cell MC being written to.

[0082] On the other hand, in memory strings MS to which memory cells MC that are not to be written belong, the selection transistor STD is cut off. As a result, the channels of these memory cells MC are electrically floating and are coupled with the word line WL to which the program voltage Vpgm is applied and the word line WL to which the transfer voltage Vpss is applied, raising the voltage to Vboost. This reduces the potential difference between the channel potential and the program voltage Vpgm applied from the word line WL, preventing charge (electrons) from being injected from the channel into the charge storage layer. This suppresses the writing of data to memory cells MC that are not to be written.

[0083] In this case, if the potential difference between the channel and the program voltage Vpgm is not sufficiently small, memory cells MC that are not intended for writing are susceptible to program disturbance. Program disturbance is a phenomenon in which the threshold voltage shifts in the positive direction, resulting in a weak write state, even in memory cells MC that are not intended for writing. As described above, by applying a write suppression voltage VDDbst to the memory string MS containing memory cells MC that are not intended for writing, the potential of the channel can be raised in advance, thereby increasing the value of the boost voltage Vboost in the channel and reducing the potential difference between the channel and the program voltage Vpgm.

[0084] In the semiconductor memory device 1 of this embodiment, the power supply voltage VDD supplied from the bit line BL is further boosted by the boost circuit BST to obtain a write suppression voltage VDDbst. Therefore, the potential difference between the channel and the program voltage Vpgm can be kept sufficiently small, thereby suppressing program disturbance in memory cells MC that are not to be written to.

[0085] (Circuit configuration and operation of the boost circuit) Figure 5 is a circuit diagram showing an example of the configuration of a boost circuit BST provided in the semiconductor memory device 1 according to the embodiment. As described above, the boost circuit BST is provided for each of the multiple bit lines LBIy. More specifically, the boost circuit BST is inserted in the middle of the corresponding bit line LBIy.

[0086] As shown in Figure 5, each booster circuit BST is a transistor TR 60 ~TR 67 It is composed of including the transistor TR. 60 ,TR 62 ,TR 64 ,TR 66 This is a low-voltage N-channel MOSFET. (Transistor TR) 61 ,TR 63 ,TR 65 ,TR 67 Each of these is a low-voltage P-channel MOSFET.

[0087] Transistor (TR) 60 The bit line LBIy is inserted in the middle of the bit line LBIy, with the drain connected to the side of bit line LBIy leading to bit line LBIstr, and the source connected to the side of bit line LBIy leading to bit line LBIx.

[0088] Transistor (TR) 61 The source is connected to the power line. Transistor TR 62 The drain is transistor TR 61 The drain is easily visible. Also, the transistor TR 61 ,TR 62 Each of the drains is a transistor TR 60 It is connected to the gate of the transistor TR. 62 The source is grounded. Transistor TR 61 ,TR 62 Each of these gates is connected to the side of bit line LBIy that leads to bit line LBIstr.

[0089] Transistor (TR) 63 The source is connected to the power line. Transistor TR 64 The drain is the transistor TR 63 The drain of the transistor TR is wrapped. 64 The source is grounded. Transistor TR 64 The gate is connected to the side of bit line LBIy that leads to bit line LBIstr.

[0090] Transistor (TR) 65 The source is connected to the power line. Transistor TR 65 The gate is a transistor TR 63 ,TR 64 It is connected to the respective drains of the transistor TR. 66 The drain is the transistor TR 65 The drain is easily visible. Also, the transistor TR 65 ,TR 66 Each of the drains is a transistor TR 63 It is connected to the gate of the transistor TR. 66The source is grounded. Transistor TR 66 's gate is connected to the drain of each of transistors TR 61 , TR 62 .

[0091] The source of transistor TR 67 is connected to the drain of each of transistors TR 65 , TR 66 . The drain of transistor TR 67 is connected to the side leading to bit line LBIx of bit line LBIy. The gate of transistor TR 67 is connected to the side leading to bit line LBIstr of bit line LBIy.

[0092] In the boost circuit BST having the above configuration, a power supply line connected to the source of transistor TR 61 is applied with, for example, a low-level voltage V LW . Voltage V LW is a voltage at which transistors TR 60 , TR 66 , etc. that are low-voltage-tolerant N-channel MOSFETs turn on. A power supply line connected to the source of transistors TR 63 , TR 65 is applied with, for example, a high-level voltage V HG . Voltage V HG is a voltage higher than the power supply voltage VDD and may be approximately equal to the write suppression voltage VDDbst applied to the memory string MS including the memory cell MC that is not the write target.

[0093] Also, among transistors TR 60 ~TR 67 included in the boost circuit BST, transistors TR 61 , TR 62 function as an inverter. Also, transistors TR 63 ~TR 66 function as a level shifter that converts the voltage level.

[0094] Next, the operation of the boost circuit BST having the above configuration will be explained using Figure 6.

[0095] Figure 6 is a schematic diagram showing the operation of a boost circuit BST provided in a semiconductor memory device 1 according to an embodiment. More specifically, Figure 6(a) shows an example of the operation of a boost circuit BST provided on a bit line LBIy connected to a memory string MS containing a memory cell MC to be written to. Figure 6(b) shows an example of the operation of a boost circuit BST provided on a bit line LBIy connected to a memory string MS containing a memory cell MC that is not to be written to.

[0096] As shown in Figure 6(a), a reference voltage VSS is supplied, for example, from the sense amplifier circuit SA to the bit line LBIy connected to the memory string MS containing the memory cell MC to be written. This reference voltage VSS is supplied by the transistor TR 61 ,TR 62 ,TR 64 ,TR 67 It is also applied to the gates of each of them. The reference voltage VSS is applied to the transistor TR, which is a low-voltage P-channel MOSFET. 61 ,TR 67 This is the voltage at which the transistor TR turns on, and it is a low-voltage N-channel MOSFET. 62 ,TR 64 This is the voltage at which the device does not turn on.

[0097] Also, transistors (TR) 61 A low-level voltage V is present in the power line connected to the source. LW When a voltage is applied, the transistor TR 63 ,TR 65 Each power line connected to the source has a high-level voltage V HG It is applied.

[0098] This results in the transistor TR 61 When it turns on, the transistor TR 61 From the source of transistor TR 60 Voltage V applied to the gate LW A voltage is applied. Therefore, the transistor TR 60When this is turned on, the voltage VSS supplied from the sense amplifier circuit SA to the bit line LBIy is transferred to the memory string MS connected to that bit line LBIy.

[0099] The voltage VSS supplied to the bit line LBIy is determined by the transistor TR 62 ,TR 64 The threshold voltage has not been reached, and these transistors TR 62 ,TR 64 It remains turned off.

[0100] Also, transistors (TR) 61 Voltage V from the source LW is a transistor TR 66 It is also applied to the gate of the transistor TR 66 It also turns on. Therefore, the transistor TR 63 The gate of the transistor TR 66 A ground voltage is applied through this. This causes the transistor TR 63 When it turns on, the transistor TR 63 Voltage V HG However, transistor TR 65 It is applied to the gate of the transistor TR. Therefore, 65 Turn off the transistor TR 63 Voltage V HG is a transistor TR 67 It will not be supplied to the source.

[0101] Also, transistors (TR) 67 The gate of the transistor TR has a voltage VSS applied from the bit line LBIy, but 67 The source is the transistor TR 66 Because it is grounded via the transistor TR 67 It remains turned off.

[0102] As shown in Figure 6(b), the bit line LBIy connected to the memory string MS containing memory cells MC that are not to be written to is supplied with, for example, a power supply voltage VDD from the sense amplifier circuit SA. This power supply voltage VDD is supplied by the transistor TR61 ,TR 62 ,TR 64 ,TR 67 It is also applied to each of the gates of the transistor TR. 61 A low-level voltage V is present in the power line connected to the source. LW When a voltage is applied, the transistor TR 63 ,TR 65 Each power line connected to the source has a high-level voltage V HG It is applied.

[0103] This results in the transistor TR 62 ,TR 64 When it turns on, the transistor TR 65 The gate of the transistor TR 64 A ground voltage is applied through it. Therefore, transistor TR 65 When it turns on, the transistor TR 65 From the source of transistor TR 67 Voltage V at the source HG It will be supplied.

[0104] Furthermore, as mentioned above, the transistor TR 67 The gate of the transistor TR has the power supply voltage VDD from the bit line BLIy applied to it. 67 A high-level voltage V is applied to the source. HG The potential difference between it and the transistor TR 67 When it turns on, the transistor TR 65 Voltage V supplied from the source HG However, transistor TR 67 It is transferred via to the memory string MS connected to the bit line LBIy.

[0105] As mentioned above, voltage V HG For example, it is approximately equal to the write suppression voltage VDDbst, and the transistor TR 67 When this is turned on, the power supply voltage VDD supplied from the sense amplifier circuit SA to the bit line LBIy is boosted to the write suppression voltage VDDbst and applied to the memory string MS connected to the bit line LBIy.

[0106] Note that the transistor TR 65 Voltage V from the source HG is a transistor TR 63 Because it is also applied to the gate of the transistor TR 63 Turn off the transistor TR 63 Voltage V from the source HG is a transistor TR 65 It is not applied to the gate of the transistor TR 65 The ON state is maintained.

[0107] Also, transistors (TR) 61 Since it is turned off, the transistor TR 61 Voltage V from the source LW is a transistor TR 60 ,TR 66 None of the gates are affected, and these transistors TR 60 ,TR 66 It remains off. Therefore, the voltage VDD supplied from the sense amplifier circuit SA to the bit line LBIy is the transistor TR 60 The signal is interrupted and not directly transferred to the memory string MS connected to that bit line LBIy.

[0108] Note that the circuit configuration of the boost circuit BST shown in Figures 5 and 6 is just one example, and the boost circuit BST can take various other configurations.

[0109] [Physical configuration of semiconductor memory devices] Next, an example of the physical configuration of the semiconductor memory device 1 of the embodiment will be described using Figures 7 to 12.

[0110] (Example of block area configuration) First, using Figures 7 to 9, we will explain the block region R of the semiconductor memory device 1. BLK This section explains an example configuration.

[0111] Figure 7 is a schematic diagram showing an example of the configuration of a part of the semiconductor memory device 1 according to the embodiment. More specifically, Figure 7(a) shows the block region R BLK This is a plan view showing examples of the configuration of each region, including Figure 7(b), where block region R BLK This is a schematic perspective view showing the connection relationship between the bit lines LBIx, LBIy, LBIstr, and BL. Figure 7(a) shows one of the multiple layers of the semiconductor memory device 1.

[0112] As shown in Figure 7(a), the semiconductor memory device 1 has multiple block regions R BLK multiple hookup regions R HU , and multiple bit line regions R BL It is equipped with.

[0113] Block region R BLK This corresponds to the physical configuration of the aforementioned block BLK (see Figure 2, etc.), and is arranged in a matrix in the X and Y directions. Hook-up region R HU This is a series of block regions R aligned in the Y direction. BLK It is located between the following. Hook-up region R HU They are arranged side by side in the X direction, and block region R BLK It is adjacent to the Y direction. Bit line region R BL This is a combination of multiple block regions R BLK , and hookup region R HU It is located between the bit line region R. BL This is a combination of multiple block regions R BLK and hookup region R HU The positions aligned in the X direction extend in the Y direction.

[0114] Furthermore, in the example shown in Figure 7(a), there are two block regions R aligned in the Y direction. BLK Between them, the bit line LBIx extends in the direction along the X direction. These two block regions R BLK Within this, each bit line LBIx is connected to multiple channel layers CN, as shown in Figure 7(b).

[0115] As shown in Figure 7(b), and as described above, block region R BLK Within the structure, multiple channel layers CN, each extending along the Y direction, are arranged in multiple stages corresponding to multiple layers, and these multi-stage stacked channel layers CN are arranged in a line along the X direction. The channel layers CN correspond to the physical configuration of channels commonly provided in multiple memory cells MC and selection transistors STD and STS included in the memory string MS described above.

[0116] Between the channel layers CN aligned in the X direction, multiple word lines WL extending along the Z direction are arranged spaced apart in the Y direction along the extension direction of the channel layers CN. The channel layers CN aligned in the X direction corresponding to each layer are connected in common to a single bit line LBIx.

[0117] As shown in Figure 7(a), the bit line region R BL A bit line LBIy extending along the Y direction is provided. Two block regions R BLK Between them, multiple bit lines LBIx extending along the X direction with one bit line LBIy in between are commonly connected to this bit line LBIy. Also, bit line LBIy is connected to the hookup region R HU In this configuration, the bit line LBIstr is connected to the bit line BL, and then electrically connected to the corresponding sense amplifier circuit SA.

[0118] As shown in Figure 7(b), multiple bit lines LBIstr are arranged, for example, in a stepped pattern, and have portions that do not overlap with each other in the Z direction. Bit lines LBIy, which are stacked in multiple stages on different layers, are connected to the bit lines LBIstr on the same layer. Furthermore, contact CCs are provided at the stepped portions of these bit lines LBIstr, and block region R BLK It is connected to multiple bit lines BL that extend along the Y direction above it.

[0119] However, as mentioned above, bit line BL and bit line LBIstr may be connected in a one-to-many relationship.

[0120] Also, block region R BLK Within, multiple bit lines LBIx are connected to each of the multiple channel layers CN that are stacked in multiple stages, and the block region R is connected to it. BLK Within the X-direction, one side extends along the Y-direction along multiple bit lines LBIy, each of which is provided with a boost circuit BST. That is, the multiple boost circuits BST are located in the corresponding block region R BLK Bit line region R aligned in the X direction BL They are arranged in multiple layers, stacked together with multiple bit lines LBIy.

[0121] Figure 8 is a plan view showing an example of the configuration of a part of the semiconductor memory device 1 according to the embodiment. More specifically, Figure 8 is an enlarged plan view of area A shown in Figure 7(a) above.

[0122] As shown in Figure 8, block region R BLK It contains multiple memory cell regions R aligned in the Y direction. MC And two adjacent memory cell regions R in the Y direction MC Ladder region R provided between LD And, block region R BLK Selected transistor region R located at the Y-direction end SGD And, there are two block regions R aligned in the Y direction. BLK Between them is the bit line region R LBI A section is provided, and two block regions R are aligned in the X direction. BLK Between them is the bit line region R BL A system is in place.

[0123] Memory cell region R MC As described above, multiple channel layers CN extending along the Y direction are arranged and connected to multiple word lines WL extending along the Z direction, penetrating multiple layers. The channel layers CN are, for example, semiconductor layers, and the memory cell region R MC In this context, it functions as a channel in the memory cell MC. Multiple channel layers CN form the ladder region R LD and selected transistor region RSGD It extends to that area as well.

[0124] Radder area R LD and selected transistor region R SGD Multiple contact electrodes CE extending along the Z direction through multiple layers and multiple gate electrodes GE are arranged in this region and connected to the channel layer CN. The multiple contact electrodes CE form hole channels in the channel layer CN, which is a semiconductor layer or the like, and supply voltage to the hole channels formed in the channel layer CN. Ladder region R comprising multiple contact electrodes CE and gate electrodes GE LD This functions as a relay circuit that transfers voltage between channel layers CN extending along the Y direction. Selected transistor region R SGD In this configuration, the gate electrode GE functions as the selected gate line SGD, and the channel layer CN functions as the channel of the selected transistor STD.

[0125] Bit line region R LBI In this region, a bit line LBIx, which is a conductive layer such as a titanium nitride layer, extends along the X direction. Bit line region R BL Two block regions R are arranged and aligned in the X direction. BLK The bit line LBIy extending along the Y direction between them is also a conductive layer, such as a titanium nitride layer.

[0126] Figure 9 shows the block region R of the semiconductor memory device 1 according to the embodiment. BLK This is a perspective cross-sectional view showing an example of a configuration including the above. More specifically, Figure 9 is a perspective cross-sectional view including the layer LR portion of region B shown in Figure 8 above.

[0127] As shown in Figure 9, the semiconductor memory device 1 comprises a plurality of layers LR (LR0, LR1, LR2...LR9...) stacked in the Z direction on a semiconductor substrate SB, with insulating layers 101 sandwiched between them. The semiconductor substrate SB is, for example, a silicon substrate containing P-type impurities such as boron. The insulating layer 101 is, for example, a silicon oxide layer.

[0128] As will be described later, these multiple layers LR are layers in which various components such as channel layers CN and bit lines LBIx, LBIy are arranged within insulating layers such as silicon nitride layers that are stacked with insulating layer 101 in between, and constitute the actual part of the semiconductor memory device 1, including memory cells MC, etc. Hereafter, multiple layers LR with insulating layer 101 interposed, or a structure in which insulating layer 101 such as silicon oxide layers and multiple insulating layers such as silicon nitride layers are stacked will also be referred to as a laminate.

[0129] Multiple channel layers CN are provided within each of the multiple layers LR, spaced apart from each other in the X direction and extending along the Y direction. The channel layers CN are semiconductor layers, such as undoped polycrystalline silicon layers. Between these channel layers CN aligned in the X direction, insulating layers 165, such as silicon oxide layers, are arranged, penetrating the multiple layers LR and insulating layer 101 and extending in the Z direction. Furthermore, multiple word lines WL, gate electrodes GE, and contact electrodes CE extend in the Z direction, penetrating the multiple layers LR and insulating layer 101 at positions overlapping with these insulating layers 165 in the Z direction.

[0130] Each of the multiple word wires WL comprises a conductive layer 122 that serves as the core material of the word wire WL, and a barrier metal layer 123 that covers the sidewalls of the conductive layer 122. The conductive layer 122 is, for example, a tungsten layer, and the barrier metal layer 123 is, for example, a titanium nitride layer.

[0131] Furthermore, a memory layer ME is provided within the multiple layers LR, covering the sidewall of the barrier metal layer 123. The memory layer ME has a stacked structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in that order from the barrier metal layer 123 side, and functions as a gate insulating layer for a memory cell MC with a channel layer CN as the channel. Each of the multiple word lines WL is connected to the channel layer CN via the memory layer ME.

[0132] The tunnel insulating layer TN is a silicon oxide layer, and the tunnel effect of the tunnel insulating layer TN causes the charge (electrons) from the channel layer CN to be injected into and held in the charge storage layer CT, thereby enabling data writing to the memory cell MC.

[0133] The charge storage layer (CT) is, for example, a polycrystalline silicon layer, and stores data by holding the charge injected from the channel layer (CN). The polycrystalline silicon layer of the charge storage layer (CT) may contain N-type impurities such as phosphorus or P-type impurities such as boron, or it may not contain these impurities.

[0134] The block insulating layer BK is, for example, a silicon oxide layer. In addition to the silicon oxide layer, the block insulating layer BK may also have an insulating metal oxide layer such as an aluminum oxide layer or a hafnium oxide layer.

[0135] Each of the multiple gate electrodes (GEs) comprises a conductive layer 152 covering the sidewall of an insulating layer 151 that serves as the core material of the gate electrode GE, and a semiconductor layer 150 covering the sidewall of the conductive layer 152. The insulating layer 151 is, for example, a silicon oxide layer, the conductive layer 152 is, for example, a titanium nitride layer, and the semiconductor layer 150 is, for example, a polycrystalline silicon layer containing N-type impurities such as phosphorus.

[0136] Furthermore, an insulating layer 155, such as a silicon oxide layer, is provided on the outside of the semiconductor layer 150, covering the sidewalls of the semiconductor layer 150.

[0137] As mentioned above, the selected transistor region R SGD In this configuration, the gate electrode GE functions as the selection gate line SGD, and the channel layer CN, connected to the gate electrode GE via the insulating layer 155, functions as the channel of the selection transistor STD, with the insulating layer 155 functioning as the gate insulating layer of the selection transistor STD.

[0138] Each of the multiple contact electrodes CE comprises a conductive layer 142 that serves as the core material of the contact electrode CE, and a semiconductor layer 140 that covers the sidewall of the conductive layer 142. Each of these contact electrodes CE may further be provided with a semiconductor layer 144 that covers the sidewall of the semiconductor layer 140. The conductive layer 142 is, for example, a titanium nitride layer; the semiconductor layer 140 is, for example, a polycrystalline silicon layer containing P-type impurities such as boron; and the semiconductor layer 144 is, for example, an undoped polycrystalline silicon layer. However, the semiconductor layer 144 may be omitted in the contact electrode CE.

[0139] Also, the selected transistor region R SGD In this configuration, multiple semiconductor layers 160 are provided within each of the multiple layers LR, each connected to one end in the Y direction of the multiple channel layers CN. The semiconductor layers 160 are, for example, polycrystalline silicon layers containing N-type impurities such as phosphorus. The aforementioned insulating layers 165 are also arranged between the semiconductor layers 160 aligned in the X direction, and multiple insulating layers 161 extend in the Z direction, penetrating the multiple layers LR and insulating layer 101 at positions that overlap with these insulating layers 165 in the Z direction.

[0140] Also, the bit line region R LBI In this configuration, multiple insulating layers 171 extending in the Z direction, penetrating multiple layers LR and insulating layer 101, are arranged in the X direction along the bit line LBIx. These insulating layers 171 are, for example, silicon oxide layers.

[0141] Also, the bit line region R LB In this configuration, multiple bit lines LBIy are provided in each of the multiple layers LR, spaced apart from each other in the X direction and extending along the Y direction. Between these bit lines LBIy aligned in the X direction, an insulating layer 185, such as a silicon oxide layer, is arranged, penetrating the multiple layers LR and the insulating layer 101 and extending in the Z direction. Furthermore, at positions overlapping with the insulating layer 185 in the Z direction, multiple insulating layers 181 extend in the Z direction, penetrating the multiple layers LR and the insulating layer 101. These insulating layers 181 are, for example, silicon oxide layers.

[0142] Furthermore, multiple layers LR and the insulating layer 101 penetrate the bit line region R. LB and block region R BLK An insulating layer 175, such as a silicon oxide layer, is positioned across from it, extending in the Z direction.

[0143] (Example of hookup area configuration) Next, using Figure 10, the hookup region R of the semiconductor memory device 1 is shown. HU This section explains an example configuration.

[0144] Figure 10 shows the hookup region R of the semiconductor memory device 1 according to the embodiment. HU This is a schematic diagram showing an example of the configuration. More specifically, Figure 10(a) is an enlarged plan view of region C shown in Figure 7(a) above, Figure 10(b) is a cross-sectional view along the line D-D' in Figure 10(a), and Figure 10(c) is a cross-sectional view along the line E-E' in Figure 10(a).

[0145] As shown in Figure 10(a), the hookup region R HU This includes multiple leader line regions R aligned in the Y direction. LL And two adjacent leader line regions R in the Y direction LL Contact area R provided between CC And, is provided.

[0146] As shown in Figures 10(a) to (c), the leader line region R LL In this region, an insulating layer 191 extending in the Z direction penetrates multiple insulating layers 102, each arranged in multiple layers LR, and multiple insulating layers 101 interposed between the multiple insulating layers 102, in the lead wire region R. LL They are arranged in the X direction along the stretching direction. The insulating layer 102 is, for example, a silicon nitride layer.

[0147] The insulating layer 191 is, for example, a silicon oxide layer or the like. In the plurality of layers LR, a conductive layer 196 such as a titanium nitride layer covering the side walls of the insulating layer 191 is provided. In the plurality of layers LR, the conductive layers 196 covering the individual insulating layers 191 are connected to each other in the X direction. As a result, in the plurality of layers LR, the conductive layer 196 extends continuously in the X direction in the lead-out region R LL and extends continuously in the X direction. Further, these conductive layers 196 are electrically connected to the bit lines LBIy arranged in the same layer LR among the plurality of bit lines LBIy described above, respectively. That is, the conductive layer 196 is connected to the corresponding channel layer CN via the bit lines LBIy and LBIx.

[0148] In the contact region R CC a plurality of contacts CC arranged in the X direction along the conductive layer 196 are disposed. These contacts CC each include a conductive layer 192 serving as the core material of the contact CC, a barrier metal layer 193 covering the side walls of the conductive layer 192, and an insulating layer 195 covering the side walls of the barrier metal layer 193. The conductive layer 192 is, for example, a tungsten layer or the like, the barrier metal layer 193 is, for example, a titanium nitride layer or the like, and the insulating layer 195 is, for example, a silicon oxide layer or the like.

[0149] The conductive layer 192 and the barrier metal layer 193 extend in the Z direction through the plurality of insulating layers 102 and the insulating layer 101 and reach the insulating layer 102 at a predetermined depth. The lower end portion of the barrier metal layer 193 has a disk shape and spreads into the insulating layer 102 located at the contact depth of the contact CC. One end portion of the disk-shaped portion of the barrier metal layer 193 is connected to the adjacent conductive layer 192. The insulating layer 195 covers the side walls of the barrier metal layer 193 and extends in the Z direction through the plurality of insulating layers 102 and the insulating layer 101, and terminates in the insulating layer 102 of the upper layer by one layer more than the insulating layer 102 reached by the conductive layer 192 and the barrier metal layer 193. The insulating layer 195 has a protruding portion protruding into the insulating layer 102 at the height position of the individual insulating layers 102 penetrated by the insulating layer 195.

[0150] As shown in Figures 10(b) and 10(c), the contact CCs in the multiple insulating layers 102 and 101 have different reach depths.

[0151] For example, two leader line regions R LL Between these two adjacent contact CCs in the Y direction, they reach an insulating layer 102 with a depth difference of one layer. These two contact CCs are connected to an adjacent conductive layer 196 in the disc-shaped portion of the barrier metal layer 193. Furthermore, two adjacent contact CCs in the X direction along the conductive layer 196 reach an insulating layer 102 with a depth difference of two layers.

[0152] In this manner, among two adjacent contact CCs in the X or Y direction, the disc-shaped portion of the barrier metal layer 193 in the contact CC with the shallower reach terminates in contact with the insulating layer 195 of the contact CC with the deeper reach. This prevents the conductive layers 192 or barrier metal layer 193 of these two contact CCs from coming into contact and causing electrical conductivity between them.

[0153] Furthermore, the disc-shaped portion of the barrier metal layer 193 does not necessarily have to have a uniform thickness, as shown in the examples in Figures 10(b) and 10(c). For example, the disc-shaped portion may be thicker near the lower end of the conductive layer 192 than the portion that extends into the insulating layer 102.

[0154] As shown in Figure 10(a), in these contact CCs, the outer edge of the disc-shaped portion of the barrier metal layer 193 is missing in the portion that contacts the conductive layer 196 or other contact CCs. On the other hand, in the portion that does not face the conductive layer 196 or other contact CCs, the lower end of the barrier metal layer 193 expands into a disc shape as described above and terminates in the insulating layer 102 to the depth reached by the contact CC.

[0155] These contact CCs are connected via plugs (not shown) or directly to the hook-up region R. HUThe upper part is connected to multiple bit lines BL that extend in the Y direction.

[0156] With the above configuration, bit lines LBIx and LBIy, which are connected to each of the multi-stage stacked channel layers CN and located in different layers LR, can be brought out to the upper surface of the stacked structure of multiple insulating layers 102 and insulating layer 101. At this time, the disc-shaped portion of the barrier metal layer 193 of each contact CC functions as the bit line LBIstr described above.

[0157] In Figures 2, 3, and 7(b) above, for the sake of simplicity in illustration and explanation, multiple bit lines LBIstr are shown as stepped shapes with different extension distances in the X direction. More specifically, the above functions of the bit line LBIstr can be realized by the configuration shown in Figure 10 above, for example.

[0158] (Example of a boost circuit configuration) Next, an example of the configuration of the boost circuit BST provided in the semiconductor memory device 1 will be described using Figures 11 and 12. Figure 11 is a schematic diagram showing an example of the various parts provided in the boost circuit BST of the semiconductor memory device 1 according to this embodiment.

[0159] More specifically, Figure 11(a) is a plan view of transistors TR6n and TR6p in the boost circuit BST, and Figure 11(b) is a perspective view of transistors TR6n and TR6p. Note that transistor TR6n is a low-voltage N-channel MOSFET, and is the same transistor as shown in Figure 5 above. 60 ,TR 62 ,TR 64 ,TR 66 This corresponds to the physical configuration of the transistor TR6p. Furthermore, transistor TR6p is a low-voltage P-channel MOSFET, and is the same transistor as shown in Figure 5 above. 61 ,TR 63 ,TR 65 ,TR 67 This corresponds to the physical configuration.

[0160] Furthermore, Figure 11(c) is a perspective view of the wiring WR of the boost circuit BST, and Figure 11(d) is a perspective view of the power supply line PW of the boost circuit BST.

[0161] As shown in Figures 11(a) and 11(b), transistors TR6n and TR6p each include a diffusion layer 130g which serves as the gate electrode of transistor TR6n and TR6p, a diffusion layer 130s which serves as the source, a diffusion layer 130d which serves as the drain, and an insulating layer 135 which serves as the gate insulating layer.

[0162] Furthermore, transistors TR6n and TR6p each include a back gate, comprising two conductive layers 132 that serve as the back gate electrodes, a semiconductor layer 130b that forms the channel of the back gate, and two insulating layers 135b that form the gate insulating layer of the back gate.

[0163] As described above, the transistors TR6n and TR6p of the boost circuit BST receive the reference voltage VSS or power supply voltage VDD applied from the bit line LBIy, and the low-level voltage V applied from each of the multiple power supply lines. LW or a high-level voltage V HG The threshold voltage is adjusted to perform on / off operations as appropriate. The back gates included in transistors TR6n and TR6p play a role in adjusting the threshold voltage of these transistors.

[0164] The diffusion layers 130g, 130s, and 130d of transistor TR6n are, for example, polycrystalline silicon layers in which N-type impurities such as phosphorus are diffused. The diffusion layers 130g, 130s, and 130d of transistor TR6p are, for example, polycrystalline silicon layers in which P-type impurities such as boron are diffused. The insulating layers 135 and 135b of transistors TR6n and TR6p are, for example, silicon oxide layers, the conductive layer 132 is, for example, a titanium nitride layer, and the semiconductor layer 130b is, for example, an undoped polycrystalline silicon layer.

[0165] Furthermore, the diffusion layers 130g, 130s, and 130d of transistors TR6n and TR6p cover the side walls of the insulating layer 131, such as a pillar-shaped silicon oxide layer, which extends through multiple layers LR within the multiple layers LR.

[0166] As a result, in the boost circuits BST provided in each of the multiple layers LR, the common transistor TR6n or transistor TR6p is positioned to overlap in the Z direction. That is, the transistor TR included in each of the multiple boost circuits BST 60 The transistors are positioned so that they overlap each other in the Z direction, 61 The transistors are positioned so that they overlap each other in the Z direction, 62 These are positioned so that they overlap each other in the Z direction. This is because they are the same as other transistors TR 63 ~TR 67 The same applies to this case. In this case, the gate electrodes of multiple transistors TR6n and TR6p, which are positioned in overlapping positions in the Z direction, are independent for each layer LR.

[0167] Furthermore, the two conductive layers 132 that form the back gate electrodes extend through multiple layers LR, between the diffusion layers 130s and 130d of transistors TR6n and TR6p. The sidewalls of these pillar-shaped conductive layers 132 are covered by insulating layers 135b within the multiple layers LR. In addition, the semiconductor layer 130b that forms the channel layer of the back gate covers the sidewalls of these insulating layers 135b within the multiple layers LR and is connected to each other on opposing surfaces.

[0168] As a result, in the boost circuit BST provided in each of the multiple layers LR, the back gates included in the multiple transistors TR6n and TR6p are also positioned to overlap each other in the Z direction. In this case, the gate electrodes are shared among the multiple back gates that overlap in the Z direction, while the channel and gate insulating layer are independent.

[0169] Further, an insulating layer 135 serving as a gate insulating layer for transistors TR6n and TR6p is disposed on the surface of a semiconductor layer 130b facing a diffusion layer 130g serving as a gate electrode for transistors TR6n and TR6p. As a result, the gate insulating layers of a plurality of transistors TR6n and TR6p disposed at overlapping positions in the Z direction are also independent for each layer LR.

[0170] As described above, transistors TR6n and TR6p that are stacked in multiple stages in a plurality of layers LR and can be driven independently for each of the plurality of layers LR can be obtained.

[0171] As shown in FIG. 11(c), each of the plurality of wirings WR has a plurality of conductive layers 133 that cover sidewalls of an insulating layer 131 extending through the plurality of layers LR in the plurality of layers LR. The conductive layers 133 disposed in the same layer LR are connected to each other, thereby forming a wiring WR extending in a predetermined direction for each of the plurality of layers LR. When one end of each of these wirings WE is connected to a diffusion layer 130g that is a gate electrode of transistors TR6n and TR6p, a diffusion layer 130s that is a source, or a diffusion layer 130d that is a drain, the plurality of transistors TR6n and TR6p are interconnected to form a booster circuit BST.

[0172] At this time, in the booster circuits BST provided in the plurality of layers LR respectively, the wirings WR at overlapping positions in the Z direction in the common portions are disposed independently of each other.

[0173] As shown in FIG. 11(d), a power supply line PW has a conductive layer 136 such as a titanium nitride layer extending through the plurality of layers LR. That is, in the booster circuits BST provided in the plurality of layers LR respectively, the power supply line PW is provided in common, and the above-described low-level voltage V LW , or a high-level voltage V HG is supplied in a batch.

[0174] Figure 12 is a plan view showing an example of the physical configuration of a boost circuit BST provided in the semiconductor memory device 1 according to the embodiment. Figure 12 shows a boost circuit BST located in any of the multiple layers LR.

[0175] As shown in Figure 12, in order to physically construct the boost converter BST, the circuit layout of the boost converter BST is changed from the example in Figure 5 above so that the sources and drains of the multiple transistors TR6n and TR6p included in the boost converter BST are aligned in a single line in the X direction, in order to facilitate wiring between each part and to efficiently place the boost converter BST in a limited space. Figure 12(b) is a circuit diagram of the boost converter BST with the circuit layout changed in this way, and has an equivalent configuration to the circuit diagram shown in Figure 5 above. Figure 12(a) shows the physical configuration of the boost converter BST with each part arranged to correspond to the circuit layout in Figure 12(b).

[0176] As shown in Figure 12(a), the transistor TR of the boost circuit BST 60 The corresponding transistor TR6n is positioned with its source facing towards the bit line LBIy to which its boost circuit BST is connected, its drain facing away from the bit line LBIy, and its gate facing towards the bit line LBIx to which the bit line LBIy is connected.

[0177] Transistor TR of the boost circuit BST 61 ,TR 62 ,TR 64 ,TR 63 The transistors TR6p, TR6n, TR6n, and TR6p that correspond to these are transistor TR 60 The transistor TR6n corresponding to this is arranged in this order from the bit line LBIy side, on the side away from the bit line LBIy.

[0178] Of these, transistors (TR) 61 ,TR 63The corresponding transistor TR6p is positioned with its source facing towards the bit line LBIy, its drain facing away from the bit line LBIy, and its gate facing the bit line LBIstr to which the bit line LBIy is connected. 62 ,TR 64 The corresponding transistor TR6n is positioned with its drain facing towards the bit line LBIy, its source facing away from the bit line LBIy, and its gate facing the bit line LBIstr to which the bit line LBIy is connected.

[0179] Also, the transistor TR of the boost circuit BST 65 ,TR 66 The transistors TR6p, TR6n, TR6n, and TR6p that correspond to these are transistor TR 63 The transistor TR6p corresponding to this is located further away from the bit line LBIy, and is arranged in this order from the bit line LBIy side.

[0180] Of these, transistors (TR) 65 The corresponding transistor TR6p is positioned with its source facing towards the bit line LBIy, its drain facing away from the bit line LBIy, and its gate facing the bit line LBIx to which the bit line LBIy is connected. 66 The corresponding transistor TR6n is positioned with its drain facing towards the bit line LBIy, its source facing away from the bit line LBIy, and its gate facing the bit line LBIx to which the bit line LBIy is connected.

[0181] Also, the transistor TR of the boost circuit BST 67 The corresponding transistor TR6p is positioned furthest from the bit line LBIy, with its source facing towards the bit line LBIy, its drain facing away from the bit line LBIy, and its gate facing the bit line LBIstr to which the bit line LBIy is connected.

[0182] By connecting the multiple transistors TR6n and TR6p arranged as described above with the aforementioned wiring WR to achieve the wiring configuration shown in Figure 12(b), a boost circuit BST having the circuit layout shown in Figure 12(b) can be obtained.

[0183] In other words, transistor TR 60 The drain of the corresponding transistor TR6n is connected to the side of bit line LBIy that leads to bit line LBIstr, and the source is connected to the side of bit line LBIy that leads to bit line LIBx.

[0184] Also, transistors TR are arranged in a single row in the X direction. 61 ,TR 62 ,TR 64 ,TR 63 ,TR 65 ,TR 66 Connect the sources and drains of the corresponding transistors TR6p, TR6n, TR6n, TR6p, TR6p, TR6n in sequence, and the transistor TR 61 ,TR 63 ,TR 65 The source of the transistor TR6p corresponding to this is connected to the power line PW mentioned above, and the transistor TR 62 ,TR 64 ,TR 66 The drain of the corresponding transistor TR6n is connected to the power line PW and grounded.

[0185] At this time, the transistor TR 61 ,TR 63 ,TR 65 Among them, the transistor TR 61 The transistor TR6p corresponds to a low-level voltage V LW The power line PW that supplies power is connected. Also, the transistor TR 63 ,TR 65 The transistor TR6p corresponds to a high-level voltage V HG The power supply line PW is connected in common.

[0186] Also, transistors (TR) 62 ,TR 64 ,TR66 Among them, the transistor TR 62 ,TR 64 The corresponding transistor TR6n is grounded by a common power line PW, and transistor TR 66 These are grounded by a different power line PW.

[0187] Also, transistors (TR) 60 ,TR 66 The gates of the corresponding transistor TR6n are connected. 61 ,TR 62 ,TR 64 The gates of the corresponding transistors TR6p, TR6n, and TR6n are connected to the side of bit line LBIy that leads to bit line LBIstr. 64 ,TR 63 The sources of the corresponding transistors TR6n and TR6p, and the transistor TTR 65 The gate of the corresponding transistor TR6n is connected to it.

[0188] Also, transistors (TR) 65 ,TR 66 The respective drains of transistors TR6p and TR6n, and transistor TR 63 The gate of the corresponding transistor TR6p is connected. 65 ,TR 66 The drains of the corresponding transistors TR6p and TR6n are, 67 It is also connected to the source of the corresponding transistor TR6p. 67 The drain of the corresponding transistor TR6p is connected to the side of bit line LBIy that leads to bit line LBIx.

[0189] Based on the above, a physical configuration of a boost circuit BST having a circuit configuration equivalent to the boost circuit BST shown in Figure 5 above can be obtained.

[0190] Incidentally, in order to boost the power supply voltage VDD applied from the sense amplifier circuit SA to a predetermined channel layer CN via the bit line BL, it is conceivable to provide a boost circuit BST at either the sense amplifier circuit SA or the bit line BL.

[0191] However, the sense amplifier circuits SA are arranged in parallel in a plane, corresponding to each individual memory string MS. Inserting a boost circuit BST into a sense amplifier circuit SA with such a configuration would increase the area of ​​the sense amplifier module 530, which is undesirable.

[0192] Furthermore, as mentioned above, multiple bit lines BL are arranged at an extremely narrow pitch, for example, below the exposure limit. Therefore, it is difficult to secure enough space around each individual bit line BL to insert a boost circuit BST.

[0193] Therefore, in the semiconductor memory device 1 of the embodiment, a block region R in which a large number of components are densely arranged is present. BLK Outside of the block region R BLK Bit line region R extending in the Y direction from one side in the X direction BL In this configuration, the boost circuit BST is inserted into the bit line LBIy, which has relatively ample space around it.

[0194] Also, block region R BLK and bit line region R BL By utilizing the stacked structure of the component, multiple boost circuits (BSTs) can be stacked in multiple stages, allowing for efficient arrangement of boost circuits (BSTs) corresponding to individual bit lines (LBIy). Furthermore, by arranging the multiple transistors TR6n and TR6p included in the boost circuit (BST) in a single line in the X direction as described above, the block region R BLK bit line region R on one side in the X direction BL They are making effective use of the space.

[0195] [Method for manufacturing a semiconductor memory device] Next, the method for manufacturing the semiconductor memory device 1 according to the embodiment will be described using Figures 13 to 23. Figures 13 to 23 are schematic diagrams illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0196] As detailed below, the method for manufacturing the semiconductor memory device 1 of the embodiment involves the block region R BLK Formation of various structures included and hookup region R HU Formation of contact CCs and other elements included in the bit line region R BL This includes the formation of a boost circuit BST, etc. Note that the order in which these components are formed can be interchanged.

[0197] (Method for forming each part of a block region) First, using Figures 13 to 17, block region R BLK The methods for forming the various components included in this will be explained. In Figures 13 to 17, (Aa) to (Ad) will later be referred to as block region R BLK This is a cross-sectional view along the X direction that includes the portion that is shown, and (Ba) to (Bd) will later be the block region R BLK This is a plan view of any layer LR that includes the part that is shown.

[0198] As shown in Figure 13(Aa)(Ba), multiple insulating layers 102 and multiple insulating layers 101 are stacked alternately, one layer at a time. As described above, insulating layer 102 is a silicon nitride layer, and insulating layer 101 is a silicon oxide layer, etc.

[0199] As shown in Figures 13(Ab) and 13(Bb), multiple slits 185T, 175T, and 165T are formed that penetrate multiple insulating layers 102 and insulating layer 101 and extend in the Y direction. Each of these slits 185T, 175T, and 165T has the same pattern as the insulating layers 185, 175, and 165 described above (see Figure 9, etc.) and is formed spaced apart from each other in the X direction.

[0200] As shown in Figure 13(Ac)(Bc), insulating layers 185, 175, and 165 are formed by filling the slits 185T, 175T, and 165T with silicon oxide layers or the like.

[0201] As shown in Figures 13(Ad) and 13(Bd), multiple holes 120H, 140H, and 161H are formed at positions overlapping with a portion of the insulating layer 165 in the Z direction, penetrating multiple insulating layers 102 and insulating layer 101. These holes 120H, 140H, and 161H are formed at positions corresponding to the word line WL, contact electrode CE, and insulating layer 161 (see Figure 9, etc.), respectively.

[0202] As shown in Figures 14(Aa)(Ba), amorphous silicon layers or the like are filled into multiple holes 120H, 140H, and 161H to form sacrificial layers 120S, 140S, and 161S.

[0203] As shown in Figures 14(Ab) and 14(Bb), multiple holes 181H and 150H are formed in positions overlapping with parts of the insulating layers 185 and 165 in the Z direction, penetrating multiple insulating layers 102 and insulating layer 101, respectively. Parallel to this, multiple holes 171H are formed near one end of the insulating layers 175 and 165 in the Y direction, penetrating multiple insulating layers 102 and insulating layer 101 and aligned in the X direction. These holes 181H, 171H, and 150H are formed in positions corresponding to the insulating layers 181 and 171 and the gate electrode GE (see Figure 9, etc.).

[0204] As shown in Figure 14(Ac)(Bc), amorphous silicon layers or the like are filled into multiple holes 181HH and 171H to form sacrificial layers 181S and 171S.

[0205] As shown in Figures 14(Ad)(Bd), amorphous silicon layers and the like are removed from multiple sacrificial layers 120S to reopen multiple holes 120H.

[0206] As shown in Figures 15(Aa)(Ba), a chemical solution such as hot phosphoric acid is used to remove a portion of the multiple insulating layers 102 through multiple holes 120H, thereby forming multiple gap layers CNG. At this time, in the Y direction, the chemical treatment is controlled so that the multiple gap layers CNG do not reach the formation regions of the sacrificial layers 140S and 161S. In the X direction, the insulating layer 175 prevents the multiple gap layers CNG from expanding further in the X direction.

[0207] As shown in Figures 15(Ab) and (Bb), a channel layer CN is formed by filling multiple gap layers CNG with polycrystalline silicon layers or the like.

[0208] As shown in Figure 15(Ac)(Bc), wet etching or the like is performed through multiple holes 120H to recede the channel layer CN from the sidewall portions of these holes 120H.

[0209] As shown in Figures 15(Ad)(Bd), a block insulating layer BK and a charge storage layer CT are sequentially formed in the recessed portion of the channel layer CN within the multiple holes 120H. The block insulating layer BK is formed by oxidizing the end face of the recessed channel CN, or by filling the recessed portion of the channel layer CN with a silicon oxide layer or the like. The charge storage layer CT is formed by filling the recessed portion of the channel layer CN with a silicon nitride layer or the like via the block insulating layer BK.

[0210] Furthermore, if a chemical vapor deposition (CVD) method is used as described above, a silicon oxide layer and a silicon nitride layer may be formed that cover the entire sidewall of the hole 120H, including the recessed portion of the channel layer CN. In this case, the unnecessary silicon oxide layer and silicon nitride layer can be removed from the end face of the insulating layer 101 exposed on the sidewall of the hole 120H by wet etching or the like. This makes it possible to form a block insulating layer BK and a charge storage layer CT independently at the height of the insulating layer 102.

[0211] As shown in Figures 16(Aa)(Ba), a tunnel insulating layer TN, such as a silicon oxide layer, is formed to cover the side walls of multiple holes 120H. A barrier metal layer 123, such as a titanium nitride layer, is also formed to cover the tunnel insulating layer TN, and a conductive layer 122, such as a tungsten layer, is filled into the remaining voids within the holes 120H. This forms a memory layer ME including a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN, as well as a word line WL including the barrier metal layer 123 and the conductive layer 122.

[0212] As shown in Figure 16(Bb), the amorphous silicon layer and the like within the multiple sacrificial layers 140S are removed, and the multiple holes 140H are opened again.

[0213] As shown in Figure 16(Bc), a semiconductor layer 144, such as a polycrystalline silicon layer, is formed to cover the side walls of multiple holes 140H. Furthermore, a semiconductor layer 140 containing P-type impurities such as boron is formed to cover the semiconductor layer 144, and a conductive layer 142, such as a titanium nitride layer, is filled into the remaining voids within the holes 140H. This forms a contact electrode CE including semiconductor layers 144, 140, and the conductive layer 142.

[0214] As shown in Figure 16(Bd), amorphous silicon layers and the like are removed from multiple sacrificial layers 150S to reopen multiple holes 150H. An insulating layer 155, such as a silicon oxide layer, and a semiconductor layer 150, such as a polycrystalline silicon layer containing N-type impurities such as phosphorus, are formed in this order within the multiple holes 150H, and a conductive layer 152, such as a titanium nitride layer, is filled into the remaining voids within the holes 150H. This forms a gate electrode GE having an insulating layer 155 on its outer periphery that serves as a gate insulating layer, and including the conductive layer 152 and the semiconductor layer 150.

[0215] As shown in Figure 17(Ba), amorphous silicon layers and the like are removed from multiple sacrificial layers 161S to reopen multiple holes 161H. In addition, a portion of the multiple insulating layers 102 is removed through the multiple holes 161H using a chemical solution such as hot phosphoric acid to form multiple gap layers 160G. At this time, in the Y direction, the chemical treatment is controlled so that the multiple gap layers 160G do not extend beyond the Y-direction end of the insulating layer 165. Furthermore, in the X direction, the insulating layer 175 prevents the multiple gap layers 160G from extending further in the X direction.

[0216] As shown in Figure 17(Bb), a semiconductor layer 160 is formed by filling multiple gap layers 160G with polycrystalline silicon layers containing N-type impurities such as phosphorus. In addition, multiple insulating layers 161 are formed by filling multiple holes 161H with silicon oxide layers.

[0217] As shown in Figure 17(Ac)(Bc), the amorphous silicon layers and the like within the multiple sacrificial layers 171S and 181S are removed, and the multiple holes 171H and 181H are opened again.

[0218] As shown in Figures 17(Ad)(Bd), multiple insulating layers 102 are removed through these holes 171H and 181H using a chemical solution such as hot phosphoric acid, and a titanium nitride layer or the like is filled into the resulting gap layer to form bit lines LBIy and LBIx, respectively.

[0219] Subsequently, multiple insulating layers 171 and 181 are formed by filling multiple holes 171H and 181H with silicon oxide layers or the like.

[0220] Based on the above, block region R BLK Various components included are formed.

[0221] (Method for forming contact in the hookup region) Next, using Figures 18 to 20, the hookup region R HUThe method for forming the contact CC included in the following will be explained. In Figures 18 to 20, (Aa) to (Ad) will later be referred to as the hookup region R HU This is a cross-sectional view along the Y direction that includes the portion that is shown, and (Ba) to (Bd) will later be the hookup region R HU This is a cross-sectional view along the X direction, including the portion that is shown.

[0222] As shown in Figure 18(Aa)(Ba), the hookup region R HU In the aforementioned block region R BLK In parallel with this, multiple insulating layers 102 and multiple insulating layers 101 are stacked alternately, one layer at a time.

[0223] As shown in Figures 18(Ab) and 18(Bb), multiple holes 191H are formed that penetrate multiple insulating layers 102 and insulating layer 101 and are aligned along the X direction.

[0224] As shown in Figures 18(Ac)(Bc), wet etching is performed through multiple holes 191H to recede the insulating layer 102 from the sidewall portions of these holes 191H. As a result, the receded portions of the insulating layer 102 protrude in the Y direction from the sidewalls of the multiple holes 191H and are connected to each other in the X direction, forming multiple slits 196T extending along the X direction at the height of each insulating layer 102.

[0225] As shown in Figure 18(Ad)(Bd), multiple conductive layers 196 are formed at the height of each insulating layer 102 by filling multiple slits 196T with titanium nitride layers or the like.

[0226] As shown in Figure 19(Aa)(Ba), multiple silicon oxide layers or the like are filled into multiple holes 191H to form multiple insulating layers 191.

[0227] As shown in Figures 19(Ab) and 19(Bb), multiple insulating layers 102 and 101 are extended in the Z direction in the region between the conductive layer 196 containing multiple insulating layers 191, forming multiple holes CCH with different reach depths. Each of these holes CCH is formed at a location where a contact CC will later be formed. However, the reach depth of these holes CCH is shallower by the length of one pair of insulating layers 102, 101 than the reach depth that the corresponding contact CC will have.

[0228] As shown in Figure 19(Ac)(Bc), wet etching or the like is performed through multiple holes CCH to recede the insulating layer 102 from the sidewall portions of these holes CCH.

[0229] As shown in Figure 19(Ad)(Bd), an insulating layer 195, such as a silicon oxide layer, is formed to cover the side walls and bottom surface of multiple holes CCH, including the recessed portion of the insulating layer 102.

[0230] As shown in Figures 20(Aa)(Ba), multiple holes CCH are added to penetrate the insulating layer 195 on the bottom surface and the insulating layer 101 below it, exposing the insulating layer 102 further below.

[0231] As shown in Figures 20(Ab) and (Bb), the insulating layer 102 exposed on the bottom surface of multiple hole CCHs is retracted to the outside of the hole CCHs by wet etching or the like. At this time, the insulating layer 102 on the upper side through which these hole CCHs penetrate is not removed because it is protected by the insulating layer 195. As a result, multiple hole CCHs with a disc-shaped void at their lower end are formed in the insulating layer 102.

[0232] As shown in Figures 20(Ac)(Bc), a barrier metal layer 193, such as a titanium nitride layer, is formed to cover the side walls and bottom surfaces of multiple holes CCH and to fill the disc-shaped void at the lower end.

[0233] As shown in Figure 20(Ad)(Bd), a conductive layer 192, such as a tungsten layer, is filled into the void remaining in the hole CCH. This forms a contact CC having a conductive layer 192, a barrier metal layer 193, and an insulating layer 195.

[0234] Based on the above, the hookup region R HU Contact CCs are formed within the structure.

[0235] (Method for forming a boost circuit in the bit line region) Next, using Figures 21 to 23, the bit line region R BL The method for forming the boost circuit BST included in this will be explained. In Figures 21 to 23, (Aa) to (Ad) are cross-sectional views along the X direction that include the portion that will later become the transistor TR6p of the boost circuit BST, and (Ba) to (Bd) are plan views of arbitrary layers LR that include the portion that will later become the transistor TR6p.

[0236] Figures 21 to 23 illustrate an example of forming transistor TR6p, in which the power supply line PW is connected to the source and the wiring WR is connected to the drain. Note that transistor TR6n can also be formed in the same way as transistor TR6p, which will be described below, except that the type of impurities diffused into the diffusion layers 130g, 130s, and 130d is different.

[0237] As shown in Figure 21(Aa)(Ba), the bit line region R BL In the aforementioned block region R BLK and hookup region R HU In parallel with this, multiple insulating layers 102 and multiple insulating layers 101 are stacked alternately, one layer at a time.

[0238] Furthermore, two holes 132H are formed that extend in the Z direction, penetrating multiple insulating layers 102 and insulating layer 101, and aligned in the X direction. In parallel with this, holes 131H are formed on both sides of these holes 132H in the X direction, and in the middle portion of these holes 132H in the X direction and at positions aligned in the Y direction, penetrating multiple insulating layers 102 and insulating layer 101, and extending in the Z direction. These holes 132H and 131H will later constitute the transistor TR6p.

[0239] Furthermore, in parallel with the formation of these holes 132H and 131H, a hole 136H is formed extending in the Z direction, penetrating multiple insulating layers 102 and insulating layer 101, further outside the hole 131H on one side in the X direction of the two holes 132H aligned in the X direction, and a plurality of holes 131H are formed extending in the Z direction, penetrating multiple insulating layers 102 and insulating layer 101, further outside the hole 131H on the other side in the X direction of these two holes 132H.

[0240] Hole 136H will later form the power line PW, and multiple holes 131H will later form the wiring WR. Therefore, when forming these multiple holes 131H, the number and arrangement of these holes 131H should be adjusted to match the arrangement of the wiring WR connected to the drain of transistor TR6p.

[0241] As shown in Figures 21(Ab) and (Bb), amorphous silicon layers or the like are filled into the holes 131H and 136H, excluding two holes 132H, from among the multiple holes 132H, 131H, and 136H, to form multiple sacrificial layers 131S and 136S, respectively.

[0242] Furthermore, wet etching or the like is performed through multiple holes 132H to recede the insulating layer 102 from the side walls of these holes 132H. As a result, at the height of the insulating layer 102, multiple holes 13BH are formed that spread outwards in a circular pattern from the side walls of the multiple holes 132H. Note that the holes 13BH surrounding adjacent holes 132H are connected to each other.

[0243] As shown in Figure 21(Ac)(Bc), a polycrystalline silicon layer and a silicon oxide layer are formed in this order in the recessed portion of the insulating layer 102, excluding the hole 132H portion of the multiple holes 13BH, and an independent semiconductor layer 130b and insulating layer 135b are formed for each individual insulating layer 102.

[0244] Furthermore, a conductive layer 132, such as a titanium nitride layer, is filled into the void remaining in the hole 132H. This forms a back gate having a conductive layer 132, an insulating layer 135b, and a semiconductor layer 130b.

[0245] As shown in Figure 21(Bd), the amorphous silicon layer and the like are removed from the sacrificial layer 131S that has been formed in a position aligned with the back gate in the Y direction, thereby reopening one hole 131H.

[0246] As shown in Figure 22(Ba), wet etching or the like is performed through the hole 131H to recede the insulating layer 102 from the side wall portion of the hole 131H. As a result, a hole 13GH is formed at the height of the insulating layer 102, extending in a circular shape from the side wall of the hole 131H outwards.

[0247] As shown in Figure 22(Bb), the sidewall portion of the semiconductor layer 130b exposed on one side in the Y direction of the hole 13GH is oxidized through the hole 13GH. As a result, the polycrystalline silicon layer of the semiconductor layer 130b is oxidized, and an insulating layer 135 such as a silicon oxide layer is formed.

[0248] As shown in Figure 22(Bc), a polycrystalline silicon layer containing P-type impurities such as boron is filled into the recessed portion of the insulating layer 102, excluding the hole 131H portion of the aforementioned hole 13GH, thereby forming an independent diffusion layer 130g for each individual insulating layer 102. In addition, a silicon oxide layer or the like is filled into the remaining voids within the hole 13GH to form the insulating layer 131.

[0249] After forming the gate electrode portion of transistor TR6p as described above, the amorphous silicon layer and the like are removed from the sacrificial layer 131S already formed on both sides of the back gate in the X direction, thereby reopening the two holes 131H.

[0250] As shown in Figures 22(Ac)(Bc), wet etching or the like is performed through these holes 131H to recede the insulating layer 102 from the sidewall portions of these holes 131H. As a result, at the height of the insulating layer 102, holes 13SH and 13DH are formed that extend in a circular pattern outward from the sidewalls of the multiple holes 131H. At this stage, there is no structural difference between these holes 13SH and 13DH, but it is assumed that holes 13SH and 13DH are formed on one side in the X direction of the semiconductor layer 130b, respectively.

[0251] As shown in Figures 22(Ad)(Bd), a polycrystalline silicon layer containing P-type impurities such as boron is filled into the recessed portion of the insulating layer 102, excluding the hole 131H portion of the aforementioned holes 13SH and 13DH, thereby forming independent diffusion layers 130s and 130d for each insulating layer 102. In addition, a silicon oxide layer or the like is filled into the remaining voids within holes 13SH and 13DH to form the insulating layer 131.

[0252] Based on the above, a transistor TR6p, which is a low-voltage P-channel MOSFET, is formed.

[0253] Furthermore, as described above, when forming diffusion layers 130s, 130d, and 130g within holes 13SH, ​​13DH, and 13GH, a low-voltage N-channel MOSFET transistor TR6n can be formed by forming a polycrystalline silicon layer containing N-type impurities such as phosphorus instead of boron.

[0254] Subsequently, the amorphous silicon layer and the like are removed from the sacrificial layer 131S already formed on the X-side of the diffusion layer 130d, thereby reopening multiple holes 131H.

[0255] As shown in Figures 23(Aa)(Ba), wet etching or the like is performed through each of the multiple holes 131H to recede the insulating layer 102 from the side walls of these holes 131H. As a result, at the height of the insulating layer 102, multiple holes 133H are formed that extend in a circular pattern from the side walls of the holes 131H outwards.

[0256] At this time, the pitch of the holes 131H is adjusted in advance so that the holes 133H formed around adjacent holes 131H are connected to each other, and the amount of recession of the insulating layer 102 from the side walls of the holes 131H by wet etching is also adjusted.

[0257] As shown in Figures 23(Ab) and (Bb), a titanium nitride layer or the like is filled into the recessed portion of the insulating layer 102, excluding the hole 131H, to form an independent conductive layer 133 for each insulating layer 102. In addition, a silicon oxide layer or the like is filled into the void remaining in the hole 131H to form an insulating layer 131.

[0258] As a result, a wiring WR can be formed in which multiple conductive layers 133 are connected to each insulating layer 102.

[0259] As shown in Figure 23(Ac)(Bc), the amorphous silicon layer, etc., is removed from the sacrificial layer 136S already formed on the X-side of the diffusion layer 130s to reopen the hole 136H. At this time, the formation position of the hole 136H is adjusted in advance so that one side wall in the X-direction of the hole 136H is in contact with the diffusion layer 130s.

[0260] As shown in Figure 23(Ad)(Bd), by filling the hole 136H with a titanium nitride layer or the like, a power line PW is formed which has a conductive layer 136 that extends in the Z direction, penetrating multiple insulating layers 102 and insulating layer 101.

[0261] Therefore, the bit line region R BL Multiple boost circuits (BSTs) included in the structure are stacked on top of each other in the Z direction to form the structure.

[0262] Furthermore, when forming the boost circuit BST, it is preferable to form the multiple transistors TR6n, TR6p, wiring WR, and multiple holes 131H, 132H, and 136H that constitute the power supply line PW included in the boost circuit BST all at once. This suppresses misalignment between the various parts included in the boost circuit BST, making it possible to form a boost circuit BST with a desired layout.

[0263] As described above, after the formation of the multiple contact CCs, the semiconductor memory device 1 of the embodiment is manufactured by forming multiple bit lines BL connected to them, etc.

[0264] [Summary] In semiconductor memory devices such as 3D non-volatile memory equipped with multiple memory cells, when writing data to a memory cell, a high-level voltage is applied to other memory cells connected to the same word line via the bit line to raise the channel potential. This suppresses data writing to memory cells that are not intended for writing.

[0265] In this case, because the channels of adjacent memory strings are capacitively coupled, there is a problem in that it is difficult to raise the channel potential of memory strings containing memory cells that are not to be written to. If the increase in channel potential is insufficient, program disturbances such as weak write states may occur in memory cells that are not to be written to.

[0266] To sufficiently increase the channel potential, one might consider increasing the voltage of the sense amplifier module. However, increasing the voltage of the sense amplifier module increases the area occupied by the sense amplifier module within the semiconductor memory device, making it difficult to miniaturize the semiconductor memory device.

[0267] Furthermore, in semiconductor memory devices such as three-dimensional non-volatile memory in which channels are stacked in multiple layers, program disturbance can also be suppressed by increasing the thickness of insulating layers, such as silicon oxide layers, interposed between channels. However, increasing the thickness of the multiple stacked insulating layers makes it difficult to miniaturize the semiconductor memory device in this case as well.

[0268] According to the semiconductor memory device 1 of this embodiment, a boost circuit BST is provided in each of the multiple insulating layers 102 and connected to each of the multiple bit lines BL. This allows a high voltage to be applied to memory cells MC that are not to be written to without increasing the voltage of the sense amplifier module 530.

[0269] In the semiconductor memory device 1 of this embodiment, the multiple boost circuits BST are arranged so as to overlap each other in the stacking direction of the multiple insulating layers 102 and the multiple insulating layers 101. This allows for the efficient arrangement of the boost circuits BST provided corresponding to each of the multiple bit lines BL, and reduces the area occupied by the multiple boost circuits BST in the semiconductor memory device 1.

[0270] In the semiconductor memory device 1 of this embodiment, the diffusion layers 130g, 130s, and 130d of each transistor TRn or transistor TR6p included in the multiple boost circuits BST overlap each other in the stacking direction of the multiple insulating layers 102 and multiple insulating layers 101. By arranging the individual components of the multiple boost circuits BST so that they overlap in the Z direction, these boost circuits BST can be arranged to overlap in the Z direction.

[0271] In the semiconductor memory device 1 of this embodiment, the diffusion layers 130g, 130s, and 130d are independently provided within the plurality of insulating layers 102 such that they surround the plurality of insulating layers 102 and the plurality of insulating layer 101 portions with an insulating layer 131 extending in the stacking direction. In this way, by providing independent diffusion layers 130g, 130s, and 130d for each insulating layer 102, using the pillar-shaped insulating layer 131 as a support, it becomes easy to arrange individually operable transistors TRn or transistor TR6p so as to overlap in the Z direction.

[0272] According to the semiconductor memory device 1 of this embodiment, the back gates of transistors TR6n and TR6p each have an insulating layer 135b and a semiconductor layer 130b, which are independently provided within the plurality of insulating layers 102 and the plurality of insulating layers 101, surrounding the conductive layer 132 that extends in the stacking direction of these insulating layers. This makes it easy to arrange transistors TR6n and TR6p, including the back gates, so that they overlap in the Z direction.

[0273] According to the semiconductor memory device 1 of this embodiment, each of the multiple boost circuits BST is connected to the corresponding bit line LBIy. Block region R is provided with multiple channel layers CN. BLK By aligning them in the X direction and connecting them to the bit line LBIy, which has relatively ample space around it, it is possible to secure space for the boost circuit BST without affecting the size of the semiconductor memory device 1.

[0274] According to the semiconductor memory device 1 of this embodiment, the diffusion layers 130s and 130d of multiple transistors TR6n and TR6p, respectively, are arranged in a single row within the corresponding insulating layer 102 of the multiple insulating layers 102, and these rows of diffusion layers 130s and 130d extend in a direction intersecting the extension direction of the bit line LBIy. As a result, a block region R provided with multiple channel layers CN serves as the arrangement space for the boost circuit BST. BLK This allows for efficient use of the space aligned in the X direction.

[0275] According to the semiconductor memory device 1 of this embodiment, among the multiple boost circuits BST, a boost circuit BST connected to the bit line BL corresponding to a memory cell MC that is not to be written to further boosts a voltage higher than the voltage applied to the memory cell MC that is to be written to, and then applies it to the memory cell MC that is not to be written to. This makes it possible to suppress program disturbance in the memory cell MC that is not to be written to.

[0276] [Differentiation] In the above-described embodiment, the boost circuit BST provided in the semiconductor memory device 1 has, for example, the circuit configuration shown in Figure 5. However, as stated above, the circuit configuration of the boost circuit BST is not limited to this. Hereinafter, a semiconductor memory device having a boost circuit BSTA having a different circuit configuration from the above-described boost circuit BST will be described using Figure 24 as a modified example of the embodiment.

[0277] Figure 24 is a circuit diagram showing an example of the configuration of a boost circuit BSTA included in a semiconductor memory device according to a modified embodiment. However, for comparison purposes, Figure 24(a) shows the boost circuit BST of the above-described embodiment again, and Figure 24(b) shows the boost circuit BSTA of the modified embodiment.

[0278] As shown in Figure 24(b), the modified boost circuit BSTA has an additional transistor TR that functions as an inverter, in addition to the configuration of the boost circuit BST of the embodiment described above. 68 ,TR 69 It is equipped with.

[0279] More specifically, the transistor TR 68 The source is connected to a power line, for example, a low-level voltage V LW A voltage is applied. (Transistor TR) 69 The drain is the transistor TR 68 It is connected to the drain of the transistor TR 69 The source is grounded. Transistor TR 68 ,TR 69Each of these gates is connected to the side of bit line LBIy that leads to bit line LBIstr.

[0280] Also, transistors (TR) 66 The gate is a transistor TR 61 ,TR 62 Instead of each drain, the transistor TR 68 ,TR 69 It is connected to each of the drains.

[0281] With this configuration, the modified boost circuit BSTA has an additional transistor TR 68 ,TR 69 Although the circuit length in the X direction is extended, the wiring of the boost circuit BST in the embodiment shown by the arrow in Figure 24(a) can be reduced. Therefore, in the modified boost circuit BSTA, it is possible to shorten the circuit length in the Y direction. The Y direction is the extension direction of the bit line LBIy and is more space-constrained than the X direction, so the configuration of the modified boost circuit BSTA, which allows for even greater space saving, is useful.

[0282] Furthermore, if we consider a cylindrical structure such as individual diffusion layers 130s, 130d formed around the pillar-shaped insulating layer 131, or a semiconductor layer 130b formed around the conductive layer 132, as one pitch, then the transistor TR 68 ,TR 69 The extension of the circuit length in the X direction due to the addition of the individual transistors TR 68 ,TR 69 The distance from the source to the drain is 4 pitches x 2 = 8 pitches + α. On the other hand, if we consider a cylindrical structure such as the conductive layer 133 formed around the pillar-shaped insulating layer 131 as 1 pitch, the reduction in circuit length in the Y direction due to the reduction of one row of wiring WR is 2 pitches + α, which is the space between the reduced wiring WR and other wiring WRs.

[0283] The modified semiconductor memory device also provides the same effects as the embodiments described above.

[0284] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0285] 1... Semiconductor memory device, BST, BSTA... Boost circuit, TR 60 ~TR 69 TR6n, TR6p…transistor, 130d, 130g, 130s…diffusion layer, 130b…semiconductor layer, 132…conductive layer, 101, 102, 135, 135b…insulating layer, 360…sequencer, 530…sense amplifier module, BL, LBIstr, LBIx, LBIy…bit line, CN…channel layer, LR…layer, MC…memory cell, MS…memory string, VDD…power supply voltage, VDDbst…write suppression voltage, VSS…reference voltage, WL…word line.

Claims

1. A laminate in which multiple first insulating layers and multiple second insulating layers are alternately stacked, A plurality of channel layers are provided in each of the plurality of first insulating layers and extend in a first direction along the plurality of first insulating layers, Word lines extending within the laminate in the stacking direction of the laminate and intersecting the plurality of channel layers, Multiple bit lines connected to each of the multiple channel layers, The system comprises a plurality of boost circuits, each provided in the plurality of first insulating layers and connected to each of the plurality of bit lines, Semiconductor memory device.

2. The aforementioned multiple boost circuits are They are arranged so as to overlap each other in the stacking direction, The semiconductor memory device according to claim 1.

3. Each of the aforementioned boost circuits includes a MOSFET having a gate electrode, a source, and a drain. The gate electrodes, sources, and drains of each MOSFET included in the plurality of boost circuits are arranged to overlap each other in the stacking direction. The semiconductor memory device according to claim 2.

4. The gate electrode, the source, and the drain are, The laminate contains an insulating first pillar extending in the lamination direction, Each of the plurality of first insulating layers is independently provided and has a first diffusion layer surrounding the first pillar, The semiconductor memory device according to claim 3.

5. The MOSFET further has a back gate, The aforementioned back gate is Within the laminate, a conductive second pillar extending in the lamination direction, A gate insulating layer is provided independently in the plurality of first insulating layers and surrounds the periphery of the second pillar, The device comprises a semiconductor layer independently provided in the plurality of first insulating layers and surrounding the gate insulating layer. The semiconductor memory device according to claim 3.

6. Each of the aforementioned boost circuits includes a plurality of MOSFETs, The sources and drains of each of the plurality of MOSFETs are arranged in a line within the corresponding first insulating layer among the plurality of first insulating layers. The semiconductor memory device according to claim 1.

7. The plurality of boost circuits are arranged in a position that overlaps with the plurality of channel layers in the first direction. The rows of sources and drains of each of the plurality of MOSFETs extend in the first direction. The semiconductor memory device according to claim 6.

8. A plurality of memory cells are arranged at the respective intersections of the plurality of channel layers and the word lines, The system further comprises a sense amplifier module from which data is read from the plurality of memory cells, Each of the aforementioned plurality of bit lines is Each of the plurality of first insulating layers is provided with a plurality of local bit lines that extend from a position overlapping with the plurality of channel layers in the first direction, in a second direction intersecting the first direction and the stacking direction, The plurality of channel layers and a plurality of global bit lines extending in the second direction, which overlap the stacking direction and electrically connect the plurality of local bit lines and the sense amplifier module, respectively. Each of the above-mentioned multiple boost circuits is Among the plurality of local bit lines, the one connected to the corresponding local bit line is The semiconductor memory device according to claim 1.

9. Each of the aforementioned boost circuits includes a plurality of MOSFETs, The sources and drains of each of the plurality of MOSFETs are arranged in a line within the corresponding first insulating layer among the plurality of first insulating layers. The rows of sources and drains of each of the plurality of MOSFETs extend in a direction intersecting the extension direction of the plurality of local bit lines. The semiconductor memory device according to claim 8.

10. A plurality of memory cells are arranged at the respective intersections of the plurality of channel layers and the word lines, The system further comprises a sequencer that controls the writing of data to the plurality of memory cells, The aforementioned sequencer, A first voltage that allows the writing of data is supplied to the memory cell to be written among the plurality of memory cells, via a first bit line among the plurality of bit lines that is electrically connected to the memory cell to be written. A second voltage, higher than the first voltage, is supplied to the memory cells that are not to be written to among the plurality of memory cells, via a second bit line, which is electrically connected to the memory cells that are not to be written to among the plurality of bit lines, thereby suppressing the writing of the data. Among the plurality of boost circuits, the boost circuit connected to the second bit line further increases the second voltage and applies it to the memory cell that is not to be written to. The semiconductor memory device according to claim 1.

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