Electronic devices and manufacturing methods

Abstract

The present invention provides an electronic device comprising a semiconductor package with terminals through which electric current flows exposed to the outside, a multilayer printed circuit board having a surface conductor layer including a first surface, a back surface conductor layer located on the opposite side of the surface conductor layer, and a plurality of conductive inner layers between the surface conductor layer and the back surface conductor layer, wherein the multilayer printed circuit board further has a pad portion located on the first surface that electrically connects the terminals of the semiconductor package to the surface conductor layer of the first surface and includes a mounting surface on which the semiconductor package on the opposite side of the first surface is mounted, and a plurality of vias located directly below the pad portion that conduct electricity between the surface conductor layer and the plurality of inner layers, and in a plan view from above the surface conductor layer, the total area of ​​the plurality of vias is 6% or more of the total area of ​​the pad portion.

Description

Technical Field

[0002]

[0001] The present invention relates to an electronic device and a manufacturing method.

Background Art

[0002] Patent Document 1 describes that "the printed circuit board includes an insulating layer, and heat dissipation vias penetrating the printed circuit board are formed in both a first region overlapping with an electronic component and a second region outside thereof" (paragraph 0007). [Prior Art Document] [Patent Document] [Patent Document 1] WO 2017 / 094670

Summary of the Invention

[0003] In a first aspect of the present invention, an electronic device is provided. The electronic device includes a semiconductor package having a terminal portion through which current flows and exposed to the outside, a surface conductor layer including a first surface, a back surface conductor layer located on the opposite side of the surface conductor layer, and a multilayer printed wiring board having a plurality of conductive inner layers between the surface conductor layer and the back surface conductor layer. The multilayer printed wiring board further includes a pad portion located on the first surface, electrically connecting the terminal portion of the semiconductor package to the first surface and including a mounting surface on which the semiconductor package on the opposite side of the first surface is mounted, and a plurality of vias located directly below the pad portion and conducting the surface conductor layer and the plurality of inner layers. In a plan view from above the surface conductor layer, the total area of the plurality of vias is 6% or more of the total area of the pad portion.

[0004] In the above electronic device, the multilayer printed wiring board may further include a plurality of other vias located around a region directly below the pad portion and conducting the surface conductor layer and the plurality of inner layers. In the above electronic device, in the plan view, the density of the plurality of vias may be higher than the density of the plurality of other vias.

[0005] In any of the above-described electronic devices, the inner diameter of the plurality of vias may be smaller than the inner diameter of the other plurality of vias.

[0006] In any of the above-described electronic devices, the terminal portion may be coupled to the coupling region on the pad portion. In the above-described electronic device, in the plan view, the plurality of vias may be located in a range that overlaps with the coupling region more often than outside the range.

[0007] In any of the above-described electronic devices, the multilayer printed circuit board may have two or more pad portions, each directly beneath which four or more of the multiple vias are located.

[0008] In any of the above-described electronic devices, the multilayer printed circuit board may have two or more pad portions, each having 20 or more of the multiple vias directly beneath it.

[0009] In any of the above-described electronic devices, the total area of ​​the plurality of vias in the plan view may be 20% or more of the total area of ​​the pad portion.

[0010] In any of the above-described electronic devices, the inner diameter of the plurality of vias may be 0.25 mm or less.

[0011] In any of the above-mentioned electronic devices, the pitch of the plurality of vias in the plan view may be 0.6 mm or less.

[0012] In any of the above-described electronic devices, the terminal portion of the semiconductor package does not need to be exposed from the surface of the semiconductor package facing the multilayer printed circuit board.

[0013] In any of the above-described electronic devices, the pad portion of the multilayer printed circuit board may be located in a position that does not overlap with the package sealing portion of the semiconductor package in the plan view.

[0014] In any of the above-described electronic devices, the plurality of vias may be filled with a non-conductive resin.

[0015] In any of the above-described electronic devices, the plurality of vias may be filled with a conductive resin.

[0016] In any of the above-described electronic devices, the plurality of vias may be filled with solder.

[0017] In any of the above-described electronic devices, the plurality of vias may be uniformly distributed across the entire region directly below the pad portion in a plan view.

[0018] In any of the above electronic devices, the semiconductor package may be a current sensor. In any of the above electronic devices, the semiconductor package may include the terminal portion and have a current conductor portion through which the current flows, a magnetic detection portion that detects the magnetic field generated by the current flowing through the current conductor portion and outputs a detection signal, a signal processing portion that outputs a signal current based on the detection signal, and a sealing portion that seals a part of the current conductor portion, the magnetic detection portion, and the signal processing portion.

[0019] Any of the above-mentioned electronic devices may be a power unit in which the current sensor is mounted on the multilayer printed circuit board including an inverter circuit.

[0020] In any of the above-described electronic devices, in the plan view, the plurality of vias may be distributed biased toward the sealing portion side of the semiconductor package within the region directly below the pad portion.

[0021] In any of the above-described electronic devices, in a plan view, the plurality of vias may be distributed in a biased manner towards the side with a higher current density within the region directly below the pad portion.

[0022] In any of the above-described electronic devices, the plurality of vias may extend from the front surface to the back surface of the multilayer printed wiring board, and may include a plurality of through vias that connect the front surface conductor layer, the plurality of inner layers, and the back surface conductor layer on the back surface.

[0023] In any of the above-described electronic devices, at least two of the plurality of through vias may be directly connected to at least one common back surface conductor layer.

[0024] In any of the above-described electronic devices, the inner wall surfaces of the plurality of through vias and the peripheries of the openings located at both ends in the extending direction of the plurality of through vias may be covered with copper plating.

[0025] In any of the above-described electronic devices, the inner wall surfaces of the plurality of through vias may be covered with copper plating. In any of the above-described electronic devices, the plurality of through vias may be filled with resin, and the openings on the front surface side may be sealed with lid plating.

[0026] In any of the above-described electronic devices, the openings on the back surface side of the plurality of through vias may also be sealed with other lid plating. Any of the above-described electronic devices may further include a heat sink disposed on the lower surface of the other lid plating.

[0027] In any of the above-described electronic devices, the plurality of through vias may be filled with solder, and the openings on the back surface side may be sealed with a heat-resistant member.

[0028] In any of the above-described electronic devices, the multilayer printed wiring board may have two or more of the pad portions. In any of the above-described electronic devices, one heat-resistant member may seal the openings on the back surface side of the plurality of through vias located directly below two or more of the pad portions.

[0029] In any of the above-described electronic devices, the plurality of through vias are filled with solder, and the solder filled in the plurality of through vias may be exposed from the openings on the back side of the plurality of through vias, but may not protrude from the openings.

[0030] In any of the above-described electronic devices, the multilayer printed wiring board may have two or more of the pad portions. In any of the above-described electronic devices, in a direction orthogonal to the direction in which two or more of the pad portions are arranged, the plurality of through vias located directly below the two or more pad portions may be distributed within a range of a width of 5 mm or less.

[0031] A method for manufacturing any of the above-described electronic devices, wherein the pad portion is formed of solder, and applying solder to the first surface in an amount greater than or equal to the sum of the solder forming the pad portion and the solder flowing into and filling the plurality of vias, and reflowing the solder applied to the first surface to fill the plurality of vias with solder and form the pad portion with solder.

[0032] The above manufacturing method may further include preliminarily adjusting the supply amount of solder according to the amount of solder applied to the first surface in a vacuum printing machine capable of supplying solder. In any of the above manufacturing methods, applying solder to the first surface may include supplying solder having a preliminarily adjusted supply amount to the first surface from the vacuum printing machine.

[0033] Any of the above manufacturing methods may include filling the inside of the vias with solder by applying pressure at a preliminarily adjusted pressure in a vacuum printing machine capable of supplying solder before the reflow.

[0034] A method for manufacturing any of the above-described electronic devices, comprising covering the openings on the back side of the plurality of through vias with a heat-resistant member, applying solder to the first surface, and reflowing the solder applied to the first surface to fill the plurality of through vias with solder.

[0035] Any of the above manufacturing methods may further include peeling the heat-resistant member from the back surface after the solder filled into the plurality of through vias has hardened to a predetermined hardness or above, or after a predetermined time has elapsed since the completion of soldering into the plurality of through vias, thereby exposing the solder filled into the plurality of through vias through the openings on the back surface.

[0036] A second aspect of the present invention provides an electronic device. The electronic device comprises a semiconductor package with terminals through which electric current flows exposed to the outside, and a multilayer printed circuit board having a surface conductor layer including a first surface, a back surface located opposite to the surface conductor layer, and a plurality of conductive inner layers between the surface conductor layer and the back surface conductor layer, wherein the multilayer printed circuit board further includes a pad portion located on the first surface, electrically connecting the terminals of the semiconductor package to the first surface, and including a mounting surface on which the semiconductor package is mounted opposite to the first surface, a plurality of vias located directly below the pad portion and providing conductivity between the surface conductor layer and the plurality of inner layers, and a plurality of other vias located around the region directly below the pad portion and providing conductivity between the surface conductor layer and the plurality of inner layers, wherein in a plan view from above the surface, the density of the plurality of vias is higher than the density of the other plurality of vias.

[0037] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0038] [Figure 1] This is a schematic plan view of an example of an electronic device 10. [Figure 2] The semiconductor package 50 of the electronic device 10 shown in Figure 1 is transparent to reveal the multilayer printed circuit board 101. [Figure 3]This is a schematic partial cross-sectional view obtained by virtually cutting a line segment VV' passing through the pad portion 140 of the multilayer printed circuit board 101 shown in Figure 1, when the electronic device 10 is equipped with a multilayer printed circuit board 101 according to the first embodiment. [Figure 4] This is an enlarged view of the dashed frame F shown in Figure 2, where the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 5] This is an enlarged view of the dashed frame F shown in Figure 2, where the electronic device 10 includes a multilayer printed circuit board 102 according to the second embodiment. [Figure 6] This table shows the results obtained by simulation of the maximum temperature rise ΔTmax [°C] of the pad portion 140 when the cooling rate [m / s] is different for each of the multiple via occupancy rates R [%]. [Figure 7] Figure 6 shows four graphs illustrating the relationship between the via occupancy rate R[%] and the maximum temperature rise ΔTmax[°C] of the pad section 140 for each of the four cooling rates shown. [Figure 8] This table shows the results obtained by simulation of the maximum temperature rise ΔTmax [°C] of the pad portion 140 in windless conditions for each of the electronic devices according to the first comparative example, the electronic device according to the second comparative example, the electronic device 10 according to the first embodiment, and the electronic device 10 according to the second embodiment. [Figure 9] This figure corresponds to an enlarged view of the dashed frame F shown in Figure 2, in an electronic device equipped with a multilayer printed circuit board C of the second comparative example. [Figure 10] This graph shows the relationship between the cooling rate [m / s] and the maximum temperature rise ΔTmax [°C] of the pad section 140. [Figure 11] The temperature distribution when the current under test is measured by simulation is shown for the electronic device equipped with the multilayer printed circuit board C of the second comparative example. [Figure 12] The temperature distribution when the current under test is measured by simulation is shown for the electronic device 10 equipped with the multilayer printed circuit board 102 of the second embodiment. [Figure 13]This is an enlarged view of the dashed frame F shown in Figure 2, where the electronic device 10 includes a multilayer printed circuit board 103 according to the third embodiment. [Figure 14] This is an enlarged view of the dashed frame F shown in Figure 2, where the electronic device 10 includes a multilayer printed circuit board 104 according to the fourth embodiment. [Figure 15] The electronic device 10 is equipped with a multilayer printed circuit board 101 according to the first embodiment, and the temperature distribution of the pad portion 140 is shown when the current to be measured is measured by simulation, either with the vias 150 left unfilled or with non-conductive resin filled inside the vias 150. [Figure 16] This table shows the simulation results from multiple examples. [Figure 17] This is an enlarged view of the dashed frame F shown in Figure 2, where the electronic device 10 includes a multilayer printed circuit board 105 according to the fifth embodiment. [Figure 18] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 19] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 20] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 21] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 22] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 23]This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 24] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 25] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 26] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 27] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 101 according to the first embodiment. [Figure 28] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 106 according to the sixth embodiment. [Figure 29] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 106 according to the sixth embodiment. [Figure 30] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 107 when the electronic device 10 includes a multilayer printed circuit board 107 according to the seventh embodiment. [Figure 31] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 107 when the electronic device 10 includes a multilayer printed circuit board 107 according to the seventh embodiment. [Figure 32] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 107 when the electronic device 10 includes a multilayer printed circuit board 107 according to the seventh embodiment. [Figure 33] This is a schematic partial cross-sectional view showing an example of a method for manufacturing a multilayer printed circuit board 107 when the electronic device 10 includes a multilayer printed circuit board 107 according to the seventh embodiment. [Modes for carrying out the invention]

[0039] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0040] Figure 1 is a schematic plan view of an example of an electronic device 10. Figure 2 shows the multilayer printed circuit board 101 through the semiconductor package 50 of the electronic device 10 shown in Figure 1. Figure 3 is a schematic partial cross-sectional view obtained by virtually cutting the line segment VV' passing through the pad portion 140 of the multilayer printed circuit board 101 shown in Figure 1, when the electronic device 10 is equipped with the multilayer printed circuit board 101 according to the first embodiment. Figure 4 is an enlarged view of the dashed frame F shown in Figure 2, when the electronic device 10 is equipped with the multilayer printed circuit board 101 according to the first embodiment.

[0041] Figure 1 shows the mutually orthogonal X, Y, and Z axes. In Figure 1, the X-axis extends horizontally in the plane of the paper, with the right side being the positive X-axis. The Y-axis extends vertically in the plane of the paper, with the top side being the positive Y-axis. The Z-axis extends in the depth direction of the paper, with the front side being the positive Z-axis. Subsequent figures also show axes corresponding to the X, Y, and Z axes shown in Figure 1, and redundant explanations are omitted.

[0042] In the first embodiment, the electronic device 10 comprises a semiconductor package 50 and a multilayer printed circuit board 101. The electronic device 10 may, for example, be a power unit in which a current sensor for detecting the current to be measured, which is the semiconductor package 50, is mounted on a printed circuit board such as the multilayer printed circuit board 101, which includes an inverter circuit. The electronic device 10 may, for example, have resistance-detection type current sensors for detecting current or magnetic field-detection type current sensors for detecting magnetism arranged in current paths connected to each phase of a three-phase AC circuit for supplying drive current to a three-phase motor. In this case, the current paths may be provided in the semiconductor package 50 and the multilayer printed circuit board 101, and the current sensors are built into the semiconductor package 50. The electronic device 10 may also be referred to as a printed circuit board on which a surface-mount type current sensor is mounted. In the following description, for example, the semiconductor package 50 is used as a current sensor, and the current flowing through the terminal portion of the semiconductor package 50, described later, is referred to as the current to be measured.

[0043] As shown in Figure 1, the semiconductor package 50 comprises a package sealing portion 51, a first terminal portion 52, and a second terminal portion 53. The first terminal portion 52 is exposed to the outside from the negative Y-axis side of the package sealing portion 51. The first terminal portion 52 includes a pair of terminals 52A and 52B aligned in the X-axis direction, and the current to be measured flows from one of the pair of terminals 52A and 52B to the other. The current to be measured flowing through the first terminal portion 52 is measured, for example, by the current sensor described above. The first terminal portion 52 may also be referred to as the high-current side terminal. The second terminal portion 53 is exposed to the outside from the positive Y-axis side of the package sealing portion 51. The second terminal portion 53 may also be referred to as the signal side terminal.

[0044] The semiconductor package 50 may be a Large Scale Integration (LSI) package with surface-mount terminals 52A that carry large currents, and heat generation inside the package encapsulation portion 51 can be significant. The heat generated inside the package encapsulation portion 51, which is covered with molded resin, is mainly conducted from the package encapsulation portion 51 to the first terminal portion 52, etc., which is exposed to the outside, that is, the heat is dissipated from the first terminal portion 52, etc.

[0045] The semiconductor package 50 is, for example, a current sensor as described above. The semiconductor package 50, which is a current sensor, may have a current conductor portion 55, a magnetic detection portion 56, a signal processing portion 57, and a sealing portion 58. The current conductor portion 55 may include the first terminal portion 52 and the second terminal portion 53 described above. The current to be measured flows through the current conductor portion 55. The magnetic detection portion 56 detects the magnetic field generated by the current to be measured flowing through the current conductor portion 55 and outputs a detection signal. The signal processing portion 57 outputs a signal current based on the detection signal input from the magnetic detection portion 56. The sealing portion 58 seals a part of the current conductor portion 55, the magnetic detection portion 56, and the signal processing portion 57. In Figure 1, the part of the current conductor portion 55, the magnetic detection portion 56, and the signal processing portion 57 sealed by the sealing portion 58 are schematically shown by dashed lines. The first terminal portion 52 and the second terminal portion 53 described above are the parts exposed to the outside from the sealing portion 58. Furthermore, as shown in Figure 1, a portion of the current conductor portion 55, i.e., the portion sealed by the sealing portion 58, the magnetic detection portion 56, the signal processing portion 57, and the sealing portion 58 may be included in the package sealing portion 51 described above. Note that the internal structure and components of the package sealing portion 51 shown in Figure 1 are merely examples, and the semiconductor package 50, which is a current sensor, may have other internal structures and components in the package sealing portion 51.

[0046] When the semiconductor package 50 is a current sensor, and the first terminal portion 52 is connected to the primary power supply system and the second terminal portion 53 is connected to the secondary power supply system, the first terminal portion 52 and the second terminal portion 53 of the semiconductor package 50 do not need to be exposed from the lower surface of the package sealing portion 51 facing the multilayer printed circuit board 101; that is, they may be completely covered by the sealing portion 58 on that side. This makes it possible to increase the creepage distance between the first terminal portion 52 and the second terminal portion 53, and as a result, the voltage resistance of the semiconductor package 50 can be maintained at a high level. In addition, the pad portion 140 of the multilayer printed circuit board 101 may be located in a position that does not overlap with the package sealing portion 51 of the semiconductor package 50 when viewed from above in a plan view of the multilayer printed circuit board 101.

[0047] As shown in Figure 3, the multilayer printed circuit board 101 has a surface conductor layer 110, a back surface conductor layer 120, a plurality of inner layers 131, a pad portion 140, a plurality of vias 150, and a plurality of peripheral vias 160. The surface conductor layer 110 includes a first surface 111. The back surface conductor layer 120 is located on the opposite side from the surface conductor layer 110. The surface conductor layer 110 and the back surface conductor layer 120 are conductive layers, for example, copper foil layers. The surface conductor layer 110 and the back surface conductor layer 120 may each be composed of conductor layers 115 and 125 and copper plating P1, which are formed by different processing steps, as in the example in Figure 3. Note that the conductor layers 115 and 125 and the copper plating P1 may all be formed of copper and may not be visually distinguishable.

[0048] The multiple inner layers 131 are conductive layers located between the surface conductor layer 110 and the back conductor layer 120, and are, for example, copper foil layers. As shown in Figure 3, the multilayer printed circuit board 101 also has multiple insulating layers 132 that are alternately stacked with the multiple inner layers 131.

[0049] The pad portion 140 is located on the first surface 111 of the surface conductor layer 110. The pad portion 140 electrically connects the first terminal portion 52 of the semiconductor package 50 to the first surface 111. More specifically, the pad portion 140 electrically connects the first terminal portion 52 to the surface conductor layer 110 via solder S. The pad portion 140 also includes the mounting surface 141 on which the semiconductor package 50 is mounted, opposite to the first surface 111 of the surface conductor layer 110.

[0050] In this example, the pad portion 140 is formed by a lid plating P2, for example. The lid plating P2 is, for example, copper plating using copper material.

[0051] As shown in Figures 1 to 4, the multiple vias 150 are located directly below the pad portion 140. In Figure 2, for the sole purpose of clarifying the explanation, the multiple vias 150 located directly below the pad portion 140 are shown by making the pad portion 140 transparent. In subsequent plan views, the multiple vias 150 located directly below the pad portion 140 will also be shown by making the pad portion 140 transparent as appropriate. In the following explanation, the area directly below the pad portion 140 may be referred to as the direct-below region A1. In the example in Figure 3, the direct-below region A1 is shown with a dashed frame. Note that the pad portion 140 does not have vias 150 formed on it, and the pad portion 140 is different from a land on which through-holes are formed.

[0052] Multiple vias 150 provide electrical conductivity between the surface conductor layer 110 and multiple inner layers 131. As shown in Figure 3, for example, the inner wall surface IW of the vias 150 is copper-plated, and the copper plating P1 on the inner wall surface IW provides electrical conductivity between the surface conductor layer 110 and the multiple inner layers 131. More specifically, the copper plating P1 of the multiple vias 150 provides electrical conductivity between the pad portion 140, the surface conductor layer 110, the multiple inner layers 131, and the back surface conductor layer 120.

[0053] Due to the multiple vias 150 located in the region A1 directly below, the heat conducted from inside the package sealing portion 51 of the semiconductor package 50 through the first terminal portion 52, and the current being measured flowing from one of the pair of terminals 52A and 52B of the first terminal portion 52 to the other, are diffused into the surface conductor layer 110, multiple inner layers 131, and back conductor layer 120, which are formed of copper foil or the like with high thermal conductivity and electrical conductivity and have a large area in the XY plane. In other words, in addition to heat being dissipated from the multiple vias 150 toward the negative Z axis, each conductor layer of the multilayer printed circuit board 101 acts as a heat sink, and heat is diffused in the XY plane direction in each of the surface conductor layer 110, back conductor layer 120, and multiple inner layers 131, and ultimately the heat can be dissipated into the atmosphere via the surface conductor layer 110 and back conductor layer 120. Furthermore, since the current being measured flows through these multiple current paths, Joule heating can be suppressed.

[0054] As shown in Figure 3, the multiple vias 150 extend from the front to the back surface of the multilayer printed circuit board 101 and may include multiple through-vias that connect the front conductor layer 110, the multiple inner layers 131, and the back conductor layer 120, or they may not include through-vias. Non-through-vias, i.e., blind vias, require careful consideration of the via depth to avoid penetrating the substrate when forming the vias, but through-vias do not require such care, making them easier to manufacture than non-through-vias. Furthermore, through-vias are easier to manufacture than non-through-vias because the air inside is easily pushed out when filling them with resin paste or the like.

[0055] Hereafter, for the sake of brevity, each via 150 will be described as a through via, and the through via will be simply referred to as via 150. Of the multiple vias 150, at least two adjacent vias 150 may be directly connected to at least one common back conductor layer 120, thereby enabling the electrical connection of these at least two vias 150 and the multiple spaced-apart inner layers 131 via the common back conductor layer 120.

[0056] As shown in Figure 3, the via 150, which is a through via, is covered not only on its inner wall surface IW but also around the openings AP located at both ends in the direction of extension of the via 150, i.e., in the Z-axis direction, with copper plating P1. Therefore, copper plating P1 covering the openings AP on the positive Z-axis side of the via 150 can be interposed between the conductor layer 115 on the surface side of the multilayer printed circuit board 101 and the pad portion 140 located directly above the via 150. As described above, the conductor layer 115 and copper plating P1 on the surface side of the multilayer printed circuit board 101 may be collectively referred to as the surface conductor layer 110. Similarly, the copper plating P1 covering the openings AP on the negative Z-axis side of the via 150 and the conductor layer 125 on the back side of the multilayer printed circuit board 101 may be collectively referred to as the back conductor layer 120.

[0057] Multiple vias 150 may not have anything filling the central axis side of the copper plating P1 on the inner wall surface IW, i.e., they may be hollow, and instead, they may be filled with resin R, solder S, copper, etc. The resin R may be non-conductive or conductive. In the first embodiment, multiple vias 150 are filled with non-conductive resin R. Multiple vias 150 filled with resin R have their openings AP on the surface side of the multilayer printed circuit board 101 sealed with pad portions 140, i.e., with lid plating P2.

[0058] In a plan view from above the surface conductor layer 110, that is, in the XY plane, the total area of ​​the multiple vias 150 is 6% or more of the total area of ​​the pad portion 140. In other words, the ratio R[%] of the total area of ​​the multiple vias 150 to the total area of ​​the pad portion 140 in the said plan view, i.e., the via occupancy rate R[%], is 6[%] or more. To put it another way, the multiple vias 150 located directly below one pad portion 140 have a total area that occupies 6% or more of the area of ​​the pad portion 140 in the said plan view. To put it another way, in the multilayer printed circuit board 101, the multiple vias 150 are formed such that the occupied area of ​​one pad portion 140 is 6% or more in the said plan view. In the following explanation, the plan view from above the surface conductor layer 110 will simply be referred to as the plan view.

[0059] An electronic device 10 equipped with a multilayer printed circuit board 101 that satisfies these area ratio conditions can effectively cool the pad portion 140, which is affected by the heat conducted from inside the package sealing portion 51 of the semiconductor package 50 through the first terminal portion 52, via a plurality of vias 150, as will be described in more detail later.

[0060] Furthermore, considering the definition of the total area of ​​the vias 150 directly below the pad portion 140, the structural upper limit of this total area is 100%. The upper limit of the ratio of the total area of ​​the multiple vias 150 to the total area of ​​the pad portion 140 can be arbitrarily set to less than 100%, depending on the specifications designed considering the magnitude of electrical resistance in the multilayer printed circuit board 101, which correlates with the change in this ratio. Furthermore, the total area of ​​the pad portion 140 in a plan view may be defined by the area of ​​the cover plating P2 or metal foil in a plan view, if the pad portion 140 is formed by cover plating P2 or metal foil. The total area of ​​the pad portion 140 in a plan view may also be the total area of ​​the cover plating P2. In other cases, the total area of ​​the pad portion 140 in plan view may refer to the total area obtained by adding the area of ​​the region where the first terminal portion 52 through which the current to be measured flows is connected to the pad portion 140 via solder S, and where the first terminal portion 52 and the pad portion 140 overlap, plus the area of ​​the fillet portion of the solder S located around that region. The overlapping region corresponds to the connection region A2 described later.

[0061] Assuming that the conditions for such area ratios are met, the multilayer printed circuit board 101, etc. according to each embodiment may be defined, for example, as having two or more pad portions 140 in which four or more vias 150 are located directly beneath them. Another example of the multilayer printed circuit board 101, etc. according to each embodiment may be defined as having two or more pad portions 140 in which 20 or more vias 150 are located directly beneath them. If the electronic device 10 is a power unit that controls a three-phase motor, it measures the current under test for at least two phases of the three-phase AC circuit, so the multilayer printed circuit board 101, etc. will have four or more such pad portions 140.

[0062] Here, we assume that the dimensions of the pad portion 140 in the XY plane are 4.6 mm in the X-axis direction and 1.4 mm in the Y-axis direction. For example, if the inner diameter D of the via 150, i.e., the diameter Φ of the circle in the XY plane, is approximately 0.38 mm, then at least four vias 150 are located directly below each pad portion 140 in order to satisfy the area ratio condition described above. For example, if the inner diameter D of the via 150 is approximately 0.25 mm, then at least nine vias 150 are located directly below each pad portion 140 in order to satisfy the area ratio condition described above.

[0063] In the first embodiment, as an example, the multilayer printed circuit board 101 has 3 × 8 = 24 vias 150 formed in the area A1 directly below the pad portion 140 of the above dimensions, as shown in Figures 2 and 4. In other embodiments, the electronic device 10 may be equipped with multilayer printed circuit boards 102, 103, 104, 105, 106, 107, etc., instead of the multilayer printed circuit board 101. These multilayer printed circuit boards 101, etc., are merely examples, and the electronic device 10 may be equipped with other multilayer printed circuit boards similar to the multilayer printed circuit boards 101, etc. Figure 5 is an enlarged view of the dashed frame F shown in Figure 2, when the electronic device 10 is equipped with a multilayer printed circuit board 102 according to the second embodiment. In the second embodiment, as an example, the multilayer printed circuit board 102 has 5 × 16 = 80 vias 150 formed in the area A1 directly below the pad portion 140 of the above dimensions, as shown in Figure 5.

[0064] The inner diameter D of the multiple vias 150 may be 0.25 mm or less. In the multilayer printed circuit board 101 according to the first embodiment, for example, the inner diameter D of the multiple vias 150 is 0.25 mm. In the multilayer printed circuit board 102 according to the second embodiment, for example, the inner diameter D of the multiple vias 150 is 0.15 mm. By reducing the inner diameter D of the multiple vias 150, the number of vias 150 that can be formed per unit area can be increased, and the heat generation in the vias 150 through which the measured current flows, such as copper plating P1, can be kept to a minimum. For example, a drill bit is used to form the holes that make up the vias 150, and the smallest diameter of a drill bit known at the time of filing this application is 0.15 mm. Alternatively, for example, it is possible to form the holes with an inner diameter D of 0.1 mm or less by laser processing, but the processing cost will be relatively high.

[0065] In a plan view, the pitch L of the multiple vias 150 may be 0.6 mm or less. In the multilayer printed circuit board 101 according to the first embodiment, as an example, the pitch L of the multiple vias 150 with an inner diameter D = 0.25 mm formed in the region A1 directly below the pad portion 140 of the above dimensions is 0.58 mm. In the multilayer printed circuit board 102 according to the second embodiment, as an example, the pitch L of the multiple vias 150 with an inner diameter D = 0.15 mm formed in the region A1 directly below the pad portion 140 of the above dimensions is 0.29 mm. By reducing the pitch L of the multiple vias 150, the number of vias 150 that can be formed per unit area can be increased, and the heat generation in the vias 150 through which the measured current flows, such as copper plating P1, can be kept to a minimum.

[0066] As shown in Figures 1, 2, 4, and 5, the multiple peripheral vias 160 are located around the region A1 directly below the pad portion 140. The multiple peripheral vias 160 provide electrical conductivity between the surface conductor layer 115 and the multiple inner layers 131. Each peripheral via 160 may have the same configuration and dimensions as the via 150, or it may have a different configuration and dimensions from the via 150, and redundant explanations are omitted. For example, the inner diameter D of the multiple vias 150 may be smaller than the inner diameter of the multiple peripheral vias 160. Note that the multiple peripheral vias 160 are just one example of other multiple vias.

[0067] As shown in Figures 1, 2, 4, and 5, in a plan view, the density of multiple vias 150 is higher than the density of multiple surrounding vias 160. In other words, in a plan view, the number of multiple vias 150 per unit area is greater than the number of multiple surrounding vias 160 per unit area. As mentioned above, increasing the via density can further reduce heat generation, but this also increases the via formation time. Therefore, it may be advantageous in terms of production efficiency to concentrate via formation in the region A1 directly below, where the temperature reduction effect is highest, and to reduce the via density as much as possible in areas other than the region A1 directly below.

[0068] Figure 6 is a table showing the results obtained by simulation of the maximum temperature rise ΔTmax [°C] of the pad portion 140 when the cooling rate [m / s] is different for each of the multiple via occupancy rates R [%].

[0069] In each simulation described from Figure 6 onward, the dimensions of the pad portion 140 in the XY plane are set to 4.6 mm in the X-axis direction and 1.4 mm in the Y-axis direction, and the thickness of the copper plating P1 on the inner wall surface IW is set to 0.0175 mm. Further explanations will be omitted. In each simulation described from Figure 6 onward, unless otherwise specified, the vias 150 and surrounding vias 160 are assumed to be either not filled with resin or filled with non-conductive resin. The cooling rate [m / s] mentioned above is the airflow velocity [m / s] when a fan blows air in the Y-axis direction to cool the mounting surface 141 of the multilayer printed circuit board 101, etc. The same applies hereafter, and further explanations will be omitted.

[0070] In the 8x5 table shown in Figure 6, the second to fifth columns of the first row represent multiple cooling rates, with the second column showing 0.0 m / s, the third column 0.5 m / s, the fourth column 1.0 m / s, and the fifth column 2.5 m / s. The second to eighth rows of the first column of the table represent multiple via occupancy rates R, with the second row showing 0%, the third row 3.05%, the fourth row 6.86%, the fifth row 11.40%, the sixth row 16%, the seventh row 18%, and the eighth row 22%.

[0071] A via occupancy rate R=0% means that no vias 150 are placed in the region A1 directly below it. A via occupancy rate R=3.05% means that there are 2 x 2 = 4 vias 150 with inner diameter D=0.25 in the region A1 directly below it. A via occupancy rate R=6.86% means that there are 3 x 3 = 9 vias 150 with inner diameter D=0.25 in the region A1 directly below it. A via occupancy rate R=11.4% means that there are 5 x 3 = 15 vias 150 with inner diameter D=0.25 in the region A1 directly below it. A via occupancy rate R=16% means that there are 7 x 3 = 21 vias 150 with inner diameter D=0.25 in the region A1 directly below it.

[0072] A via occupancy rate R=18% means that, for example, 8 × 3 = 24 vias 150 with an inner diameter D=0.25 are arranged in the region A1 directly beneath the via. In other words, a via occupancy rate R=18% corresponds to the simulation result for an electronic device 10 equipped with a multilayer printed circuit board 101 according to the first embodiment. A via occupancy rate R=22% means that, for example, 5 × 16 = 80 vias 150 with an inner diameter D=0.15 are arranged in the region A1 directly beneath the via. In other words, a via occupancy rate R=22% corresponds to the simulation result for an electronic device 10 equipped with a multilayer printed circuit board 102 according to the second embodiment.

[0073] In the 8x5 table shown in Figure 6, columns 2 through 4 show the simulation results for the maximum temperature rise ΔTmax [°C] of the pad section 140 for each via occupancy rate R, with rows 2 through 8 representing the simulation results for each of the multiple cooling rates.

[0074] Figure 7 shows four graphs illustrating the relationship between via occupancy rate R[%] and the maximum temperature rise ΔTmax[°C] of the pad section 140 for each of the four cooling rates shown in Figure 6. In Figure 7, the horizontal axis represents via occupancy rate R[%], and the vertical axis represents the maximum temperature rise ΔTmax[°C] of the pad section 140.

[0075] As shown in the simulation results in Figures 6 and 7, it can be seen that the slope of the maximum temperature rise ΔTmax changes significantly around a via occupancy rate R = 6.86% under all airflow conditions. Furthermore, it can be seen that when the via occupancy rate R is 6.86% or higher, even under airless conditions where no cooling air is being blown onto the electronic device 10, the maximum temperature rise ΔTmax in the pad portion 140, which has a temperature distribution due to the heat from the semiconductor package 50, can be reduced by 20.1°C or more compared to the case where no vias 150 are formed in the region A1 directly below it. Additionally, it can be seen that ΔTmax can be reduced by 18.5°C or more when the cooling rate is 0.5 m / s, by 16.3°C or more when the cooling rate is 1.0 m / s, and by 14.6°C or more when the cooling rate is 2.5 m / s.

[0076] According to the simulation results shown in Figures 6 and 7, it is understood that the electronic device 10, which includes a multilayer printed circuit board 101 according to the first embodiment with a via occupancy rate R of 18%, can reduce ΔTmax by 24.8°C even under windless conditions.

[0077] As described above, in the multilayer printed circuit board 102 according to the second embodiment, the via occupancy rate R is 22%. As in the multilayer printed circuit board 102 according to the second embodiment, the total area of ​​the multiple vias 150 may be 20% or more of the total area of ​​the pad portion 140 in a plan view. According to the simulation results shown in Figures 6 and 7, it is understood that the electronic device 10 equipped with the multilayer printed circuit board 102 according to the second embodiment can reduce ΔTmax by 32.4°C even under windless conditions. Furthermore, it is understood that ΔTmax can be reduced by 28.7°C when the cooling rate is 0.5 m / s, by 25.2°C when the cooling rate is 1.0 m / s, and by 22.5°C when the cooling rate is 2.5 m / s.

[0078] Figure 8 is a table showing the results of simulations for the maximum temperature rise ΔTmax [°C] of the pad portion 140 in windless conditions for each of the electronic devices according to the first comparative example, the electronic device according to the second comparative example, the electronic device 10 according to the first embodiment, and the electronic device 10 according to the second embodiment. In the 5x2 table shown in Figure 8, the first row is labeled ΔTmax [°C] in windless conditions, and the first column is labeled as follows: the second row is labeled First Comparative Example, the third row is labeled Second Comparative Example, the fourth row is labeled First Embodiment, and the fifth row is labeled Second Embodiment. The first comparative example represents a configuration in which no vias 150 are placed in the region A1 directly below, i.e., via occupancy rate R = 0%, and corresponds to the first and second columns of the second row of the table in Figure 6.

[0079] Figure 9 is a diagram corresponding to an enlarged view of the dashed frame F shown in Figure 2, in an electronic device equipped with a multilayer printed circuit board C of the second comparative example. In the multilayer printed circuit board C of the second comparative example, 1 × 3 = 3 peripheral vias 160 are formed in the region A1 directly below the pad portion 140 of the above dimensions in each embodiment. More specifically, in the multilayer printed circuit board C of the second comparative example, peripheral vias 160 are formed in the region A1 directly below, similar to the region around the region A1, and multiple peripheral vias 160 are uniformly formed at the same density in the region A1 directly below and the region around the region A1 directly below. In the multilayer printed circuit board C of the second comparative example, the via occupancy rate R due to the peripheral vias 160 in the region A1 directly below is less than 6%.

[0080] Figure 10 is a graph showing the relationship between the cooling rate [m / s] and the maximum temperature rise ΔTmax [°C] of the pad portion 140. In Figure 10, the horizontal axis represents the cooling rate [m / s], and the vertical axis represents the maximum temperature rise ΔTmax [°C] of the pad portion 140. Figure 10 shows graphs plotting ΔTmax at 0.5 m / s intervals from a cooling rate of 0.0 m / s to a cooling rate of 2.5 m / s under windless conditions for each of the second comparative example, the first example, and the second example shown in Figure 8.

[0081] According to the simulation results in Figures 8 and 10, it is understood that, compared to the ΔTmax of the electronic device equipped with the multilayer printed circuit board C according to the second comparative example, the electronic device 10 equipped with the multilayer printed circuit board 101 according to the first embodiment can achieve a ΔTmax that is 10.5°C lower, even under windless conditions. Compared to the ΔTmax of the electronic device equipped with the multilayer printed circuit board C according to the second comparative example, it is understood that, even under windless conditions, the electronic device 10 equipped with the multilayer printed circuit board 102 according to the second embodiment can achieve a ΔTmax that is 18.1°C lower.

[0082] Figure 11 shows the temperature distribution when the current under test is measured by simulation in an electronic device equipped with a multilayer printed circuit board C of the second comparative example. Figure 12 shows the temperature distribution when the current under test is measured by simulation in an electronic device 10 equipped with a multilayer printed circuit board 102 of the second embodiment. In Figures 11 and 12, the temperature distribution is shown by the intensity of the color, with darker colors indicating higher temperatures. In Figures 11 and 12, the multilayer printed circuit boards C and 102 are not located on the terminal 52A side of the first terminal section 52, and only the structure of via 150 and peripheral via 160 is shown.

[0083] In the second comparative example shown in Figure 11, the first terminal section 52 is generally hot, and the multilayer printed circuit board C located on the terminal 52B side of the first terminal section 52 is cooler the further it is from terminal 52B. In the second embodiment shown in Figure 12, the terminal 52B side of the first terminal section 52 is cooler the further it is from terminal 52A, and the multilayer printed circuit board 102 located on the terminal 52B side of the first terminal section 52 is also cooler the further it is from terminal 52B. Comparing Figure 11 and Figure 12, it can be seen that the pad section 140 to which terminal 52B is connected is cooled more effectively in the second embodiment shown in Figure 12 than in the second comparative example shown in Figure 11. Furthermore, according to the temperature distribution at terminal 52B in Figure 12, it can be seen that the current density of the measured current flowing from one terminal 52A to the other of the pair of terminals 52A and 52B is relatively higher on the inside where the pair of terminals 52A and 52B face each other, resulting in a higher temperature on the inside than on the outside.

[0084] As explained above, the semiconductor package 50 in the electronic device 10 may be an LSI package having surface-mount terminals 52A that carry large currents, which can cause significant heat generation inside the package encapsulation portion 51. The heat conducted from inside the package encapsulation portion 51 through the first terminal portion 52 can cause the pad portion 140 of the multilayer printed circuit board 101 to rise in temperature. In the electronic device 10 of this example, multiple vias 150 are placed directly below the pad portion 140, and these multiple vias 150 have a via occupancy rate R of 6% or more relative to the pad portion 140. As a result, the electronic device 10 of this example can effectively cool the pad portion 140 that is rising in temperature via the multiple vias 150. Consequently, the range of currents that can flow through the multilayer printed circuit board 101 can be expanded, making it possible to miniaturize the multilayer printed circuit board 101 while maintaining high cooling efficiency, and to make it inexpensive. Furthermore, the high cooling efficiency reduces the energy required for cooling, enabling energy savings in the electronic device 10, and also allowing for quieter operation when using cooling devices such as cooling fans.

[0085] In the multilayer printed circuit board 101 according to the first embodiment and the multilayer printed circuit board 102 according to the second embodiment described above, as an example, as shown in Figures 2, 4, and 5, the multiple vias 150 are uniformly distributed over the entire region A1 directly below the pad portion 140 in a plan view. Alternatively, the multiple vias 150 do not have to be uniformly distributed over the entire region A1 directly below the pad portion 140 in a plan view.

[0086] Figure 13 is an enlarged view of the dashed frame F shown in Figure 2, when the electronic device 10 is equipped with a multilayer printed circuit board 103 according to the third embodiment. In the multilayer printed circuit board 103 according to the third embodiment, unlike the multilayer printed circuit board 101 according to the first embodiment, in a plan view, the multiple vias 150 are distributed biased toward the side with a higher current density of the current under measurement in the region A1 directly below the pad portion 140. That is, the multiple vias 150 located in the region A1 directly below one pad portion 140 are arranged at a higher density as they approach the side of the other pad portion 140 in the X-axis direction. Other configurations in the multilayer printed circuit board 103 according to the third embodiment are the same as the corresponding configurations in the multilayer printed circuit board 101 according to the first embodiment, so the same reference numbers are used and redundant explanations are omitted.

[0087] Figure 14 is an enlarged view of the dashed frame F shown in Figure 2, when the electronic device 10 is equipped with a multilayer printed circuit board 104 according to the fourth embodiment. In the multilayer printed circuit board 104 according to the fourth embodiment, unlike the multilayer printed circuit board 101 according to the first embodiment, in a plan view, the multiple vias 150 are distributed biased toward the sealing portion 58 side of the semiconductor package 50 in the region A1 directly below the pad portion 140. That is, the multiple vias 150 located in the region A1 directly below the pad portion 140 are arranged at a higher density as they approach the semiconductor package 50 side in the Y-axis direction. This arrangement is sometimes referred to as being closer to the standoff. Other configurations in the multilayer printed circuit board 104 according to the fourth embodiment are the same as the corresponding configurations in the multilayer printed circuit board 101 according to the first embodiment, so the same reference numbers are used and redundant explanations are omitted. Note that in Figure 14, the sealing portion 58 located at the top of the page of Figure 14 is not shown.

[0088] Figure 15 shows the temperature distribution of the pad portion 140 when the current to be measured is measured by simulation, in a case where the electronic device 10 is equipped with a multilayer printed circuit board 101 according to the first embodiment, and the vias 150 are left unfilled or filled with non-conductive resin. In Figure 15, the temperature distribution is shown by the intensity of the color, with darker colors indicating higher temperatures.

[0089] The lower part of Figure 15 shows the results obtained by simulation of the maximum temperature rise ΔTmax [°C], minimum temperature rise ΔTmin [°C], and average temperature rise ΔTave [°C] in the pad portion 140. As shown in Figure 15, in this example, ΔTmax = 62.8°C, ΔTmin = 59.7°C, and ΔTave = 62.0°C.

[0090] Figure 16 is a table showing the simulation results for multiple embodiments. In the table in Figure 16, the first row lists the item names, specifically the presence or absence of filling in via 150 and / or the name of the filling material in the second column, ΔTmax in the third column, ΔTmin in the fourth column, and ΔTave in the fifth column. The first column lists the embodiment numbers, specifically the first embodiment in the second, fifth, and eighth rows, the third embodiment in the third, sixth, and ninth rows, and the fourth embodiment in the fourth, seventh, and tenth rows.

[0091] When the electronic device 10 is equipped with a multilayer printed circuit board 103 according to the third embodiment, and the vias 150 are left unfilled or filled with non-conductive resin, the temperature distribution of the pad portion 140 when the current to be measured is measured by simulation shows a similar trend to the temperature distribution shown in Figure 15. The simulation results for this example are shown in the third row of the table in Figure 16. In this example, ΔTmax = 63.9°C, ΔTmin = 61.2°C, and ΔTave = 63.3°C.

[0092] When the electronic device 10 is equipped with a multilayer printed circuit board 104 according to the fourth embodiment, and the vias 150 are left unfilled or filled with non-conductive resin, the temperature distribution of the pad portion 140 when the current to be measured is measured by simulation shows a similar trend to the temperature distribution shown in Figure 15. The simulation results for this example are shown in the fourth row of the table in Figure 16. In this example, ΔTmax = 63.3°C, ΔTmin = 60.4°C, and ΔTave = 62.5°C.

[0093] When the via 150 is left unfilled or filled with a non-conductive resin, heat conduction in the via 150 occurs mainly through the copper plating P1 on the inner wall surface IW. Comparing the simulation results of each embodiment shown in the second to fourth rows of Figure 16 for the cases where the via 150 is left unfilled or filled with a non-conductive resin, it can be seen that in the first embodiment, ΔTmax is 0.5°C lower than in the fourth embodiment and ΔTmax is 1.1°C lower than in the third embodiment.

[0094] When the electronic device 10 is equipped with a multilayer printed circuit board 101 according to the first embodiment and solder S is filled into the vias 150, the temperature distribution of the pad portion 140 when the current under test is measured by simulation also shows a similar trend to the temperature distribution shown in Figure 15. The simulation results for this example are shown in the fifth row of the table in Figure 16. In this example, ΔTmax = 60.8°C, ΔTmin = 58.0°C, and ΔTave = 60.1°C.

[0095] When the electronic device 10 is equipped with a multilayer printed circuit board 103 according to the third embodiment and solder S is filled into the vias 150, the temperature distribution of the pad portion 140 when the current under test is measured by simulation also shows a similar trend to the temperature distribution shown in Figure 15. The simulation results for this example are shown in the 6th row of the table in Figure 16. In this example, ΔTmax = 61.9°C, ΔTmin = 59.4°C, and ΔTave = 61.3°C.

[0096] When the electronic device 10 is equipped with a multilayer printed circuit board 104 according to the fourth embodiment and solder S is filled into the vias 150, the temperature distribution of the pad portion 140 when the current under test is measured by simulation also shows a similar trend to the temperature distribution shown in Figure 15. The simulation results for this example are shown in the 7th row of the table in Figure 16. In this example, ΔTmax = 61.3°C, ΔTmin = 58.6°C, and ΔTave = 60.6°C.

[0097] When solder S is filled into via 150, heat conduction in via 150 occurs mainly through the copper plating P1 on the inner wall surface IW and the filled solder S. Comparing the simulation results of each embodiment shown in rows 5 to 7 of Figure 16 when solder S is filled into via 150, it can be seen that in the first embodiment, ΔTmax is 0.5°C lower than in the fourth embodiment and ΔTmax is 1.1°C lower than in the third embodiment.

[0098] When the electronic device 10 is equipped with a multilayer printed circuit board 101 according to the first embodiment and copper is filled in the vias 150, the temperature distribution of the pad portion 140 when the current to be measured is measured by simulation also shows a similar trend to the temperature distribution shown in Figure 15. The simulation results for this example are shown in the 8th row of the table in Figure 16. In this example, ΔTmax = 57.4℃, ΔTmin = 54.9℃, and ΔTave = 56.7℃.

[0099] When the electronic device 10 is equipped with a multilayer printed circuit board 103 according to the third embodiment and copper is filled in the vias 150, the temperature distribution of the pad portion 140 when the current to be measured is measured by simulation also shows a similar trend to the temperature distribution shown in Figure 15. The simulation results for this example are shown in the 9th row of the table in Figure 16. In this example, ΔTmax = 58.5℃, ΔTmin = 56.3℃, and ΔTave = 57.9℃.

[0100] When the electronic device 10 is equipped with a multilayer printed circuit board 104 according to the fourth embodiment and copper is filled in the vias 150, the temperature distribution of the pad portion 140 when the current under test is measured by simulation also shows a similar trend to the temperature distribution shown in Figure 15. The simulation results for this example are shown in the 10th row of the table in Figure 16. In this example, ΔTmax = 58.2°C, ΔTmin = 56.3°C, and ΔTave = 57.8°C.

[0101] When copper is packed inside via 150, heat conduction in via 150 occurs mainly through the copper plating P1 on the inner wall surface IW and the packed copper. Comparing the simulation results of each embodiment shown in rows 8 to 10 of Figure 16 when copper is packed inside via 150, it can be seen that in the first embodiment, ΔTmax is 0.8°C lower than in the fourth embodiment and ΔTmax is 1.1°C lower than in the third embodiment.

[0102] Based on the above multiple simulation results, it is understood that for the multilayer printed circuit board 101 of the first embodiment, when solder S is filled into the via 150, the ΔTmax is 2.0°C lower compared to when the via 150 is left unfilled or when non-conductive resin is filled into the via 150. It is also understood that when copper is filled into the via 150, the ΔTmax is 5.4°C lower compared to when the via 150 is left unfilled or when non-conductive resin is filled into the via 150.

[0103] Furthermore, it is understood that if the number and dimensions of the multiple vias 150 placed in the area A1 directly below are the same, there will be no significant difference in heat dissipation in the pad portion 140. In particular, it is understood that when the multiple vias 150 are uniformly distributed across the entire area A1 directly below in a plan view, as in the multilayer printed circuit board 101 of the first embodiment, the heat dissipation is slightly better than when the multiple vias 150 are unevenly distributed within the area A1 directly below in a plan view, as in the multilayer printed circuit board 103 of the third embodiment and the multilayer printed circuit board 104 of the fourth embodiment.

[0104] Furthermore, it is understood that when a highly thermally conductive material is filled into a via 150 with copper plating P1 on its inner wall surface IW, the temperature rise in the pad portion 140 can be suppressed more effectively compared to when the via 150 with copper plating P1 on its inner wall surface IW is not filled or when a non-conductive resin is filled into the via 150. However, it is also understood that even when the via 150 with copper plating P1 on its inner wall surface IW is not filled or when a non-conductive resin is filled into the via 150, the ΔTmax is only about 5.4°C higher compared to when copper is filled into the via 150 with copper plating P1 on its inner wall surface IW.

[0105] Figure 17 is an enlarged view of the dashed frame F shown in Figure 2, when the electronic device 10 is equipped with a multilayer printed circuit board 105 according to the fifth embodiment. In the multilayer printed circuit board 105 according to the fifth embodiment, unlike the multilayer printed circuit board 101 according to the first embodiment, in a plan view, the multiple vias 150 are located in greater numbers within the area overlapping with the coupling region A2, which is the area where the first terminal portion 52 is coupled on the pad portion 140, than outside this area. That is, the multiple vias 150 located in the area A1 directly below the pad portion 140 are arranged at a higher density within the area A1 that overlaps with the coupling region A2. Other configurations in the multilayer printed circuit board 105 according to the fifth embodiment are the same as the corresponding configurations in the multilayer printed circuit board 101 according to the first embodiment, so the same reference numbers are used and redundant explanations are omitted.

[0106] In Figure 17, the coupling region A2 is shown as a dotted rectangle. In the example shown in Figure 24, all of the vias 150 are located within the area directly beneath the pad A1 that overlaps with the coupling region A2. As in the multilayer printed circuit board 105 of the fifth embodiment, by concentrating the vias 150 within the area directly beneath the pad A1 that overlaps with the coupling region A2, the pad 140 can dissipate heat more efficiently than when more vias are located outside this area.

[0107] Figures 18 to 27 are schematic partial cross-sectional views showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 is equipped with a multilayer printed circuit board 101 according to the first embodiment. In each embodiment, a four-layer board is described as an example, but the same applies to multilayer printed circuit boards with four or more layers.

[0108] First, as shown in Figure 18, multiple inner layers 131 and insulating layers 132 are formed, and as shown in Figure 19, multiple inner layers 131 are patterned. As shown in Figure 20, multiple insulating layers 132, a conductor layer 115, and a conductor layer 125 are formed on the patterned multiple inner layers 131, and as shown in Figure 21, multiple through holes are formed by drilling or laser cutting to form multiple vias 150. As shown in Figure 22, copper plating P1 is applied to the inner wall surface IW of the through holes and around the openings AP at both ends, thereby making the conductor layer 115, the multiple inner layers 131, and the conductor layer 125 electrically conductive. Figure 22 shows the surface conductor layer 110 including the conductor layer 115 and copper plating P1, and the back surface conductor layer 120 including the conductor layer 125 and copper plating P1. As shown in Figure 23, the conductor layer 115 and conductor layer 125 with copper plating P1, i.e., the surface conductor layer 110 and the back surface conductor layer 120, are patterned.

[0109] As shown in Figure 24, a thermosetting resin paste is injected into multiple through holes, thereby forming multiple vias 150. In the first embodiment, the resin paste is non-conductive, but it may also be conductive. A non-conductive resin paste is, for example, epoxy resin. As for the conductive resin paste, a material that has good filling properties and migration resistance and is relatively inexpensive is preferable. For example, a silver paste, which is a mixture of silver nanoparticles and conductive particles on the order of microns, can be considered a suitable example. In addition, solder paste can also be considered a suitable example because, although its resistance value is higher than that of silver paste, it is relatively inexpensive. Furthermore, copper paste, which has a lower electrical resistance value than solder paste, can also be considered as an alternative material to copper plating or silver paste, but it is relatively prone to oxidation.

[0110] One method for injecting thermosetting resin paste into multiple through-holes is to inject the resin paste into each through-hole using a dispenser. However, if the through-holes are densely arranged, it is also possible to shorten the filling time by injecting the resin paste into multiple through-holes at once under pressure using vacuum printing technology with a pressure printing press. The size of the pressure surface of the pressure printing press is adjustable; for example, by setting the size to approximately the size of two pad sections 140, it is possible to inject resin paste into two pad sections 140 at once.

[0111] As shown in Figure 25, the resin paste filled in the multiple vias 150 is heated and cured in an oven, and the portions of the heat-cured resin that protrude from the openings AP of the surface conductor layer 110 and the back conductor layer 120 are flattened and cleaned. As shown in Figure 26, a cover plating P2 is applied to the openings AP on the surface side of the multiple vias 150 on the surface side of the multilayer printed circuit board 101, thereby forming a pad portion 140. As shown in Figure 27, solder paste is applied to the entire pad portion 140, and the first terminal portion 52 is reflow mounted onto the pad portion 140, thereby achieving good electrical bonding to the bottom surface and the side surface where the fillet is formed of the first terminal portion 52. Since the solder paste applied to the pad portion 140 is not absorbed by the multiple vias 150, the amount of solder paste applied to the pad portion 140 may be only the amount necessary for soldering the first terminal portion 52.

[0112] As described above, according to the example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 is equipped with a multilayer printed circuit board 101 according to the first embodiment, for example, the solder paste for reflow mounting the first terminal portion 52 onto the pad portion 140 does not enter into the multiple through holes due to the interposition of the lid plating P2, thus making it easier to control the amount of solder used for reflow mounting.

[0113] Figures 28 to 29 are schematic partial cross-sectional views showing an example of a method for manufacturing a multilayer printed circuit board 101 when the electronic device 10 includes a multilayer printed circuit board 106 according to the sixth embodiment. The steps shown in Figures 28 to 29 are subsequent steps to those in Figure 26, and redundant explanations of the steps in Figures 18 to 27 are omitted.

[0114] In the multilayer printed circuit board 106 according to the sixth embodiment, unlike the multilayer printed circuit board 101 according to the first embodiment, the multiple vias 150 are also sealed with other cover plating P2 at the openings AP on the back side of the multilayer printed circuit board 106. Another difference is that the electronic device 10 equipped with the multilayer printed circuit board 106 according to the sixth embodiment further includes a heat sink 200 disposed on the lower surface of the other cover plating P2. Other configurations in the multilayer printed circuit board 106 according to the sixth embodiment are the same as the corresponding configurations in the multilayer printed circuit board 101 according to the first embodiment, so the same reference numbers are used and redundant explanations are omitted.

[0115] As shown in Figure 28, following the process in Figure 27, the cover plating P2 is also applied to the opening AP on the back side of the via 150 on the multilayer printed circuit board 106. As shown in Figure 29, solder paste is applied to the entire surface of the pad portion 140, and the first terminal portion 52 is reflow mounted onto the pad portion 140, thereby providing good electrical bonding to the bottom surface and the side surface where the fillet is formed of the first terminal portion 52. Also, as shown in Figure 29, a heat sink 200 is placed on the cover plating P2 on the back side. The heat sink 200 may be a flat plate, or it may be a heat sink fin with an uneven shape to increase the surface area. In the electronic device equipped with the multilayer printed circuit board 106 according to the sixth embodiment, the heat sink 200 can be further provided to promote heat dissipation from the multiple vias 150 and pad portions 140.

[0116] Figures 30 to 33 are schematic partial cross-sectional views showing an example of a method for manufacturing a multilayer printed circuit board 107 when the electronic device 10 is equipped with a multilayer printed circuit board 107 according to the seventh embodiment. The steps shown in Figures 30 to 33 are subsequent steps to those shown in Figure 23, and redundant explanations of the steps in Figures 18 to 23 are omitted.

[0117] In the multilayer printed circuit board 107 according to the seventh embodiment, the differences from the multilayer printed circuit board 101 according to the first embodiment are that the multiple vias 150 are filled with solder S, and the openings AP at both ends of the multiple vias 150 are not coated with cap plating P2, and the pad portions 140 are formed of solder S. In the multilayer printed circuit board 107 according to the seventh embodiment, the openings AP on the back side of the multiple vias 150 on the multilayer printed circuit board 107 can be sealed with a heat-resistant material 300. Other configurations in the multilayer printed circuit board 107 according to the seventh embodiment are the same as the corresponding configurations in the multilayer printed circuit board 101 according to the first embodiment, so the same reference numbers are used and redundant explanations are omitted.

[0118] As shown in Figure 30, the openings AP on the back side of multiple vias 150 are covered with a heat-resistant member 300. The heat-resistant member is, for example, a heat-resistant tape or a heat-resistant sheet. Heat-resistant tapes include, for example, polyimide tape, glass cloth tape, and paper tape for drafts that can be bonded at room temperature. Heat-resistant sheets are made of, for example, polyimide and bonded by heating. This prevents solder S injected into the multiple vias 150 in subsequent processes from leaking out of the openings AP. The process of covering the openings AP with the heat-resistant member 300 may be performed manually or automatically by machine.

[0119] As shown in Figure 31, solder S is applied to the first surface 111 of the surface conductor layer 110. More specifically, an amount of solder S equal to or greater than the sum of the solder that forms the pad portion 140 and the solder S that flows into and fills the multiple vias 150 is applied to the first surface 111 on the region A1 directly below where the multiple vias 150 are formed.

[0120] One method for applying solder S to the first surface 111 and injecting it into multiple through holes is to manually apply the solder S to the first surface 111 using a metal mask and inject it into the through holes. However, if the through holes are densely arranged, it is also possible to use a vacuum printing machine to apply and pressurize the solder S and inject it into multiple through holes at once to shorten the filling time.

[0121] Prior to the process shown in Figure 31, the amount of solder S supplied may be pre-adjusted in a vacuum printing machine capable of supplying solder S, according to the amount of solder S to be applied to the first surface 111. In this case, the solder S may be filled into the via 150 by the vacuum printing machine's function of pre-adjusting the amount of solder S supplied and the function of pressurizing and injecting the solder S with a pre-adjusted force.

[0122] For example, when applying solder S to the first surface 111 by hand and injecting it into the through holes, the amount of solder S may be calculated in advance by adding the amount of solder absorbed into the via 150, which is determined by the inner diameter D of the via 150, the number of vias 150, and the thickness of the multilayer printed circuit board 107, to an appropriate amount of solder that allows the first terminal portion 52 to be connected to the predetermined area of ​​the pad portion 140 with low resistance. This total amount of solder S may then be applied to the first surface 111. For example, when applying and pressurizing solder S and injecting it into multiple through holes at once using a vacuum printing machine, the same total amount may be calculated in advance and set as the supply amount by the vacuum printing machine.

[0123] As an example of an appropriate amount of solder that allows the first terminal portion 52 to be connected to the predetermined area of ​​the pad portion 140 with low resistance, solder S with a thickness of 100 μm to 150 μm may remain and harden on the first surface 111 on the region A1 directly below which the surface area corresponds to the area of ​​the pad portion 140, even after the via 150 has been filled. For example, consider the case where a metal mask with a thickness of 200 μm is used to apply solder S to the entire first surface 111 with a thickness of 200 μm.

[0124] In this case, if the inner diameter of via 150 is D=0.25mm, the number of vias is 3×8=24, and the via occupancy rate is R=20%, the thickness of the residual and hardened solder S will be 147μm. In this case, if the inner diameter of via 150 is D=0.15mm, the number of vias is 5×16=80, and the via occupancy rate is R=20%, the thickness of the residual and hardened solder S will be 136μm.

[0125] The thickness of the solder S applied to the first surface 111 may be less than or equal to the thickness of the metal mask, and from the viewpoint of heat dissipation, it may be about the same as the thickness of the metal mask. It has been confirmed that when solder S with a thickness similar to that of a metal mask, for example, 60 μm to 200 μm, is applied to the first surface 111, there is no difference in solder adhesion strength, impact resistance, or vibration resistance due to differences in the amount of solder applied within that thickness range.

[0126] As shown in Figure 32, the solder S applied to the first surface 111 is reflowed to fill the multiple vias 150 with solder S and to form a pad portion 140 with solder S. At the same time, the first terminal portion 52 is reflow mounted onto the pad portion 140, thereby achieving good electrical bonding between the bottom surface and the side surface where the fillet is formed of the first terminal portion 52.

[0127] As shown in Figure 32, the electronic device 10 may still have the heat-resistant member 300 even after the completion of the multilayer printed circuit board 107, or alternatively, the heat-resistant member 300 may be removed after the completion of the multilayer printed circuit board 107. As described above, the multilayer printed circuit board 107 provided by the electronic device 10 may have two or more pad portions 140, in which case one heat-resistant member 300 may seal the openings AP on the back side of the multilayer printed circuit board 107 of a plurality of through vias 150 located directly beneath the two or more pad portions 140. In this case as well, in the direction perpendicular to the direction in which the two or more pad portions 140 are aligned, i.e., in the Y-axis direction, the plurality of through vias 150 located directly beneath the two or more pad portions 140 may be distributed within a width range of 5 mm or less. By arranging the two or more pad portions 140 in a horizontal row, one heat-resistant member 300 can collectively seal the openings AP on the back side of a plurality of vias 150 located directly beneath the two or more pad portions 140. For example, if the electronic device 10 includes two current sensors arranged in the current path for a three-phase motor as semiconductor packages 50, it is possible to provide a heat-resistant member 300 that spans multiple vias 150 corresponding to four pad portions 140 corresponding to four terminals 52A etc. extending from the two semiconductor packages 50.

[0128] When removing the heat-resistant member 300 after the completion of the multilayer printed circuit board 107, as shown in Figure 33 following Figure 32, the heat-resistant member 300 is peeled off from the back side after the solder S filled into the multiple vias 150 has hardened to a predetermined hardness or after a predetermined time has elapsed since the completion of filling the multiple vias 150 with solder S, exposing the solder S filled into the multiple vias 150 through the openings AP on the back side. The peeling off of the heat-resistant member 300 can be done manually. When the heat-resistant member 300 is removed after the completion of the multilayer printed circuit board 107, the solder S filled into the multiple vias 150 is exposed through the openings AP on the back side of the multiple vias 150, but does not protrude from the openings AP. After the heat-resistant member 300 is peeled off, the solder S does not protrude from the openings AP on the back side, and there is no step on the back side.

[0129] As described above, in the example of a method for manufacturing a multilayer printed circuit board 107 when the electronic device 10 is equipped with a multilayer printed circuit board 107 according to the seventh embodiment, as shown in Figures 30 to 33, for example, by filling the vias 150 with solder S, which has higher conductivity and heat dissipation than resin paste, the electrical resistance of the vias 150 can be reduced and heat dissipation improved compared to cases where the vias are not filled. Furthermore, since processes such as applying lid plating P2 and flattening the filling material protruding from the opening AP are unnecessary, assembly can be done at a low cost. Also, since it is not necessary to inject resin into each via 150 and the heat curing process of the resin in an oven is unnecessary, manufacturing costs can be reduced.

[0130] In the multiple embodiments described above, even when the multiple vias 150 located in the region A1 directly below are filled with conductive resin R or solder S instead of non-conductive resin R, copper plating P1 has overwhelmingly higher thermal conductivity and lower electrical resistance than conductive resin R or solder S. Therefore, applying copper plating P1 to the inner wall surface IW is preferable from the viewpoint of thermal conductivity and electrical resistance. However, it is also possible to reduce manufacturing costs by omitting the copper plating process and filling the vias 150 only with conductive resin R or solder S without copper plating P1. Note that filling multiple vias 150 with copper is preferable from the viewpoint of thermal conductivity and electrical resistance, but it increases manufacturing costs.

[0131] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0132] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0133] 10 Electronic equipment 50 Semiconductor Packages 51 Package sealing section 52 1st terminal section 52A, 52B terminals 53 2nd terminal section 55 Current conductor section 56 Magnetic detection unit 57 Signal Processing Unit 58 Sealing part 101 Multilayer Printed Circuit Board 110 Surface Conductor Layer 111 Page 1 115 Conductor layer 120 Back surface conductor layer 125 Conductor layer 131 Inner Layer 132 Insulating layer 140 Pad section 141 Implementation aspects 150 Beer IW Interior Wall Surface AP aperture P1 Copper Plating R resin S solder 160 surrounding beers P2 Lid Plating F Dashed line frame A1 direct area A2 binding area L pitch D Inner diameter 102 Multilayer Printed Wiring Board C Multilayer Printed Circuit Board 103 Multilayer Printed Wiring Board 104 Multilayer Printed Circuit Board 105 Multilayer Printed Wiring Board 106 Multilayer Printed Circuit Board 200 Heat sink 107 Multilayer Printed Circuit Boards 300 Heat-resistant material

Claims

1. A semiconductor package in which the terminals through which current flows are exposed to the outside, Surface conductor layer including the first surface, A back surface conductor layer located on the opposite side of the aforementioned surface conductor layer, and Multiple conductive inner layers between the surface conductor layer and the back conductor layer A multilayer printed circuit board having Equipped with, The aforementioned multilayer printed circuit board further, A pad portion located on the first surface, electrically connecting the terminal portion of the semiconductor package to the first surface, and including the mounting surface on the opposite side of the first surface to which the semiconductor package is mounted, A plurality of vias located directly below the pad portion, which provide electrical conductivity between the surface conductor layer and the plurality of inner layers. It has, In a plan view from above the surface conductor layer, the total area of ​​the plurality of vias is 6% or more of the total area of ​​the pad portion. electronic equipment.

2. The multilayer printed circuit board further has a plurality of other vias located around the area directly below the pad portion, which provide electrical conductivity between the surface conductor layer and the plurality of inner layers. In the plan view, the density of the plurality of vias is higher than the density of the other plurality of vias. The electronic device according to claim 1.

3. The inner diameter of the aforementioned plurality of vias is smaller than the inner diameter of the other plurality of vias. The electronic device according to claim 2.

4. The terminal portion is connected to the coupling region on the pad portion, In the plan view, the plurality of vias are located more frequently within the overlapping area with the coupling region than outside the area. The electronic device according to any one of claims 1 to 3.

5. The multilayer printed circuit board has two or more pad portions, each having four or more of the multiple vias directly beneath it. The electronic device according to any one of claims 1 to 3.

6. The multilayer printed circuit board has two or more pad portions, each having 20 or more of the multiple vias directly beneath it. The electronic device according to any one of claims 1 to 3.

7. In the plan view, the total area of ​​the plurality of vias is 20% or more of the total area of ​​the pad portion. The electronic device according to any one of claims 1 to 3.

8. The inner diameter of the aforementioned multiple vias is 0.25 mm or less. The electronic device according to any one of claims 1 to 3.

9. In the aforementioned plan view, the pitch of the plurality of vias is 0.6 mm or less. The electronic device according to any one of claims 1 to 3.

10. The terminal portion of the semiconductor package is not exposed from the surface of the semiconductor package facing the multilayer printed circuit board. The electronic device according to any one of claims 1 to 3.

11. The pad portion of the multilayer printed circuit board is located in a position that does not overlap with the package sealing portion of the semiconductor package in the plan view. The electronic device according to any one of claims 1 to 3.

12. The plurality of vias are filled with a non-conductive resin. The electronic device according to any one of claims 1 to 3.

13. The plurality of vias are filled with a conductive resin. The electronic device according to any one of claims 1 to 3.

14. The aforementioned multiple vias are filled with solder. The electronic device according to any one of claims 1 to 3.

15. In the aforementioned plan view, the plurality of vias are uniformly distributed across the entire region directly below the pad portion. The electronic device according to any one of claims 1 to 3.

16. The aforementioned semiconductor package is a current sensor, The aforementioned semiconductor package is The terminal portion includes the current conductor portion through which the current flows, A magnetic detection unit that detects the magnetic field generated by the flow of the current in the current conductor and outputs a detection signal, A signal processing unit that outputs a signal current based on the detection signal, A sealing portion that seals a part of the current conductor portion, the magnetic detection portion, and the signal processing portion. Having, The electronic device according to any one of claims 1 to 3.

17. The power unit includes the current sensor mounted on the multilayer printed circuit board, which also includes an inverter circuit. The electronic device according to claim 16.

18. In the plan view, the plurality of vias are distributed in a region directly below the pad portion, with a bias toward the sealing portion side of the semiconductor package. The electronic device according to claim 16.

19. In the plan view, the plurality of vias are distributed in a biased manner towards the side with a higher current density in the region directly below the pad portion. The electronic device according to any one of claims 1 to 3.

20. The plurality of vias extend from the front surface to the back surface of the multilayer printed circuit board and include a plurality of through vias that provide electrical conductivity between the front conductor layer, the plurality of inner layers, and the back conductor layer. The electronic device according to any one of claims 1 to 3.

21. At least two of the plurality of through vias are directly connected to at least one common back surface conductor layer. The electronic device according to claim 20.

22. The inner wall surfaces of the plurality of through vias, and the periphery of the openings located at both ends of the plurality of through vias in the extending direction, are covered with copper plating. The electronic device according to claim 20.

23. The inner wall surfaces of the aforementioned multiple through vias are covered with copper plating. The plurality of through vias are filled with resin, and the openings on the surface side are sealed with cap plating. The electronic device according to claim 20.

24. The multiple through vias are also sealed with other capping on the openings on the back side. The system further comprises a heat sink plate positioned on the lower surface of the other plated cover. The electronic device according to claim 23.

25. The aforementioned multiple through vias are filled with solder, and the openings on the back side are sealed with a heat-resistant material. The electronic device according to claim 20.

26. The multilayer printed circuit board has two or more pad portions, One of the heat-resistant members seals the openings on the back side of the plurality of through vias located directly beneath two or more of the pad portions. The electronic device according to claim 25.

27. The aforementioned multiple through vias are filled with solder. The solder filled in the plurality of through vias is exposed from the opening on the back side of the plurality of through vias, but does not protrude from the opening. The electronic device according to claim 20.

28. The multilayer printed circuit board has two or more pad portions, In a direction perpendicular to the direction in which two or more pad portions are aligned, the multiple through vias located directly below the two or more pad portions are distributed within a width range of 5 mm or less. The electronic device according to claim 27.

29. A method for manufacturing an electronic device according to claim 14, The aforementioned pad portion is formed of solder, Applying a total amount of solder to the first surface equal to or greater than the sum of the solder forming the pad portion and the solder flowing into and filling the plurality of vias, The solder applied to the first surface is reflowed to fill the plurality of vias with solder, and the pad portion is formed with solder. A manufacturing method that includes the following features.

30. A vacuum printing machine capable of supplying solder is further provided with the ability to pre-adjust the amount of solder supplied according to the amount of solder to be applied to the first surface, Applying solder to the first surface includes supplying a pre-adjusted amount of solder to the first surface from the vacuum printing machine. The manufacturing method according to claim 29.

31. Before the aforementioned reflow, In a vacuum printing machine capable of supplying solder, The device includes filling the inside of a via with solder by applying pressure with a pre-adjusted pressure. The manufacturing method according to claim 29.

32. A method for manufacturing an electronic device according to claim 27, The openings on the back side of the plurality of through vias are covered with a heat-resistant material, Applying solder to the first surface, The solder applied to the first surface is reflowed to fill the plurality of through vias with solder. A manufacturing method that includes the following features.

33. After the solder filled into the multiple through vias has hardened to a predetermined hardness or beyond, or after a predetermined time has elapsed since the completion of soldering into the multiple through vias, the heat-resistant material is peeled off from the back surface, exposing the solder filled into the multiple through vias through the openings on the back surface. It also has, The manufacturing method according to claim 32.

34. A semiconductor package in which the terminals through which current flows are exposed to the outside, Surface conductor layer including the first surface, A back surface conductor layer located on the opposite side of the aforementioned surface conductor layer, and Multiple conductive inner layers between the surface conductor layer and the back conductor layer A multilayer printed circuit board having Equipped with, The aforementioned multilayer printed circuit board further, A pad portion located on the first surface, electrically connecting the terminal portion of the semiconductor package to the first surface, and including the mounting surface on the opposite side of the first surface to which the semiconductor package is mounted, A plurality of vias located directly below the pad portion, which provide electrical conductivity between the surface conductor layer and the plurality of inner layers, Located around the region directly below the pad portion, and comprising several other vias that provide electrical conductivity between the surface conductor layer and the multiple inner layers. It has, In a plan view from above the surface conductor layer, the density of the plurality of vias is higher than the density of the other plurality of vias. electronic equipment.

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