Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can remove excess carbon at the interface between the gate insulating film and the semiconductor substrate. [Solution] At the interface between the gate insulating film 6 and the semiconductor substrate 5, Ge atoms and Mg atoms that have become insulators and assimilated with the gate insulating film 6 are present in the gate insulating film 6. Excess carbon deposited by surface oxidation of the semiconductor substrate 5 is removed before the formation of the gate insulating film 6 by rearranging the bonds between the excess carbon, N atoms supplied to the surface of the semiconductor substrate 5 by N radical irradiation, and Ge atoms on the surface of the semiconductor substrate 5 by Ge irradiation, and by the electromigration phenomenon. Ge atoms remaining on the surface of the semiconductor substrate after the removal of excess carbon are reduced by rearranging the bonds between the Ge atoms, N atoms remaining on the surface of the semiconductor substrate 5, and Mg atoms deposited on the surface of the semiconductor substrate 5 by Mg irradiation, and by oxidation-reduction reactions due to the bond energy difference.

Description

[Technical Field]

[0001] This disclosure relates to silicon carbide semiconductor devices and methods for manufacturing silicon carbide semiconductor devices. [Background technology]

[0002] Patent Document 1 below describes a technique for forming a gate insulating layer by thermal oxidation of an amorphous silicon film containing elements such as Ge (germanium) and Mg (magnesium), and for increasing the threshold by a fixed negative charge formed by a composite of C (carbon) that diffuses from the surface of the SiC (silicon carbide) layer into the gate insulating layer during thermal oxidation, and elements and O (oxygen) in the gate insulating layer. Patent Document 2 below describes a technique for increasing channel mobility by forming an interlayer containing an alkaline earth metal between a SiC substrate and a gate oxide film. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6526549 [Patent Document 2] Special Publication No. 2014-523131 [Overview of the project] [Problems that the invention aims to solve]

[0004] In Patent Document 1, the gate characteristics are adversely affected by the fixed negative charge formed in the gate insulating layer during its formation. In Patent Document 2, excess carbon derived from the oxidation of the SiC substrate is incorporated into the interlayer and gate oxide film, which may reduce the reliability of the gate oxide film.

[0005] This disclosure aims to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device in which excess carbon at the interface between the gate insulating film and the semiconductor substrate is removed. [Means for solving the problem]

[0006] A silicon carbide semiconductor device according to one aspect of this disclosure is as follows: It comprises a semiconductor substrate made of silicon carbide, a gate insulating film made of silicon oxide provided on the surface of the semiconductor substrate, and a gate electrode provided on the surface of the gate insulating film, wherein germanium atoms and alkaline earth metal atoms are present at the interface between the gate insulating film and the semiconductor substrate.

[0007] A method for manufacturing a silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A predetermined step of oxidizing the surface of a semiconductor substrate made of silicon carbide; a removal step of removing carbon atoms deposited on the surface of the semiconductor substrate in the predetermined step; a first forming step of depositing a gate insulating film made of silicon oxide on the surface of the semiconductor substrate from which the carbon atoms have been removed; and a second forming step of forming a gate electrode on the surface of the gate insulating film. The removal step includes a first removal step of first irradiating the surface of the semiconductor substrate with nitrogen atoms having unpaired electrons to remove the carbon atoms from the surface of the semiconductor substrate; a first step of depositing germanium atoms on the surface of the semiconductor substrate; and a second step of second irradiating the surface of the semiconductor substrate with nitrogen atoms having unpaired electrons to remove the carbon atoms remaining on the surface of the semiconductor substrate after the first removal step. [Effects of the Invention]

[0008] The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to this disclosure have the effect of being able to remove excess carbon at the interface between the gate insulating film and the semiconductor substrate. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 2] This is a flowchart illustrating the outline of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 3]Figure 2 is a flowchart outlining the process in step S3. [Figure 4] This is a cross-sectional view (part 1) showing the state of a silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 5] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device in the process of being manufactured according to the embodiment. [Figure 6] This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device in the process of being manufactured according to the embodiment. [Figure 7] This is a cross-sectional view (part 4) showing the state of a silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 8] Figure 5 is a schematic diagram showing the state of the SiC surface. [Figure 9] Figure 6 is a schematic diagram (part 1) showing the state of the SiC surface. [Figure 10] Figure 6 is a schematic diagram (part 2) showing the state of the SiC surface. [Figure 11] Figure 6 is a schematic diagram showing the state of the SiC surface (part 3). [Figure 12] Figure 6 is a schematic diagram showing the state of the SiC surface (part 4). [Figure 13] Figure 6 is a schematic diagram showing the state of the SiC surface (part 5). [Figure 14] Figure 6 is a schematic diagram showing the state of the SiC surface (part 6). [Figure 15] This is a chemical reaction equation that explains the behavior of Ge atoms remaining at the SiO2 / SiC interface. [Figure 16] Figure 6 is a schematic diagram showing the state of the SiC surface (part 7). [Figure 17] Figure 6 is a schematic diagram showing the state of the SiC surface (part 8). [Figure 18] This is a schematic diagram showing the state of the SiC surface in Figure 6 (part 9). [Figure 19] Figure 6 is a schematic diagram showing the state of the SiC surface (part 10). [Figure 20] Figure 6 is a schematic diagram showing the state of the SiC surface (part 11). [Figure 21] Figure 7 is a schematic diagram showing the state of the SiO2 / SiC interface. [Figure 22] This is a schematic diagram showing the structure of a typical semiconductor manufacturing device. [Figure 23] Figure 22 is a schematic diagram showing the structure of a radical generator. [Figure 24] This is a diagram showing the bond energies of a given bond species. [Figure 25] This is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device according to the embodiment. [Figure 26] This figure shows the results of measuring the interface state density at the SiO2 / SiC interface in Examples 1 and 2 and Comparative Example 1. [Figure 27] This figure shows the results of calculating the field effect mobility for Example 3 and Comparative Example 2. [Figure 28] This is a flowchart illustrating the manufacturing process of a silicon carbide semiconductor device as an example. [Modes for carrying out the invention]

[0010] <Summary of the embodiments of this disclosure> (1) A silicon carbide semiconductor device according to one aspect of this disclosure is as follows: It comprises a semiconductor substrate made of silicon carbide, a gate insulating film made of silicon oxide provided on the surface of the semiconductor substrate, and a gate electrode provided on the surface of the gate insulating film, wherein germanium atoms and alkaline earth metal atoms are present at the interface between the gate insulating film and the semiconductor substrate.

[0011] According to the disclosure described above, excess carbon originating from SiC oxidation at the interface between the gate insulating film and the semiconductor substrate is replaced with germanium atoms, and there is no excess carbon at the interface between the gate insulating film and the semiconductor substrate. Because there is no excess carbon that would become a hole trap level at the interface between the gate insulating film and the semiconductor substrate, Coulomb scattering due to hole charging does not occur, and as a result the channel mobility (field-effect mobility μ) is reduced. FEIt is possible to prevent the decrease. Also, according to the above disclosure, a part of the germanium atoms at the interface between the gate insulating film and the semiconductor substrate is replaced by alkaline earth metal atoms, resulting in a structure that reduces the density of germanium atoms serving as electron trap levels in the gate insulating film as much as possible. As a result, an increase in the interface state density at the interface between the gate insulating film and the semiconductor substrate can be suppressed, so that adverse effects on gate characteristics (such as a decrease in the long-term reliability of the gate insulating film and fluctuations in the gate threshold voltage) can be suppressed, and the reliability of the silicon carbide semiconductor device can be improved.

[0012] (2) Also, in the silicon carbide semiconductor device according to this disclosure, in the above-mentioned (1), the density of the germanium atoms at the interface between the gate insulating film and the semiconductor substrate is 1×10 8 atoms / cm 2 or more and 1×10 12 atoms / cm 2 or less.

[0013] According to the above disclosure, even if germanium atoms at the interface between the gate insulating film and the semiconductor substrate become electron trap levels, no adverse effects on gate characteristics occur.

[0014] (3) Also, in the silicon carbide semiconductor device according to this disclosure, in the above-mentioned (1) or (2), the density of the alkaline earth metal atoms at the interface between the gate insulating film and the semiconductor substrate is 1×10 11 atoms / cm 2 or more and 1×10 13 atoms / cm 2 or less.

[0015] According to the above disclosure, it serves as a criterion indicating that the density of germanium atoms at the interface between the gate insulating film and the semiconductor substrate is low enough not to adversely affect gate characteristics.

[0016] (4) In addition, in any one of (1) to (3) above, the silicon carbide semiconductor device according to this disclosure may have germanium atoms at the interface between the gate insulating film and the semiconductor substrate constituting an oxide or oxynitride in the gate insulating film.

[0017] According to the disclosure described above, germanium atoms at the interface between the gate insulating film and the semiconductor substrate assimilate (integrate) with the gate insulating film, thereby maintaining the insulating properties of the gate insulating film.

[0018] (5) In addition, in any one of (1) to (4) above, the silicon carbide semiconductor device according to this disclosure may have the alkaline earth metal atoms at the interface between the gate insulating film and the semiconductor substrate forming an oxide in the gate insulating film.

[0019] According to the disclosure described above, alkaline earth metal atoms at the interface between the gate insulating film and the semiconductor substrate assimilate with the gate insulating film, maintaining the insulating properties of the gate insulating film. Furthermore, the alkaline earth metal atoms at the interface between the gate insulating film and the semiconductor substrate become oxides, resulting in a large band gap and virtually no electron flow, thus preventing the formation of trap levels. Therefore, it is possible to prevent an increase in the interface level density at the interface between the gate insulating film and the semiconductor substrate.

[0020] (6) Furthermore, in the silicon carbide semiconductor device relating to this disclosure, in any one of the above-described (1) to (5), there is no excess carbon at the interface between the gate insulating film and the semiconductor substrate.

[0021] According to the disclosure described above, the interface state density at the interface between the gate insulating film and the semiconductor substrate can be reduced, thereby preventing adverse effects on gate characteristics caused by excess carbon.

[0022] (7) The silicon carbide semiconductor device according to this disclosure further comprises, in any one of (1) to (6) above, a first semiconductor region of a first conductivity type provided inside the semiconductor substrate, a second semiconductor region of a second conductivity type provided between the front surface of the semiconductor substrate and the first semiconductor region, and a third semiconductor region of a first conductivity type selectively provided between the front surface of the semiconductor substrate and the second semiconductor region. The gate insulating film is provided in contact with the region of the second semiconductor region between the third semiconductor region and the first semiconductor region. The gate electrode may be provided on the opposite side of the second semiconductor region, with the gate insulating film in between.

[0023] According to the disclosure described above, it can be applied to silicon carbide semiconductor devices equipped with an insulated gate structure.

[0024] (8) In addition, in any one of (1) to (7) above, the silicon carbide semiconductor device relating to this disclosure may have a magnesium atom instead of an alkaline earth metal atom.

[0025] According to the disclosure described above, since the vapor pressure of magnesium is very high, even when heating to a temperature of approximately 350°C to 450°C in the process of removing carbon atoms deposited on the surface of the semiconductor substrate, a sufficient amount of magnesium vapor (a large excess flux amount for magnesium irradiation) can be easily obtained.

[0026] (9) A method for manufacturing a silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A predetermined step of oxidizing the surface of a semiconductor substrate made of silicon carbide; a removal step of removing carbon atoms deposited on the surface of the semiconductor substrate in the predetermined step; a first forming step of depositing a gate insulating film made of silicon oxide on the surface of the semiconductor substrate from which the carbon atoms have been removed; and a second forming step of forming a gate electrode on the surface of the gate insulating film. The removal step includes a first removal step of first irradiating the surface of the semiconductor substrate with nitrogen atoms having unpaired electrons to remove the carbon atoms from the surface of the semiconductor substrate; a first step of depositing germanium atoms on the surface of the semiconductor substrate; and a second step of second irradiating the surface of the semiconductor substrate with nitrogen atoms having unpaired electrons to remove the carbon atoms remaining on the surface of the semiconductor substrate after the first removal step.

[0027] According to the above disclosure, before depositing the gate insulating film, all excess carbon on the surface of the semiconductor substrate can be removed by rearranging the bonds between excess carbon (carbon atoms) deposited on the surface of the semiconductor substrate, nitrogen atoms irradiated onto the surface of the semiconductor substrate in the second removal step, and germanium atoms deposited onto the surface of the semiconductor substrate in the second removal step. By removing all excess carbon from the surface of the semiconductor substrate beforehand and then depositing the gate insulating film, no excess carbon remains at the interface between the gate insulating film and the semiconductor substrate. The absence of excess carbon that would become hole trap levels at the interface between the gate insulating film and the semiconductor substrate prevents a decrease in channel mobility.

[0028] (10) In addition, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the first removal step described in (9) above, the semiconductor substrate may be heated to a temperature of 500°C or more and 800°C or less.

[0029] According to the disclosure described above, the detachment of carbon atoms in the first removal step can be accelerated.

[0030] (11) In addition, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the second removal step described in (9) or (10) above, the semiconductor substrate may be heated to a temperature of 500°C or more and 800°C or less.

[0031] According to the disclosure described above, the removal of carbon atoms in the second removal step can be accelerated.

[0032] (12) Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in any one of (9) to (11) described above, in the second removal step, the set of the first step and the second step is performed multiple times to reduce the density of germanium atoms remaining on the surface of the semiconductor substrate to 1 × 10⁻¹⁶ 11 atoms / cm 2 The above 1 x 10 12 atoms / cm 2 It is best to keep it within the following range.

[0033] According to the disclosure described above, all carbon atoms remaining on the surface of the semiconductor substrate after the first removal step can be removed in the second removal step.

[0034] (13) Furthermore, in any one of the above-described methods for manufacturing a silicon carbide semiconductor device, the removal step may further include, after the second removal step, a third removal step of depositing alkaline earth metal atoms onto the surface of the semiconductor substrate to remove the germanium atoms from the surface of the semiconductor substrate.

[0035] According to the above disclosure, before the deposition of the gate insulating film, the density of germanium atoms on the surface of the semiconductor substrate can be reduced by rearranging the bonds between germanium atoms remaining on the surface of the semiconductor substrate after the second removal step, nitrogen atoms on the surface of the semiconductor substrate after the second removal step, and alkaline earth metal atoms deposited on the surface of the semiconductor substrate in the third removal step. The density of germanium atoms remaining at the interface between the gate insulating film and the semiconductor substrate can be reduced to a degree that does not adversely affect the gate characteristics even if the germanium atoms become electron trap levels. Therefore, the reliability of the silicon carbide semiconductor device can be improved.

[0036] (14) In addition, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, the alkaline earth metal atom may be a magnesium atom in (13) described above.

[0037] According to the disclosure described above, since the vapor pressure of magnesium is very high, even when heating to a temperature of approximately 350°C to 450°C in the third removal step, a sufficient amount of magnesium vapor (a large excess flux amount for magnesium irradiation) can be easily obtained.

[0038] (15) Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the third removal step described in (14) above, it is preferable to supply magnesium atoms to the surface of the semiconductor substrate in an amount exceeding the amount of magnesium atoms deposited on the surface of the semiconductor substrate.

[0039] According to the disclosure described above, the rearrangement of bonds between germanium atoms remaining on the surface of the semiconductor substrate after the second removal step, nitrogen atoms on the surface of the semiconductor substrate after the second removal step, and magnesium atoms deposited on the surface of the semiconductor substrate in the third removal step is promoted. This makes it possible to reduce the density of germanium atoms remaining on the surface of the semiconductor substrate to an extent that does not adversely affect the gate characteristics, and also to reduce the density of magnesium atoms remaining on the surface of the semiconductor substrate.

[0040] (16) In addition, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the third removal step described in (14) or (15) above, the semiconductor substrate may be heated to a temperature of 1000°C or more and 1100°C or less.

[0041] According to the disclosure described above, the evaporation of germanium atoms in the third removal step can be accelerated.

[0042] (17) Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this disclosure may include, in any one of (9) to (16) above, a heat treatment step of oxynitriding the interface between the gate insulating film and the semiconductor substrate by heat treatment after the first forming step and before the second forming step.

[0043] According to the disclosure described above, germanium atoms and alkaline earth metal atoms at the interface between the gate insulating film and the semiconductor substrate can be assimilated with the gate insulating film, thereby maintaining the insulating properties of the gate insulating film. Furthermore, the alkaline earth metal atoms at the interface between the gate insulating film and the semiconductor substrate become oxides, resulting in a large band gap and virtually no electron emission, thus preventing them from becoming trapped levels. Therefore, it is possible to prevent an increase in the interface level density at the interface between the gate insulating film and the semiconductor substrate.

[0044] (18) Furthermore, in any one of (14) to (17) described above, the silicon carbide semiconductor device manufacturing method according to this disclosure is characterized in that, in the first removal step, the first group is removed from the surface of the semiconductor substrate by an electromigration phenomenon of the first group due to a covalent bond between the carbon atom and the first irradiated nitrogen atom. In the second removal step, the second group is removed from the surface of the semiconductor substrate by an electromigration phenomenon of the second group due to a covalent bond between the germanium atom and the second irradiated nitrogen atom.

[0045] According to the disclosure described above, the first and second removal steps can remove excess carbon from the surface of the semiconductor substrate by utilizing the electromigration phenomenon of the first and second groups.

[0046] (19) In addition, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the third removal step described in (18) above, it is preferable to reduce the second group with the magnesium atom and evaporate and remove the germanium atom whose bond with the nitrogen atom has been broken.

[0047] According to the disclosure described above, the third removal step can remove germanium atoms from the surface of the semiconductor substrate by utilizing the difference between the bond energy between magnesium atoms and nitrogen atoms and the bond energy between germanium atoms and nitrogen atoms.

[0048] <Knowledge forming the basis of this disclosure> The manufacturing method for a silicon carbide semiconductor device as an example is described below. Figure 28 is a flowchart outlining the manufacturing method for a silicon carbide semiconductor device as an example. First, SiC regions constituting a predetermined device structure are formed by epitaxial growth of silicon carbide (SiC) or ion implantation into the surface region of SiC (step S101). Next, the SiC surface is cleaned by hydrogen (H2) etching or sacrificial oxidation (step S102). Next, a silicon oxide (SiO2) film, which will serve as a gate insulating film, is deposited on the SiC surface (step S103).

[0049] During wafer cleaning in step S101 and the processing in step S102, the SiC surface is oxidized, and carbon (C) atoms constituting SiC are detached and segregated at the interface between the SiO2 film and SiC (hereinafter referred to as the SiO2 / SiC interface). The excess carbon is incorporated into the SiO2 film and becomes a hole trap level, thus reducing channel mobility. Furthermore, crystal defects (interface levels) at the SiO2 / SiC interface can cause a decrease in the long-term reliability of the gate insulating film and fluctuations in the gate threshold voltage.

[0050] Therefore, the crystal defects caused by excess carbon at the SiO2 / SiC interface are reduced by heat treatment (oxynitriding annealing) using nitric oxide (NO) gas or dinitrogen monoxide (N2O) gas (step S104). Subsequently, gate electrodes and surface electrodes are formed on the SiC surface (steps S105, S106), completing the silicon carbide semiconductor device of the reference example. However, even after performing the treatment in step S104, the excess carbon at the SiO2 / SiC interface is not sufficiently reduced, and there is room for improvement.

[0051] Therefore, the problem to be solved in this embodiment is to prevent a decrease in channel mobility by removing excess carbon at the SiO2 / SiC interface. Preferably, the goal is to improve the reliability of the silicon carbide semiconductor device by suppressing the adverse effects on gate characteristics caused by interface states at the SiO2 / SiC interface.

[0052] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0053] (Details of the embodiment) The silicon carbide semiconductor device according to an embodiment will be described below. Figure 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment. The silicon carbide semiconductor device 10 according to the embodiment shown in Figure 1 is a lateral (i.e., planar gate type) MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field-effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor), and has a gate electrode 7 on the front surface of the semiconductor substrate 5 via a gate insulating film 6, and germanium (Ge) atoms and magnesium (Mg) atoms are present at the interface (SiO2 / SiC interface) between the gate insulating film 6 and the semiconductor substrate 5.

[0054] The semiconductor substrate 5 is n - This semiconductor chip is formed by epitaxially growing an epitaxial layer 11 made of p-type silicon carbide (SiC) and an epitaxial layer 12 made of p-type SiC in that order. The epitaxial layers 11 and 12 are each n - The semiconductor substrate 5 comprises a p-type region (first semiconductor region) 1 and a p-type region (second semiconductor region) 2. The semiconductor substrate 5 has its first main surface on the epitaxial layer 12 side as the front surface and its second main surface on the epitaxial layer 11 side as the back surface. A starting substrate (bulk substrate: not shown) made of SiC used during the epitaxial growth of the epitaxial layers 11 and 12 may remain on the back surface of the semiconductor substrate 5. The epitaxial layer 11 itself may be the starting substrate.

[0055] Between the front surface of the semiconductor substrate 5 and the p-type region 2, there is a n that is exposed on the front surface of the semiconductor substrate 5 and in contact with the p-type region 2. + Type source region (third semiconductor region) 3 and n + The drain regions 4 are selectively provided, separated from each other. + Type source regions 3 and n + The p-type drain region 4 is a diffusion region formed by ion implantation into the epitaxial layer 12. + Type source regions 3 and n + The area excluding the type drain region 4 becomes the p-type region 2.+ Type source area 3 and n + The p-type region 2 extends to the front surface of the semiconductor substrate 5, separated from the type drain region 4. On the front surface of the semiconductor substrate 5, the p-type region 2, n + Type source area 3 and n + A gate electrode 7 is provided on the portion sandwiched between the type drain region 4, via a gate insulating film 6.

[0056] The gate insulating film 6 is a silicon oxide (SiO2) film deposited using a general deposition method. At the interface between the gate insulating film 6 and the semiconductor substrate 5, Ge atoms are present at intervals approximately equal to the maximum migration distance of Ge-containing groups (specifically "-GeN groups": see Figure 14) generated during the pre-formation treatment of the gate insulating film 6 (processing in steps S12 and S13 described later: see Figure 3). The maximum migration distance of a group (a group of atoms that can move as a single aggregate during a chemical reaction) is the upper limit of the distance a group can move due to the electromigration phenomenon. In addition, at the interface between the gate insulating film 6 and the semiconductor substrate 5, Mg atoms are present at intervals such that collisions between Mg-containing groups (specifically "-MgN groups": see Figure 19) generated during the pre-formation treatment of the gate insulating film 6 (processing in step S15 described later: see Figure 3) do not occur.

[0057] At the interface between the gate insulating film 6 and the semiconductor substrate 5, the density of Ge atoms (number of atoms per unit area) is lower than the density of Mg atoms, for example, 1 × 10⁻⁶ 8 atoms / cm 2 The above 1 x 10 12 atoms / cm 2 The following extent (preferably 1 x 10) 9 atoms / cm 2 The density of Mg atoms at the interface between the gate insulating film 6 and the semiconductor substrate 5 is, for example, 1 × 10⁻⁶. 11 atoms / cm 2 The above 1 x 10 13 atoms / cm 2The following applies: Ge atoms at the interface between the gate insulating film 6 and the semiconductor substrate 5 are assimilated (integrated) with the gate insulating film 6 by forming oxides or oxynitrides within the gate insulating film 6. Mg atoms at the interface between the gate insulating film 6 and the semiconductor substrate 5 are assimilated (integrated) with the gate insulating film 6 by forming oxides within the gate insulating film 6. There is no excess carbon at the interface between the gate insulating film 6 and the semiconductor substrate 5. Excess carbon refers to individual carbon atoms whose bonds with silicon (Si) atoms constituting SiC (the material of the semiconductor substrate 5) have been broken, or aggregates of individual carbon atoms bonded to each other.

[0058] The interlayer insulating film 8 is provided over the entire surface of the front surface of the semiconductor substrate 5 and covers the gate electrode 7. The gate insulating film 6 may extend between the semiconductor substrate 5 and the interlayer insulating film 8. The interlayer insulating film 8 may also serve as a field oxide film (not shown). The field oxide film is provided over the entire area (not shown) of the semiconductor substrate 5, excluding the active region (the region where the MOSFET cells (functional units) are located), between the front surface of the semiconductor substrate 5 and the interlayer insulating film 8 (or between the gate insulating film 6 and the interlayer insulating film 8). Contact holes 8a and 8b penetrate the interlayer insulating film 8 and the gate insulating film 6 in the depth direction to reach the semiconductor substrate 5. Contact hole 8c penetrates the interlayer insulating film 8 in the depth direction to reach the gate electrode 7.

[0059] Contact holes 8a and 8b each contain n + Type source regions 3 and n + The drain region 4 is exposed. The extended portion of the gate electrode 7 is exposed in the contact hole 8c. The gate electrode 7 is, for example, a polysilicon (poly-Si) layer. The extended portion of the gate electrode 7 (gate polysilicon wiring layer) functions as a gate runner, which is the connection portion with the gate pad (not shown). The source electrode 13 is n in the contact hole 8a + The drain electrode 14 makes ohmic contact with the source region 3. The drain electrode 14 is in contact with the contact hole 8b. + It makes ohmic contact with the drain region 4. The gate metal wiring layer 15 is formed on the extended portion of the gate electrode 7 in the contact hole 8c and functions as a gate runner.

[0060] The source electrode 13 and drain electrode 14 have a laminated structure in which, for example, an ohmic electrode film, a barrier metal, and an electrode film containing aluminum (Al) (hereinafter referred to as the Al electrode film) are stacked in this order. The gate metal wiring layer 15 and gate pad are Al electrode films. The ohmic electrode film is, for example, a nickel silicide (NixSiy, x,y are positive numbers) film and makes ohmic contact with the front surface of the semiconductor substrate 5. The barrier metal is, for example, a titanium (Ti) film and has the function of preventing atomic diffusion and interaction between opposing regions or between metals with the barrier metal in between. The Al electrode film is an Al film or an Al alloy film. The outermost surface of the front surface of the semiconductor substrate 5 is covered with a passivation film (not shown).

[0061] A method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Figure 2 is a flowchart showing an overview of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figure 3 is a flowchart showing an overview of the process in step S3 of Figure 2. Figures 4 to 7 are cross-sectional views showing the state of the silicon carbide semiconductor device during the manufacturing process according to the embodiment. Figures 4 to 7 show the state during the processes in steps S1 to S4 of Figure 2, respectively. Figure 8 is a schematic diagram showing the state of the SiC surface in Figure 5. Figures 9 to 14 and 16 to 20 are schematic diagrams showing the state of the SiC surface in Figure 6. Figure 15 is a chemical reaction equation explaining the behavior of Ge atoms remaining at the SiO2 / SiC interface. Figure 21 is a schematic diagram showing the state of the SiO2 / SiC interface in Figure 7.

[0062] In Figures 8-21, the thickness of the semiconductor substrate 5 is simplified and shown as thin in order to clarify the state of the front surface (SiC surface) of the semiconductor substrate 5, and the internal structure of the semiconductor substrate 5 is omitted from the illustration. Also, in Figures 8-21, the step (step portion: not shown), terrace (atomic-level flat portion sandwiched between adjacent steps), and kink (connection portion between two steps: not shown) structures of the SiC surface are illustrated in a simplified manner. Figure 22 is a schematic diagram showing the structure of a typical semiconductor manufacturing apparatus. Figure 23 is a schematic diagram showing the structure of the radical generator (radical source) in Figure 22. Figure 24 is a chart showing the bond energy of a given bond species (energy required to break the covalent bond of 1 mole of substance).

[0063] First, as shown in Figure 4, on the front surface of an n-type starting substrate (starting wafer: not shown) made of SiC, n - For example, nitrogen (N) doped n is a type region 1. - A semiconductor substrate (SiC substrate) 5 is fabricated by epitaxially growing a type epitaxial layer 11 and a p-type epitaxial layer 12, for example, an Al-doped layer, which will become the p-type region 2, in this order. The semiconductor substrate 5 may be prepared by removing the starting substrate by grinding from the back side to the product thickness used for the silicon carbide semiconductor device, or it may be prepared with the starting substrate remaining. - Type domain 1 is n - It may be composed of a starting substrate of type n. The semiconductor substrate 5 has the first main surface on the p-type epitaxial layer 12 side as the front surface, and n - The second main surface on the side of the epitaxial layer 11 is designated as the back surface.

[0064] Next, by photolithography and ion implantation of a predetermined conductive type of impurity, n + Type source regions 3 and n + A diffusion region of a predetermined conductivity type, such as the type drain region 4 (hereinafter referred to as the SiC region), is formed (step S1 (predetermined process) in Figure 2). In ion implantation for forming the SiC region, for example, phosphorus (P) can be used as the n-type impurity, and for example, Al can be used as the p-type impurity. -A semiconductor substrate 5 of type n may be prepared, and in the process of step S1, a p-type region 2 may be selectively formed inside the semiconductor substrate 5 by ion implantation. In this case, n - p-type region 2 of the semiconductor substrate 5, n + Type source regions 3 and n + The part excluding the drain region 4 is n - This becomes type domain 1.

[0065] Between the various processes in step S1, cleaning processes such as RCA cleaning (wet cleaning using a mixed acid of strong acid and strong base) are performed to remove organic matter, particles, and ionic contamination generated in the various processes, and to prepare the semiconductor substrate 5 for the next manufacturing process. The semiconductor substrate 5 is oxidized by exposure to the atmosphere or immersion in a cleaning solution (acidic solution). Crystal defect structures containing oxygen (O) atoms and excess carbon are generated on the front surface (SiC surface) of the semiconductor substrate 5 due to SiC oxidation. Therefore, the front surface of the semiconductor substrate 5 is cleaned by etching 22, and these crystal defect structures are removed along with the surface layer of the semiconductor substrate 5 (step S2 in Figure 2, Figure 5 (predetermined process)).

[0066] The etching 22 in step S2 is H2 etching performed, for example, in the processing chamber 21 of a general etching apparatus, where the semiconductor substrate 5 is exposed to a gas atmosphere containing hydrogen (H2) gas with a purity of about 3% to 100%, and the semiconductor substrate 5 is heated to a temperature of about 1300°C to 1500°C. If the gas atmosphere for H2 etching is a mixed gas atmosphere containing gases other than H2 gas, by using noble gases that do not react easily with other atoms, such as argon (Ar), neon (Ne), or krypton (Kr), the semiconductor substrate 5 can be etched 22 without oxidation, and the re-oxidation of the front surface of the semiconductor substrate 5 can be suppressed. The gas atmosphere for H2 etching is preferably set to a pressure of about 0.5 Torr to 760 Torr and a gas flow rate of about 100 sccm or more, depending on the processing capacity (exhaust capacity) of the etching apparatus.

[0067] The etching 22 in step S2 may be replaced with H2 plasma etching instead of H2 etching. When the etching 22 in step S2 is H2 plasma etching, for example, the semiconductor substrate 5 is inserted into the processing chamber 21 of a typical plasma processing apparatus, and the surface of the semiconductor substrate 5 is exposed to the H2 plasma generated using H2 gas as a raw material gas, or the surface of the semiconductor substrate 5 is etched 22 by irradiating the surface of the semiconductor substrate 5 with hydrogen (H) active species (radicals or ions) in the H2 plasma. At this time, after inserting the semiconductor substrate 5 into the processing chamber 21, it is preferable to evacuate the processing chamber 21 to reduce the pressure (preferably to a vacuum of about 0.05 Pa or less) to reduce the amount of O2 in the processing chamber 21 as much as possible before generating the H2 plasma.

[0068] The H2 plasma may be generated after the processing chamber 21 has been evacuated two or three times. In this case, for example, after evacuating the processing chamber 21, the introduction of a noble gas such as Ar into the processing chamber 21 and the subsequent evacuation of the processing chamber 21 are repeated alternately before generating the H2 plasma. This reduces the amount of residual O2 and moisture (H2O) in the processing chamber 21 before H2 plasma etching can be performed. The pressure inside the processing chamber 21 can be, for example, a typical 1 Pa to 100 Pa. For generating the H2 plasma, general plasma generation techniques such as capacitively coupled plasma (CCP), inductively coupled plasma (ICP), and electron cyclotron resonance (ECR) plasma can be used.

[0069] H2 plasma produced by CCP plasma is generated using a radio frequency (RF) power supply in a common bandwidth (e.g., 13.56 MHz). H2 plasma produced by ICP plasma is generated by passing an RF current of 13.56 MHz, 27.12 MHz, or 40.68 MHz through a coil wound around a hollow cylindrical discharge tube, generating an electric field within the discharge tube by electromagnetic induction. This causes a portion of the H2 gas inside the discharge tube to ionize through collisions with electrons generated inside the discharge tube by the RF discharge in the coil and accelerated by the electric field inside the discharge tube. H2 plasma produced by ECR plasma is generated using microwaves (2.45 GHz). The source gas for H2 plasma may be 100% pure H2 gas or H2 gas diluted with a noble gas such as Ar.

[0070] In step S2, etching 22 may be performed using rare gas plasma etching instead of H2 etching. Rare gas plasma etching can be performed in the same way as H2 plasma etching, except that the plasma source gas is a rare gas such as Ar, Ne, or Kr instead of H2 gas. In rare gas plasma etching as well, by using a rare gas that does not react easily with other atoms, re-oxidation of the surface of the semiconductor substrate 5 can be suppressed. Rare gas plasma etching is a sputter etching method that removes the surface layer of the semiconductor substrate 5 at the atomic level by ionizing and colliding with the rare gas. For this reason, it is advisable to adjust the discharge power (RF power) for plasma generation and the bias voltage (RF voltage) applied to the semiconductor substrate 5 to avoid excessive ion collisions with the surface of the semiconductor substrate 5.

[0071] Damage to the surface of the semiconductor substrate 5 caused by ion collisions during rare gas plasma etching may be repaired by heating the semiconductor substrate 5 in an oxygen-free atmosphere before the processing in step S3 described later. An oxygen-free atmosphere means either the processing chamber 21 is evacuated, or the processing chamber 21 is filled with an inert gas atmosphere such as Ar gas or an inert gas atmosphere containing hydrogen gas. This heating treatment should be performed at a temperature of approximately 800°C or higher, which is sufficient to repair damage to the SiC surface, and 1000°C or lower, which is sufficient to prevent the deposition of graphene (excess carbon) due to Si sublimation. In the processing in step S2, after H2 etching, sacrificial oxidation of the surface of the semiconductor substrate 5 may be performed in a mixed gas atmosphere containing carbon tetrafluoride (CF4) and oxygen (O2).

[0072] Next, as shown in Figure 6, the front surface of the semiconductor substrate 5 is cleaned in the processing chamber 31 under a vacuum (oxygen-free atmosphere) (step S3 (removal process) in Figure 2). The process in step S3 will be explained with reference to Figures 3, 8 to 23. The front surface (SiC surface) of the semiconductor substrate 5 is oxidized during the process in step S2 described above and during the transport of the semiconductor substrate 5, resulting in the deposition of excess carbon originating from SiC oxidation, and becoming a Si-rich surface 5a with a relatively large number of silicon (Si) atoms (Figure 8). The excess carbon on the front surface of the semiconductor substrate 5 is incorporated into the gate insulating film 6 and becomes a hole trap level. Therefore, the excess carbon on the front surface of the semiconductor substrate 5 is removed by the process in step S3 before the process in step S4 (deposition of the gate insulating film 6) described later.

[0073] Here, we will explain using the example of a case where excess carbon (indicated as "C" in Figure 8) is present at high density over almost the entire surface of the semiconductor substrate 5. However, even if excess carbon is only partially present on the surface of the semiconductor substrate 5, the effects of the process in step S3 can be obtained. In the process in step S3, first, the semiconductor substrate 5 is inserted into the processing chamber 31 via the load lock chamber (vacuum pre-chamber) 33 preceding the processing chamber 31, so as not to open the processing chamber 31 of the vacuum apparatus 30 to the atmosphere (see Figure 22). Then, in the evacuated processing chamber 31, the surface of the semiconductor substrate 5, which has been heated by a heating means 32 such as a heater, is irradiated (first irradiation) 47 with atomic nitrogen (N) radicals (N atoms with unpaired electrons) generated in the discharge tube 41 (see Figure 23) of the radical generator 40, thereby nitriding the surface of the semiconductor substrate 5 (step S11 (first removal step) in Figure 3).

[0074] The vacuum apparatus 30 includes a heating means 32 such as a heater for heating the semiconductor substrate 5, a plurality of metal cells 36 with evaporation sources (Figure 22 shows a simplified diagram of one metal cell 36), and a radical generator 40 for generating atomic N radicals, all located within a processing chamber 31. The pressure inside the processing chamber 31 is maintained at a predetermined level by controlling the opening and closing of a gate valve 34 between the processing chamber 31 and the load lock chamber 33, and by controlling the operation of a vacuum exhaust means 35 such as a pump located downstream of the processing chamber 31. It is preferable to control the exhaust speed using the vacuum exhaust means 35 to bring the gas atmosphere inside the processing chamber 31 to a predetermined pressure before performing N radical irradiation 47 inside the processing chamber 31. Increasing the number of radical generators 40 increases the flux (total magnetic flux) of the N radical irradiation 47, allowing a predetermined irradiation amount (total supply amount) to be obtained in a short time.

[0075] The radical generator 40 is a so-called ICP plasma source (Figure 23), which is formed by coupling an RF power supply 46 to a coil 42 wound around a hollow cylindrical discharge tube 41 with a diameter of approximately 30 nm to 50 nm, via a matching box (impedance matching circuit) 45 to maximize power transfer from the RF power supply 46 into the discharge tube 41. N radicals (active species of N in N2 plasma) are generated by the ICP plasma when an RF current of, for example, 13.56 MHz is passed through the coil 42 wound around the discharge tube 41 to generate an electric field in the discharge tube 41 by electromagnetic induction, and the nitrogen (N2) gas inside the discharge tube 41 is ionized by collisions with electrons generated inside the discharge tube 41 by the RF discharge in the coil 42 and accelerated by the electric field inside the discharge tube 41.

[0076] The discharge tube 41 is made of, for example, PBN (pyrolytic boron nitride). One end 41a of the discharge tube 41 is an open end and has multiple openings 43 that serve as outlets for N radicals into the processing chamber 31 when N radicals are irradiated 47. The other end 41b of the discharge tube 41 is a supply port for N2 gas, which is the raw material gas for N radicals, and is connected to a gas supply source (not shown) via a gas pipe (piping) 44. The flow rate of N2 gas introduced into the discharge tube 41 is, for example, about 1.5 sccm (Standard Cubic Centimeter per Minute). The coil 42 is, for example, a copper (Cu) tube with a hollow section through which cold water flows. The power supplied into the discharge tube 41 from the RF power supply 46 is, for example, about 500W.

[0077] The radical generator 40 may also be an ECR plasma source that generates N radicals by passing a DC current through a coil 42 wound around a hollow cylindrical discharge tube 41 to generate a magnetic field inside the discharge tube 41, and then supplying microwaves (for example, around 2.45 GHz) to the magnetic field inside the discharge tube 41 to induce a resonance phenomenon, instead of an ICP plasma source. By adjusting the plasma conditions using an ICP plasma source or an ECR plasma source, the electron density inside the discharge tube 41 can be increased, and almost all of the N2 gas inside the discharge tube 41 can be ionized into atomic N radicals. Specifically, the flux amount of the N radical irradiation 47 is, for example, 1.0 × 10⁻⁶. 15 / cm 2 sec or more 5.0×10 15 / cm 2 It can be kept within a range of approximately 1 / sec or less.

[0078] During the process in step S11, it is preferable to heat the semiconductor substrate 5 at a temperature in the range of approximately 500°C to 800°C, where electromigration of cyano groups is likely to occur. For example, the heating temperature of the semiconductor substrate 5 should be set to approximately 800°C, and the flux amount of the N radical irradiation 47 should be 1.2 × 10⁻⁶. 15 / cm 2 If the irradiation time is set to approximately 1 second, the entire surface of the semiconductor substrate 5 will be nitrided in about 1 second. The irradiation dose of N radicals 47 can be increased by increasing the number of radical generators 40 or the irradiation time of N radicals 47. As a result of the process in step S11, the excess carbon on the surface of the semiconductor substrate 5 is nitrided to form cyano groups (-CN groups (groups in which a C atom and an N atom are bonded by a triple bond): the first group). Therefore, almost the entire surface of the semiconductor substrate 5 becomes a nitrided surface 5b (dashed line portion) due to cyano groups. The Si-rich surface 5a exposed on the surface of the semiconductor substrate 5 is also nitrided to form a Si nitrided surface 5b, so the entire surface of the semiconductor substrate 5 becomes a nitrided surface 5b (Figure 9).

[0079] After all the excess carbon on the surface of the semiconductor substrate 5 has been nitrided to form cyano groups, the surface of the semiconductor substrate 5 is further irradiated with N radicals 47 under the same conditions. During the N radical irradiation 47 on the surface of the semiconductor substrate 5, the cyano groups on the surface of the semiconductor substrate 5 move along the surface of the semiconductor substrate 5 by electromigration and collide with other nearby cyano groups. These two colliding cyano groups react immediately to form a dicyanide (NCCN) molecule in which the carbon atoms of the two cyano groups are bonded together by a single bond. Since the NCCN molecule is a gaseous low molecular weight (gas molecule) and has a short stay (adsorption) time on the surface, it desorbs from the surface of the semiconductor substrate 5. The higher the heating temperature of the semiconductor substrate 5, the more likely collisions between cyano groups are to occur, and the easier it is for the NCCN molecule to desorb from the surface of the semiconductor substrate 5, thus promoting the desorption of the NCCN molecule. N radicals are highly reactive and cause collisions between cyano groups even when the semiconductor substrate 5 is at room temperature (for example, around 25°C). For this reason, N radical irradiation 47 may be performed without heating the semiconductor substrate 5, while it remains at room temperature.

[0080] By continuing N radical irradiation 47 on the surface of the semiconductor substrate 5, the elements in the underlying layer exposed by the detachment of NCCN molecules are nitrided. If the element in the underlying layer exposed by the detachment of NCCN molecules is excess carbon, this excess carbon is nitrided to form a cyano group. The newly generated cyano group, like the cyano group generated at the beginning of the N radical irradiation 47, moves across the surface of the semiconductor substrate 5 by electromigration, collides with other nearby cyano groups, and is defused as an NCCN molecule. Because the detachment and generation of NCCN molecules occur alternately and repeatedly, the surface density of cyano groups on the surface of the semiconductor substrate 5 decreases. If the element in the underlying layer exposed by the detachment of NCCN molecules is Si, this Si (i.e., the Si-rich surface 5a) is nitrided to form a Si nitrided surface 5b (dashed line) (Figure 10). Figure 10 schematically shows the detachment of molecules with arrows. The silicon nitride (Si) nitride (Si3N4) plane 5b forms a stable, hexagonal crystal structure and does not form low molecular weight molecules. Therefore, the silicon nitride (Si) plane 5b is maintained in the areas where Si has been nitrided.

[0081] When the surface density of cyano groups on the surface of the semiconductor substrate 5 decreases due to the elimination of NCCN molecules, the distance between adjacent cyano groups increases, preventing collisions between cyano groups. As a result, cyano groups remain on the surface of the semiconductor substrate 5 at intervals approximately equal to the maximum migration distance. At this time, the density of cyano groups remaining on the surface of the semiconductor substrate 5 is 1 × 10⁻⁶. 11 atoms / cm 2 The above 1 x 10 12 atoms / cm 2 The following is the extent of the process. The irradiation time of the N radical irradiation 47 can be obtained in advance, for example, by simulation, so that cyano groups remain on the surface of the semiconductor substrate 5 at a density within the given range. On the surface of the semiconductor substrate 5, the portion where cyano groups remain becomes a nitrided surface 5b due to the cyano groups, and the Si-rich surface 5a exposed by the detachment of NCCN molecules becomes a Si nitrided surface 5b. The entire surface of the surface of the semiconductor substrate 5 becomes a nitrided surface 5b (dashed line portion), and the majority of it is a Si nitrided surface 5b (Figure 11).

[0082] Next, a layer of Ge atoms is deposited on the surface of the semiconductor substrate 5 by irradiating it with Ge atoms 37 using a vacuum deposition method (Step S12 (First Step) in Figure 3). Then, for example, N radical irradiation (Second Irradiation) 47 is performed on the surface of the semiconductor substrate 5 using the same method and conditions as in Step S11 (Step S13 (Second Step) in Figure 3). The processes in Steps S12 and S13 are carried out in a vacuum-evacuated processing chamber 31, without exposing the semiconductor substrate 5 to the atmosphere, and with the semiconductor substrate 5 heated at the same temperature as in Step S11. In the process of Step S12, a Ge metal cell (a metal cell using Ge as the metal material) 36 is heated to vaporize (sublimate) Ge atoms, and the vaporized Ge atoms (evaporated particles) are irradiated (hereinafter referred to as Ge irradiation) 37 on the surface of the semiconductor substrate 5. Since the temperature of the Ge metal cell 36 needs to be controlled to between approximately 1000°C and 1500°C, it is preferable to use, for example, electron beam heating, which can evaporate almost all elements.

[0083] This Ge irradiation 37 deposits (evaporates) a layer of several atomic layers (for example, about 1 to 5 atomic layers) of Ge atoms onto the surface of the semiconductor substrate 5, creating a state where multiple Ge atoms exist near the cyano groups remaining on the surface of the semiconductor substrate 5 (Figure 12). N radical irradiation 47 nitrides the Ge atoms and cyano groups on the surface of the semiconductor substrate 5. The Ge atoms are nitrided to become "-GeN groups (groups in which Ge atoms and N atoms are bonded by a triple bond: second group)". The "-GeN groups" move across the surface of the semiconductor substrate 5 by electromigration, colliding with other nearby "-GeN groups" and nearby cyano groups, and forming molecules with these groups. Most of the "-GeN groups" become Ge3N4 molecules, which are formed by covalent bonds (single bonds) with N atoms, with three "-GeN groups" bonded together. The cyano group is bonded to two "-GeN groups" by a covalent bond (single bond) with the N atom, forming a Ge2N3-CN molecule (Figure 13).

[0084] These Ge3N4 and Ge2N3-CN molecules are gaseous low-molecular-weight molecules (gas molecules), and have a short stay (adsorption) time on the surface, so they detach from the surface of the semiconductor substrate 5. Figure 13 schematically shows the detachment of molecules with arrows. Therefore, by performing the treatment combination of steps S12 and S13 (Ge irradiation 37 and N radical irradiation 47) multiple times (step S14 (second removal step): No. in Figure 3), the surface density of "-GeN groups" and cyano groups on the surface of the semiconductor substrate 5 decreases. The "-GeN groups" and cyano groups on the surface of the semiconductor substrate 5 have the same mechanism for forming low-molecular-weight molecules and detaching. For this reason, the maximum migration distance of "-GeN groups" and cyano groups is almost the same, and the probability of collision between groups is almost the same. All cyano groups (groups containing excess carbon) on the front surface of the semiconductor substrate 5 are removed by collisions with the newly generated "-GeN groups" in steps S12 and S13.

[0085] The "-GeN groups" on the surface of the semiconductor substrate 5 behave similarly to the cyano groups on the surface of the semiconductor substrate 5 during the processing in step S11. With each pair of processing steps S12 and S13, collisions with neighboring "-GeN groups" cease, and the "-GeN groups" remain on the surface of the semiconductor substrate 5 at intervals approximately equal to the maximum migration distance of the "-GeN groups". The density of these "-GeN groups" remaining on the surface of the semiconductor substrate 5 is approximately the same as the density of cyano groups remaining on the surface of the semiconductor substrate 5 after the processing in step S11. At this time, the surface of the semiconductor substrate 5 becomes a nitrided surface 5b due to the "-GeN groups" in the areas where the "-GeN groups" remain, and the nitrided surface 5b of Si is maintained in the areas between adjacent "-GeN groups" by repeating the processing in step S13 (irradiation with N radicals 47). Therefore, the entire surface of the front side of the semiconductor substrate 5 is a nitrided surface 5b (dashed line portion), and the majority of it is a Si nitrided surface 5b (Figure 14).

[0086] The number of times the set of steps S12 and S13 should be performed can be determined in advance, for example, by simulation, so that all cyano groups on the surface of the semiconductor substrate 5 are replaced with "-GeN groups". On the other hand, if the gate insulating film 6 is deposited while Ge atoms (i.e., "-GeN groups") remain on the surface of the semiconductor substrate 5, an oxide containing Ge atoms will be formed at the interface between the gate insulating film 6 and the semiconductor substrate 5. The oxide containing Ge atoms is a silicate ([SiO4]) that constitutes the siloxane bond (-Si-O-Si group) of the gate insulating film 6. 4- The central metal atom (Si atom) is a Ge atom (Ge 4+ This is an oxide in which Ge atoms are substituted. Oxides containing Ge atoms are highly conductive of electrons (easily transfer and release them: Figure 15), so electron trap levels easily form at the interface between the gate insulating film 6 and the semiconductor substrate 5, which adversely affects gate characteristics such as gate threshold voltage fluctuations and decreased electron mobility.

[0087] Therefore, after the removal of cyano groups from the surface of the semiconductor substrate 5 is completed (Step S14 (Second Removal Step) in Figure 3: Yes), it is preferable to reduce the density of Ge atoms on the surface of the semiconductor substrate 5 by irradiating and depositing Mg atoms 38 onto the surface of the semiconductor substrate 5 using a vacuum deposition method (Step S15 (Third Removal Step) in Figure 3). The process in Step S15 is preferably carried out in the same vacuum-evacuated processing chamber 31 as the processes in Steps S12 and S13, and is carried out immediately after the final process in Step S13. In the process in Step S15, first, the temperature of the semiconductor substrate 5 is raised to a temperature in the range of approximately 1000°C to 1100°C (for example, approximately 1070°C). Next, a metal cell of Mg (a metal cell using Mg as the metallic material) 36 is heated by, for example, electron beam heating or resistance heating, to vaporize (sublimate) the Mg atoms (evaporated particles), and these Mg atoms are irradiated onto the surface of the semiconductor substrate 5 (hereinafter referred to as Mg irradiation) 38, thereby depositing (vapor-depositing) a layer of Mg atoms onto the surface of the semiconductor substrate 5.

[0088] Because the vapor pressure of Mg is very high, even when resistance heating is used to heat the Mg metal cell 36 to a temperature of approximately 350°C to 450°C, a sufficient amount of flux required for Mg irradiation 38 can be obtained. For this reason, resistance heating is used in Mg irradiation 38, and a Mg metal cell 36 specialized for low-temperature control may be used. Generally, when using commercially available Mg metal cells 36, the surface of the metal cell 36 is covered with surface oxides and hydroxides, so when the Mg metal cell 36 is heated and Mg atoms are vaporized, flake-like dust is scattered from the surface of the Mg metal cell 36. For this reason, it is advisable to perform a purification treatment to remove surface oxides and hydroxides from the commercially available Mg metal cell 36 before use. The amount of flux required for Mg irradiation 38 is, for example, 1.0 × 10⁻⁶. 15 / cm 2 sec or more 5.0×10 15 / cm 2 It is within a range of approximately 1 / sec or less.

[0089] The flux amount range for the Mg irradiation 38 described above is excessive, to the point that if all irradiated Mg atoms were deposited on the surface of the semiconductor substrate 5, several atomic layers of Mg atoms would be deposited in one second. However, the number of Mg atoms deposited on the surface of the semiconductor substrate 5 is limited. Only one atomic layer of Mg atoms is deposited on the surface of the semiconductor substrate 5 by one Mg irradiation 38. The excess Mg atoms (elementary Mg atoms) that are not deposited on the surface of the semiconductor substrate 5 evaporate (vaporize) as their vapor pressure increases with the heating temperature of the semiconductor substrate 5. If the semiconductor substrate 5 is heated to, for example, about 1070°C, the vapor pressure of Mg atoms near the surface of the semiconductor substrate 5 is 1 atmosphere (≈ 1 × 10⁻⁶). 5 It is approximately Pa. Although not shown in Figures 16 and 17 described later, the evaporation of excess Mg atoms occurs continuously during the process in step S15. Also, the density of Mg atoms deposited on the surface of the semiconductor substrate 5 does not exceed the density of N atoms on the surface of the semiconductor substrate 5. The density of N atoms when the entire surface of the surface of the semiconductor substrate 5 is a nitrided surface 5b is 10 15 atoms / cm 2 It is to that extent.

[0090] In step S15, the density of Ge atoms on the surface of the semiconductor substrate 5 is reduced by supplying an excess amount of Mg atoms that exceeds the amount of Mg atoms deposited on the surface of the semiconductor substrate 5 (1 atomic layer), thereby promoting the reduction of the nitrided surface 5b (desorption of N atoms from the nitrided surface 5b). Specifically, among the metal atoms (Ge atoms, Si atoms, and Mg atoms) present on the surface of the semiconductor substrate 5 during step S15, Mg atoms have a higher electronegativity than the other metal atoms and the largest bond energy with N atoms (the negative energy of the electrons) (see Figure 24). The nitrided surface 5b with the "-GeN group", which has the smallest bond energy with N atoms, is reduced, and N atoms are desorbed from the nitrided surface 5b with the "-GeN group". The Mg atom combines with the N atom that has been removed from the nitrided surface 5b by the "-GeN group" to form a "-MgN group" (a group in which the Mg atom and the N atom are bonded in a triple bond) and remains on the surface of the semiconductor substrate 5. In other words, the Mg atom pulls a shared electron pair from the nitrided surface 5b by the "-GeN group," increasing its electron density (oxidation), stabilizing as a "-MgN group," and remains on the surface of the semiconductor substrate 5 (Figure 16). Figure 16 schematically shows the direction of movement of the N atom of the "-GeN group" with arrows.

[0091] The elemental Ge atoms, whose bonds with N atoms are broken by the reduction of the nitrided surface 5b by the "-GeN group," evaporate as their vapor pressure increases at the heating temperature of the semiconductor substrate 5 (Figure 17). Figure 17 schematically shows the evaporation of elemental Ge atoms with arrows. When the semiconductor substrate 5 is heated to, for example, about 1070°C, the vapor pressure of Ge atoms near the surface of the semiconductor substrate 5 is about 1 atmosphere. When an excess of Mg atoms is supplied to the surface of the semiconductor substrate 5, exceeding the amount of Mg atoms deposited, the reduction of the nitrided surface 5b is promoted, and the Si nitrided surface 5b is also reduced. The Si nitrided surface 5b becomes a Si-rich surface 5a as its bonds with N atoms are broken. In addition, the bond energy between N atoms is overwhelmingly larger than the bond energy between Mg atoms and N atoms (see Figure 24). Therefore, when "-MgN groups" collide with each other, the N atoms of the "-MgN groups" bond together to form nitrogen (N2) molecules (low molecular weight gaseous molecules), which then detach from the surface of the semiconductor substrate 5. The elemental Mg atoms, whose bonds with the N atoms have been broken, evaporate (vaporize) depending on the heating temperature of the semiconductor substrate 5 (Figure 18). Figure 18 schematically shows the evaporation of N2 molecules and the evaporation of elemental Mg atoms with arrows.

[0092] The evaporation of elemental Ge atoms, N2 molecules, and elemental Mg atoms due to the reduction of the nitrided surface 5b described above continues until collisions between "-MgN groups" cease, and "-MgN groups" remain on the surface of the semiconductor substrate 5 at intervals that prevent collisions between "-MgN groups". The surface of the semiconductor substrate 5 becomes a Si-rich surface 5a, except for the areas where "-MgN groups" remain (Figure 19). Even if an excess of Mg atoms is supplied to the surface of the semiconductor substrate 5, the density of Mg atoms remaining on the surface of the semiconductor substrate 5 is 1 × 10⁻¹⁶ 11 atoms / cm 2 The above 1 x 10 13 atoms / cm 2 The following is an example. Depending on the reduction rate of the nitrided surface 5b, it is preferable to control the amount of Mg atoms supplied per unit time to the front surface of the semiconductor substrate 5 by repeatedly alternating between Mg irradiation 38 (supply of Mg atoms) and pausing Mg irradiation 38 (non-supply of Mg atoms) multiple times. For example, the flux amount is 5.0 × 10 15 / cm 2If a set of 2 seconds of Mg irradiation 38 followed by a 20-second pause in Mg irradiation 38 is repeated five times, the total density of Mg atoms irradiated onto the surface of the semiconductor substrate 5 will be 5 × 10⁻¹⁴. 16 atoms / cm 2 The density of Mg atoms remaining on the surface of semiconductor substrate 5 is approximately 2 × 10⁻⁶. 12 atoms / cm 2 It is to that extent.

[0093] Therefore, to ensure that "-MgN groups" remain on the surface of the semiconductor substrate 5 at intervals that prevent collisions between "-MgN groups", the irradiation conditions for Mg irradiation 38, the pause time for Mg irradiation 38, and the number of times the Mg irradiation 38 and pause combinations are performed can be obtained in advance, for example, through simulation. Even after the processing in step S15, Ge atoms remain on the surface of the semiconductor substrate 5 at a certain density, but the density of Ge atoms on the surface of the semiconductor substrate 5 can be reduced to such an extent that even if these Ge atoms become electron trap levels, it will not adversely affect the gate characteristics (not shown in Figures 18-21). Furthermore, it is presumed that the density of N atoms remaining on the surface of the semiconductor substrate 5 after the processing in step S15 is the same as the density of Mg atoms (density of "-MgN groups") remaining on the surface of the semiconductor substrate 5 after the processing in step S15. Therefore, it is estimated that the density of N atoms on the front surface of the semiconductor substrate 5 after the treatment in step S15 is about three orders of magnitude lower than the total density of Si, Ge, and Mg atoms, resulting in a relatively wide Si-rich surface 5a. In the treatment in step S15, instead of Mg irradiation 38, other alkaline earth metal atoms such as calcium (Ca), strontium (Sr), and barium (Ba) may be irradiated onto the front surface of the semiconductor substrate 5 and deposited.

[0094] If the density of N atoms on the surface of the semiconductor substrate 5 is relatively low, the surface of the semiconductor substrate 5 is easily activated, and the adsorption of trace amounts of gas onto the surface of the semiconductor substrate 5 occurs easily. Therefore, by irradiating the surface of the semiconductor substrate 5 with N radicals 47, the Si-rich surface 5a of the surface of the semiconductor substrate 5 is converted into a Si nitride surface 5b, thereby nitriding and deactivating (passivating) the entire surface of the surface of the semiconductor substrate 5 (Step S16 in Figure 3, Figure 20). The process in Step S16 is carried out in the same vacuum-evacuated processing chamber 31 as in the process in Step S15, without exposing the semiconductor substrate 5 to the atmosphere, and using, for example, the same method and conditions as in the process in Step S11, with a flux amount of, for example, 1.0 × 10⁻⁶. 15 / cm 2 This process is performed for approximately 20 seconds. Instead of N radical irradiation 47 in step S16, the surface of the semiconductor substrate 5 may be nitrided by heat treatment under the same conditions as the process in step S5 described later.

[0095] Next, an oxide film (SiO2) that will become the gate insulating film 6 is deposited on the front surface of the semiconductor substrate 5 (Step S4 in Figure 2, Figure 7 (First Formation Process)). In the process of Step S4, for example, a high-temperature oxide layer (HTO) may be deposited as the gate insulating film 6 by the Low-Pressure Chemical Vapor Deposition (LPCVD) method. Alternatively, the gate insulating film 6 may be deposited by vacuum deposition in the same vacuum-evacuated processing chamber 31 as in the process of Step S16, without exposing the semiconductor substrate 5 to the atmosphere. In this case, the vacuum apparatus 30 (see Figure 22) further includes a Si evaporation source (not shown) and a radical generator (radical source: not shown) that generates atomic oxygen (O) radicals in the processing chamber 31. The radical generator 40 (see Figure 23) of the vacuum apparatus 30 may have the function of generating multiple types of radicals. The method for generating O radicals is the same as the method for generating N radicals, except that the source gas is O2 gas.

[0096] During the process in step S4, since all excess carbon on the surface of the semiconductor substrate 5 has been removed in the process in step S3 described above, no crystal defects caused by excess carbon occur at the interface between the gate insulating film 6 and the semiconductor substrate 5. Also, during the process in step S4, Ge atoms ("-GeN groups": not shown) and Mg atoms ("-MgN groups") remaining on the surface of the semiconductor substrate 5 are incorporated into the gate insulating film 6 (Figure 21). The density of Ge atoms remaining on the surface of the semiconductor substrate 5 is 1 × 10⁻¹⁶ 8 atoms / cm 2 The above 1 x 10 12 atoms / cm 2 Because the level is low, even if Ge atoms at the interface between the gate insulating film 6 and the semiconductor substrate 5 reach electron trap levels, it does not adversely affect the gate characteristics. Although the density of Mg atoms remaining on the surface of the semiconductor substrate 5 is relatively high, these Mg atoms are transformed into oxide (MgO) by the treatment in step S5 described later and by heat treatment and thermal history in subsequent processes, resulting in a large band gap and virtually no electron flow. For this reason, Mg atoms at the interface between the gate insulating film 6 and the semiconductor substrate 5 do not reach trap levels. The thickness of the gate insulating film 6 is, for example, about 50 nm.

[0097] Next, the interface between the gate insulating film 6 and the semiconductor substrate 5 is oxynitrided by heat treatment (oxynitriding annealing) in a heat treatment furnace at an atmospheric pressure atmosphere of approximately 1150°C to 1300°C using a gas containing N atoms and oxygen (O) atoms (for example, a mixed gas of 90% N2 gas and 10% N2O gas) (Step S5 (Heat Treatment Process) in Figure 2). The process in Step S5 assimilates the interface between the gate insulating film 6 and the semiconductor substrate 5 (nitrided surface 5b) and the "-GeN groups" and "-MgN groups" at the interface between the gate insulating film 6 and the semiconductor substrate 5 with the gate insulating film 6. The "-GeN groups" at the interface between the gate insulating film 6 and the semiconductor substrate 5 are transformed into oxides or oxynitrides within the gate insulating film 6. The "-MgN groups" at the interface between the gate insulating film 6 and the semiconductor substrate 5 undergo thermal decomposition, and the Mg atoms and N atoms are transformed into oxides, respectively. The Mg atoms are converted into an oxide (magnesium oxide (MgO)) in the gate insulating film 6, and the oxide (gas) of the N atoms evaporates and is exhausted to the outside of the heat treatment furnace.

[0098] Next, a gate electrode 7 is formed on the surface of the gate insulating film 6 (step S6 (second formation step) in Figure 2). In the process of step S6, a polysilicon layer is deposited by a general deposition method such as LPCVD, and the portion that will become the gate electrode 7 is left by patterning the polysilicon layer. A portion of the polysilicon layer may be extended in the region excluding the active region to form a gate polysilicon wiring layer that functions as a gate runner. Next, an interlayer insulating film 8 is formed on the entire surface of the front surface of the semiconductor substrate 5. Next, contact holes 8a and 8b that penetrate the interlayer insulating film 8 and the gate insulating film 6 in the depth direction, and a contact hole 8c that penetrates the interlayer insulating film 8 in the depth direction are formed.

[0099] Next, an aluminum (Al) film or an Al alloy film is deposited on the front surface of the semiconductor substrate 5 and patterned to form a source electrode 13, a drain electrode 14, a gate metal wiring layer 15, and a gate pad (not shown) as surface electrodes (step S7 in Figure 2). The source electrode 13 is formed in the contact hole 8a n + It is electrically connected to the source region 3. The drain electrode 14 is connected to the contact hole 8b. + It is electrically connected to the drain region 4. The gate polysilicon wiring layer is formed on the front surface of the semiconductor substrate 5 via a field oxide film (not shown). The gate metal wiring layer 15 is formed on the gate polysilicon wiring layer at the contact hole 8c and functions as a gate runner.

[0100] The field oxide film can be formed at any timing before the formation of the interlayer insulating film 8. The interlayer insulating film 8 may also serve as the field oxide film. Then, the entire front surface of the semiconductor substrate 5 is covered and protected with a passivation film (not shown). Then, the passivation film is partially removed by photolithography and etching, and the portions that will become electrode pads (source pad, drain pad, and gate pad) are exposed in different openings of the passivation film, thereby completing the silicon carbide semiconductor device 10 (lateral MOSFET) of FIG. 1. The portion of the source electrode 13 that is exposed in the opening of the passivation film functions as the source pad. The portion of the drain electrode 14 that is exposed in the opening of the passivation film functions as the drain pad.

[0101] Also, in the method for manufacturing a silicon carbide semiconductor device according to the above-described embodiment, instead of the lateral MOSFET, a vertical MOSFET having a planar gate structure may be fabricated. In this case, at the time of the process of step S1, an n + type drain region n + type starting substrate, epitaxial layers 11 and 12 that will become the n - type region 1 and the p-type region 2 are epitaxially grown, and at the time of the process of step S7, a train electrode is formed on the back surface of the n + type starting substrate. The n + type drain region may be formed by ion implantation of n-type impurities into the back surface of the semiconductor substrate 5 before the process of step S7. In this method for manufacturing a vertical MOSFET, instead of the planar gate structure, a trench gate structure may be formed.

[0102] FIG. 25 is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device according to an embodiment. The silicon carbide semiconductor device 50 according to the embodiment shown in FIG. 25 is a vertical MOSFET having a trench gate structure to which the structure of the silicon carbide semiconductor device 10 according to the embodiment shown in FIG. 1 is applied, and includes a trench gate structure in which a gate electrode 67 is embedded via a gate insulating film 66 in a trench 65 formed on the front surface side of a semiconductor substrate 54. The semiconductor substrate 54 is an n +On the front surface of the n-type starting substrate (bulk substrate) 51, - The n-type drift region (first semiconductor region) 62 and the p- - type base region (second semiconductor region) 63 are formed by epitaxially growing epitaxial layers 52 and 53 in this order, which is a semiconductor chip.

[0103] The semiconductor substrate 54 has the first main surface on the epitaxial layer 53 side as the front surface, and the n- + type starting substrate 51 side second main surface as the back surface. The n- + type starting substrate 51 is the n- + type drain region 61. Between the front surface of the semiconductor substrate 54 and the p- - type base region 63, on the front surface of the semiconductor substrate 54 and in contact with the p- - type base region 63, an n- + type source region (third semiconductor region) 64 and a p- + type contact region (not shown) are selectively provided respectively. The n- + type source region 64 and the p- + type contact region are diffusion regions formed by ion implantation into the epitaxial layer 53. The portion of the p-type epitaxial layer 53 excluding the n- + type source region 64 and the p- + type contact region becomes the p- - type base region 63.

[0104] The trench 65 penetrates from the front surface of the semiconductor substrate 54 through the n- + type source region 64 and the p- - type base region 63 to the n- -It terminates inside the mold drift region 62. The trench 65 preferably has a substantially tapered cross-sectional shape, narrowing in width from the opening towards the bottom. This is because, by inclining the side walls of the trench 65 at an obtuse angle with respect to the bottom surface of the trench 65, the amount of flux per unit time for N radical irradiation 47, Ge irradiation 37, and Mg irradiation 38 (see Figure 6) on the side walls of the trench 65 during the process of step S3 described above can be increased compared to the case where the side walls and bottom surface of the trench 65 are at a substantially right angle. A gate insulating film 66 is provided along the inner walls (side walls and bottom surface) of the trench 65.

[0105] The configuration of the gate insulating film 66 is the same as that of the gate insulating film 6 in Figure 1, except that it is provided along the inner wall of the trench 65. The configuration of the interface between the gate insulating film 66 and the semiconductor substrate 54 is the same as that of the interface between the gate insulating film 6 and the semiconductor substrate 5 in Figure 1. That is, Ge atoms and Mg atoms are present at the interface between the gate insulating film 66 and the semiconductor substrate 54. The Ge atoms at the interface between the gate insulating film 66 and the semiconductor substrate 54 are assimilated with the gate insulating film 66 by forming oxides or oxynitrides within the gate insulating film 66. The Mg atoms at the interface between the gate insulating film 66 and the semiconductor substrate 54 are assimilated with the gate insulating film 66 by forming oxides within the gate insulating film 66. The interfaces between the gate insulating film 66 and the semiconductor substrate 54 are the interface between the gate insulating film 66 and the inner wall of the trench 65 (SiC surface), and the interface between the gate insulating film 66 and the front surface of the semiconductor substrate 54 (SiC surface).

[0106] The gate electrode 67 is provided on the gate insulating film 66 inside the trench 65. The gate electrode 67 may protrude upward from inside the trench 65. The configuration of the gate electrode 67 is the same as that of the gate electrode 7 in Figure 1, except that it is embedded inside the trench 65. The interlayer insulating film 68 is provided over the entire surface of the front surface of the semiconductor substrate 54 and covers the gate electrode 67. The configuration of the interlayer insulating film 68, contact holes 68a, 68c, source electrode 69, gate metal wiring layer 60 and gate pad (not shown) is the same as that of the interlayer insulating film 8, contact holes 8a, 8c, source electrode 13, gate metal wiring layer 15 and gate pad (not shown) in Figure 1. The drain electrode 55 is provided over the entire back surface of the semiconductor substrate 54, n + It is electrically connected to the drain region 61.

[0107] The method for manufacturing the silicon carbide semiconductor device 50 according to the embodiment shown in Figure 25 is the same as the method for manufacturing the silicon carbide semiconductor device 10 according to the embodiment shown in Figure 1 (see Figures 2 and 3), but with the processing of step S1 (n + Type source region 64 and p + After the formation of the contact region, the trench 65 can be formed, and then the processes in steps S2 to S7 can be carried out as described above. To form the trench 65, first, an oxide film (SiO2) that serves as an etching mask is deposited on the surface of the semiconductor substrate 5, for example by CVD, and the portion of the oxide film corresponding to the trench 65 formation region is opened by photolithography and dry etching using a mixed gas containing, for example, methane trifluoride (CHF3) gas, CF4 gas, and Ar gas. Then, the resist mask used to open the oxide film is removed.

[0108] Using this oxide film as a mask, trenches 65 are formed by dry etching using a mixed gas containing sulfur hexafluoride (SF6) gas, O2 gas, and Ar gas, for example, using an ICP etching apparatus. Then, the oxide film used as the etching mask is removed, for example, by hydrofluoric acid (HF). After removing the oxide film used as the etching mask, heat treatment may be performed to control the cross-sectional shape of the trenches 65 before the process in step S2. In the process in step S2, the inner walls of the trenches 65 and the front surface of the semiconductor substrate 54 are cleaned by etching 22, etc. (see Figure 5). In the process in step S3, the inner walls of the trenches 65 and the front surface of the semiconductor substrate 54 are irradiated with N radicals 47, Ge 37, and Mg 38 (see Figures 3 and 6).

[0109] During N radical irradiation 47, Ge irradiation 37, and Mg irradiation 38, the amount of flux per unit time applied to the sidewall of the trench 65 (the surface inclined with respect to the front surface of the semiconductor substrate 54) is less than the amount of flux per unit time applied to the front surface of the semiconductor substrate 54. Therefore, when forming a trench gate structure, it is preferable to increase the irradiation time compared to when manufacturing a lateral MOSFET to ensure a predetermined amount of N radical irradiation 47, Ge irradiation 37, and Mg irradiation 38 applied to the sidewall of the trench 65. In the process of step S4, a gate insulating film 66 is deposited from the inner wall of the trench 65 to the front surface of the semiconductor substrate 54. In the process of step S6, a gate electrode 67 is embedded on the gate insulating film 66 inside the trench 65 to form a trench gate structure.

[0110] As described above, according to the embodiment, all excess carbon deposited on the surface of the semiconductor substrate is removed in advance before depositing the gate insulating film. The excess carbon deposited on the surface of the semiconductor substrate can be easily removed by rearranging the bonds between the excess carbon, N atoms irradiated onto the surface of the semiconductor substrate, and Ge atoms deposited on the surface of the semiconductor substrate, and by utilizing the electromigration phenomenon. Ge atoms remain at the interface between the gate insulating film and the semiconductor substrate of the product (silicon carbide semiconductor device) in place of the excess carbon, and there is no excess carbon. By not having excess carbon that would become a hole trap level at the interface between the gate insulating film and the semiconductor substrate, a decrease in channel mobility can be prevented.

[0111] Furthermore, according to the embodiment, before depositing the gate insulating film, the density of Ge atoms remaining on the surface of the semiconductor substrate is reduced to such an extent that even if Ge atoms remaining at the interface between the gate insulating film and the semiconductor substrate become electron trap levels, it will not adversely affect the gate characteristics. The Ge atoms remaining on the surface of the semiconductor substrate can be easily reduced by rearranging the bonds between the Ge atoms, Si atoms or N atoms bonded to Ge atoms on the surface (nitride surface) of the semiconductor substrate, and Mg atoms deposited on the surface of the semiconductor substrate, and by oxidation-reduction reactions due to the bond energy difference. By reducing the density of Ge atoms at the interface between the gate insulating film and the semiconductor substrate to such an extent that it does not adversely affect the gate characteristics, the reliability of the silicon carbide semiconductor device can be improved.

[0112] Furthermore, according to this embodiment, Ge and Mg atoms present at the interface between the gate insulating film and the semiconductor substrate are incorporated into the gate insulating film and assimilated into it. As a result, the insulating properties of the gate insulating film are maintained. The Mg atoms at the interface between the gate insulating film and the semiconductor substrate become oxides within the gate insulating film, resulting in a large band gap and virtually no electron flow, thus preventing them from becoming trap levels. Therefore, an increase in the interface level density at the interface between the gate insulating film and the semiconductor substrate can be prevented.

[0113] (Verification example) The effect of the treatment in step S3 (cleaning of the SiC surface) of the silicon carbide semiconductor device manufacturing method according to the above embodiment (see Figures 2 and 3) was verified using a general MOS capacitor (not shown). Figure 26 is a chart showing the results of measuring the interface state density at the SiO2 / SiC interface for Examples 1 and 2 and Comparative Example 1. Figure 27 is a chart showing the results of calculating the field effect mobility for Example 3 and Comparative Example 2 by simulation. MOS capacitors (hereinafter referred to as Examples 1 and 2) were fabricated on an n-type SiC substrate according to the manufacturing method of the silicon carbide semiconductor device 10 according to the above embodiment.

[0114] The SiC substrate is an epitaxial substrate formed by depositing a 5 μm thick n-type epitaxial layer on the front surface of a bulk substrate made of 4H-SiC (four-layer periodic hexagonal silicon carbide) after planarizing the front surface by CMP (Chemical Mechanical Polishing). The front surface of the SiC substrate is a (0001) plane, the so-called Si plane, with an off-angle of about 4 degrees in the <11-20> direction. A gate insulating film and an Al gate electrode layer were deposited in this order on the front surface of the SiC substrate (the main surface on the epitaxial layer side), and an Al electrode layer was deposited on the back surface of the SiC substrate (the main surface on the bulk substrate side).

[0115] The SiC substrate, gate insulating film, and Al gate electrode layer of Examples 1 and 2 correspond to the semiconductor substrate 5, gate insulating film 6, and gate electrode 7 in Figure 1, respectively. Examples 1 and 2 were fabricated by first performing RCA cleaning and H2 etching on the front surface (SiC surface) of the SiC substrate (corresponding to steps S1 and S2 in Figure 2), then removing excess carbon from the SiC surface by cleaning the SiC surface (corresponding to step S3 in Figure 2), depositing a gate insulating film on the SiC surface (corresponding to step S4 in Figure 2), and finally performing oxynitriding annealing, deposition of the Al gate electrode layer, and deposition of the Al electrode layer (corresponding to steps S5 to S7 in Figure 2).

[0116] Examples 1 and 2 use the same processing conditions for steps S2 and S4-S7, but differ in the processing conditions for step S3 (surface treatment conditions for cleaning the SiC surface). For the H2 etching in step S2, the H2 gas pressure was set to 700 Pa and the SiC substrate temperature to 1450°C for 5 minutes. In Example 1, the processing in step S3 corresponds to the processing in steps S11-S14 in Figure 3, but steps S15 and S16 in Figure 3 are not performed (surface treatment conditions: Ge irradiation). In Example 2, the processing in step S3 is performed as shown in steps S11-S16 in Figure 3 (surface treatment conditions: Ge irradiation + Mg irradiation).

[0117] In step S4 (deposition of gate insulating film), LPCVD was used, with a deposition gas mixture of SiH4 and O2, a pressure in the processing chamber of 0.2 Pa, and a SiC substrate temperature of 600°C to deposit HTO with a thickness of approximately 50 nm as the gate insulating film. Step S5 (oxynitriding annealing) was performed at atmospheric pressure at a temperature of 1200°C for 60 minutes using a gas mixture of 90% N2 and 10% NO. Steps S6 and S7 (formation of electrode layer) were performed using vacuum deposition by resistance heating. The Al gate electrode layer was formed into a circular planar shape with a diameter of 200 μm using a metal mask.

[0118] Comparative Example 1 is a MOS capacitor manufactured according to the silicon carbide semiconductor device manufacturing method of the Reference Example (see Figure 28). Comparative Example 1 is the same as Examples 1 and 2 except that the processing in step S3 is not performed (surface treatment condition: no surface treatment). The processing conditions in steps S102 to S106 of Comparative Example 1 are the same as the processing conditions in steps S2, S4 to S7 of Examples 1 and 2, respectively. The interface state density of the SiO2 / SiC interface (interface between the gate insulating film and the SiC substrate) in Figure 26 was calculated using the High-Low CV method with the measured high-frequency CV characteristics at 1 MHz and low-frequency CV characteristics at 100 Hz for Examples 1, 2 and Comparative Example 1.

[0119] As shown in Figure 26, in Examples 1 and 2, Ge atoms remain at the SiO2 / SiC interface due to Ge irradiation (corresponding to the treatment in step S12), but the interface state density (crystal defect density) at the SiO2 / SiC interface is reduced compared to Comparative Example 1, which did not undergo Ge irradiation. In Example 2, Ge atoms remain at the SiO2 / SiC interface due to Mg irradiation (corresponding to the treatment in step S15), but the density of Ge atoms remaining at the SiO2 / SiC interface is lower than in Example 1, which did not undergo Mg irradiation, resulting in a lower interface state density at the SiO2 / SiC interface compared to Example 1.

[0120] Therefore, it was confirmed that by the processing in steps S11 to S14 of the manufacturing method of the silicon carbide semiconductor device 10 according to the embodiment (see Figure 3), all excess carbon on the SiC surface can be removed, and the interface state density of the SiO2 / SiC interface can be reduced. Furthermore, it was confirmed that by the processing in step S15 of the manufacturing method of the silicon carbide semiconductor device 10 according to the embodiment, the Ge atoms remaining at the SiO2 / SiC interface can be reduced, and the interface state density of the SiO2 / SiC interface can be further reduced.

[0121] Therefore, based on the interface state densities of the SiO2 / SiC interface in Example 2 and Comparative Example 1 described above, the field-effect mobility of a lateral MOSFET (hereinafter referred to as Example 3 and Comparative Example 2) having the structure of the silicon carbide semiconductor device 10 according to the embodiment of Figure 1 is calculated and the results are shown in Figure 27. Example 3 and Comparative Example 2 each have an insulated gate structure formed under the same conditions as Example 2 and Comparative Example 1 described above. In Example 3, the semiconductor substrate 5 is formed on the front surface of the starting substrate, a 4H-SiC substrate, with n - n becomes type domain 1 - The material is formed by epitaxially growing a type-type epitaxial layer 11 and a p-type epitaxial layer 12 that becomes the p-type region 2 in this order.

[0122] The front surface of the 4H-SiC substrate is a (0001) plane with an off-angle of approximately 4 degrees in the <11-20> direction. The dopant of the epitaxial layer 11 is nitrogen (N). The dopant and acceptor concentrations of the p-type epitaxial layer 12 are N.A These are aluminum (Al) and 1 × 10 16 / cm 3 n + Type source regions 3 and n + The drain region 4 is a SiC region formed by phosphorus (P) ion implantation into the epitaxial layer 12. RCA cleaning and HF cleaning were performed on the SiC surface (surface of the 4H-SiC substrate, exposed surfaces of epitaxial layers 11 and 12) between various processes such as epitaxial growth and impurity ion implantation (corresponding to step S1 in Figure 2).

[0123] On the front surface (SiC surface: the surface facing the epitaxial layer 12) of the semiconductor substrate 5, the gate insulating film 6 was deposited after performing the same treatment as in Example 2, specifically step S2 in Figure 2 and step S3 in Figure 3 (surface treatment conditions: Ge irradiation 37 + Mg irradiation 38) (corresponding to step S4 in Figure 2). Therefore, in Example 3, as in Example 2, Mg atoms and Ge atoms remain at the interface between the gate insulating film 6 and the semiconductor substrate 5 (SiO2 / SiC interface). After oxynitriding annealing, the gate electrode 7 was deposited on the gate insulating film 6. The conditions for depositing the gate insulating film 6 and oxynitriding annealing (corresponding to steps S4 and S6 in Figure 2) were the same as in Example 2.

[0124] The gate electrode 7 is a 50 nm thick polysilicon layer deposited using the LPCVD method. An interlayer insulating film 8 was deposited on the front surface of the semiconductor substrate 5 so as to cover the gate electrode 7. The interlayer insulating film 8 is a 700 nm thick SiO2 film deposited by the plasma-enhanced chemical vapor deposition (PECVD) method. Contact holes 8a to 8c were formed in the interlayer insulating film 8 by photolithography and either dry etching using boron trichloride (BCl3) gas with an ICP etching apparatus or wet etching using a buffered hydrofluoric acid (BHF) solution.

[0125] Al electrode films were deposited as the source electrode 13, drain electrode 14, and gate metal wiring layer 15, respectively, to fill the contact holes 8a to 8c (corresponding to step S7 in Figure 2). The source electrode 13 and drain electrode 14 include a nickel silicide film as an ohmic electrode film and a Ti film as a barrier metal between the Al electrode film and the semiconductor substrate 5. Comparative Example 2, like Comparative Example 1, did not undergo the treatment in step S3 in Figure 2 (surface treatment conditions: no surface treatment), and there were no Mg or Ge atoms at the SiO2 / SiC interface. The conditions for Comparative Example 2 were the same as those for Example 3, except for the state of the SiO2 / SiC interface.

[0126] As shown in Figure 27, Example 3 showed a significantly larger peak value (maximum value) of field-effect mobility compared to Comparative Example 2. It was confirmed that the reduction in the interface state density at the SiO2 / SiC interface (see Figure 26) greatly contributed to the improvement in field-effect mobility.

[0127] In summary, this disclosure is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of this disclosure. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but this disclosure also holds true if the first conductivity type is p-type and the second conductivity type is n-type. Furthermore, although each embodiment was described using a MOSFET, it also holds true if an IGBT is used. [Industrial applicability]

[0128] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to this disclosure are useful for power semiconductor devices used in power converters, power supply devices for various industrial machines, and the like. [Explanation of Symbols]

[0129] 1 n - type area 2 p-type region 3.64 n + Type source area 4,61 n + Type drain region 5.54 Semiconductor substrates 5a Si-rich surface 5b Nitride surface 6,66 Gate insulating film 7.67 Temporary Inspection 8.68 Interlayer insulating film 8a~8c, 68a~68c Contact Holes 10,50 Silicon Carbide Semiconductor Devices 11, 12, 52, 53 Epitaxial layer 13~15,55,60,69 Surface electrode 21. Etching apparatus processing chamber 22 Etching 30 Vacuum equipment 31. Processing chamber of a vacuum device 32 Heating means 33 Load Lock Room 34 Gate valve 35 Vacuum exhaust means 36 Metal Cells 37 Ge irradiation 38 Mg irradiation 40 Radical Generator 41 Discharge tube 41a One end of the discharge tube 41b Other end of the discharge tube 42. Coil wrapped around the discharge tube 43. Opening of the discharge tube 44. Gas tube of a discharge tube 45 Matching Box 46 RF power supply 47 N radical irradiation 62 n - Type drift region 63 p - Type-based domain 65 Trench

Claims

1. A semiconductor substrate made of silicon carbide, A gate insulating film made of silicon oxide is provided on the surface of the semiconductor substrate, A gate electrode provided on the surface of the gate insulating film, Equipped with, A silicon carbide semiconductor device characterized in that germanium atoms and alkaline earth metal atoms are present at the interface between the gate insulating film and the semiconductor substrate.

2. The density of germanium atoms at the interface between the gate insulating film and the semiconductor substrate is 1 × 10⁻¹⁶ 8 atoms / cm 2 The above 1 x 10 12 atoms / cm 2 The silicon carbide semiconductor device according to claim 1, characterized in that it is as follows.

3. The density of alkaline earth metal atoms at the interface between the gate insulating film and the semiconductor substrate is 1 × 10⁻⁶ 11 atoms / cm 2 The above 1 x 10 13 atoms / cm 2 The silicon carbide semiconductor device according to claim 1, characterized in that it is as follows.

4. The silicon carbide semiconductor device according to claim 1, characterized in that the germanium atoms at the interface between the gate insulating film and the semiconductor substrate constitute an oxide or oxynitride in the gate insulating film.

5. The silicon carbide semiconductor device according to claim 1, characterized in that the alkaline earth metal atoms at the interface between the gate insulating film and the semiconductor substrate constitute an oxide in the gate insulating film.

6. The silicon carbide semiconductor device according to claim 1, characterized in that there is no excess carbon at the interface between the gate insulating film and the semiconductor substrate.

7. A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the front surface of the semiconductor substrate and the second semiconductor region, Equipped with, The gate insulating film is provided in contact with the region of the second semiconductor region between the third semiconductor region and the first semiconductor region. The silicon carbide semiconductor device according to claim 1, characterized in that the gate electrode is provided on the opposite side of the second semiconductor region, with the gate insulating film in between.

8. The silicon carbide semiconductor device according to claim 1, characterized in that the alkaline earth metal atom is a magnesium atom.

9. A predetermined step involves oxidizing the surface of a semiconductor substrate made of silicon carbide, A removal step to remove carbon atoms deposited on the surface of the semiconductor substrate in the predetermined step, A first forming step involves depositing a gate insulating film made of silicon oxide on the surface of the semiconductor substrate from which the carbon atoms have been removed. A second forming step of forming a gate electrode on the surface of the gate insulating film, Includes, The aforementioned removal process is, A first removal step involves first irradiating the surface of the semiconductor substrate with nitrogen atoms having unpaired electrons to remove carbon atoms from the surface of the semiconductor substrate, A method for manufacturing a silicon carbide semiconductor device, comprising: a first step of depositing germanium atoms onto the surface of the semiconductor substrate; and a second step of irradiating the surface of the semiconductor substrate with nitrogen atoms having unpaired electrons, thereby removing the carbon atoms remaining on the surface of the semiconductor substrate after the first removal step.

10. The method for manufacturing a silicon carbide semiconductor device according to claim 9, characterized in that the semiconductor substrate is heated at a temperature of 500°C or more and 800°C or less in the first removal step.

11. The method for manufacturing a silicon carbide semiconductor device according to claim 9, characterized in that the semiconductor substrate is heated at a temperature of 500°C or more and 800°C or less in the second removal step.

12. In the second removal step, the combination of the first step and the second step is performed multiple times to make the density of the germanium atoms remaining on the surface of the semiconductor substrate fall within a range of 1×10 11 atoms / cm 2 or more and 1×10 12 atoms / cm 2 or less. The method for manufacturing a silicon carbide semiconductor device according to claim 9, characterized by this.

13. The method for manufacturing a silicon carbide semiconductor device according to claim 9, characterized in that the removal step further includes a third removal step, after the second removal step, of depositing alkaline earth metal atoms onto the surface of the semiconductor substrate to remove the germanium atoms from the surface of the semiconductor substrate.

14. The method for manufacturing a silicon carbide semiconductor device according to claim 13, characterized in that the alkaline earth metal atom is a magnesium atom.

15. The method for manufacturing a silicon carbide semiconductor device according to claim 14, characterized in that, in the third removal step, magnesium atoms are supplied to the surface of the semiconductor substrate in an amount exceeding the amount of magnesium atoms deposited on the surface of the semiconductor substrate.

16. The method for manufacturing a silicon carbide semiconductor device according to claim 14, characterized in that the third removal step involves heating the semiconductor substrate at a temperature of 1000°C or higher and 1100°C or lower.

17. A method for manufacturing a silicon carbide semiconductor device according to claim 9, characterized in that, after the first forming step and before the second forming step, the method includes a heat treatment step of oxynitriding the interface between the gate insulating film and the semiconductor substrate by heat treatment.

18. In the first removal step, the first group is removed from the surface of the semiconductor substrate by the electromigration phenomenon of the first group due to the covalent bond between the carbon atom and the first irradiated nitrogen atom. The method for manufacturing a silicon carbide semiconductor device according to claim 14, characterized in that in the second removal step, the second group is removed from the surface of the semiconductor substrate by an electromigration phenomenon of the second group due to a covalent bond between the germanium atom and the second irradiated nitrogen atom.

19. The method for manufacturing a silicon carbide semiconductor device according to claim 18, characterized in that the third removal step involves reducing the second group with the magnesium atoms to evaporate and remove the germanium atoms whose bond with the nitrogen atoms has been broken.

Images