Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can suppress long-term fluctuations in the forward voltage Vft of a temperature sense diode. [Solution] The device comprises a low-concentration region 30 of a first or second conductivity type having an impurity concentration lower than that of the cathode region 26 and the anode region 28, provided between the cathode region 26 and the anode region 28; an interlayer insulating film 24 covering the cathode region 26, the anode region 28 and the low-concentration region 30; a cathode electrode 34 provided on the interlayer insulating film 24 and connected to the cathode region 26 via a first contact hole 48 penetrating the interlayer insulating film 24; and an anode electrode 36 provided on the interlayer insulating film 24 and connected to the anode region 28 via a second contact hole 49 penetrating the interlayer insulating film 24. The cathode electrode 34 or anode electrode 36 covers the upper part of the low-concentration region 30 and further covers the upper part of the cathode region 26 or the anode region 28 by 4 μm or more.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in order to improve reliability, it has a high-functional structure having a sensing element such as a temperature sensing unit that detects temperature and protects from high temperature or the like. In the high-functional structure, for example, high-functional units such as a current sensing unit, a temperature sensing unit, and an overvoltage protection unit are arranged.

[0003] FIG. 16 is a cross-sectional view showing the structure of a temperature sensing diode of a conventional semiconductor device. The temperature sensing diode 152 is a diode for detecting the temperature provided in the temperature sensing unit. The conventional temperature sensing diode 152 is formed on a field oxide film 132 on a semiconductor substrate 144 on which a semiconductor element such as an IGBT or a MOSFET is formed, and an n + -type cathode region 126 and a p + -type anode region 128 are provided. Further, between the n + -type cathode region 126 and the p + -type anode region 128, a p - -type low concentration region 130 and an n - -type low concentration region (not shown) are provided. There is a known semiconductor device in which the p - -type low concentration region 130 and the n - -type low concentration region stabilize the distribution of the impurity concentration in the PN junction portion and its vicinity, reduce the variation in the forward voltage of the diode, and improve the accuracy of temperature detection (see, for example, Patent Document 1 below).

[0004] n + -type cathode region 126, p + -type anode region 128 and p- An interlayer insulating film 124 is provided on the low-concentration region 130, and through the opening of the interlayer insulating film 124, n + The cathode electrode 134 is in the type cathode region 126, p + An anode electrode 136 is connected to the type anode region 128. A barrier metal 125 and a metal plug 143 are formed at the opening of the interlayer insulating film 124.

[0005] The temperature sense diode 152 is formed, for example, as follows: First, an undoped polycrystalline silicon layer is grown on the field oxide film 132. Boron (B) is ion-implanted into the undoped polycrystalline silicon layer. The undoped polycrystalline silicon layer is left only in the temperature sense portion by patterning and etching. The ion-implanted B is diffused by heat treatment to form a p-type polycrystalline silicon layer. Simultaneously, a thermal oxide film 123 is formed covering this p-type polycrystalline silicon layer by thermal oxidation.

[0006] Next, B is partially ion-implanted, and P (phosphorus) is partially ion-implanted to form an interlayer insulating film 124. The interlayer insulating film 124 is, for example, a laminated film of a high-temperature oxide (HTO) and a BPSG (Boron Phospho Silicate Glass) film. Next, the ion-implanted B and P are diffused by heat treatment, n + Type cathode region 126 and p + A type anode region 128 is formed.

[0007] Next, contact holes are formed in the interlayer insulating film 124 by patterning and etching, Al-Si (aluminum silicon alloy) is formed by sputtering, and the cathode electrode 134 and anode electrode 136 are formed by patterning and etching the Al-Si.

[0008] Furthermore, there is a known temperature sensor that can suppress malfunctions even with respect to disturbance noise such as electromagnetic interference by making substantially equal the capacitance formed between one of the two different conductivity types constituting the diode and the base region of the semiconductor element, and the capacitance formed between the other conductivity type and the base region of the semiconductor element (see, for example, Patent Document 2 below).

[0009] Furthermore, there is a known semiconductor device that improves the temperature detection accuracy of a temperature sense diode that utilizes the temperature dependence due to Vf by shortening the length of the current path from the edge of the first contact hole on the side closer to the interface to the interface, and the length of the current path from the edge of the second contact hole on the side closer to the interface to the interface, whichever of the cathode region and anode region has a larger sheet resistance (see, for example, Patent Document 3 below). [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 2002-190575 [Patent Document 2] Japanese Patent Publication No. 2002-280556 [Patent Document 3] International Publication No. 2015 / 87483 [Overview of the project] [Problems that the invention aims to solve]

[0011] The temperature sense diode 152 generates a forward voltage Vft when a constant forward current flows between the anode and cathode. Since this forward voltage Vft decreases as the temperature rises, the temperature sense diode 152 is a device that uses this characteristic to detect temperature. In order to improve the detection accuracy for temperature changes, the temperature sense diode 152 needs to suppress the value and distribution of parasitic resistance (sheet resistance and contact resistance in the current path). To achieve this, the n contact between the cathode electrode 134 and the anode electrode 136 is controlled.+ Type cathode region 126, p + The type anode region 128 suppresses contact resistance as a region with a high carrier concentration. On the other hand, in order to stabilize the distribution of impurity concentration in the pn junction and suppress the distribution of sheet resistance, n + Type cathode region 126, p + Between the type anode region 128, there are p with a low carrier concentration. - Type low concentration region 130 and n - A low-concentration region of type n is necessary. + Type cathode region 126, p + The carrier concentration in the type anode region 128 is 1 × 10⁻⁶. 15 / cm 3 It is about the size of a unit, p - Type low concentration region 130 and n - The carrier concentration in the low-concentration region is 1 × 10⁻⁶. 13 / cm 3 It's about the size of a unit.

[0012] However, due to disturbances in subsequent processes and prolonged use at high temperatures, p - Type low concentration region 130 and n - One problem is that resistance fluctuations occur in the low-concentration region, causing the Vft value to fluctuate over the long term.

[0013] This invention aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress fluctuations in the forward voltage Vft of a temperature sense diode over a long period of time, in order to solve the problems of the prior art described above. [Means for solving the problem]

[0014] To solve the above-mentioned problems and achieve the objectives of the present invention, the semiconductor device according to this invention has the following features: A cathode region of a first conductivity type is provided on an insulating film. An anode region of a second conductivity type is provided on the insulating film. A low-concentration region of the first or second conductivity type is provided between the cathode region and the anode region, having an impurity concentration lower than that of the cathode region and the anode region. An interlayer insulating film is provided covering the cathode region, the anode region and the low-concentration region. A cathode electrode is provided on the interlayer insulating film, connected to the cathode region via a first contact hole penetrating the interlayer insulating film. An anode electrode is provided on the interlayer insulating film, connected to the anode region via a second contact hole penetrating the interlayer insulating film. The cathode electrode or the anode electrode covers the upper part of the low-concentration region and further covers the upper part of the cathode region or the anode region by 4 μm or more.

[0015] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the cathode region, the anode region, and the low-concentration region are polycrystalline silicon layers.

[0016] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the thickness of the cathode electrode and the anode electrode is 4 μm or more.

[0017] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a semiconductor device according to this invention has the following features. First, a first step is performed in which a first impurity ion is implanted into a semiconductor layer provided on an insulating film. Next, a second step is performed in which a second impurity ion is implanted into a part of the semiconductor layer into which the first impurity ion has been implanted. Next, a third step is performed in which a third impurity ion is implanted into a part of the semiconductor layer into which the first impurity ion has been implanted. Next, a fourth step is performed in which the first impurity ion, the second impurity ion and the third impurity ion are activated to form a low-concentration region in the region into which the first impurity ion has been implanted, an anode region in the region into which the second impurity ion has been implanted, and a cathode region in the region into which the third impurity ion has been implanted. Next, a fifth step is performed in which an interlayer insulating film is formed to cover the semiconductor layer. Next, a sixth step is performed in which a first contact hole is formed that penetrates the interlayer insulating film and exposes a part of the cathode region, and a second contact hole is formed that penetrates the interlayer insulating film and exposes a part of the anode region. Next, a seventh step is performed in which a metal film is formed that covers the interlayer insulating film. Next, an eighth step is performed to selectively remove the metal film and form a cathode electrode connected to the cathode region via the first contact hole and an anode electrode connected to the anode region via the second contact hole. In the eighth step, the cathode electrode or the anode electrode is formed to cover the upper part of the low-concentration region.

[0018] Furthermore, in the semiconductor device manufacturing method according to this invention, in the fourth step described above, the dose amount of the first impurity ion is 1 × 10 13 cm -2 ~5×10 14 cm -2 The dose amounts of the second and third impurity ions are 5 × 10 14 cm -2 ~5×10 16 cm -2 It is characterized by the following:

[0019] Furthermore, the method for manufacturing a semiconductor device according to this invention is characterized in that, in the invention described above, the first impurity ion is a boron ion, a phosphorus ion, or an arsenic ion, the second impurity ion is a boron ion, and the third impurity ion is a phosphorus ion or an arsenic ion.

[0020] According to the invention described above, the cathode electrode or anode electrode is p - Type low concentration region or n - It covers the upper part of the low-concentration region. As a result, if charged particles / ions are irradiated and diffused due to disturbance factors in the subsequent process, the charged particles / ions will be p - Low concentration region and n - It is possible to prevent reaching the low concentration region of the type. Charged particles and ions are not trapped or bound to unbound hands at the polysilicon grain boundaries, p - Low concentration region and n - The potential barrier height does not fluctuate in the low-concentration region. Therefore, even when used at high temperatures for extended periods, p - Low concentration region and n - No fluctuations in sheet resistance occur in the low-concentration region. [Effects of the Invention]

[0021] The semiconductor device and method for manufacturing the semiconductor device according to the present invention have the effect of suppressing fluctuations in the forward voltage Vft of the temperature sense diode over the long term. [Brief explanation of the drawing]

[0022] [Figure 1] This is a cross-sectional view showing the structure of a semiconductor device according to an embodiment. [Figure 1A] This is a cross-sectional view showing another structure of the temperature sense diode of the semiconductor device according to the embodiment. [Figure 2] This is a cross-sectional view (part 1) showing the state of a temperature sense diode in the semiconductor device according to the embodiment during the manufacturing process. [Figure 3]This is a cross-sectional view (part 2) showing the temperature sense diode of the semiconductor device according to the embodiment in the process of being manufactured. [Figure 4] This is a cross-sectional view (part 3) showing the state of a temperature sense diode in the semiconductor device according to the embodiment during the manufacturing process. [Figure 5] This is a cross-sectional view (part 4) showing the state of a temperature sense diode in the semiconductor device according to the embodiment during the manufacturing process. [Figure 6] This is a cross-sectional view (part 5) showing the state of a temperature sense diode in the semiconductor device according to the embodiment during the manufacturing process. [Figure 7] This is a cross-sectional view (part 6) showing the state of a temperature sense diode in the semiconductor device according to the embodiment during the manufacturing process. [Figure 8] This is a cross-sectional view (7) showing the state of a temperature sense diode in the semiconductor device according to the embodiment during the manufacturing process. [Figure 9] This is a cross-sectional view (part 8) showing the state of a temperature sense diode in the semiconductor device according to the embodiment during the manufacturing process. [Figure 10] This is a cross-sectional view (part 9) showing the temperature sense diode of the semiconductor device according to the embodiment in the process of being manufactured. [Figure 11] This is a cross-sectional view (10) showing the state of a temperature sense diode in the semiconductor device according to the embodiment during the manufacturing process. [Figure 12] This is a cross-sectional view (11) showing the state of a temperature sense diode in the semiconductor device according to the embodiment during the manufacturing process. [Figure 13] This is a cross-sectional view showing a conventional semiconductor device's temperature sense diode irradiated with charged particles. [Figure 14] This is a cross-sectional view showing a state in which charged particles are irradiated onto a temperature sense diode of a semiconductor device according to an embodiment. [Figure 15] This graph shows the change in forward voltage Vft of a temperature sense diode in a conventional semiconductor device and a temperature sense diode in a semiconductor device according to the embodiment. [Figure 16]This is a cross-sectional view showing the structure of a temperature sense diode in a conventional semiconductor device. [Modes for carrying out the invention]

[0023] Preferred embodiments of the semiconductor device and method for manufacturing the semiconductor device according to the present invention will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p indicate higher and lower impurity concentrations, respectively, than layers or regions without these prefixes. In the following description of embodiments and attached drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In this specification, in the notation of Miller indices, "-" indicates a bar attached to the exponent immediately following it, and a "-" before the exponent indicates a negative exponent. Furthermore, it is preferable to include up to 5% variation when describing them as the same or equivalent, taking into account manufacturing variations.

[0024] (Embodiment) The structure of a semiconductor device according to this embodiment will be explained using an IGBT as an example. Figure 1 is a cross-sectional view showing the structure of a semiconductor device according to this embodiment. The semiconductor device according to this embodiment is an IGBT 50 equipped with a temperature sense diode 52.

[0025] IGBT50 has an IGBT region 51, which is the operating region of the IGBT, and a temperature sense diode 52, which is the temperature sense region, arranged in parallel on the same semiconductor substrate. - n is a type drift layer - An n-type storage layer 16 may be provided on the surface layer of the front side of the n-type semiconductor substrate 18. The n-type storage layer 16 is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. -A p-type base region 14 is provided on the front side of the semiconductor substrate 18, extending from the IGBT region 51 to the temperature sense diode 52. The IGBT region 51 has n-type base regions that penetrate the p-type base region 14. - A gate trench 46 is provided that reaches the semiconductor substrate 18. The gate trench 46 has n on both sides. + A type emitter region 12 is provided and arranged in a stripe-like planar layout at predetermined intervals in the IGBT region 51, separating the p-type base region 14 into multiple regions (mesa sections). + p + A type contact region 13 may be provided. Inside the gate trench 46, a gate insulating film 8 is provided along the inner wall of the gate trench 46, and a gate electrode 10 is provided inside the gate insulating film 8.

[0026] In the IGBT region 51, within the p-type base region 14, each mesa contains n + Type emitter region 12 and p + A type contact region 13 is selectively provided. + The type emitter region 12 faces the gate electrode 10 across the gate insulating film 8 provided on the inner wall of the gate trench 46. + The type emitter region 12 is p + It is located on the trench 46 side of the type contact area 13. + The type contact area 13 does not necessarily have to be provided. + If a contact region 13 is not provided, n + The p-type base region 14 extends to the surface of the semiconductor substrate 44 at a location further from the trench 46 than the type emitter region 12, and is exposed on the surface of the semiconductor substrate 44. In the temperature sense diode 52, the interior of the p-type base region 14 contains n + The type emitter region 12 is not provided. The front surface electrode 37 is connected via a contact hole to n + It is in contact with the type emitter region 12 and is electrically insulated from the gate electrode 10 by the interlayer insulating film 24. +A selective opening may be provided in the type emitter region 12, and the front electrode 37 and the p-type base region 14 may be electrically connected at this opening. The front electrode 37 functions as an emitter electrode in the IGBT region 51.

[0027] n - Inside the semiconductor substrate 18, on the back side of the substrate, n + A field stop (FS) layer 20 may be provided. + The type FS layer 20, when off, has a p-type base region 14 and n - From the pn junction between the semiconductor substrate 18, as described later, + It has the function of suppressing the elongation of the depletion layer extending towards the collector region 22.

[0028] n - n + n - At a shallow position from the back surface of the type semiconductor substrate 18, p + A type collector region 22 is provided, and the back electrode (not shown) is p + Surface of type collector region 22 (n - It is provided on the entire back surface of the semiconductor substrate. The back surface electrode functions as a collector electrode in the IGBT region 51. + Type collector area 22, n - Semiconductor substrate 18, n + The n-type FS layer 20, the n-type storage layer 16, and the p-type base region 14 together are referred to as the semiconductor substrate 44.

[0029] Furthermore, as shown in Figure 1, the IGBT 50 includes a temperature sense diode 52 provided on the main surface of the semiconductor substrate 44 via a field oxide film 32. The temperature sense diode 52 is designed to immediately detect abnormal temperature rises when the power element is energized, thereby suppressing element failure due to thermal runaway. The temperature sense diode 52 is located in the center of the semiconductor chip, surrounded by the active region of the IGBT 50. The temperature sense diode 52 is a first-conductivity type (n-type) n-electrode provided on the field oxide film 32. +The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. + The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. + The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided.

[0030] [[ID=⑧]]Also, a p - type low - concentration region 30 is provided between the n - type cathode region 26 and the p - type anode region 28. Instead of the p - type low - concentration region 30, an n - type low - concentration region (not shown) may be provided. The temperature - sense diode 52 forms a pn junction by the pn junction formed by the n - type cathode region 26 and the p - type low - concentration region 30, or the pn junction formed by the n - type low - concentration region and the p - type anode region 28. [[ID=⑨]] + [[ID=⑩]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=⑪]] + [[ID=⑫]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=⑬]] - [[ID=⑭]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=⑮]] - [[ID=⑯]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=⑰]] - [[ID=⑱]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=⑲]] + [[ID=⑳]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㉑]] - [[ID=㉒]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㉓]] - [[ID=㉔]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㉕]] + [[ID=㉖]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㉗]] [[ID=㉘]]

[0031] [[ID=㉙]] [[ID=㉚]]To suppress the contact resistance, the n - type cathode region 26 and the p - type anode region 28 in contact with the cathode electrode 34 and the anode electrode 36 described later have increased carrier concentrations. Also, to stabilize the impurity - concentration distribution of the pn - junction portion and reduce the resistance variation, the p - type low - concentration region 30 or the n - type low - concentration region has a lower carrier concentration than the n - type cathode region 26 and the p - type anode region 28. For example, the carrier concentrations of the n - type cathode region 26 and the p - type anode region 28 are on the order of 1×10 / cm³, and the carrier concentrations of the p - type low - concentration region 30 and the n - type low - concentration region are on the order of 1×10 / cm³. Also, because the p - type low - concentration region 30 and the n - type low - concentration region have low carrier concentrations and high sheet resistances, the p - type low - concentration region 30 and the n - type low - concentration region [[ID=㉛]] + [[ID=㉜]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㉝]] + [[ID=㉞]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㉟]] - [[ID=㊱]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㊲]] - [[ID=㊳]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㊴]] + [[ID=㊵]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㊶]] + [[ID=㊷]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㊸]] + [[ID=㊹]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㊺]] + [[ID=㊻]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㊼]] 15 [[ID=㊽]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. [[ID=㊾]] 3 [[ID=㊿]]The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. - The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. - The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. 13 The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. 3 The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. - The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. - The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. - The type - cathode region 26 and an n - type cathode region 26 and a p - type anode region 28 of the second conductivity type (p - type) provided so as to form a pn junction on the field oxide film 32 are provided. -- The width of the low-concentration region should preferably be short, preferably around a few μm.

[0032] Also, n + Type cathode region 26 and p + The type anode region 28 is covered by an interlayer insulating film 24. Through the first contact hole 48 that penetrates the interlayer insulating film 24, n + It is equipped with a cathode electrode 34 that is electrically connected to the type cathode region 26. Through the second contact hole 49 that penetrates the interlayer insulating film 24, p + It is equipped with an anode electrode 36 that is electrically connected to a type anode region 28. In addition, in this embodiment, p - No contact holes are provided on the low-concentration region 30, and the interlayer insulating film 24 is p - It covers the low-concentration region 30. - The same applies to the low-concentration region. Furthermore, the first contact hole 48 and the second contact hole 49 may have a barrier metal 25 formed on their bottom and side surfaces, consisting of Ti, TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), etc., or a stack thereof. Also, the cathode electrode 34 and the anode electrode 36, and n + Type cathode region 26 and p + To ensure good connection with the type anode region 28, the first contact hole 48 and the second contact hole 49 may have metal plugs 43 made of tungsten (W) or molybdenum (Mo) formed in them. Figure 1A is a cross-sectional view showing another structure of the temperature sense diode of the semiconductor device according to the embodiment. Figure 1A shows the configuration of the temperature sense diode 52 when the thermal oxide film 23, barrier metal 25 and metal plugs 43 are not provided.

[0033] Furthermore, as shown in Figure 1, the anode electrode 36 is p - It covers the upper part of the low-concentration region 30. In other words, it extends downward from the anode electrode 36 (from the p-type base region 14 to n - In the region facing the direction toward the semiconductor substrate 18, p - A low-concentration region 30 is provided. Also, the cathode electrode 34 is p- The upper part of the low-concentration region 30 may be covered. - Type low concentration region 30, not n - The same applies to the low-concentration region. Furthermore, as will be described later, the cathode electrode 34 and anode electrode 36 have the function of shielding charged particles and ions, so that the leakage of charged particles and ions can be prevented, p - Type low concentration region 30 and p + Type anode region 28 or n + From the boundary of type cathode region 26 to p + Type anode region 28 or n + It is preferable that the upper part of the cathode region 26 is covered by extending 4 μm or more. Furthermore, since the cathode electrode 34 and anode electrode 36 have the function of shielding charged particles and ions, it is preferable that they have a thickness of 4 μm or more.

[0034] The field oxide film 32 is, for example, a silicon dioxide (SiO2) film. The interlayer insulating film 24 may be a film containing at least one of, for example, HTO, NSG (Non-Doped Silicate Glass), or BPSG film. The cathode electrode 34 and anode electrode 36 are formed of, for example, an aluminum (Al) film, or an aluminum alloy film such as aluminum-silicon (Al-Si), aluminum-copper (Al-Cu), or aluminum-copper-silicon (Al-Cu-Si).

[0035] Also, n + Type cathode region 26 and p + The sides and bottom of the type anode region 28 are surrounded by an interlayer insulating film 24 and a field oxide film 32. In the IGBT 50 according to this embodiment, for convenience, the case of having one temperature sense diode 52 is shown, but in some cases, multiple diodes may be connected in series to increase the detection voltage. In that case, the entire assembly becomes a temperature sense diode, and each individual temperature sense diode becomes a unit of temperature sense diode.

[0036] (Method for manufacturing a semiconductor device according to an embodiment) Next, a method for manufacturing a semiconductor device according to the embodiment will be described. Figures 2 to 12 are cross-sectional views showing the state of a temperature sense diode in the manufacturing process of a semiconductor device according to the embodiment.

[0037] First, a field oxide film 32 is formed over the entire surface of the main surface of the semiconductor substrate 44. The field oxide film 32 is a silicon dioxide (SiO2) film formed by thermal oxidation or the like. This stage is shown in Figure 2. Next, a photoresist (not shown) may be used as an etching mask to selectively remove the field oxide film 32 on the IGBT region 51 formation region by wet etching or the like, followed by the removal of the photoresist, and then the IGBT region 51 may be formed. Since this IGBT region 51 can be manufactured (fabricated) in the same way as a normal IGBT, the description of the manufacturing method is omitted.

[0038] Next, an undoped polycrystalline silicon layer 38 is formed on the field oxide film 32 by chemical vapor deposition (CVD). The state up to this point is shown in Figure 3. Next, for example, boron(B) ions are implanted as p-type first impurity ions into the entire surface of the undoped polycrystalline silicon layer 38 (first step). The implantation of the first impurity ions is, for example, with a dose of 1 × 10⁻⁶. 13 cm -2 ~5×10 14 cm -2 The procedure is carried out under certain conditions. The first impurity ion may be an n-type impurity such as a phosphorus ion or an arsenide ion. When using a phosphorus ion or an arsenide ion as the first impurity ion, the dose may be the same as when using a boron(B) ion. The state up to this point is shown in Figure 4.

[0039] Next, a photoresist (not shown) is used as an etching mask to selectively remove the polycrystalline silicon layer 38 and field oxide film 32 on the temperature sense diode 52 formation region, leaving the rest by dry etching, and then the photoresist is removed. The state up to this point is shown in Figure 5.

[0040] Next, the polycrystalline silicon layer 38 is subjected to a heat treatment to activate the first impurity ions (boron ions), thereby converting the polycrystalline silicon layer 38 into a p-type polycrystalline silicon layer 40. At this time, a thermal oxide film 23 is formed covering the p-type polycrystalline silicon layer 40. The thermal oxide film 23 may be a silicon dioxide (SiO2) film produced by thermal oxidation, or it may be an HTO film formed after the formation of the p-type polycrystalline silicon layer 40. The thermal oxide film 23 may not be formed at all. The state up to this point is shown in Figure 6.

[0041] Next, a photoresist (not shown) is used as an ion implantation mask, and the p-type polycrystalline silicon layer 40 is p + In the region where the p-type anode region 28 is formed, for example, boron(B) ions are implanted as p-type second impurity ions (second step). The implantation of the second impurity ions is performed with a dose of, for example, 5 × 10⁻⁶. 14 cm -2 ~5×10 16 cm -2 The process is carried out under certain conditions. The implantation of the second impurity ion is more preferably performed in doses of, for example, 1 × 10⁻⁶. 15 cm -2 ~5×10 16 cm -2 The conditions can be of a certain degree. The implantation of the second impurity ion is performed in the IGBT region 51. + This can be done simultaneously with ion implantation to form the contact region. The state up to this point is shown in Figure 7.

[0042] Next, a photoresist (not shown) is used as an ion implantation mask, and the n of the p-type polycrystalline silicon layer 40 is implanted. + In the region where the n-type cathode region 26 is formed, for example, phosphorus (P) ions are implanted as n-type third impurity ions (third step). The implantation of the third impurity ions is performed in doses of, for example, 5 × 10⁻⁶. 14 cm -2 ~5×10 16 cm -2 The procedure is carried out under certain conditions. The implantation of the third impurity ion is performed in the IGBT region 51. +This may be done simultaneously with ion implantation to form the n-type emitter region 12. Arsenic (As) ions may be used as the n-type third impurity ions. When arsenic (As) ions are used as the n-type third impurity ions, the dose may be the same as when phosphorus (P) ions are used. The state up to this point is shown in Figure 8.

[0043] Next, an interlayer insulating film 24 is formed, for example by CVD, so as to cover the entire surface of the main surface of the semiconductor substrate 44 with the p-type polycrystalline silicon layer 40 (5th step). The interlayer insulating film 24 is, for example, an HTO film, an NSG film, a BPSG film, or a stack of these. The state up to this point is shown in Figure 9.

[0044] Next, by applying a heat treatment to activate the second impurity ions (boron ions) and third impurity ions (phosphorus ions) of the p-type polycrystalline silicon layer 40, n + Type cathode region 26, p + Type anode region 28 and p - A low-concentration region 30 of the p-type is formed (fourth step). At this time, the region of the p-type polycrystalline silicon layer 40 in which p-type and n-type impurity ions were not implanted is p - This corresponds to the low-concentration region 30. The state up to this point is shown in Figure 10.

[0045] Next, penetrate the interlayer insulating film 24, n + A first contact hole 48 that exposes a portion of the type cathode region 26, and a p that penetrates the interlayer insulating film 24. + A second contact hole 49 is formed, exposing a portion of the type anode region 28 (step 6). The state up to this point is shown in Figure 11.

[0046] Next, a metal film, such as Al or an Al alloy such as AlSi, is formed on the interlayer insulating film 24 by sputtering so as to fill the interiors of the first contact hole 48 and the second contact hole 49 (step 7). Before this step, a barrier metal 25 made of Ti, TiN, Ta, TaN, etc., or a stack thereof, may be formed on the bottom and side surfaces of the first contact hole 48 and the second contact hole 49. Also, the cathode electrode 34 and the anode electrode 36, and n + Type cathode region 26 and p + To ensure good connection with the type anode region 28, the first contact hole 48 and the second contact hole 49 may have metal plugs 43 made of W or Mo formed in them. This state is shown in Figure 12. Subsequently, the cathode electrode 34 and anode electrode 36 are formed by patterning and etching this metal film 42 (step 8). The cathode electrode 34 and anode electrode 36 may be formed simultaneously with the emitter electrode of the IGBT region 51. In this case, as shown in Figure 1, the anode electrode 36 is p - The pattern is applied to cover the upper part of the low-concentration region 30. As described above, the temperature-sensing diode 52 shown in Figure 1 is formed.

[0047] Furthermore, the cathode electrode 34 is p - The pattern may be made to cover the upper part of the low-concentration region 30. Furthermore, p - Type low concentration region 30, not n - A low-concentration region of type n may be formed. In this case, for example, phosphorus ions are implanted as n-type impurity ions into the entire surface of the undoped polycrystalline silicon layer 38, and the polycrystalline silicon layer 38 is converted into an n-type polycrystalline silicon layer by applying a heat treatment to activate the impurity ions (phosphorus ions) of the polycrystalline silicon layer 38. However, since B has better diffusivity than P, n - From the low concentration region of type p - It is preferable to form a low-concentration region 30.

[0048] Also, n + Type cathode region 26 and p +It is also possible to perform either the second or third step of forming the type anode region 28 between the sixth and seventh steps of forming the first contact hole 48 and the second contact hole 49. For example, p - If a low-concentration region 30 is formed, a second step of implanting a second impurity ion (boron ion) may be performed between the sixth and seventh steps. In this case, an additional heat treatment to activate the second impurity ion (boron ion) may be applied.

[0049] Here, Figure 13 is a cross-sectional view showing a state in which a charged particle is irradiated onto a temperature sense diode of a conventional semiconductor device. Figure 14 is a cross-sectional view showing a state in which a charged particle is irradiated onto a temperature sense diode of a semiconductor device according to the embodiment. As shown in Figure 13, in a conventional temperature sense diode of a semiconductor device, the cathode electrode 134 and the anode electrode 136 are p - It does not cover the upper part of the low-concentration region 130. (Not shown in the figure) - The same applies to the low-concentration region. Therefore, if charged particles / ions (hydrones, hydrogen molecular ions, polyatomic ions contained in the resin used in the assembly process, etc.) are irradiated and diffused due to disturbance factors in the subsequent process, the charged particles / ions will p - Type low concentration region 130 and n - It reaches a low concentration region of type . In this case, charged particles and ions are captured and bound to the unbound hands at the polysilicon grain boundaries. As a result, p - Type low concentration region 130 and n - In the low-concentration region of type p, the potential barrier height fluctuates, - Type low concentration region 130 and n - In the low-concentration region, sheet resistance fluctuations occur, causing the Vft value to change over the long term.

[0050] In contrast, in the temperature sense diode of the semiconductor device according to the embodiment, the cathode electrode 34 or the anode electrode 36 is p - It covers the upper part of the low-concentration region 30. Figure 14 shows the case where the anode electrode 36 covers it. (Not shown) -The same applies to the low-concentration region. As a result, if charged particles / ions are irradiated or diffused due to disturbance factors in the subsequent process, the cathode electrode 34 or anode electrode 36 shields the charged particles / ions, so the charged particles / ions p - Type low concentration region 30 and n - It is possible to prevent reaching the low concentration region of the type. Charged particles and ions do not get trapped or bound to unbound hands at the polysilicon grain boundaries, p - Type low concentration region 30 and n - The potential barrier height does not fluctuate in the low-concentration region, and even when used for extended periods at high temperatures, p - Type low concentration region 30 and n - This design prevents fluctuations in sheet resistance in the low-concentration region, suppressing long-term fluctuations in Vft values, thereby ensuring the long-term reliability of the product and guaranteeing the specifications of its electrical characteristics.

[0051] Figure 15 is a graph showing the change in forward voltage Vft of a conventional semiconductor device temperature sense diode and a semiconductor device temperature sense diode according to the embodiment. In Figure 15, the vertical axis represents the forward voltage Vft_RT at room temperature, and the horizontal axis represents the time the semiconductor device was left at a high temperature. As shown in Figure 15, in the conventional semiconductor device temperature sense diode, the forward voltage Vft_RT gradually decreases, whereas in the semiconductor device temperature sense diode according to the embodiment, the forward voltage Vft_RT hardly decreases at all.

[0052] As described above, according to the embodiment, the cathode electrode or anode electrode is p - Type low concentration region or n - It covers the upper part of the low-concentration region. As a result, if charged particles / ions are irradiated and diffused due to disturbance factors in the subsequent process, the charged particles / ions will be p - Low concentration region and n - It is possible to prevent reaching the low concentration region of the type. Charged particles and ions do not get trapped or bound to unbound hands at the polysilicon grain boundaries, p - Low concentration region and n -In the low-concentration region, the potential barrier height does not fluctuate, and even when used at high temperatures for extended periods, p - Low concentration region and n - This design prevents fluctuations in sheet resistance in the low-concentration region, suppressing long-term fluctuations in Vft value, ensuring long-term product reliability, and guaranteeing the specified electrical characteristics.

[0053] In the above description, the present invention has been explained using the example of a MOS gate structure constructed on the first main surface of a silicon substrate. However, the present invention is not limited to this, and various types of semiconductors (e.g., silicon carbide (SiC)), the surface orientation of the main surface of the substrate, etc., can be changed. Furthermore, although the embodiments of the present invention have been explained using a trench-type IGBT as an example, the present invention is not limited to this, and can be applied to semiconductor devices with various configurations, such as planar-type semiconductor devices and MOSFETs. In addition, in each embodiment of the present invention, the first conductivity type is set to n-type and the second conductivity type to p-type, but the present invention also holds true if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial applicability]

[0054] As described above, the semiconductor device and method for manufacturing the semiconductor device according to the present invention are useful for high-voltage semiconductor devices used in power supply devices such as power converters and various industrial machines. [Explanation of Symbols]

[0055] 8 gate insulating film 10 Guard Station 12 n + Type emitter region 13 p + Type Contact Area 14 p-type base region 16 n-type storage layer 18 n - Semiconductor substrate 20 n + type FS layer 22 pages + Type collector area 23, 123 Thermal Oxide Film 24, 124 Interlayer insulating film 25, 125 Barrier Metal 26, 126 n + Type cathode region 28, 128 p + Type Anode Region 30, 130 p - type low concentration area 32, 132 Field Oxide Film 34, 134 Cathode electrodes 36, 136 anode electrodes 37 Front surface electrode 38. Undoped polycrystalline silicon layer 40 p-type polycrystalline silicon layer 42 Metal film 43, 143 Metal plug 44, 144 Semiconductor substrates 46 Gate Trench 48. First Contact Hole 49. Second Contact Hole 50 IGBT 51 IGBT area 52, 152 Temperature Sense Diodes

Claims

1. A cathode region of the first conductivity type provided on an insulating film, A second conductivity type anode region provided on the insulating film, A low-concentration region of a first conductivity type or a second conductivity type is provided between the cathode region and the anode region, and the impurity concentration is lower than that of the cathode region and the anode region. An interlayer insulating film covering the cathode region, the anode region, and the low-concentration region, A cathode electrode provided on the interlayer insulating film and connected to the cathode region via a first contact hole penetrating the interlayer insulating film, An anode electrode provided on the interlayer insulating film and connected to the anode region via a second contact hole penetrating the interlayer insulating film, Equipped with, A semiconductor device characterized in that the cathode electrode or the anode electrode covers the upper part of the low-concentration region, and further covers the upper part of the cathode region or the anode region by 4 μm or more.

2. The semiconductor device according to claim 1, characterized in that the cathode region, the anode region, and the low-concentration region are polycrystalline silicon layers.

3. The semiconductor device according to claim 1, characterized in that the thickness of the cathode electrode and the anode electrode is 4 μm or more.

4. A first step involves implanting a first impurity ion into a semiconductor layer provided on an insulating film, A second step of implanting a second impurity ion into a portion of the semiconductor layer into which the first impurity ion has been implanted, A third step of implanting a third impurity ion into a portion of the semiconductor layer into which the first impurity ion has been implanted, A fourth step involves activating the first impurity ion, the second impurity ion, and the third impurity ion, forming a low-concentration region in the region where the first impurity ion is implanted, forming an anode region in the region where the second impurity ion is implanted, and forming a cathode region in the region where the third impurity ion is implanted. A fifth step involves forming an interlayer insulating film that covers the semiconductor layer, A sixth step involves forming a first contact hole that penetrates the interlayer insulating film and exposes a portion of the cathode region, and forming a second contact hole that penetrates the interlayer insulating film and exposes a portion of the anode region, A seventh step involves forming a metal film that covers the interlayer insulating film, An eighth step involves selectively removing the metal film to form a cathode electrode connected to the cathode region via the first contact hole and an anode electrode connected to the anode region via the second contact hole. Includes, A method for manufacturing a semiconductor device, characterized in that, in the eighth step, the cathode electrode or the anode electrode is formed to cover the upper part of the low-concentration region.

5. In the fourth step described above, The dose amount of the first impurity ion is 1 × 10 13 cm -2 ~5 x 10 14 cm -2 The dose amounts of the second impurity ion and the third impurity ion are 5 × 10 14 cm -2 ~5 x 10 16 cm -2 A method for manufacturing a semiconductor device according to claim 4, characterized in that it is provided as follows.

6. The first impurity ion is a boron ion, a phosphorus ion, or an arsenic ion. The second impurity ion is a boron ion. The method for manufacturing a semiconductor device according to claim 4, characterized in that the third impurity ion is a phosphorus ion or an arsenide ion.

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