Semiconductor package including memory die

Abstract

To improve the reliability of semiconductor packages, including memory dies. [Solution] The semiconductor package according to the present invention includes: a plurality of first data memory dies belonging to different ranks and sharing a first control bus and a first data bus; a first error correction memory die sharing a first control bus with the first data memory dies and connected to a first error correction bus; a plurality of second data memory dies belonging to different ranks and sharing a second control bus and a second data bus; and a second error correction memory die sharing a second control bus with the second data memory dies and connected to a second error correction bus.

Description

Technical Field

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[0003] ,

[0005] ,

[0001] The present invention relates to a semiconductor package including a memory die.

Background Art

[0002] Recently, as the number of application fields utilizing artificial intelligence and big data has increased, the amount of data to be processed has been explosively increasing. Many computer systems (e.g., data centers, servers, etc.) require a large amount of memory, and applications using these computer systems require more memory than the system capabilities. Due to such requirements for capacity expansion, it is common to include two or more memory dies in a single semiconductor package. Particularly, computer systems such as data centers and servers require high reliability for such semiconductor packages.

Summary of the Invention

Problems to be Solved by the Invention

[0003] An object of the present invention is to provide a technique for enhancing the reliability of a semiconductor package including a memory die.

Means for Solving the Problems

[0004] A semiconductor package according to an embodiment of the present invention can include a plurality of first data memory dies belonging to different ranks and sharing a first control bus and a first data bus, a first error correction memory die sharing the plurality of first data memory dies and the first control bus and connected to a first error correction bus, a plurality of second data memory dies belonging to different ranks and sharing a second control bus and a second data bus, and a second error correction memory die sharing the plurality of second data memory dies and the second control bus and connected to a second error correction bus.

[0005] A semiconductor package according to one embodiment of the present invention may include a plurality of first data memory dies corresponding to a plurality of ranks of a first channel, a first error correction memory die corresponding to the plurality of ranks of the first channel, a plurality of second data memory dies corresponding to a plurality of ranks of a second channel, and a second error correction memory die corresponding to the plurality of ranks of the second channel.

[0006] A semiconductor package according to one embodiment of the present invention may include a plurality of first data memory dies sharing a control bus and a first chip selection signal, a first error correction memory die sharing the control bus and the first chip selection signal with the plurality of first data memory dies, a plurality of second data memory dies sharing the control bus and a second chip selection signal, and a second error correction memory die sharing the control bus and the second chip selection signal with the plurality of second data memory dies.

[0007] A semiconductor package according to one embodiment of the present invention may include a plurality of first data memory dies corresponding to a first rank of a first channel, a first error correction memory die corresponding to a first rank of the first channel, a plurality of second data memory dies corresponding to a second rank of the first channel, a second error correction memory die corresponding to a second rank of the first channel, a plurality of third data memory dies corresponding to a first rank of the second channel, a third error correction memory die corresponding to a first rank of the second channel, a plurality of fourth data memory dies corresponding to a second rank of the second channel, and a fourth error correction memory die corresponding to a second rank of the second channel. [Effects of the Invention]

[0008] According to the present invention, the reliability of semiconductor packages including memory dies can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a diagram showing the configuration of a semiconductor package (100) according to the first embodiment of the present invention. [Figure 2] Figure 2 is a diagram showing the configuration of a semiconductor package (200) according to a second embodiment of the present invention. [Figure 3] Figure 3 is a diagram showing the configuration of a semiconductor package (300) according to a third embodiment of the present invention. [Figure 4] Figure 4 is a diagram showing the configuration of a semiconductor package (400) according to the fourth embodiment of the present invention. [Figure 5] Figure 5 is a diagram showing the configuration of a semiconductor package (500) according to the fifth embodiment of the present invention. [Figure 6] Figure 6 is a diagram showing the configuration of a semiconductor package (600) according to the sixth embodiment of the present invention. [Modes for carrying out the invention]

[0010] The embodiments relating to the technical concept of the present invention will be described below with reference to the attached drawings.

[0011] Figure 1 is a diagram showing the configuration of a semiconductor package 100 according to the first embodiment of the present invention.

[0012] Referring to Figure 1, the semiconductor package 100 includes a first data memory die 111-114, a first error correction memory die 116, a second data memory die 121-124, and a second error correction memory die 126.

[0013] The first data memory dies 111 to 114 share the first control bus CONTROL_A and the first data bus DATA_A, and can receive different chip selection signals CS_A0 to CS_A3. That is, the first data memory dies 111 to 114 can be memory dies of different ranks on the same memory channel (hereinafter referred to as A channel). The first control bus CONTROL_A is a bus for transmitting control signals to control the first data memory dies 111 to 114, and the control signals transmitted to the first control bus CONTROL_A can include command address signals, clock signals, etc. Since the first data bus DATA_A is exemplified as being 16 bits, each of the first data memory dies 111 to 114 can be connected to the first data bus DATA_A using 16 data terminals. That is, each of the first data memory dies 111 to 114 can have an X16 configuration. Furthermore, the first data bus DATA_A may include not only 16 data lines, but also one or more lines for transmitting one or more data strobe signals for strobbing data.

[0014] The first error correction memory die 116 shares the first control bus CONTROL_A with the first data memory dies 111-114 and can be connected to the first error correction bus ECC_A. The first error correction memory die 116 can receive chip selection signals CS_A0-CS_A3 as input. Since the first error correction memory die 116 corresponds to all ranks of the A channel, the example given shows that all chip selection signals CS_A0-CS_A3 are input, but it is naturally possible to modify it so that a single signal is input by performing an OR operation on the chip selection signals CS_A0-CS_A3. The first error correction bus ECC_A is a data bus, and since the data stored in the first error correction memory die 116 is an error correction code that is not normal data, it is named the error correction bus. Since the first error correction bus ECC_A is exemplified as a 4-bit bus, the first error correction memory die 116 can be connected to the first error correction bus ECC_A using four data terminals. In other words, the first error correction memory die 116 can have an X4 configuration. Furthermore, the first error correction bus ECC_A may include not only four data lines, but also one or more lines for transmitting one or more data strobe signals for strobbing data.

[0015] The second data memory dies 121-124 share the second control bus CONTROL_B and the second data bus DATA_B, and can receive different chip selection signals CS_B0-CS_B3. That is, the second data memory dies 121-124 can be memory dies of different ranks on the same memory channel (hereinafter referred to as the B channel). The second control bus CONTROL_B is a bus for transmitting control signals to control the second data memory dies 121-124, and the control signals transmitted to the second control bus CONTROL_B can include command address signals, clock signals, etc. Since the second data bus DATA_B is exemplified as a 16-bit bus, each of the second data memory dies 121-124 can be connected to the second data bus DATA_B using 16 data terminals. That is, each of the second data memory dies 121-124 can have an X16 configuration. Furthermore, the second data bus DATA_B may include not only 16 data lines, but also one or more lines for transmitting one or more data strobe signals to strobe data.

[0016] The second error correction memory die 126 shares the second control bus CONTROL_B with the second data memory dies 121-124 and can be connected to the second error correction bus ECC_B. The second error correction memory die 126 can receive chip selection signals CS_B0-CS_B3 as input. Since the second error correction memory die 126 corresponds to all ranks of the B channel, it is illustrated that all of the chip selection signals CS_B0-CS_B3 are input, but it is naturally possible to modify it so that a single signal is input by performing an OR operation on the chip selection signals CS_B0-CS_B3. The second error correction bus ECC_B is a data bus, and since the data stored in the second error correction memory die 126 is an error correction code that is not normal data, it is named the error correction bus. Since the second error correction bus ECC_B is illustrated as a 4-bit bus, the second error correction memory die 126 can be connected to the second error correction bus ECC_B using four data terminals. In other words, the second error correction memory die 126 may have an X4 configuration. Furthermore, the second error correction bus ECC_B may include not only four data lines, but also one or more lines for transmitting one or more data strobe signals for strobbing data.

[0017] The first control bus CONTROL_A, the first data bus DATA_A, the first error correction bus ECC_A, the second control bus CONTROL_B, the second data bus DATA_B, and the second error correction bus ECC_B can be connected to a memory controller that controls the semiconductor package 100.

[0018] The first data memory dies 111-114, the first error correction memory die 116, the second data memory dies 121-124, and the second error correction memory die 126 each have the same storage capacity, but the first data memory dies 111-114 and the second memory dies 121-124 have an X16 configuration, while the first error correction memory die 116 and the second error correction memory die 126 have an X4 configuration. In other words, although all memory dies 111-114, 116, 121-124, and 126 are the same memory die, the only difference is that memory dies 111-114 and 121-124 are set to X16, while memory dies 116 and 126 are set to X4.

[0019] During a write operation on channel A, the first data memory die corresponding to the selected rank among the first data memory dies 111-114, i.e., the activated chip selection signal among the chip selection signals CS_A0-CS_A3, writes data to the first data bus DATA_A, and the first error correction memory die 116 writes the first error correction code to the first error correction bus ECC_A. The first error correction code can be an error correction code for correcting errors in the data on the first data bus DATA_A. In other words, during a write operation on channel A, a write operation can be performed on any one of the first data memory dies 111-114 and the first error correction memory die 116. Although the storage capacity of each of the first data memory dies 111-114 and the first error correction memory die 116 are the same, the number of bits written at one time is different because the first data memory dies 111-114 are composed of X16 bits and the first error correction memory die 116 is composed of X4 bits, making this operation possible. In other words, during a write operation, the number of bits of the data being written is four times the number of bits of the first error correction code, so the first error correction memory die 116 can store the first error correction code corresponding to all the data on the first data memory dies 111 to 114.

[0020] During the read operation of channel A, data read from the selected rank among the first data memory dies 111 to 114, that is, the data memory die corresponding to the activated chip select signal among the chip select signals CS_A0 to CS_A3, is transmitted to the first data bus DATA_A, and the first error correction code read from the first error correction memory die 116 can be transmitted to the first error correction bus ECC_A. That is, during the read operation of channel A, the read operation can be performed by any one of the first data memory dies 111 to 114 and the first error correction memory die 116. The memory controller can correct the error of the data transmitted to the first data bus DATA_A by using the first error correction code transmitted to the first error correction bus ECC_A.

[0021] During a write operation on channel B, the second data memory die corresponding to the selected rank among the second data memory dies 121-124, i.e., the activated chip selection signal among the chip selection signals CS_B0-CS_B3, writes data to the second data bus DATA_B, and the second error correction memory die 126 writes the second error correction code to the second error correction bus ECC_B. The second error correction code can be an error correction code for correcting errors in the data on the second data bus DATA_B. In other words, during a write operation on channel B, the write operation can be performed on any one of the second data memory dies 121-124 and the second error correction memory die 126. Although the storage capacity of each of the second data memory dies 121-124 and the second error correction memory die 126 are the same, the number of bits written at one time is different because the second data memory dies 121-124 are composed of X16 and the second error correction memory die 126 is composed of X4, so this operation is possible. In other words, during a write operation, the number of bits of the data being written is four times the number of bits of the second error correction code, so the second error correction memory die 126 can store the second error correction code corresponding to all the data on the second data memory dies 121 to 124.

[0022] During the read operation of Channel B, data read from the selected rank among the second data memory dies 121 to 124, that is, the data corresponding to the activated chip select signal among the chip select signals CS_B0 to CS_B3, is transmitted to the second data bus DATA_B, and the second error correction code read from the second error correction memory die 126 can be transmitted to the second error correction bus ECC_B. That is, during the read operation of Channel B, a read operation can be performed by any one of the second data memory dies 121 to 124 and the second error correction memory die 126. The memory controller can correct the error of the data transmitted to the second data bus DATA_B by using the second error correction code transmitted to the second error correction bus ECC_B.

[0023] The semiconductor package 100 includes a first error correction memory die 116 that stores a first error correction code for correcting errors of the first data memory dies 111 to 114 of Channel A, and a second error correction memory die 126 that stores a second error correction code for correcting errors of the second data memory dies 121 to 124 of Channel B. Therefore, errors occurring in the semiconductor package 100 can be corrected, and as a result, the reliability of the semiconductor package 100 can be improved. Also, since all the memory dies 111 to 114, 116, 121 to 124, and 126 can be configured with the same memory die, the complexity and cost of the semiconductor package 100 can be reduced.

[0024] The memory dies 111-114, 116, 121-124, and 126 may be stacked vertically or arranged horizontally within the semiconductor package 100. For example, the memory dies 111-114 and 116 of channel A may be stacked vertically, and the memory dies 121-124 and 126 of channel B may be stacked vertically next to them, or all the memory dies 111-114, 116, 121-124, and 126 may be stacked vertically, or all the memory dies 111-114, 116, 121-124, and 126 may be arranged horizontally.

[0025] Figure 2 is a diagram showing the configuration of a semiconductor package 200 according to a second embodiment of the present invention.

[0026] The semiconductor package 200 in Figure 2 further includes an error correction die 210, compared to the semiconductor package 100 in Figure 1.

[0027] The error correction die 210 plays a role in buffering the bus (CONTROL_A, DATA_A, CONTROL_B, DATA_B, CS_A0~CS_A3, CS_B0~CS_B3), and during write operations it generates error correction codes to be stored in the error correction memory dies 116 and 126, and during read operations it can perform error correction operations.

[0028] During a write operation on channel A, the error correction die 210 can encode the data on data bus DATA_A to generate a first error correction code and transmit it to the first error correction bus ECC_A. Then, during a read operation on channel A, the error correction die 210 can use the first error correction code from the first error correction bus ECC_A to correct errors in the data on the first data bus DATA_A and transmit it to the memory controller via the first data bus DATA_A.

[0029] During a write operation on channel B, the error correction die 210 can encode the data on data bus DATA_B to generate a second error correction code and transmit it to the second error correction bus ECC_B. Then, during a read operation on channel B, the error correction die 210 can use the second error correction code from the second error correction bus ECC_B to correct errors in the data on the second data bus DATA_B and transmit the corrected error code to the memory controller via the second data bus DATA_B.

[0030] If the semiconductor package 200 is equipped with an error correction die 210, the semiconductor package 200 itself will generate the error correction code and perform the error correction operation, and the memory controller will not be involved.

[0031] Figure 2 illustrates a semiconductor package 200 equipped with one error correction die 210, but depending on the embodiment, a larger number of error correction dies can be provided, such as an independent error correction die for each channel.

[0032] Figure 3 is a diagram showing the configuration of a semiconductor package 300 according to a third embodiment of the present invention.

[0033] Referring to Figure 3, the semiconductor package 300 includes a first data memory die 311-314, a first error correction memory die 316, a second data memory die 351-354, and a second error correction memory die 356.

[0034] The first data memory dies 311-314 share the control bus CONTROL and the chip selection signal CS_0, and can be connected to different data buses. Since the 32-bit data bus DATA is divided into 8-bit sections and connected to the first data memory dies 311-314, the data bus DATA of the first data memory dies 311-314 may be independent. Each of the first memory dies 311-314 can be connected to the data bus DATA using 8 data terminals. That is, each of the first memory dies 311-314 can have an X8 configuration. The data bus DATA may include not only 32 data lines but also additional lines for strobbing data. The control bus CONTROL is a bus for transmitting control signals to control the first data memory dies 311-314, and the control signals transmitted to the control bus CONTROL may include command address signals, clock signals, etc.

[0035] The first error correction memory die 316 shares the control bus CONTROL and chip selection signal CS_0 with the first data memory dies 311-314 and can be connected to the error correction bus ECC. That is, the first error correction memory die 316 and the first memory dies 311-314 can belong to the same channel and the same rank. The error correction bus ECC is a data bus, and it is named as such because the data stored in the first error correction memory die 316 is an error correction code that is not normal data. Since the error correction bus ECC is exemplified as an 8-bit bus, the first error correction memory die 316 can have an X8 configuration. In addition, the error correction bus ECC may include one or more lines for transmitting one or more data strobe signals, in addition to the eight data lines.

[0036] The second data memory dies 351-354 share the control bus CONTROL and the chip selection signal CS_1, and can be connected to different data buses. Since the 32-bit data bus DATA is divided into 8-bit units and connected to the second data memory dies 351-354, the data bus DATA of the second data memory dies 351-354 may be independent. Each of the second memory dies 351-354 can be connected to the data bus DATA using 8 data terminals. That is, each of the second memory dies 351-354 can have an X8 configuration. The second data memory dies 351-354 can share the data bus DATA with the first data memory dies 311-314. For example, the second data memory die 351 can share the data bus DATA with the first data memory die 311, and the second data memory die 353 can share the data bus DATA with the first data memory die 313. The second error correction memory die 356 shares the control bus CONTROL and chip selection signal CS_1 with the second data memory dies 351-354 and can be connected to the error correction bus ECC. That is, the second error correction memory die 356 and the second memory dies 351-354 can belong to the same channel and the same rank. The second error correction memory die 356 can share the error correction bus ECC with the first error correction memory die 316.

[0037] The control bus CONTROL, data bus DATA, and error correction bus ECC can be connected to a memory controller that controls the semiconductor package 300.

[0038] The first data memory dies 311-314, the first error correction memory die 316, the second data memory dies 351-354, and the second error correction memory die 356 can each have the same storage capacity and the same X8 configuration. In other words, all memory dies 311-314, 316, 351-354, and 356 can be the same memory die.

[0039] The semiconductor package 300 consists of two ranks per channel. During a write operation of rank 0 corresponding to the chip selection signal CS_0, data from the data bus DATA can be written to the first data memory dies 311-314, and the first error correction code of the error correction bus ECC can be written to the first error correction memory die 316. The first error correction code may be an error correction code corresponding to the data written to the first data memory dies 311-314. During the write operation, the number of bits of the data to be written may be four times the number of bits of the first error correction code.

[0040] During a rank 0 read operation corresponding to the chip selection signal CS_0, data read from the first data memory dies 311-314 is transmitted to the data bus DATA, and the first error correction code read from the first error correction memory die 316 is transmitted to the error correction bus ECC. The memory controller can use the first error correction code transmitted to the error correction bus to correct errors in the data transmitted to the data bus DATA.

[0041] During a rank 1 write operation corresponding to the chip selection signal CS_1, data from the data bus DATA can be written to the second data memory dies 351-354, and a second error correction code from the error correction bus ECC can be written to the second error correction memory die 356. The second error correction code may be an error correction code corresponding to the data written to the second data memory dies 351-354. The number of bits of the data written during the write operation may be four times the number of bits of the first error correction code.

[0042] During a rank 1 read operation corresponding to the chip selection signal CS_1, data read from the second data memory dies 351-354 is transmitted to the data bus DATA, and the second error correction code read from the second error correction memory die 356 is transmitted to the error correction bus ECC. The memory controller can use the second error correction code transmitted to the error correction bus to correct errors in the data transmitted to the data bus DATA.

[0043] The semiconductor package 300 includes a first error correction memory die 316 that stores a first error correction code for correcting errors in the first data memory dies 311-314 of rank 0, and a second error correction memory die 356 that stores a second error correction code for correcting errors in the second data memory dies 351-354 of rank 1. As a result, errors occurring in the semiconductor package 300 can be corrected, thereby increasing the reliability of the semiconductor package 300. Furthermore, since all memory dies 311-314, 316, 351-354, and 356 can be made from the same memory die, the complexity and cost of the semiconductor package 300 can be reduced.

[0044] The memory dies 311-314, 316, 351-354, and 356 may be stacked vertically or arranged horizontally within the semiconductor package 300.

[0045] Figure 4 is a diagram showing the configuration of a semiconductor package 400 according to the fourth embodiment of the present invention.

[0046] The semiconductor package 400 in Figure 4, compared to the semiconductor package 300 in Figure 3, further includes an error correction die 410.

[0047] The error correction die 410 buffers the bus (CONTROL, DATA, CS_0, CS_1), generates error correction codes to be stored in the error correction memory dies 316 and 356 during write operations, and performs error correction operations during read operations.

[0048] During a rank 0 write operation, the error correction die 410 can encode the data on the data bus DATA to generate a first error correction code and transmit it to the error correction bus ECC. Then, during a rank 0 read operation, the error correction die 410 can use the first error correction code from the error correction bus ECC to correct errors in the data on the data bus DATA and transmit it to the memory controller via the data bus DATA.

[0049] During a rank 1 write operation, the error correction die 410 can encode the data on the data bus DATA to generate a second error correction code and transmit it to the error correction bus ECC. Then, during a rank 1 read operation, the error correction die 410 can use the second error correction code from the error correction bus ECC to correct errors in the data on the data bus DATA and transmit it to the memory controller via the data bus DATA.

[0050] If the semiconductor package 400 is equipped with an error correction die 410, the semiconductor package 400 itself will generate the error correction code and perform the error correction operation, and the memory controller will not be involved.

[0051] Figure 4 illustrates a semiconductor package 400 equipped with one error correction die 410, but depending on the embodiment, a larger number of error correction dies may be provided, such as error correction dies arranged by rank.

[0052] Figure 5 is a diagram showing the configuration of a semiconductor package 500 according to a fifth embodiment of the present invention.

[0053] Referring to Figure 5, the semiconductor package 500 includes a first data memory die 511, 512, a first error correction memory die 514, a second data memory die 521, 522, a second error correction memory die 524, a third data memory die 531, 532, a third error correction memory die 534, a fourth data memory die 541, 542, and a fourth error correction memory die 544.

[0054] The semiconductor package 500 can consist of two channels, channel A and channel B, and two ranks for each channel, link 0 and rank 1.

[0055] The first data memory dies 511 and 512 and the first error correction memory die 514 can share the first control bus CONTOL_A and the chip selection signal CS_A0. That is, the first data memory dies 511 and 512 and the first error correction memory die 514 can belong to rank 0 of channel A. The first data memory dies 511 and 512 are connected to different data buses, but can be connected to the 16-bit first data bus DATA_A in 8-bit increments. That is, the first data memory dies 511 and 512 can have an X8 configuration. The first error correction memory die 514 is connected to the first error correction bus ECC_A and can have an X8 configuration.

[0056] The second data memory dies 521 and 522 and the second error correction memory die 524 can share the first control bus CONTOL_A and the chip selection signal CS_A1. That is, the second data memory dies 521 and 522 and the second error correction memory die 524 can belong to rank 1 of channel A. The second data memory dies 521 and 522 are connected to different data buses, but can be connected to the 16-bit first data bus DATA_A in 8-bit increments. That is, the second data memory dies 521 and 522 can have an X8 configuration. The second error correction memory die 524 is connected to the first error correction bus ECC_A and can have an X8 configuration.

[0057] The third data memory dies 531 and 532 and the third error correction memory die 534 can share the second control bus CONTOL_B and the chip selection signal CS_B0. That is, the third data memory dies 531 and 532 and the third error correction memory die 534 can belong to rank 0 of channel B. The third data memory dies 531 and 532 are connected to different data buses, but can be connected to the 16-bit second data bus DATA_B in 8-bit increments. That is, the third data memory dies 531 and 532 can have an X8 configuration. The third error correction memory die 534 is connected to the second error correction bus ECC_B and can have an X8 configuration.

[0058] The fourth data memory dies 541 and 542 and the fourth error correction memory die 544 can share the second control bus CONTOL_B and the chip selection signal CS_B1. That is, the fourth data memory dies 541 and 542 and the fourth error correction memory die 544 can belong to rank 1 of channel B. The fourth data memory dies 541 and 542 are connected to different data buses, but can be connected to the 16-bit second data bus DATA_B in 8-bit increments. That is, the third data memory dies 541 and 542 can have an X8 configuration. The fourth error correction memory die 544 is connected to the second error correction bus ECC_B and can have an X8 configuration.

[0059] The memory dies 511, 512, 514, 521, 522, 524, 531, 532, 534, 541, 542, and 544 of the semiconductor package 500 can have the same capacity and the same X8 configuration. In other words, all memory dies 511, 512, 514, 521, 522, 524, 531, 532, 534, 541, 542, and 544 can be the same memory die.

[0060] During rank 0 write and read operations on channel A, write and read operations can be performed on the first data memory dies 511 and 512 and the first error correction memory die 514. During rank 1 write and read operations on channel A, write and read operations can be performed on the second data memory dies 521 and 522 and the second error correction memory die 524. Since the first data bus DATA_A is 16 bits and the first error correction bus ECC_A is 8 bits, the number of bits in the data can be twice the number of bits in the error correction code.

[0061] During rank 0 write and read operations on channel B, write and read operations can be performed on the third data memory dies 531 and 532 and the third error correction memory die 534. During rank 1 write and read operations on channel B, write and read operations can be performed on the fourth data memory dies 541 and 542 and the fourth error correction memory die 544. Since the second data bus DATA_B is 16 bits and the second error correction bus ECC_B is 8 bits, the number of bits in the data can be twice the number of bits in the error correction code.

[0062] The semiconductor package 500 includes a first error correction memory die 514 that stores a first error correction code for correcting errors in the first data memory dies 511 and 512 of channel A rank 0, a second error correction memory die 524 that stores a second error correction code for correcting errors in the second data memory dies 521 and 522 of channel A rank 1, a third error correction memory die 534 that stores a third error correction code for correcting errors in the third data memory dies 531 and 532 of channel B rank 0, and a fourth error correction memory die 544 that stores a fourth error correction code for correcting errors in the fourth data memory dies 541 and 542 of channel B rank 1. As a result, errors occurring in the semiconductor package 500 can be corrected, and the reliability of the semiconductor package 500 can be increased. Furthermore, since all memory dies 511, 512, 514, 521, 522, 524, 531, 532, 534, 541, 542, and 544 can be constructed from the same memory die, the complexity and cost of the semiconductor package 500 can be reduced.

[0063] The memory dies 511, 512, 514, 521, 522, 524, 531, 532, 534, 541, 542, and 544 may be stacked vertically or arranged horizontally within the semiconductor package 500.

[0064] Figure 6 is a diagram showing the configuration of a semiconductor package 600 according to the sixth embodiment of the present invention.

[0065] The semiconductor package 600 in Figure 6, compared to the semiconductor package 500 in Figure 5, further includes an error correction die 610.

[0066] The error correction die 610 plays a role in buffering the bus (CONTROL_A, DATA_A, CONTROL_B, DATA_B, CS_A0, CS_A1, CS_B0, CS_B1), and during write operations, it generates error correction codes to be stored in the error correction memory dies 515, 524, 534, and 544, and during read operations, it can perform error correction operations.

[0067] If the semiconductor package 600 is equipped with an error correction die 610, the semiconductor package 600 itself will generate the error correction code and perform the error correction operation, and the memory controller will not be involved.

[0068] Figure 6 illustrates a semiconductor package 600 equipped with one error correction die 610, but depending on the embodiment, a larger number of error correction dies can be provided, such as an error correction die for each channel.

[0069] Although embodiments of the present invention have been described above with reference to the attached drawings, these are merely for illustrating embodiments based on the technical idea of ​​the present invention, and the present invention is not limited to the embodiments described above. Within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration of the embodiments can be made by a person with ordinary skill in the art to which the present invention belongs, and these can also be said to fall within the scope of the present invention. [Explanation of Symbols]

[0070] 100: Semiconductor Packages 111~114: First data memory die 116: First Error Correction Memory Die 121~124: Second data memory die 126: Second error correction memory die

Claims

1. A first control bus and a first data bus are shared, and a plurality of first data memory dies belonging to different ranks are provided. A first error correction memory die that shares the plurality of first data memory dies with the first control bus and is connected to the first error correction bus, A second control bus and a second data bus are shared, and a plurality of second data memory dies belonging to different ranks are provided. A second error correction memory die that shares the plurality of second data memory dies with the second control bus and is connected to the second error correction bus, A semiconductor package that includes this.

2. When a read and write operation is performed on any one of the plurality of first data memory dies, a read and write operation is performed on the first error correction memory die. When a read and write operation is performed on any one of the plurality of second data memory dies, a read and write operation is performed on the second error correction memory die. The semiconductor package according to claim 1.

3. The first error correction memory die stores a first error correction code for correcting errors in the data stored in the plurality of first data memory dies. The second error correction memory die stores a second error correction code for correcting errors in the data stored on the plurality of second data memory dies. The semiconductor package according to claim 2.

4. The number of bits of data input / output during read and write operations of the plurality of first data memory dies is greater than the number of bits of the first error correction code input / output during read and write operations of the first error correction memory die. The number of bits of data input / output during read and write operations of the plurality of second data memory dies is greater than the number of bits of the second error correction code input / output during read and write operations of the second error correction memory die. The semiconductor package according to claim 3.

5. The capacity of each of the plurality of first data memory dies and the capacity of the first error correction memory die are the same. The capacity of each of the aforementioned second data memory dies and the capacity of the aforementioned second error correction memory die are the same. The semiconductor package according to claim 4.

6. The number of the aforementioned plurality of first data memory dies is N (where N is an integer of 2 or more), The number of data terminals used in each of the plurality of first data memory dies is N times the number of data terminals used in the first error correction memory die. The number of the aforementioned plurality of second data memory dies is N (where N is an integer of 2 or more), The number of data terminals used in each of the aforementioned plurality of second data memory dies is N times the number of data terminals used in the second error correction memory die. The semiconductor package according to claim 4.

7. Further includes one or more error correction dies, The one or more error correction dies described above are: During a write operation on any one of the plurality of first data memory dies, a first error correction code is generated to be written to the first error correction memory die, and during a read operation on any one of the plurality of first data memory dies, the first error correction code read from the first error correction memory die is used to correct errors in the data read from any one of the plurality of first data memory dies. During a write operation on any one of the plurality of second data memory dies, a second error correction code is generated to be written to the second error correction memory die, and during a read operation on any one of the plurality of second data memory dies, the second error correction code read from the second error correction memory die is used to correct errors in the data read from any one of the plurality of second data memory dies. The semiconductor package according to claim 3.

8. Each of the aforementioned plurality of first data memory dies receives one of the chip selection signals 1-1 to 1-N as input. The first error correction memory die receives the chip selection signals 1-1 to 1-N, Each of the aforementioned plurality of second data memory dies receives one of the chip selection signals 2-1 to 2-N as input. The second error correction memory die receives one of the chip selection signals 2-1 to 2-N as input. The semiconductor package according to claim 6.

9. Multiple first data memory dies, each corresponding to one of the multiple ranks of the first channel, A first error correction memory die corresponding to the plurality of ranks of the first channel, Multiple second data memory dies, each corresponding to one of the multiple ranks of the second channel, A second error correction memory die corresponding to the plurality of ranks of the second channel, A semiconductor package that includes this.

10. During the read and write operation of the first channel, Read and write operations are performed on the first data memory die and the first error correction memory die corresponding to the rank selected from the plurality of first data memory dies. During the read and write operation of the second channel, Read and write operations are performed on the second data memory die and the second error correction memory die corresponding to the rank selected from the plurality of second data memory dies. The semiconductor package according to claim 9.

11. The capacity of each of the plurality of first data memory dies is the same as the capacity of the first error correction memory die, and the number of data terminals used in each of the plurality of first data memory dies is greater than the number of data terminals used in the first error correction memory die. The capacity of each of the plurality of second data memory dies is the same as the capacity of the second error correction memory die, and the number of data terminals used by each of the plurality of second data memory dies is greater than the number of data terminals used by the second error correction memory die. The semiconductor package according to claim 10.

12. Further includes one or more error correction dies, The one or more error correction dies described above are: During a write operation on the first channel, a first error correction code is generated to be written to the first error correction memory die, and during a read operation on the first channel, the first error correction code read from the first error correction memory die is used to correct errors in the data read from any one of the plurality of first data memory dies. During a write operation on the second channel, a second error correction code is generated to be written to the second error correction memory die, and during a read operation on the second channel, the second error correction code read from the second error correction memory die is used to correct errors in the data read from any one of the plurality of second data memory dies. The semiconductor package according to claim 10.

13. Multiple first data memory dies sharing a control bus and a first chip selection signal, A plurality of first data memory dies, a first error correction memory die that shares the control bus and the first chip selection signal, A plurality of second data memory dies sharing the control bus and the second chip selection signal, A second error correction memory die that shares the plurality of second data memory dies, the control bus, and the second chip selection signal, A semiconductor package that includes this.

14. The number of the plurality of first data memory dies and the plurality of second data memory dies is N (where N is an integer of 2 or more). The plurality of first data memory dies and the first error correction memory die use one different one from the first to N+1 data buses. The plurality of second data memory dies and the second error correction memory die each use one different one from the first to N+1 data buses. The semiconductor package according to claim 13.

15. During the write operation of the plurality of first data memory dies, a first error correction code corresponding to the data written to the plurality of first data memory dies is written to the first error correction memory die. During the write operation of the plurality of second data memory dies, a second error correction code corresponding to the data written to the plurality of second data memory dies is written to the second error correction memory die. The semiconductor package according to claim 14.

16. Each of the plurality of first data memory dies and the first error correction memory die has the same storage capacity and uses the same number of data terminals. Each of the aforementioned second data memory dies and second error correction memory dies has the same storage capacity and uses the same number of data terminals. The semiconductor package according to claim 15.

17. Further includes one or more error correction dies, The one or more error correction dies described above are: During a write operation of the plurality of first data memory dies, a first error correction code is generated to be written to the first error correction memory die, and during a read operation of the plurality of first data memory dies, the first error correction code read from the first error correction memory die is used to correct the errors of the 8 read from the plurality of first data memory dies. During a write operation to the plurality of second data memory dies, a second error correction code is generated to be written to the second error correction memory die, and during a read operation to the plurality of second data memory dies, the second error correction code read from the second error correction memory die is used to correct the errors in the 8 read from the plurality of second data memory dies. The semiconductor package according to claim 15.

18. Multiple first data memory dies corresponding to the first rank of the first channel, A first error correction memory die corresponding to the first rank of the first channel, A plurality of second data memory dies corresponding to the second rank of the first channel, A second error correction memory die corresponding to the second rank of the first channel, Multiple third data memory dies corresponding to the first rank of the second channel, A third error correction memory die corresponding to the first rank of the second channel, A plurality of fourth data memory dies corresponding to the second rank of the second channel, A fourth error correction memory die corresponding to the second rank of the second channel, A semiconductor package that includes this.

19. During the read and write operation of the first rank of the first channel, read and write operations are performed on the plurality of first data memory dies and the first error correction memory die. During the read and write operations of the second rank of the first channel, read and write operations are performed on the plurality of second data memory dies and the second error correction memory dies. During the read and write operation of the first rank of the second channel, the read and write operations of the plurality of third data memory dies and the third error correction memory die are performed. During the read and write operations of the second rank of the second channel, read and write operations are performed on the plurality of fourth data memory dies and the fourth error correction memory die. The semiconductor package according to claim 18.

20. Each of the plurality of first data memory dies, the first error correction memory die, each of the plurality of second data memory dies, the second error correction memory die, each of the plurality of third data memory dies, the third error correction memory die, each of the plurality of fourth data memory dies, and the fourth error correction memory die have the same storage capacity and use the same number of data terminals. The semiconductor package according to claim 19.

21. Further includes one or more error correction dies, The one or more error correction dies described above are: During the write operation of the first rank of the first channel, a first error correction code is generated to be written to the first error correction memory die, and during the read operation of the first rank of the first channel, the first error correction code read from the first error correction memory die is used to correct errors in the data read from the plurality of first data memory dies. During the write operation of the second rank of the first channel, a second error correction code is generated to be written to the second error correction memory die, and during the read operation of the second rank of the first channel, the second error correction code read from the second error correction memory die is used to correct errors in the data read from the plurality of second data memory dies. During the write operation of the first rank of the second channel, a third error correction code is generated to be written to the third error correction memory die, and during the read operation of the first rank of the second channel, the errors in the data read from the plurality of third data memory dies are corrected using the third error correction code read from the third error correction memory die. During the write operation of the second rank of the second channel, a fourth error correction code is generated to be written to the fourth error correction memory die, and during the read operation of the second rank of the second channel, the fourth error correction code read from the fourth error correction memory die is used to correct errors in the data read from the plurality of fourth data memory dies. The semiconductor package according to claim 19.

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