Indication device

Abstract

The present invention provides a display device in which the uniformity of brightness in the display area around the optical hole is improved. [Solution] The display device according to the embodiment of this specification includes a display panel including a display area containing a plurality of pixels, optical holes within the display area and a hole bezel area around the optical holes, a plurality of scan lines extending in a first direction in the display area and separated by the optical holes, a plurality of bypass connecting lines arranged in the display area and connecting the separated portions of the plurality of scan lines, and a plurality of data lines extending in a second direction intersecting the first direction in the display area and passing through the hole bezel area.

Description

Technical Field

[0001] This specification relates to a display device.

Background Art

[0002] Display devices are applied to various electronic devices such as television receivers (TVs), mobile phones, notebook computers, and tablets.

[0003] Display devices include organic light emitting display devices (OLEDs) that emit light by themselves, liquid crystal display devices (LCDs) that require a separate light source, and the like.

[0004] In addition to the function of displaying images, a display device may include sensors and cameras for sensing and photographing objects.

[0005] In recent years, in order to reduce the bezel area of a display panel, display devices have been developed in which sensors and cameras are arranged within the display area where images are displayed on the display panel, and the display area has optical holes.

Summary of the Invention

Problems to be Solved by the Invention

[0006] When an optical hole is provided in the display area of a display panel, signal lines are designed to bypass through the hole bezel area around the optical hole. The gate lines (including scan lines and emission control lines) and data lines in the hole bezel area are densely arranged.

[0007] The gate lines are arranged separately above and below the center line of the optical hole. If the alignment of the gate lines is disrupted during the manufacturing process, the parasitic capacitance between the upper gate line (located above the center line of the optical hole) and the data line will differ from the parasitic capacitance between the lower gate line (located below the center line of the optical hole) and the data line. In other words, a step in parasitic capacitance occurs with respect to the center line of the optical hole. Due to these differences in parasitic capacitance, the kickback voltage of the upper gate line and the kickback voltage of the lower gate line will differ. This results in a problem where a difference in brightness occurs in the display area with respect to the center line of the optical hole.

[0008] This specification aims to provide a display device in which the uniformity of brightness in the display area around the optical hole is improved.

[0009] This specification aims to provide a display device that can reduce production energy and greenhouse gas emissions.

[0010] The problems described herein are not limited to those mentioned above, and any other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0011] A display device according to the embodiments of this specification includes a display panel including a display area containing a plurality of pixels, optical holes within the display area and hole bezel areas around the optical holes, a plurality of scan lines extending in a first direction in the display area and separated by the optical holes, a plurality of bypass connecting lines arranged in the display area and connecting the separated portions of the plurality of scan lines, and a plurality of data lines extending in a second direction intersecting the first direction in the display area and passing through the hole bezel areas.

[0012] A display device according to the embodiments of this specification includes a display panel including a display area containing a plurality of pixels, optical holes within the display area, and a hole bezel area around the optical holes, and a plurality of scan lines that supply scan signals to the plurality of pixels, wherein a first portion of a first scan line extends in a first direction, a second portion of the first scan line extends in both the first and second directions, and the second portion of the first scan line bypasses the hole bezel area.

[0013] According to the embodiments of this specification, the first and second portions of the first scan line are positioned above the centerline of the optical aperture, the first portion of the second scan line among the plurality of scan lines extends in a first direction, the second portion of the second scan line extends in both the first and second directions, the second portion of the second scan line bypasses the aperture bezel region and is positioned below the centerline of the optical aperture, and the second portion of the first scan line and the second portion of the second scan line are positioned symmetrically with respect to the centerline of the optical aperture.

[0014] According to the embodiments of this specification, a first portion of a second scan line among a plurality of scan lines extends in a first direction, a second portion of the second scan line extends in a first direction, and a second portion of the second scan line passes through the hole bezel region and bypasses the optical hole.

[0015] According to embodiments of this specification, the second portion of the first scanline includes a first bypass portion extending in a second direction and a second bypass portion extending in a first direction.

[0016] According to embodiments of this specification, the display device further includes a plurality of data lines that supply data voltages to a plurality of pixels, wherein a first data line of the plurality of data lines includes a first portion that extends in a second direction and is located outside the perforated bezel region, and the first data line further includes a second portion that passes through the perforated bezel region and bypasses the optical hole. [Effects of the Invention]

[0017] According to the present invention, a specific scan line among the gate lines that greatly affects the brightness of a pixel is configured to bypass and connect through a display area around the optical aperture, and the bypass connecting lines are configured to be arranged symmetrically above and below the center line of the optical aperture. As a result, even if the alignment of a specific scan line is disrupted, no difference in parasitic capacitance occurs between the specific scan lines located above and below the center line of the optical aperture.

[0018] Therefore, a difference in kickback voltage does not occur between specific scan lines located above and below the center line of the optical hole, and the uniformity of brightness in the display area around the optical hole can be improved.

[0019] According to the embodiments described herein, by improving the poor image quality caused by differences in brightness in the display area, the production energy required for additional production of the display device can be reduced, and greenhouse gas emissions can be reduced.

[0020] The effects described herein are not limited to those mentioned above, and any other effects not mentioned can be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawing]

[0021] [Figure 1] This is a schematic block diagram showing a display device according to one embodiment of the present invention. [Figure 2] This figure shows the configuration of the gate drive unit in a display device according to one embodiment of this specification. [Figure 3] This is an equivalent circuit diagram showing the pixel circuit of a pixel in a display device according to an embodiment of the present invention. [Figure 4] This is a schematic plan view showing a display device according to one embodiment of this specification. [Figure 5] This is a schematic cross-sectional view showing the pixels of a display device according to an embodiment of the present invention. [Figure 6] Figure 4 is a plan view showing region VI, and shows some of the signal lines around the optical hole. [Figure 7]It is a diagram showing other signal lines around the optical aperture. [Figure 8] It is a diagram showing other signal lines around the optical aperture. [Figure 9] It is a cross-sectional view taken along the line IX-IX’ of FIG. 6. [Figure 10] It is a diagram showing some of the signal lines around the optical aperture according to an embodiment of the present specification. [Figure 11] It is a diagram showing a cross-sectional view of the A1 region of FIG. 10. [Figure 12] It is a diagram showing a cross-sectional view of the A2 region of FIG. 10. [Figure 13] It is a diagram showing the parasitic capacitance between the first scan line and the data line around the optical aperture in an embodiment of the present specification. [Figure 14] It is a diagram showing some of the signal lines around the optical aperture according to a comparative example. [Figure 15] It is a cross-sectional view taken along the line XV-XV’ of FIG. 14. [Figure 16] It is a diagram showing the parasitic capacitance between the first scan line and the data line in a comparative example. [Figure 17] It is a diagram showing the luminance difference in the display area around the optical aperture in a comparative example.

Embodiments for Carrying Out the Invention

[0022] The advantages, features, and methods for achieving them of the present invention will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in various different forms. However, this embodiment is provided to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the invention.

[0023] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings for illustrative purposes are illustrative, and this specification is not limited to those depicted. The same reference numerals throughout this specification refer to the same components. Furthermore, in describing this specification, specific descriptions of related known technologies are omitted if it is deemed that such descriptions would obscure the essence of this specification. Where "includes," "has," or "becomes" is used in this specification, other parts may be added unless "only" is used. Where a component is shown singularly, it includes multiple components unless otherwise explicitly stated.

[0024] When interpreting the constituent elements, even if there is no explicit mention of the error range, it shall be interpreted as including the error range.

[0025] When describing the positional relationship between two parts, for example, using phrases like "on top of," "above," "below," "to the side," or "adjacent," one or more other parts may be located between the two parts, unless phrases like "immediately," "directly," or "near" are used.

[0026] When describing temporal relationships, for example, when describing the sequence of events using phrases like "after," "next," "then," or "before," it may include cases that are not consecutive, unless "immediately" or "directly" is used.

[0027] While terms such as "First," "Second," etc., are used to describe various components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0028] In describing the components of this specification, terms such as 1st, 2nd, A, B, (a), or (b) may be used. These terms are used to distinguish a component from other components, and the terms do not limit the nature, order, sequence, or number of the component.

[0029] Where it is stated that one component "connects," "joins," "connects," or "adheres" to another component, that component may directly connect, join, connect, or adhere to the other component, but other components may interpose between each component that may indirectly connect, join, connect, or adhere to the other component unless otherwise explicitly stated.

[0030] Where it is stated that a component or layer "contacts" or "overlaps" with another component or layer, it should be understood that while the component or layer may directly contact or overlap with another component or layer, other components may be interposed between each component that may indirectly contact or overlap without any particular express statement.

[0031] "At least one" must be understood to include any combination of one or more of the relevant components. For example, "at least one of the first, second, and third components" can be interpreted as including not only the first, second, or third component alone, but also any combination of two or more of the first, second, and third components.

[0032] The terms "first direction," "second direction," "third direction," "X-axis direction," "Y-axis direction," and "Z-axis direction" should not be interpreted solely as geometric relationships where the relationships are perpendicular to each other, but rather as having a broader range of directions within which the configuration of this specification can function.

[0033] The features of some of the embodiments described herein can be combined or linked together in part or in whole, allowing for various technical interdependencies and drives, and each embodiment can be implemented independently of others or in conjunction with others.

[0034] The following describes various embodiments of this specification in detail with reference to the attached drawings.

[0035] Figure 1 is a schematic block diagram showing a display device according to one embodiment of the present invention.

[0036] Referring to Figure 1, the display device 10 includes a display panel 100 containing multiple pixels (P), a controller 200, a gate drive unit 300 that supplies a gate signal to each of the multiple pixels (P), a data drive unit 400 that supplies a data signal to each of the multiple pixels (P), and a power supply unit 500 that supplies the power necessary for driving each of the multiple pixels (P).

[0037] The display panel 100 includes a display area where pixels (P) are located and a non-display area arranged to surround the display area. A gate drive unit 300 may be located in the non-display area.

[0038] Multiple gate lines (GL) and multiple data lines (DL) in the display panel 100 intersect with each other, and each of the multiple pixels (P) is connected to a gate line (GL) and a data line (DL). Specifically, a single pixel (P) is supplied with a gate signal from a gate drive unit 300 via a gate line (GL), a data signal from a data drive unit 400 via a data line (DL), and a high potential drive voltage (EVDD) and a low potential drive voltage (EVSS) from a power supply unit 500.

[0039] Here, the gate line (GL) supplies the scan signal (SC) and the light emission control signal (EM), and the data line (DL) supplies the data voltage (Vdata). In various embodiments, the gate line (GL) may also include a plurality of scan lines (SCL) that supply the scan signal (SC) and a light emission control line (EML) that supplies the light emission control signal (EM). The gate line (GL) may also include the first to fourth scan lines (SCL1, SCL2, SCL3, SCL4) and the light emission control line (EML). In addition, a plurality of pixels (P) may be supplied with a bias voltage (Vobs) and an initialization voltage (Var, Vini) via a power line (VL).

[0040] Furthermore, each pixel (P) includes a light-emitting element and a pixel circuit that controls the driving of the light-emitting element.

[0041] The pixel circuit includes multiple switching elements, driving elements, and capacitors. Here, the switching elements and driving elements can be made up of thin-film transistors. The driving elements in the pixel circuit control the amount of current supplied to the light-emitting element by the data voltage, thereby adjusting the amount of light emitted by the light-emitting element. The multiple switching elements also operate the pixel circuit by receiving scan signals (SC) supplied via multiple scan lines (SCLs) and light emission control signals (EM) supplied via light emission control lines (EMLs).

[0042] The display panel 100 can be implemented as an opaque display panel or a transparent display panel. A transparent display panel can be applied to a transparent display device in which an image is displayed on the screen and the actual background is visible.

[0043] The display panel 100 can be manufactured as a flexible display panel. The flexible display panel can be implemented as an organic light-emitting display panel using a plastic substrate.

[0044] Each pixel (P) can be divided into red, green, and blue pixels to represent a color. Each pixel (P) may also contain a white pixel.

[0045] A touch sensor may be placed on the display panel 100. Touch input may be sensed using a separate touch sensor or via pixels (P). The touch sensor can be an on-cell type or an add-on type placed on the screen of the display panel, or it can be implemented as an in-cell type touch sensor built into the display panel 100.

[0046] The controller 200 processes video data (RGB) input from an external host system appropriately according to the size and resolution of the display panel 100 and supplies it to the data drive unit 400. The controller 200 generates a gate control signal (GCS) and a data control signal (DCS) using synchronization signals input from an external source, such as a dot clock signal (CLK), a data enable signal (DE), a horizontal synchronization signal (Hsync), and a vertical synchronization signal (Vsync). The controller 200 controls the gate drive unit 300 and the data drive unit 400 by supplying the generated gate control signal (GCS) and data control signal (DCS) to the gate drive unit 300 and the data drive unit 400, respectively.

[0047] The controller 200 may be configured in combination with various processors, such as a microprocessor, mobile processor, or application processor, depending on the device in which it is implemented.

[0048] The external host system may be, for example, a TV system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, or a vehicle system.

[0049] The controller 200 generates a gate control signal (GCS) to control the operating timing of the gate drive unit 300 and a data control signal (DSC) to control the operating timing of the data drive unit 400, based on timing signals (Vsync, Hsync, DE) received from an external host system. The controller 200 controls the operating timing of the display panel drive unit to synchronize the gate drive unit 300 and the data drive unit 400.

[0050] The voltage level of the gate control signal (GCS) output from the controller 200 may be converted to a gate-on voltage (VGL, VEL) and a gate-off voltage (VGH, VEH) via a level shifter (not shown) and supplied to the gate drive unit 300. The level shifter converts the low-level voltage of the gate control signal (GCS) to a gate-low voltage (VGL) and the high-level voltage of the gate control signal (GCS) to a gate-high voltage (VGH). The gate control signal (GCS) includes a start pulse and a shift clock.

[0051] The gate drive unit 300 supplies scan signals (SC) to the gate lines (GL) in response to gate control signals (GCS) supplied from the controller 200. The gate drive unit 300 may be arranged on one or both sides of the display panel 100 in a GIP (Gate In Panel) configuration.

[0052] The gate drive unit 300 sequentially outputs gate signals to multiple gate lines (GL) under the control of the controller 200. The gate drive unit 300 can sequentially supply the gate signals to the gate lines (GL) by shifting the gate signals using a shift register.

[0053] The gate signal may include a scan signal (SC) and an emission control signal (EM) in an organic light-emitting display device. The scan signal (SC) includes a scan pulse that swings between a gate-on voltage (VGL) and a gate-off voltage (VGH). The emission control signal (EM) may include an emission control signal pulse that swings between a gate-on voltage (VEL) and a gate-off voltage (VEH).

[0054] The scan pulse is synchronized with the data voltage (Vdata) to select the pixel (P) on the line where the data will be entered. The light emission control signal (EM) defines the light emission time of the pixel (P).

[0055] The gate drive unit 300 may include a light emission control signal drive unit 310 and at least one scan drive unit 320.

[0056] The light emission control signal drive unit 310 outputs a light emission control signal pulse in response to the start pulse and shift clock from the controller 200, and sequentially shifts the light emission control signal pulse according to the shift clock.

[0057] At least one scan drive unit 320 outputs a scan pulse in response to a start pulse and a shift clock from the controller 200, and shifts the scan pulse in accordance with the shift clock timing.

[0058] The data drive unit 400 converts video data (RGB) into data voltage (Vdata) in response to the data control signal (DCS) supplied from the controller 200, and supplies the converted data voltage (Vdata) to the pixels (P) via data lines (DL).

[0059] Although Figure 1 shows that the data drive unit 400 is arranged in one configuration on one side of the display panel 100, the number and placement of the data drive units 400 are not limited thereto.

[0060] In other words, the data drive unit 400 is composed of multiple integrated circuits (ICs) and may be arranged in multiple sections on one side of the display panel 100.

[0061] The power supply unit 500 generates the DC power necessary to drive the pixel array and the display panel drive unit of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power supply unit 500 receives a DC input voltage applied from a host system (not shown) and can generate DC voltages such as gate-on voltage (VGL, VEL), gate-off voltage (VGH, VEH), high-potential drive voltage (EVDD), and low-potential drive voltage (EVSS). The gate-on voltage (VGL, VEL) and gate-off voltage (VGH, VEH) are supplied to a level shifter (not shown) and the gate drive unit 300. The high-potential drive voltage (EVDD) and low-potential drive voltage (EVSS) are supplied to the pixels (P) in common.

[0062] Figure 2 is a diagram relating to the configuration of a gate drive unit in a display device according to one embodiment of this specification.

[0063] Referring to Figure 2, the gate drive unit 300 includes a light emission control signal drive unit 310 and a scan drive unit 320. The scan drive unit 320 can be composed of first to fourth scan drive units 321, 322, 323, and 324. The second scan drive unit 322 can be composed of odd-numbered second scan drive units 322_O and even-numbered second scan drive units 322_E.

[0064] The gate drive unit 300 may include shift registers configured symmetrically on both sides of the display area (AA). Alternatively, the gate drive unit 300 may be configured such that the shift register on one side of the display area (AA) includes the second scan drive units 322_O, 322_E, the fourth scan drive unit 324, and the light emission control signal drive unit 310, while the shift register on the other side of the display area (AA) includes the first scan drive unit 321, the second scan drive units 322_O, 322_E, and the third scan drive unit 323. However, it is not limited to this, and the light emission control signal drive unit 310 and the first to fourth scan drive units 321, 322, 323, and 324 may be arranged differently depending on the embodiment.

[0065] Each stage (STG1 to STGn) of the shift register may include a first scan signal generation unit (SC11 to SC1(n)), a second scan signal generation unit (SC2_O1 to SC2_O(n), SC2_E1 to SC2_E(n)), a third scan signal generation unit (SC31 to SC3(n)), a fourth scan signal generation unit (SC41 to SC4(n)), and a light emission control signal generation unit (EM1 to EM(n)), respectively.

[0066] The first scan signal generation unit (SC11~SC1(n)) outputs the first scan signal (SC11~SC1(n)) via the first scan line (SCL1) of the display panel 100. The second scan signal generation unit (SC21~SC2(n)) outputs the second scan signal (SC21~SC2(n)) via the second scan line (SCL2) of the display panel 100. The third scan signal generation unit (SC31~SC3(n)) outputs the third scan signal (SC31~SC3(n)) via the third scan line (SCL3) of the display panel 100. The fourth scan signal generation unit (SC41~SC4(n)) outputs the fourth scan signal (SC41~SC4(n)) via the fourth scan line (SCL4) of the display panel 100. The light emission control signal generation unit (EM1~EM(n)) outputs light emission control signals (EM1~EM(n)) via the light emission control line (EML) of the display panel 100.

[0067] The first scan signals (SC11~SC1(n)) can be used to drive A transistors (e.g., compensation transistors) included in the pixel circuit. The second scan signals (SC21~SC2(n)) can be used to drive B transistors (e.g., data supply transistors) included in the pixel circuit. The third scan signals (SC31~SC3(n)) can be used to drive C transistors (e.g., bias transistors) included in the pixel circuit. The fourth scan signals (SC41~SC4(n)) can be used to drive D transistors (e.g., initialization transistors) included in the pixel circuit. The light emission control signals (EM1~EM(n)) can be used to drive E transistors (e.g., light emission control transistors) included in the pixel circuit. For example, by controlling the light emission control transistors of the pixels using the light emission control signals (EM1~EM(n)), the light emission time of the light-emitting element can be made variable.

[0068] The odd-numbered second scan drive units 322_O are connected to the second scan line of the odd-numbered pixel row and can apply a drive signal, while the even-numbered second scan drive units 322_E are connected to the second scan line of the even-numbered pixel row and can apply a drive signal. The odd-numbered second scan drive units 322_O are arranged on both sides of the display area (AA) and can be driven in a dual-feeding manner, applying a drive signal in both directions to each odd-numbered pixel row. The even-numbered second scan drive units 322_E are arranged on both sides of the display area (AA) and can be driven in a dual-feeding manner, applying a drive signal in both directions to each even-numbered pixel row.

[0069] Referring to Figure 2, a bias voltage bus line (VobsL), a first initialization voltage bus line (VarL), and a second initialization voltage bus line (ViniL) may be arranged between the gate drive unit 300 and the display area (AA).

[0070] The bias voltage bus line (VobsL), the first initialization voltage bus line (VarL), and the second initialization voltage bus line (ViniL) can supply the bias voltage (Vobs), the first initialization voltage (Var), and the second initialization voltage (Vini) from the power supply unit 500 to the pixel circuit, respectively.

[0071] In the drawings, the bias voltage bus line (VobsL), the first initialization voltage bus line (VarL), and the second initialization voltage bus line (ViniL) are shown to be located only on one side of the display area (AA), either the left or the right. However, they are not limited to this arrangement and may be located on both sides, and even if they are located on one side, their position is not restricted to the left or right side.

[0072] Referring to Figure 2, the display area (AA) may have one or more optical holes (OH).

[0073] One or more optical holes (OH) may be arranged to overlap with one or more optical electronic devices, such as imaging devices like cameras (image sensors), proximity sensors, and illuminance sensors. One or more optical holes (OH) may have a light transmittance of a certain level or higher for the operation of the optical electronic devices.

[0074] Figure 3 is an equivalent circuit diagram showing the pixel circuit of a pixel in a display device according to an embodiment of the present invention.

[0075] Figure 3 shows an example of a pixel circuit, but the pixel circuit is not limited to the configuration shown in Figure 3 as long as it has a structure that can control the light emission of the light-emitting element (EL). For example, the pixel circuit may include a further scan signal and a switching thin-film transistor connected thereto, and a switching thin-film transistor to which a further initialization voltage is applied, and various arrangements are possible for the connection relationships of the switching elements and the connection positions of the capacitors.

[0076] Referring to Figure 3, each of the multiple pixels (P) may include a pixel circuit having a drive transistor (DT) and a light-emitting element (EL) connected to the pixel circuit.

[0077] The pixel circuit can drive the light-emitting element (EL) by controlling the drive current flowing to it. The pixel circuit may include a drive transistor (DT), first to seventh transistors (T1 to T7), and a capacitor (Cst). Each of the transistors (DT, T1 to T7) may include a first electrode, a second electrode, and a gate electrode. Either the first electrode or the second electrode may be the source electrode, and the other of the first electrode or the second electrode may be the drain electrode.

[0078] Each of the transistors (DT, T1-T7) may be a P-type thin-film transistor or an N-type thin-film transistor. In the embodiment shown in Figure 3, the first transistor (T1) and the seventh transistor (T7) are N-type thin-film transistors, while the other transistors (DT, T2-T6) are P-type thin-film transistors. However, the embodiment is not limited to this, and depending on the embodiment, all or part of the transistors (DT, T1-T7) may be P-type thin-film transistors or N-type thin-film transistors. Furthermore, the N-type thin-film transistors may be oxide thin-film transistors, and the P-type thin-film transistors may be polycrystalline silicon thin-film transistors.

[0079] In the following explanation, we will use the example that the first transistor (T1) and the seventh transistor (T7) are N-type thin-film transistors, while the other transistors (DT, T2~T6) are P-type thin-film transistors. Therefore, the first transistor (T1) and the seventh transistor (T7) turn on when a high voltage is applied, while the other transistors (DT, T2~T6) turn on when a low voltage is applied.

[0080] For example, the first transistor (T1) constituting the pixel circuit can function as a compensation transistor, the second transistor (T2) as a data supply transistor, the third and fourth transistors (T3, T4) as light emission control transistors, the fifth transistor (T5) as a bias transistor, and the sixth and seventh transistors (T6, T7) as initialization transistors.

[0081] The light-emitting element (EL) may include an anode electrode and a cathode electrode. The anode electrode of the light-emitting element (EL) may be connected to a fifth node (N5), and the cathode electrode may be connected to a low-voltage drive (EVSS).

[0082] The drive transistor (DT) may include a first electrode connected to a second node (N2), a second electrode connected to a third node (N3), and a gate electrode connected to a first node (N1). The drive transistor (DT) can supply a drive current to the light-emitting element (EL) based on the voltage at the first node (N1) (or the data voltage stored in the capacitor (Cst) described later).

[0083] The first transistor (T1) may include a first electrode connected to a first node (N1), a second electrode connected to a third node (N3), and a gate electrode that receives a first scan signal (SC1(n)) via a first scan line (SCL1). The first transistor (T1) is turned on in response to the first scan signal (SC1(n)) and connected between the first node (N1) and the third node (N3) to sample the threshold voltage (Vth) of the drive transistor (DT). These first transistors (T1) may also be compensation transistors.

[0084] A capacitor (Cst) may be connected or formed between the first node (N1) and the fourth node (N4). The capacitor (Cst) can store or maintain the provided high potential drive voltage (EVDD).

[0085] The second transistor (T2) may include a first electrode connected to a data line (DL) to receive a data voltage (Vdata), a second electrode connected to a second node (N2), and a gate electrode that receives a second scan signal (SC2(n)) via a second scan line (SCL2). The second transistor (T2) can be turned on in response to the second scan signal (SC2(n)) and transmit the data voltage (Vdata) to the second node (N2). These second transistors (T2) may also be data supply transistors.

[0086] The third transistor (T3) and the fourth transistor (T4) (or the first and second light-emitting control transistors) are connected between the high potential drive voltage (EVDD) and the light-emitting element (EL) to form a current transfer path through which the drive current generated by the drive transistor (DT) travels.

[0087] The third transistor (T3) may include a first electrode connected to the fourth node (N4) to receive a high potential drive voltage (EVDD), a second electrode connected to the second node (N2), and a gate electrode that receives a light emission control signal (EM(n)) via a light emission control line (EML).

[0088] The fourth transistor (T4) may include a first electrode connected to the third node (N3), a second electrode connected to the fifth node (N5) (or the anode electrode of the light-emitting element (EL)), and a gate electrode that receives a light-emitting control signal (EM(n)) via the light-emitting control line (EML).

[0089] The third and fourth transistors (T3, T4) are turned on in response to the light emission control signal (EM(n)), in which case a drive current is supplied to the light-emitting element (EL), and the light-emitting element (EL) can emit light with a brightness corresponding to the drive current (Id).

[0090] The fifth transistor (T5) may include a first electrode that receives a bias voltage (Vobs), a second electrode connected to a second node (N2), and a gate electrode that receives a third scan signal (SC3(n)) via a third scan line (SCL3). These fifth transistors (T5) may also be bias transistors.

[0091] The sixth transistor (T6) may include a first electrode that receives a first initialization voltage (Var), a second electrode connected to the fifth node (N5), and a gate electrode that receives a third scan signal (SC3(n)) via the third scan line (SCL3).

[0092] The sixth transistor (T6) is turned on in response to the third scan signal (SC3(n)) before the light-emitting element (EL) emits light (or after the light-emitting element (EL) emits light), and can initialize the anode electrode (or pixel electrode) of the light-emitting element (EL) using a first initialization voltage (Var). The light-emitting element (EL) may have a parasitic capacitor formed between the anode electrode and the cathode electrode. While the light-emitting element (EL) is emitting light, the parasitic capacitance is charged, and the anode electrode of the light-emitting element (EL) may have a specific voltage. Therefore, by applying the first initialization voltage (Var) to the anode electrode of the light-emitting element (EL) via the sixth transistor (T6), the amount of charge accumulated in the light-emitting element (EL) can be initialized.

[0093] In this specification, the gate electrodes of the fifth and sixth transistors (T5, T6) are configured to receive a common third scan signal (SC3(n)). However, the specification is not limited to this, and the gate electrodes of the fifth and sixth transistors (T5, T6) may be configured to receive separate scan signals and be controlled independently.

[0094] The seventh transistor (T7) may include a first electrode that receives a second initialization voltage (Vini), a second electrode connected to the first node (N1), and a gate electrode that receives a fourth scan signal (SC4(n)) via the fourth scan line (SCL4).

[0095] The seventh transistor (T7) is turned on in response to the fourth scan signal (SC4(n)), and the gate electrode of the drive transistor (DT) can be initialized using the second initialization voltage (Vini). Unwanted charge may remain on the gate electrode of the drive transistor (DT) due to the high potential drive voltage (EVDD) stored in the capacitor (Cst). Therefore, by applying the second initialization voltage (Vini) to the gate electrode of the drive transistor (DT) via the seventh transistor (T7), the amount of residual charge can be initialized.

[0096] In the pixel circuit shown in Figure 3, the brightness of the pixel's light-emitting element is determined by the voltage charged to the first node (N1). The transistors directly connected to the first node (N1) are the first transistor (T1) and the seventh transistor (T7). The signal that turns the first transistor (T1) on / off is the first scan signal (SC1(n)), and the signal that turns the seventh transistor (T7) on / off is the fourth scan signal (SC4(n)). Therefore, when the parasitic capacitance of the first scan line (SCL1) and the fourth scan line (SCL4) changes, the voltage at the first node (N1) changes. Consequently, the variation in the parasitic capacitance of the first scan line (SCL1) and the fourth scan line (SCL4) has a more sensitive effect on the brightness of the pixel's light-emitting element compared to the other scan lines (SCL2, SCL3) and the light emission control line (EML).

[0097] Figure 4 is a schematic plan view showing a display device according to one embodiment of this specification.

[0098] Referring to Figure 4, the display device 10 according to one embodiment of this specification may include a display panel 100, a data drive unit 400, a printed circuit board (PCB), and the like.

[0099] The display panel 100 includes a display area (AA) and a non-display area (NAA). The display area (AA) and the non-display area (NAA) may be areas of the substrate of the display panel 100. The display area (AA) is the area where the image is displayed. The non-display area (NAA) is an area located outside the display area (AA) where the image is not displayed.

[0100] The display area (AA) is an area where multiple pixels are arranged. The non-display area (NAA) is an area where the gate drive unit 300 and various wiring are arranged.

[0101] The display area (AA) includes a plurality of data lines (DL) and a plurality of gate lines (GL) arranged to intersect each other. The plurality of gate lines (GL) may extend in a first direction (DR1), for example, and the plurality of data lines (DL) may extend in a second direction (DR2), for example. The plurality of gate lines (GL) may include first to fourth scan lines (SCL1, SCL2, SCL3, SCL4) that supply scan signals and light emission control lines (EML) that supply light emission control signals.

[0102] The display panel 100 may include an optical hole (OH) located in the display area (AA). The optical hole (OH) may penetrate the display panel 100. The optical hole (OH) may be surrounded by the display area (AA). The optical hole (OH) may be a camera hole. Multiple data lines (DL) and multiple gate lines (GL) may be configured to bypass the optical hole (OH).

[0103] The non-display area (NAA) may be arranged to surround the display area (AA). The non-display area (NAA) may be located above, below, to the left, and to the right of the display area (AA). The gate drive unit 300 may be located, for example, in the non-display area (NAA) on the left and right sides of the display area (AA). The gate drive unit 300 may be formed directly on the substrate of the display panel 100 using a GIP (gate driver in panel) method.

[0104] A data drive unit 400 and a printed circuit board (PCB) may be bonded to a non-display area (NAA) located below the display area (AA). A controller 200, a power supply unit 500, etc., may be mounted on the printed circuit board (PCB).

[0105] A portion of the non-display area (NAA) located below the display panel 100 may be curved with a predetermined curvature. This allows the data drive unit 400 and the printed circuit board (PCB) to be located below the display panel 100. This can reduce the area of ​​the lower bezel of the display device that is visible from the front of the display device 10.

[0106] Figure 5 is a schematic cross-sectional view showing the pixels of a display device according to an embodiment of the present invention.

[0107] Referring to Figure 5, the display panel 100 of the display device according to an embodiment of the present invention may include a substrate 101, a first thin-film transistor 120, a storage capacitor 130, a second thin-film transistor 140, a light-emitting element 160, and a touch sensor 186.

[0108] The substrate 101 may contain an insulating material. The substrate 101 may contain a flexible polymer material. The substrate 101 may have a multilayer structure. For example, the substrate 101 may include a lower substrate layer and an upper substrate layer made of a polymer material such as polyimide (PI), and an intermediate layer made of an inorganic insulating material disposed between the lower substrate layer and the upper substrate layer.

[0109] A first buffer layer 105 may be placed on the substrate 101. The first buffer layer 105 may be placed over the entire display area (AA) of the substrate 101. The first buffer layer 105 may contain an insulating material. For example, the first buffer layer 105 may contain an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. The first buffer layer 105 may have a multilayer structure.

[0110] A first light-shielding layer 109 may be placed on the first buffer layer 105. The first light-shielding layer 109 may contain a metallic substance. For example, the first light-shielding layer 109 may contain a metallic substance such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

[0111] The second buffer layer 112 may be placed on the first buffer layer 105 so as to cover the first light-shielding layer 109. The second buffer layer 112 may contain an insulating material. For example, the second buffer layer 112 may contain an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. The second buffer layer 112 may have a multilayer structure.

[0112] Each sub-pixel may have a pixel circuit. For example, the pixel circuit may include a first thin-film transistor 120, a second thin-film transistor 140, and a storage capacitor 130.

[0113] The first thin-film transistor 120 may be electrically connected to the light-emitting element 160. The first thin-film transistor 120 may include a first semiconductor pattern 121, a first gate insulating layer 122, a first gate electrode 123, a first source electrode 124, and a first drain electrode 125. The first thin-film transistor 120 may be a P-type thin-film transistor. The first thin-film transistor 120 may be a polycrystalline silicon thin-film transistor. The first thin-film transistor 120 may be a driver transistor.

[0114] The first semiconductor pattern 121 may be arranged on the second buffer layer 112 so as to overlap with the first light-shielding layer 109. Light passing through the substrate 101 and traveling toward the first semiconductor pattern 121 can be blocked by the first light-shielding layer 109. Therefore, changes in the characteristics of the first thin-film transistor 120 due to external light can be prevented.

[0115] The first semiconductor pattern 121 may contain a semiconductor material. For example, the first semiconductor pattern 121 may contain a polycrystalline semiconductor material. For example, the first semiconductor pattern 121 may contain low-temperature polycrystalline silicon (Low Temperature Poly-Si: LTPS).

[0116] The first gate insulating layer 122 may be located on the first semiconductor pattern 121. The first gate insulating layer 122 may extend outside the first semiconductor pattern 121. For example, the first gate insulating layer 122 may extend along the upper surface of the second buffer layer 112. The first gate insulating layer 122 may contain an insulating material. For example, the first gate insulating layer 122 may contain an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0117] The first gate electrode 123 may be located on the first gate insulating layer 122. The first gate electrode 123 may be superimposed on the first semiconductor pattern 121. The first gate electrode 123 may contain a conductive material. For example, the first gate electrode 123 may contain a metallic material such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The first gate electrode 123 can be electrically insulated from the first semiconductor pattern 121 by the first gate insulating layer 122. The first gate electrode 123 can be electrically connected to the first light-shielding layer 109.

[0118] The first interlayer insulating layer 114 may be located on the first gate electrode 123. The first interlayer insulating layer 114 may extend outside the first gate electrode 123. The first interlayer insulating layer 114 may extend along the upper surface of the first gate insulating layer 122. The first interlayer insulating layer 114 may contain an insulating material. For example, the first interlayer insulating layer 114 may contain an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0119] The first source electrode 124 and the first drain electrode 125 can be electrically connected to the first semiconductor pattern 121.

[0120] The storage capacitor 130 may include a first storage electrode 131 and a second storage electrode 132. For example, the first storage electrode 131 may be located in the same layer as the first gate electrode 123. For example, the first storage electrode 131 may be made of the same material as the first gate electrode 123. The first storage electrode 131 may be placed on the first gate insulating layer 122 near the first gate electrode 123. The second storage electrode 132 may be placed on the first interlayer insulating layer 114 so as to overlap with the first storage electrode 131.

[0121] The first storage electrode 131 and the second storage electrode 132 may contain a conductive material. For example, the first storage electrode 131 and the second storage electrode 132 may contain metallic materials such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

[0122] A second light-shielding layer 115 may be disposed on the first interlayer insulating layer 114. The second light-shielding layer 115 may be located in the same layer as the second storage electrode 132. The second light-shielding layer 115 may be made of the same material as the second storage electrode 132.

[0123] The isolation insulating layer 116 may be disposed on the first interlayer insulating layer 114 so as to cover the second storage electrode 132 and the second light-shielding layer 115. The isolation insulating layer 116 may contain an insulating material. For example, the isolation insulating layer 116 may contain an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. For example, the isolation insulating layer 116 may have a multilayer structure containing silicon oxide and silicon nitride.

[0124] The second thin-film transistor 140 can be electrically coupled to the first thin-film transistor 120. For example, the second thin-film transistor 140 may include a second semiconductor pattern 141, a second gate insulating layer 142, a second gate electrode 143, a second source electrode 145, and a second drain electrode 146. The second thin-film transistor 140 may be an N-type thin-film transistor. The second thin-film transistor 140 may be an oxide thin-film transistor. The second thin-film transistor 140 may be a switching transistor.

[0125] The second semiconductor pattern 141 may be located on a different layer from the first semiconductor pattern 121. The second semiconductor pattern 141 may be placed on the isolation insulating layer 116 so as to overlap with the second light-shielding layer 115. Light that passes through the substrate 101 and travels toward the second semiconductor pattern 141 can be blocked by the second light-shielding layer 115. Therefore, changes in the characteristics of the second thin-film transistor 140 due to external light can be prevented.

[0126] The second semiconductor pattern 141 may contain a semiconductor material. The second semiconductor pattern 141 may contain a different material from that of the first semiconductor pattern 121. For example, the second semiconductor pattern 141 may contain an oxide semiconductor such as IGZO.

[0127] The second gate insulating layer 142 may be located on the second semiconductor pattern 141. The second gate insulating layer 142 may extend outside the second semiconductor pattern 141. For example, the second gate insulating layer 142 may extend along the upper surface of the isolation insulating layer 116. The second gate insulating layer 142 may contain an insulating material. The second gate insulating layer 142 may contain an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0128] The second gate electrode 143 may be located on the second gate insulating layer 142. The second gate electrode 143 may be superimposed on the second semiconductor pattern 141. The second gate electrode 143 may contain a conductive material. For example, the second gate electrode 143 may contain a metallic material such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). For example, the second gate electrode 143 may be made of the same material as the first gate electrode 123. The second gate electrode 143 can be electrically insulated from the second semiconductor pattern 141 by the second gate insulating layer 142. The second gate electrode 143 can be electrically connected to the second light-shielding layer 115.

[0129] The second interlayer insulating layer 118 may be located on the second gate electrode 143. The second interlayer insulating layer 118 may extend outside the second gate electrode 143. The second interlayer insulating layer 118 may extend along the upper surface of the isolation insulating layer 116. The second interlayer insulating layer 118 may contain an insulating material. For example, the second interlayer insulating layer 118 may contain an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. For example, the second interlayer insulating layer 118 may have a multilayer structure containing silicon oxide and silicon nitride.

[0130] The first source electrode 124, the first drain electrode 125, the second source electrode 145, and the second drain electrode 146 may be arranged on the second interlayer insulating layer 118. The first source electrode 124, the first drain electrode 125, the second source electrode 145, and the second drain electrode 146 may contain a conductive material. For example, the first source electrode 124, the first drain electrode 125, the second source electrode 145, and the second drain electrode 146 may contain metallic materials such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). For example, the first source electrode 124, the first drain electrode 125, the second source electrode 145, and the second drain electrode 146 may have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0131] The first source electrode 124 and the first drain electrode 125 can be electrically connected to the first semiconductor pattern 121. For example, the first source electrode 124 and the first drain electrode 125 can directly contact the first semiconductor pattern 121 through contact holes penetrating the second interlayer insulating layer 118, the second gate insulating layer 142, the isolation insulating layer 116, the first interlayer insulating layer 114, and the first gate insulating layer 122.

[0132] The second source electrode 145 and the second drain electrode 146 can be electrically connected to the second semiconductor pattern 141. For example, the second source electrode 145 and the second drain electrode 146 can directly contact the second semiconductor pattern 141 through contact holes that penetrate the second interlayer insulating layer 118 and the second gate insulating layer 142.

[0133] The storage capacitor 130 can be electrically connected to the second drain electrode 146 of the second thin-film transistor 140. For example, the second drain electrode 146 can contact the second storage electrode 132 through contact holes that penetrate the second interlayer insulating layer 118, the second gate insulating layer 142, and the isolation insulating layer 116.

[0134] The light-emitting element 160 may be arranged on the pixel circuit. For example, the first thin-film transistor 120, the second thin-film transistor 140, and the storage capacitor 130 of each sub-pixel may be located between the substrate 101 and the light-emitting element 160.

[0135] A first planarization layer 150 and a second planarization layer 154 may be sequentially stacked between the pixel circuit and the light-emitting element 160. The first planarization layer 150 and the second planarization layer 154 can provide a flat surface so as to cover any steps caused by the pixel circuit. For example, the first planarization layer 150 and the second planarization layer 154 may contain an organic insulating material.

[0136] A pixel contact electrode 152 may be placed on the first planarization layer 150. A light-emitting element 160 may be placed on the second planarization layer 154. The light-emitting element 160 may include a first electrode 161, a light-emitting layer 165, and a second electrode 167. The light-emitting element 160 can be electrically connected to the first drain electrode 125 of the first thin-film transistor 120 via the pixel contact electrode 152. The pixel contact electrode 152 may contain a conductive material. For example, the pixel contact electrode 152 may contain metallic materials such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). For example, the pixel contact electrode 152 may have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0137] A bank layer 156 may be placed on the second planarization layer 154. The bank layer 156 may contain an organic insulating material. For example, the bank layer 156 may be made of a photosensitive acrylic or polyimide organic material.

[0138] The bank layer 156 can cover the edge of the first electrode 161. The bank layer 156 may have openings that expose a portion of the first electrode 161.

[0139] The light-emitting region can be defined by a portion of the first electrode 161 exposed by an opening in the bank layer 156. The first electrode 161 may contain a conductive material. The first electrode 161 may have high reflectivity. For example, the first electrode 161 may contain metallic materials such as aluminum (Al) and silver (Ag). The first electrode 161 may have a multilayer structure. For example, the first electrode 161 may have a structure in which metals such as aluminum (Al) and silver (Ag) are arranged between transparent conductive materials such as ITO and IZO.

[0140] The light-emitting layer 165 and the second electrode 167 of the light-emitting element 160 may be laminated on the first electrode 161 and the bank layer 156.

[0141] The light-emitting layer 165 may include a light-emitting material layer 163. For example, the light-emitting material layer 163 may include an organic light-emitting material. The light-emitting layer 165 may have a multilayer structure. For example, the light-emitting layer 165 may include at least one of a first light-emitting common layer 162 located between the first electrode 161 and the light-emitting material layer 163, and a second light-emitting common layer 164 located between the light-emitting material layer 163 and the second electrode 167. For example, the first light-emitting common layer 162 may include at least one of a hole injection layer (HIL) and a hole transport layer (HTL). The second light-emitting common layer 164 may include at least one of an electron transport layer (ETL) and an electron injection layer (EIL).

[0142] For example, if the subpixels of each pixel are designed to emit light of different colors from each other, the light-emitting material layer 163 of each subpixel can be separated from the light-emitting material layer 163 of adjacent subpixels. The light-emitting material layer 163 of each subpixel can be formed separately using a fine metal mask (FMM). The edges of the light-emitting material layer 163 may be located on the bank layer 156.

[0143] For example, a spacer 158 may be placed on the bank layer 156. The spacer 158 can prevent damage to the bank layer 156 and the light-emitting material layer 163 by contact with a fine metal mask. For example, the spacer 158 may be made of a photosensitive acrylic or polyimide organic material. The bank layer 156 and the spacer 158 may be formed simultaneously in a single photolithography process, but are not limited to this. The bank layer 156 and the spacer 158 may be formed by separate processes.

[0144] The first common light-emitting layer 162 and the second common light-emitting layer 164 of the light-emitting layer 165 may extend along the surface of the bank layer 156. The first common light-emitting layer 162 and the second common light-emitting layer 164 of the light-emitting layer 165 may cover the top and side surfaces of the spacer 158. For example, the first common light-emitting layer 162 and the second common light-emitting layer 164 may be arranged in common with adjacent subpixels. For example, each of the first common light-emitting layer 162 and the second common light-emitting layer 164 may be arranged in common with all pixels in the display area (AA).

[0145] The second electrode 167 may be arranged in common with adjacent subpixels. For example, the second electrode 167 may be arranged in common with all pixels in the display area (AA). The second electrode 167 may contain a conductive material. For example, the second electrode 167 may be a transparent electrode made of a transparent conductive material such as ITO and IZO.

[0146] A sealing portion 170 may be located on the light-emitting element 160. The sealing portion 170 can prevent damage to the light-emitting element 160 due to external impacts and moisture. The sealing portion 170 may have a multilayer structure. For example, the sealing portion 170 may include sequentially stacked first sealing layer 172, second sealing layer 174, and third sealing layer 176. For example, the first sealing layer 172 and the third sealing layer 176 may contain an inorganic insulating material, and the second sealing layer 174 may contain an organic insulating material.

[0147] The sealing portion 170 may extend not only to the display area (AA) but also to the non-display area (NAA).

[0148] Figure 6 is a plan view of area VI in Figure 4, showing some of the wiring around the optical aperture. For ease of explanation, Figure 6 shows the first scan line (SCL1), the fourth scan line (SCL4), the data line (DL), the lower bypass connection line (BCL1), and the upper bypass connection line (BCL2).

[0149] Referring to Figure 6, the display area (AA) of the display panel 100 may be provided with an optical hole (OH). A ring-shaped hole bezel area (OHBZ) may be provided around the optical hole (OH). Various signal wiring that bypasses the optical hole (OH) may be arranged in the hole bezel area (OHBZ).

[0150] Multiple data lines (DL) in the display area (AA) may extend in the second direction (DR2). Although the drawing only shows multiple data lines (DL) located in the display areas (AA) above and below the optical aperture (OH), multiple data lines (DL) are also located in the display areas (AA) to the left and right of the optical aperture (OH). The following describes the multiple data lines (DL) located above and below the optical aperture (OH).

[0151] Multiple data lines (DLs) can bypass optical holes (OHs) via perforated bezel areas (OHBZs).

[0152] Multiple data lines (DLs) may include a first data line (DL1) and a second data line (DL2) arranged alternately in a first direction (DR1).

[0153] The first data line (DL1) may include a first portion located above the optical hole (OH), a second portion located below the optical hole (OH), and a first data linking line (DCL1) located in the hole bezel region (OHBZ) and connecting the first and second portions. The first and second portions of the first data line (DL1) may be located in the same layer. The first data linking line (DCL1) of the first data line (DL1) may be located in a lower layer than the first and second portions of the first data line (DL1). The first and second portions of the first data line (DL1) may be made of the same material as the pixel contact electrode 152 and located in the same layer. The first data linking line (DCL1) of the first data line (DL1) may be made of the same material as the second source electrode 145 and the second drain electrode 146 and located in the same layer.

[0154] The second data line (DL2) may include a first portion positioned above the optical hole (OH), a second portion positioned below the optical hole (OH), and a second data linking line (DCL2) positioned in the hole bezel region (OHBZ) and connecting the first and second portions. The first portion, second portion, and second data linking line (DCL2) of the second data line (DL2) may be positioned in the same layer as the first and second portions of the first data line (DL1). The second data linking line (DCL2) may be positioned in a higher layer than the first data linking line (DCL1). The first portion, second portion, and second data linking line (DCL2) of the second data line (DL2) may be made of the same material as the pixel contact electrode 152 and positioned in the same layer.

[0155] Multiple first scan lines (SCL1) and multiple fourth scan lines (SCL4) in the display area (AA) may extend in the first direction (DR1). Although the drawing only shows multiple first scan lines (SCL1) and multiple fourth scan lines (SCL4) located in the display areas (AA) to the left and right of the optical aperture (OH), multiple first scan lines (SCL1) and multiple fourth scan lines (SCL4) are also located in the display areas (AA) below and above the optical aperture (OH). The first scan lines (SCL1) and multiple fourth scan lines (SCL4) may be arranged alternately in the second direction (DR2). The following describes the multiple first scan lines (SCL1) and multiple fourth scan lines (SCL4) located to the left and right of the optical aperture (OH).

[0156] Multiple first scan lines (SCL1) and multiple fourth scan lines (SCL4) may be separated by optical holes (OH). Each first scan line (SCL1) may include a first portion located on one side or to the left of the optical hole (OH) and a second portion located on the other side or to the right of the optical hole (OH). The first and second portions of each first scan line (SCL1) may be separated by optical holes (OH). Each fourth scan line (SCL4) may include a first portion located on one side or to the left of the optical hole (OH) and a second portion located on the other side or to the right of the optical hole (OH). The first and second portions of each fourth scan line (SCL4) may be separated by optical holes (OH).

[0157] The end of the first portion of each first scan line (SCL1) may be located within the display area (AA) on one side or the left side of the optical aperture (OH). The end of the second portion of each first scan line (SCL1) may be located within the display area (AA) on the other side or the right side of the optical aperture (OH). The end of the first portion of each fourth scan line (SCL4) may be located within the display area (AA) on one side or the left side of the optical aperture (OH). The end of the second portion of each fourth scan line (SCL4) may be located within the display area (AA) on the other side or the right side of the optical aperture (OH).

[0158] The first and second portions of the first scan line (SCL1) or the fourth scan line (SCL4), which are positioned below the center line of the optical aperture (OH), may be connected by a lower bypass connecting line (BCL1) located within the display area (AA). The lower bypass connection line (BCL1) may include a first lower connection section (BCL1a) connected to the first portion of the first scan line (SCL1) or the fourth scan line (SCL4), a second lower connection section (BCL1b) connected to the first lower connection section (BCL1a), a third lower connection section (BCL1c) connected to the second lower connection section (BCL1b), a fourth lower connection section (BCL1d) connected to the third lower connection section (BCL1c), and a fifth lower connection section (BCL1e) connected to the fourth lower connection section (BCL1d) and the second portion of the first scan line (SCL1) or the fourth scan line (SCL4). The centerline of the optical hole (OH) may be a line that passes through the center of the optical hole (OH) and extends in the first direction (DR1). The first and fourth scan lines, which are positioned below the center line of the optical aperture (OH), may be lower scan lines (SCLL).

[0159] The first lower connector (BCL1a) may extend in a display area (AA) in a direction away from the optical hole (OH) in the first direction (DR1). The first lower connector (BCL1a) may extend in a display area (AA) in a direction aligned with the extending direction of the first scan line (SCL1) and the fourth scan line (SCL4). The first lower connector (BCL1a) may extend in a display area (AA) in a direction intersecting the direction in which the multiple data lines (DL) extend.

[0160] The second lower connecting portion (BCL1b) may extend in a display area (AA) in a second direction (DR2) intersecting the first direction (DR1). The second lower connecting portion (BCL1b) may also extend in a display area (AA) in a direction intersecting the extending directions of the first scan line (SCL1) and the fourth scan line (SCL4).

[0161] The third lower connector (BCL1c) may extend in the first direction (DR1) within the display area (AA). The third lower connector (BCL1c) may extend in the display area (AA) in a direction aligned with the extending direction of the first scan line (SCL1) and the fourth scan line (SCL4). The third lower connector (BCL1c) may extend in the display area (AA) in a direction intersecting the direction in which the multiple data lines (DL) extend.

[0162] The fourth lower connecting portion (BCL1d) may extend in the display area (AA) in a second direction (DR2) that intersects with the first direction (DR1). The fourth lower connecting portion (BCL1d) may extend in the display area (AA) in a direction that intersects with the extending directions of the first scan line (SCL1) and the fourth scan line (SCL4).

[0163] The fifth lower connector (BCL1e) may extend in the display area (AA) in a direction that approaches the optical aperture (OH) in the first direction (DR1). The fifth lower connector (BCL1e) may extend in the display area (AA) in a direction that aligns with the extending direction of the first scan line (SCL1) and the fourth scan line (SCL4). The fifth lower connector (BCL1e) may extend in the display area (AA) in a direction that intersects with the direction in which the multiple data lines (DL) extend.

[0164] The lower bypass connecting line (BCL1) may be located on a different layer from the first scan line (SCL1) and the fourth scan line (SCL4). The lower bypass connecting line (BCL1) may be located on a higher layer than the first scan line (SCL1) and the fourth scan line (SCL4).

[0165] The first lower connector (BCL1a), the third lower connector (BCL1c), and the fifth lower connector (BCL1e) may be located on the same layer and above the first scan line (SCL1) and the fourth scan line (SCL4). The first lower connector (BCL1a) and the fifth lower connector (BCL1e) may penetrate the insulating layer and be connected to the first scan line (SCL1) and the fourth scan line (SCL4).

[0166] The second lower connector (BCL1b) and the fourth lower connector (BCL1d) may be located in the same layer and may be located in a layer above the first lower connector (BCL1a), the third lower connector (BCL1c), and the fifth lower connector (BCL1e). The second lower connector (BCL1b) may penetrate the insulating layer and be connected to the first lower connector (BCL1a) and the third lower connector (BCL1c). The fourth lower connector (BCL1d) may penetrate the insulating layer and be connected to the third lower connector (BCL1c) and the fifth lower connector (BCL1e).

[0167] The first and second portions of the first scan line (SCL1) or the fourth scan line (SCL4), which are positioned above the center line of the optical aperture (OH), may be connected by an upper bypass connecting line (BCL2) positioned within the display area (AA). The upper bypass connecting line (BCL2) may include a first upper connecting section (BCL2a) connected to the first portion of the first scan line (SCL1) or the fourth scan line (SCL4), a second upper connecting section (BCL2b) connected to the first upper connecting section (BCL2a), a third upper connecting section (BCL2c) connected to the second upper connecting section (BCL2b), a fourth upper connecting section (BCL2d) connected to the third upper connecting section (BCL2c), and a fifth upper connecting section (BCL2e) connected to the fourth upper connecting section (BCL2d) and the second portion of the first scan line (SCL1) or the fourth scan line (SCL4). The first and fourth scan lines positioned above the centerline of the optical aperture (OH) may be upper scan lines (SCLU).

[0168] The first upper connector (BCL2a) may extend in a display area (AA) in a direction away from the optical hole (OH) in the first direction (DR1). The first upper connector (BCL2a) may extend in a display area (AA) in a direction aligned with the extending direction of the first scan line (SCL1) and the fourth scan line (SCL4). The first upper connector (BCL2a) may extend in a display area (AA) in a direction intersecting the direction in which the multiple data lines (DL) extend.

[0169] The second upper connecting portion (BCL2b) may extend in a display area (AA) in a second direction (DR2) intersecting the first direction (DR1). The second upper connecting portion (BCL2b) may also extend in a display area (AA) in a direction intersecting the extending directions of the first scan line (SCL1) and the fourth scan line (SCL4).

[0170] The third upper connector (BCL2c) may extend in the first direction (DR1) with a display area (AA). The third upper connector (BCL2c) may extend in the display area (AA) in a direction aligned with the extending direction of the first scan line (SCL1) and the fourth scan line (SCL4). The third upper connector (BCL2c) may extend in the display area (AA) in a direction intersecting the direction in which the multiple data lines (DL) extend.

[0171] The fourth upper connecting portion (BCL2d) may extend in a display area (AA) in a second direction (DR2) intersecting the first direction (DR1). The fourth upper connecting portion (BCL2d) may also extend in a display area (AA) in a direction intersecting the extending directions of the first scan line (SCL1) and the fourth scan line (SCL4).

[0172] The fifth upper connector (BCL2e) may extend in a display area (AA) in a direction that approaches the optical hole (OH) in the first direction (DR1). The fifth upper connector (BCL2e) may extend in a display area (AA) in a direction that aligns with the extending direction of the first scan line (SCL1) and the fourth scan line (SCL4). The fifth upper connector (BCL2e) may extend in a display area (AA) in a direction that intersects with the direction in which the multiple data lines (DL) extend.

[0173] The upper bypass connecting line (BCL2) may be located on a different layer from the first scan line (SCL1) and the fourth scan line (SCL4). The upper bypass connecting line (BCL2) may be located on a layer higher than the first scan line (SCL1) and the fourth scan line (SCL4).

[0174] The first upper connector (BCL2a), the third upper connector (BCL2c), and the fifth upper connector (BCL2e) may be arranged on the same layer and above the first scan line (SCL1) and the fourth scan line (SCL4). The first upper connector (BCL2a) and the fifth upper connector (BCL2e) may penetrate the insulating layer and be connected to the first scan line (SCL1) and the fourth scan line (SCL4).

[0175] The second upper connector (BCL2b) and the fourth upper connector (BCL2d) may be located in the same layer and may be located in a layer higher than the first upper connector (BCL2a), the third upper connector (BCL2c), and the fifth upper connector (BCL2e). The second upper connector (BCL2b) may penetrate the insulating layer and be connected to the first upper connector (BCL2a) and the third upper connector (BCL2c). The fourth upper connector (BCL2d) may penetrate the insulating layer and be connected to the third upper connector (BCL2c) and the fifth upper connector (BCL2e).

[0176] As shown in Figure 6, the lower bypass connecting line (BCL1) and the upper bypass connecting line (BCL2) may be arranged symmetrically above and below the center line of the optical hole (OH).

[0177] Figures 7 and 8 show other signal lines around the optical hole.

[0178] Referring to Figure 7, the multiple third scan lines (SCL3) and multiple light emission control lines (EML) in the display area (AA) may extend in the first direction (DR1). Although the drawing only shows the multiple third scan lines (SCL3) and multiple light emission control lines (EML) located in the display areas (AA) to the left and right of the optical aperture (OH), multiple third scan lines (SCL3) and multiple light emission control lines (EML) are also located in the display areas (AA) to the lower and upper sides of the optical aperture (OH). The third scan lines (SCL3) and light emission control lines (EML) may be arranged alternately in the second direction (DR2). The following describes the multiple third scan lines (SCL3) and multiple light emission control lines (EML) located to the left and right of the optical aperture (OH).

[0179] Multiple third scan lines (SCL3) and multiple emission control lines (EML) may be separated by optical holes (OH). Each third scan line (SCL3) may include a first portion located on one or the left side of the optical hole (OH) and a second portion located on the other or right side of the optical hole (OH). The first and second portions of each third scan line (SCL3) may be separated by optical holes (OH). Each emission control line (EML) may include a first portion located on one or the left side of the optical hole (OH) and a second portion located on the other or right side of the optical hole (OH). The first and second portions of each emission control line (EML) may be separated by optical holes (OH).

[0180] The end of the first portion of each third scan line (SCL3) may be located within the display area (AA) on one side or the left side of the optical opening (OH). The end of the second portion of each third scan line (SCL3) may be located within the display area (AA) on the other side or the right side of the optical opening (OH). The end of the first portion of each light emission control line (EML) may be located within the display area (AA) on one side or the left side of the optical opening (OH). The end of the second portion of each light emission control line (EML) may be located within the display area (AA) on the other side or the right side of the optical opening (OH).

[0181] The first and second portions of each third scanline (SCL3) may be connected by a first connecting wire (CNL1) located in the perforated bezel area (OHBZ). The first and second portions of each light emission control line (EML) may be connected by a second connecting wire (CNL2) located in the perforated bezel area (OHBZ). The first connecting wire (CNL1) and the second connecting wire (CNL2) may be arranged alternately in the second direction (DR2).

[0182] Multiple third scan lines (SCL3) and multiple light emission control lines (EML) may be arranged on the same layer. Multiple third scan lines (SCL3) and multiple light emission control lines (EML) may be arranged on the same layer as the first gate electrode 123.

[0183] The first and second connecting wires (CNL1, CNL2) may be located above the multiple third scan lines (SCL3) and the multiple light emission control lines (EML). The first and second connecting wires (CNL1, CNL2) may be located on the same layer as the second light shielding layer 115 or the second storage electrode 132.

[0184] Referring to Figure 8, multiple second scan lines (SCL2) in the display area (AA) may extend in the first direction (DR1). Multiple second scan lines (SCL2) may bypass the optical hole (OH) and pass through the hole bezel area (OHBZ). Multiple second scan lines (SCL2) may be located in the display area (AA) and hole bezel area (OHBZ) to the left and right of the optical hole (OH). Multiple second scan lines (SCL2) may include multiple odd-numbered second scan lines (SCL2_O) and multiple even-numbered second scan lines (SCL2_E). Although the drawing only shows multiple second scan lines (SCL2) that bypass the optical hole (OH) and pass through the hole bezel area (OHBZ), multiple second scan lines (SCL2) are also located in the display area (AA) below and above the optical hole (OH). Multiple second scan lines (SCL2) may be located on the same layer as the first gate electrode 123.

[0185] Figure 9 is a cross-sectional view taken along the line IX-IX' in Figure 6.

[0186] Referring to Figure 9, the first buffer layer 105, the second buffer layer 112, and the first gate insulating layer 122 may be arranged sequentially on the substrate 101.

[0187] Multiple second scan lines (SCL2) may be arranged on the first gate insulating layer 122. The multiple second scan lines (SCL2) may be made of the same material as the first gate electrode 123 and arranged on the same layer. The first interlayer insulating layer 114 may be arranged on the multiple second scan lines (SCL2).

[0188] Multiple first connecting lines (CNL1) and multiple second connecting lines (CNL2) may be arranged on the first interlayer insulating layer 114. Separating insulating layers 116 may be arranged on the multiple first connecting lines (CNL1) and multiple second connecting lines (CNL2).

[0189] A second gate insulating layer 142 and a second interlayer insulating layer 118 may be sequentially laminated on the isolation insulating layer 116.

[0190] A plurality of first data linking lines (DCL1) may be arranged on the second interlayer insulating layer 118. The plurality of first data linking lines (DCL1) may be made of the same material and arranged on the same layer as the second source electrode 145 and the second drain electrode 146. A first planarization layer 150 may be arranged on the plurality of first data linking lines (DCL1).

[0191] Multiple second data linking lines (DCL2) may be arranged on the first planarization layer 150. The multiple second data linking lines (DCL2) may be made of the same material as the pixel contact electrodes 152 and arranged on the same layer. The second planarization layer 154 may be arranged on the multiple second data linking lines (DCL2).

[0192] The bank layer 156 and the sealing portion 170 may be arranged on the second flattening layer 154.

[0193] Referring to Figures 10 to 12, the connection structure of the lower bypass connection line will be described. The description of the connection structure of the lower bypass connection line can be applied similarly or in a similar manner to the upper bypass connection line.

[0194] Figure 10 shows some wiring around an optical hole according to one embodiment of this specification. Figure 11 shows a cross-sectional view of area A1 in Figure 10. Figure 12 shows a cross-sectional view of area A2 in Figure 10.

[0195] Referring to Figures 10 and 11, a first buffer layer 105 may be placed on the substrate 101, and a second buffer layer 112 may be placed on the first buffer layer 105 so as to cover the first light-shielding layer 109. A first semiconductor pattern 121 may be placed on the second buffer layer 112, and a first gate insulating layer 122 may be placed on the second buffer layer 112 so as to cover the first semiconductor pattern 121. A first gate electrode 123 may be placed on the first gate insulating layer 122 so as to overlap with the first semiconductor pattern 121.

[0196] A first interlayer insulating layer 114 may be arranged on multiple first gate electrodes 123. A second light-shielding layer 115 may be arranged on the first interlayer insulating layer 114. The second light-shielding layer 115 may extend in a first direction (DR1).

[0197] A separation insulating layer 116 may be placed on the second light-shielding layer 115. The separation insulating layer 116 may be placed on the first interlayer insulating layer 114 so as to cover the second light-shielding layer 115.

[0198] A second gate insulating layer 142 may be placed on the isolation insulating layer 116. A fourth scan line (SCL4) may be placed on the second gate insulating layer 142. The fourth scan line (SCL4) may extend in the first direction (DR1). The fourth scan line (SCL4) may overlap with the second light-shielding layer 115. The fourth scan line (SCL4) may be made of the same material and placed in the same layer as the second gate electrode 143. Although not shown, a first scan line (SCL1) may also be placed on the second gate insulating layer 142 next to the fourth scan line (SCL4). The first scan line (SCL1) may extend in the first direction (DR1). The second light-shielding layer 115 may also be placed below the first scan line (SCL1).

[0199] The second interlayer insulating layer 118 may be placed on the second gate insulating layer 142 so as to cover the fourth scanline (SCL4).

[0200] A fifth lower connecting portion (BCL1e) of the lower bypass connecting line (BCL1) may be located on the second interlayer insulating layer 118. The fifth lower connecting portion (BCL1e) may extend in the first direction (DR1). The fifth lower connecting portion (BCL1e) on the right side of the optical hole (OH) may be simultaneously connected to the fourth scan line (SCL4) and the second light-shielding layer 115. The fifth lower connecting portion (BCL1e) may penetrate the second interlayer insulating layer 118 and be connected to the fourth scan line (SCL4), and may also penetrate the second interlayer insulating layer 118, the second gate insulating layer 142, and the isolation insulating layer 116 and be connected to the second light-shielding layer 115. Thus, the same signal can be transmitted to the second light-shielding layer 115 and the fourth scan line (SCL4), and the second light-shielding layer 115 can function as a back gate for a thin-film transistor connected to the fourth scan line (SCL4). The fifth lower connecting portion (BCL1e) may be made of the same material as the second source electrode 145 and the second drain electrode 146 and placed in the same layer.

[0201] The first planarization layer 150 may be placed on the fifth lower connection portion (BCL1e) of the lower bypass connection line (BCL1). The first planarization layer 150 may be placed on the second interlayer insulating layer 118 so as to cover the fifth lower connection portion (BCL1e).

[0202] The fourth lower connecting portion (BCL1d) of the lower bypass connecting line (BCL1) may be located on the first planarization layer 150. The fourth lower connecting portion (BCL1d) may extend in the second direction (DR2). The fourth lower connecting portion (BCL1d) may penetrate the first planarization layer 150 and be connected to the fifth lower connecting portion (BCL1e). The fourth lower connecting portion (BCL1d) may be made of the same material as the pixel contact electrode 152 and located in the same layer.

[0203] The second flattening layer 154 may be placed on the fourth lower connecting portion (BCL1d). The second flattening layer 154 may be placed on the first flattening layer 150 so as to cover the fourth lower connecting portion (BCL1d).

[0204] A bank layer 156, a light-emitting element 160, and a sealing portion 170 may be arranged on the second planarization layer 154.

[0205] Referring to Figures 10 and 12, the third lower connecting portion (BCL1c) of the lower bypass connecting line (BCL1) may be located on the second interlayer insulating layer 118. The third lower connecting portion (BCL1c) may extend in the first direction (DR1). The third lower connecting portion (BCL1c) may be located in the same layer as the second source electrode 145 and the second drain electrode 146, and made of the same material.

[0206] A fourth lower connecting portion (BCL1d) may be located on the first planarization layer 150. The fourth lower connecting portion (BCL1d) may extend in the second direction (DR2). The fourth lower connecting portion (BCL1d) may penetrate the first planarization layer 150 and be connected to the third lower connecting portion (BCL1c). The fourth lower connecting portion (BCL1d) may be located in the same layer as the data line (DL) and the pixel contact electrode 152, and made of the same material.

[0207] As described above, the first lower connecting portion (BCL1a) of the lower bypass connecting line (BCL1) may be located on the second interlayer insulating layer 118. Similar to the fifth lower connecting portion (BCL1e), the first lower connecting portion (BCL1a) on the left side of the optical hole (OH) may be simultaneously connected to the fourth scan line (SCL4) and the second light-shielding layer 115.

[0208] The second lower connecting portion (BCL1b) of the lower bypass connecting line (BCL1) may be located on the first flattening layer 150. The second lower connecting portion (BCL1b) may penetrate the first flattening layer 150 and be connected to the first lower connecting portion (BCL1a). Alternatively, the second lower connecting portion (BCL1b) may penetrate the first flattening layer 150 and be connected to the third lower connecting portion (BCL1c). The second lower connecting portion (BCL1b) may be located on the same layer as the data line (DL).

[0209] In Figures 10 to 12, the connection structure between the fourth scan line (SCL4) and the lower bypass connection line (BCL1) described above may be the same as or similar to the connection structure between the first scan line (SCL1) and the lower bypass connection line (BCL1).

[0210] Figure 13 shows the parasitic capacitance between the first scan line and the data line around the optical aperture in one embodiment of this specification.

[0211] Referring to Figure 13, as in one embodiment of this specification, the first scan line (SCL1) and the fourth scan line (SCL4) of the gate line (GL), which have a significant effect on the brightness of the pixels, are connected by bypassing them through the display area (AA) around the optical hole (OH), and the lower bypass connecting line (BCL1) and the upper bypass connecting line (BCL2) are arranged symmetrically above and below the center line of the optical hole (OH). This prevents a difference in parasitic capacitance between the first and fourth scan lines located above and below the center line of the optical hole from occurring even if the alignment of the first scan line (SCL1) and the fourth scan line (SCL4) is disrupted.

[0212] Therefore, according to one embodiment of this specification, it is possible to improve the uniformity of brightness in the display area around the optical hole without causing a difference in kickback voltage between the first and fourth scan lines located above and below the center line of the optical hole.

[0213] Figure 14 shows some signal lines around the optical hole in a comparative example. Figure 15 is a cross-sectional view taken along the line XV-XV' in Figure 14.

[0214] Referring to Figure 14, multiple first scan lines (SCL1) and multiple fourth scan lines (SCL4) bypass the optical holes (OH) through the hole bezel region (OHBZ).

[0215] Referring to Figure 15, unlike in Figure 9, the first scan line (SCL1) and the fourth scan line (SCL4) may be positioned between the second gate insulating layer 142 and the second interlayer insulating layer 118. If the alignment of the first scan line (SCL1) and the fourth scan line (SCL4) is disrupted, the parasitic capacitance between the first scan line (SCL1) and the fourth scan line (SCL4) and the first data linkage line (DCL1) may fluctuate.

[0216] Figure 16 shows the parasitic capacitance between the first scan line and the data line in the comparative example. Figure 17 shows the brightness difference of the display area around the optical aperture in the comparative example.

[0217] Referring to Figure 16, if the alignment of the first scan lines is disrupted, a step in parasitic capacitance occurs at the center line position of the optical hole (OH). Due to these differences in parasitic capacitance, the kickback voltage of the upper first scan line and the kickback voltage of the lower first scan line will differ. This results in a difference in brightness of the display area relative to the center line of the optical hole.

[0218] Referring to Figure 17, as shown in Figure 16, if the parasitic capacitance of the lower first scan line is even lower than that of the upper first scan line, the brightness of the display area located below the center line of the optical hole may be even greater than the brightness of the display area located above the center line of the optical hole (Brightness 1 > Brightness 2).

[0219] The display devices according to the various embodiments of this specification can be described as follows.

[0220] A display device according to the embodiments of this specification includes a display panel including a display area containing a plurality of pixels, optical holes within the display area and hole bezel areas around the optical holes, a plurality of scan lines extending in a first direction in the display area and separated by the optical holes, a plurality of bypass connecting lines arranged in the display area and connecting the separated portions of the plurality of scan lines, and a plurality of data lines extending in a second direction intersecting the first direction in the display area and passing through the hole bezel areas.

[0221] According to some embodiments of this specification, the multiple bypass connecting lines include a plurality of lower bypass connecting lines connecting the respective detached portions of a plurality of scan lines located below the centerline of the optical aperture, and a plurality of upper bypass connecting lines connecting the respective detached portions of a plurality of scan lines located above the centerline of the optical aperture.

[0222] According to some embodiments of this specification, the plurality of lower bypass connecting lines and the plurality of upper bypass connecting lines may be arranged symmetrically with respect to the center line of the optical hole.

[0223] According to some embodiments of this specification, each separated scan line includes a first portion located on one side of the optical aperture and a second portion located on the other side of the optical aperture. Each lower bypass connecting line may include a first lower connecting portion connected to the first portion of the corresponding scan line located below the centerline of the optical aperture, a second lower connecting portion connected to the first lower connecting portion, a third lower connecting portion connected to the second lower connecting portion, a fourth lower connecting portion connected to the third lower connecting portion, and a fifth lower connecting portion connected to the fourth lower connecting portion and the second portion of the scan line.

[0224] According to some embodiments of this specification, the first lower connector, the third lower connector, and the fifth lower connector may extend in the second direction, while the second lower connector and the fourth lower connector may extend in the first direction.

[0225] According to some embodiments of this specification, the first lower connector, the third lower connector, and the fifth lower connector may be located on the same layer and above the corresponding scanline. The second lower connector and the fourth lower connector may be located on the same layer and above the first lower connector, the third lower connector, and the fifth lower connector.

[0226] According to some embodiments of this specification, the second lower connector and the fourth lower connector may be located on the same layer as the multiple data lines in the display area.

[0227] According to some embodiments of this specification, the first lower connector, the third lower connector, and the fifth lower connector may be located in the same layer as the source electrodes of a plurality of oxide thin-film transistors arranged in a plurality of pixels.

[0228] According to some embodiments of this specification, each separated scan line includes a first portion located on one side of the optical aperture and a second portion located on the other side of the optical aperture. Each upper bypass connecting line may include a first upper connecting portion connected to the corresponding first portion of the scan line located above the centerline of the optical aperture, a second upper connecting portion connected to the first upper connecting portion, a third upper connecting portion connected to the second upper connecting portion, a fourth upper connecting portion connected to the third upper connecting portion, and a fifth upper connecting portion connected to the fourth upper connecting portion and the second portion of the scan line.

[0229] According to some embodiments of this specification, the first upper connector, the third upper connector, and the fifth upper connector may extend in the second direction, while the second upper connector and the fourth upper connector may extend in the first direction.

[0230] According to some embodiments of this specification, the first upper connector, the third upper connector, and the fifth upper connector may be located on the same layer and above the corresponding scanline. The second upper connector and the fourth upper connector may be located on the same layer and above the first upper connector, the third upper connector, and the fifth upper connector.

[0231] According to some embodiments of this specification, the second upper connector and the fourth upper connector may be located on the same layer as the multiple data lines in the display area.

[0232] According to some embodiments of this specification, the first upper connector, the third upper connector, and the fifth upper connector may be located in the same layer as the source electrodes of a plurality of oxide thin-film transistors arranged in a plurality of pixels.

[0233] According to some embodiments of this specification, multiple scan lines may be connected to the gate electrodes of multiple oxide thin-film transistors arranged in multiple pixels.

[0234] The embodiments of this specification have been described in more detail above with reference to the attached drawings. However, this specification is not necessarily limited to these embodiments, and various modifications are possible without departing from the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by these embodiments. Accordingly, the embodiments described above should be understood to be illustrative and not limiting in all respects. [Explanation of Symbols]

[0235] 10 Display device 100 Display Panels AA display area NAA Hidden Area OH optical hole OHBZ hole bezel area 300 Gate drive unit 400 Data-driven unit DL Dataline GL Gate Line SCL1 1st scanline SCL2 2nd scanline SCL3 3rd scanline SCL4 4th scanline EML Light Emission Control Line BCL1 Lower bypass connecting line BCL2 Upper Bypass Connection Line

Claims

1. A display panel including a display area containing multiple pixels, an optical hole within the display area, and a hole bezel area surrounding the optical hole, A plurality of scan lines extending in a first direction within the display area and separated by the optical holes, A plurality of bypass connecting lines are arranged within the display area and connect the separated portions of each of the plurality of scan lines, A plurality of data lines extend in a second direction intersecting the first direction in the display area and passing through the perforated bezel area, including, Display device.

2. The plurality of bypass connecting lines include a plurality of lower bypass connecting lines that connect the separated portions of a plurality of scan lines located below the center line of the optical aperture, and a plurality of upper bypass connecting lines that connect the separated portions of a plurality of scan lines located above the center line of the optical aperture. The display device according to claim 1.

3. The plurality of lower bypass connecting lines and the plurality of upper bypass connecting lines are arranged symmetrically in the vertical direction with respect to the center line of the optical hole. The display device according to claim 2.

4. Each of the plurality of scan lines includes a first portion located on one side of the optical hole and a second portion located on the other side of the optical hole. Each of the plurality of lower bypass connecting lines includes a first lower connecting portion connected to the first portion of the corresponding scan line located below the center line of the optical hole, a second lower connecting portion connected to the first lower connecting portion, a third lower connecting portion connected to the second lower connecting portion, a fourth lower connecting portion connected to the third lower connecting portion, and a fifth lower connecting portion connected to the fourth lower connecting portion and the second portion of the scan line. The display device according to claim 2.

5. The first lower connecting portion, the third lower connecting portion, and the fifth lower connecting portion extend in the second direction, and the second lower connecting portion and the fourth lower connecting portion extend in the first direction. The display device according to claim 4.

6. The first lower connecting portion, the third lower connecting portion, and the fifth lower connecting portion are arranged on the same layer and are located above the corresponding scan lines. The second lower connecting portion and the fourth lower connecting portion are arranged on the same layer and are positioned on a higher layer than the first lower connecting portion, the third lower connecting portion and the fifth lower connecting portion. The display device according to claim 4.

7. The second lower connecting portion and the fourth lower connecting portion are arranged on the same layer as the plurality of data lines in the display area. The display device according to claim 6.

8. The first lower connecting portion, the third lower connecting portion, and the fifth lower connecting portion are arranged in the same layer as the source electrodes of the plurality of oxide thin-film transistors arranged in the plurality of pixels. The display device according to claim 6.

9. Each of the plurality of scan lines includes a first portion located on one side of the optical hole and a second portion located on the other side of the optical hole. Each of the plurality of upper bypass connecting lines includes a first upper connecting portion connected to the first portion of the corresponding scan line positioned above the center line of the optical hole, a second upper connecting portion connected to the first upper connecting portion, a third upper connecting portion connected to the second upper connecting portion, a fourth upper connecting portion connected to the third upper connecting portion, and a fifth upper connecting portion connected to the fourth upper connecting portion and the second portion of the scan line. The display device according to claim 2.

10. The first upper connecting portion, the third upper connecting portion, and the fifth upper connecting portion extend in the second direction, and the second upper connecting portion and the fourth upper connecting portion extend in the first direction. The display device according to claim 9.

11. The first upper connecting portion, the third upper connecting portion, and the fifth upper connecting portion are arranged on the same layer and are positioned above the corresponding scan lines. The second upper connecting portion and the fourth upper connecting portion are arranged on the same layer and are positioned on a higher layer than the first upper connecting portion, the third upper connecting portion and the fifth upper connecting portion. The display device according to claim 9.

12. The second upper connecting portion and the fourth upper connecting portion are arranged on the same layer as the plurality of data lines in the display area. The display device according to claim 11.

13. The first upper connecting portion, the third upper connecting portion, and the fifth upper connecting portion are arranged in the same layer as the source electrodes of the plurality of oxide thin-film transistors arranged in the plurality of pixels. The display device according to claim 11.

14. The plurality of scan lines are connected to the gate electrodes of the plurality of oxide thin-film transistors arranged in the plurality of pixels. The display device according to claim 1.

15. A display panel including a display area containing multiple pixels, optical holes within the display area, and a hole bezel area around the optical holes, Multiple scan lines that supply scan signals to the multiple pixels, Includes, A first portion of the first scan line among the plurality of scan lines extends in a first direction, a second portion of the first scan line extends in both the first and second directions, and the second portion of the first scan line bypasses the hole bezel region. Display device.

16. The first and second portions of the first scan line are positioned above the center line of the optical hole. The first portion of the second scan line among the plurality of scan lines extends in the first direction, and the second portion of the second scan line extends in both the first and second directions. The second portion of the second scan line is positioned below the center line of the optical hole, bypassing the hole bezel region. The second portion of the first scan line and the second portion of the second scan line are arranged symmetrically with respect to the center line of the optical hole, The display device according to claim 15.

17. The first portion of the second scan line among the plurality of scan lines extends in the first direction, The second portion of the second scan line extends in the first direction, The second portion of the second scan line passes through the hole bezel region and bypasses the optical hole. The display device according to claim 15.

18. The first portion of the second scan line is arranged in the first layer, The second portion of the second scan line is located on the second layer which is located on the first layer. The display device according to claim 17.

19. The second portion of the first scan line includes a first bypass portion extending in the second direction and a second bypass portion extending in the first direction. The display device according to claim 15.

20. The first portion of the first scan line is arranged in the first layer, The second bypass portion is located on the second layer which is located on the first layer, The first bypass portion is located on the third layer which is located on the second layer, The display device according to claim 19.

21. The system further includes a plurality of data lines that supply data voltages to the plurality of pixels, The first data line among the plurality of data lines includes a first portion that extends in the second direction and is located outside the hole bezel region, The first data line further includes a second portion that passes through the hole bezel region and bypasses the optical hole. The display device according to claim 15.

22. The second data line among the plurality of data lines includes a first portion that extends in the second direction and is located outside the hole bezel region, The second data line further includes a second portion that passes through the hole bezel region and bypasses the optical hole, The second portion of the first data line is arranged in the first layer, The second portion of the second data line is located on the second layer which is located on the first layer. The display device according to claim 21.

23. The second portion of the first scan line includes a first bypass portion extending in the second direction and a second bypass portion extending in the first direction. The aforementioned second bypass section is located in the first layer, The first bypass portion is located on the second layer which is located on the first layer, The first portion of the first data line is located in the second layer. The display device according to claim 21.

Images