Variable frequency display device

Abstract

The present invention provides a variable frequency display device that can reduce VRR flicker that occurs during sudden changes in frame frequency. [Solution] In a frame of a display panel driven at a frame frequency lower than a preset maximum frame frequency within a variable frame frequency range, the sense signal has at least one or more gate-on sections to turn on the second switch transistor during the vertical blank section.

Description

Technical Field

[0001] This specification relates to a frequency-variable display device.

Background Art

[0002] A frequency-variable display device varies the frame frequency of the video output on the screen according to the attributes of the video data received from an external video source. The frequency-variable display device supports a VRR (Variable Refresh Rate) function that varies the frame frequency within a preset frequency range.

[0003] In the VRR operation, when the frame frequency suddenly changes from a low-speed frame to a high-speed frame or vice versa, the user may recognize a flicker phenomenon due to the cognitive luminance deviation. To reduce the cognitive luminance deviation, a luminance algorithm technology that adjusts the data gain according to the frame frequency is known. However, since this technology determines the data gain of the current frame based on the frequency information of the previous frame, it has a limit in reducing the cognitive luminance deviation (i.e., VRR flicker) between the first frame immediately after the sudden change in the frame frequency and the frame immediately before it.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Therefore, this embodiment provides a frequency-variable display device that may reduce VRR flicker occurring when the frame frequency suddenly changes.

Means for Solving the Problems

[0005] The variable frequency display device according to this embodiment includes a display panel comprising a plurality of subpixels, each subpixel having a drive transistor having a gate electrode connected to a first node, a drain electrode connected to a high potential power supply voltage, and a source electrode connected to a second node; a first switch transistor that connects the first node to a data line supplied with a data voltage in response to a scan signal; a second switch transistor that connects the second node to a reference voltage line supplied with an initialization voltage in response to a sense signal; a storage capacitor connected between the first node and the second node; and a light-emitting element having an anode electrode connected to the second node and a cathode electrode connected to a low potential power supply voltage; and the gate of the first switch transistor. The system includes a gate driver that supplies the scan signal to a scan gate line connected to a gate electrode and the sense signal to a sense gate line connected to the gate electrode of a second switch transistor, wherein one frame interval includes a vertical active interval to which the data voltage is input to the subpixel and a vertical blank interval adjacent to the vertical active interval to which the data voltage is non-input, and in one frame of a display panel driven at a frame frequency lower than a preset maximum frame frequency within a variable frame frequency range, the sense signal has at least one or more gate-on intervals to turn on the second switch transistor during the vertical blank interval.

[0006] The variable frequency display device according to this embodiment includes a display panel comprising a plurality of subpixels, each subpixel including a light-emitting element having a drive transistor having a gate electrode connected to a first node, a drain electrode connected to a high potential power supply voltage, and a source electrode connected to a second node; a first switch transistor that connects the first node to a data line supplied with a data voltage in response to a scan signal; a second switch transistor that connects the second node to a reference voltage line supplied with an initialization voltage in response to a sense signal; a storage capacitor connected between the first node and the second node; and a gate driver that supplies the scan signal to a scan gate line connected to the gate electrode of the first switch transistor and the sense signal to a sense gate line connected to the gate electrode of the second switch transistor, wherein in one frame of the display panel driven at a frame frequency lower than a preset maximum frame frequency within a variable frame frequency range, the scan signal supplied to one of the subpixels includes one gate-on section, and the sense signal supplied to one of the subpixels includes at least two or more gate-on sections.

[0007] In yet another aspect of the present disclosure, the display device includes a display panel configured to be driven at a variable frame frequency within a frequency range, the display panel including subpixels, each subpixel including a drive transistor having a gate electrode connected to a first node and a first electrode connected to a second node; a first switch transistor having a gate electrode connected to a scan gate line and a first electrode connected to a data line configured to receive a data voltage and a second electrode connected to the first node; a second switch transistor having a gate electrode connected to a sense gate line and a first electrode connected to a reference voltage line configured to receive an initialization voltage and a second electrode connected to a second node; a light-emitting element connected to the second node; a data driver configured to supply a data voltage to the data line; and a gate driver configured to supply a scan signal to a scan gate line and a sense signal to a sense gate line. During the nth frame (n is a natural number) of the display panel driven at a frame frequency lower than a preset maximum frame frequency within a frequency range, the scan signal may have one gate-on interval and the sense signal may have two or more gate-on intervals.

[0008] This embodiment applies to a variable-frequency display device in which the length of the vertical blank section changes depending on the frame frequency. By performing a copy programming operation at least once during the vertical blank section at a frame frequency lower than the preset maximum frame frequency, the luminance flashing phenomenon and VRR flicker that occur when the frame frequency changes abruptly can be reduced.

[0009] The effects described herein are not limited to those described above, and a variety of other effects are included herein. [Brief explanation of the drawing]

[0010] [Figure 1] A block diagram showing a variable frequency display device according to this embodiment. [Figure 2]This figure shows the connection configuration of a single pixel according to this embodiment. [Figure 3] This diagram shows the vertical active section and vertical blank section that make up one frame interval. [Figure 4] This figure shows that the length of the vertical front pouch included in the vertical blank section changes depending on the magnitude of the frame frequency. [Figure 5] This figure shows that perceived brightness differs depending on the frame frequency. [Figure 6] This figure shows VRR flicker that occurs under conditions of abrupt changes in frame frequency. [Figure 7] This figure shows that VRR flicker is more visible at low gradation levels compared to high gradation levels. [Figure 8] This figure shows that VRR flicker is more visible at low gradation levels compared to high gradation levels. [Figure 9a] This figure shows a conventional VRR drive system in which programmed operation is performed only during the vertical active section. [Figure 9b] This figure shows a VRR drive system in an embodiment where programming operations are performed in the vertical active section and copy programming operations are performed in the vertical blank section. [Figure 10] This figure shows the supply configuration of scan signals and sense signals in a VRR drive system of an embodiment that is distinguished from conventional VRR drive systems. [Figure 11] This figure shows the voltage difference between the gate and source of subpixels using the VRR driving method of the embodiment in the vertical active section and the vertical blank section belonging to one frame section. [Figure 12a] This figure shows the behavior of subpixels in the programming interval of the vertical active interval in Figure 11. [Figure 12b] This figure shows the operation of subpixels in the emission section of the vertical active section in Figure 11. [Figure 12c] This figure shows the behavior of subpixels in the copy programming section of the vertical blank section in Figure 11. [Figure 12d]It is a diagram showing the operation of sub-pixels in the light-emitting section of the vertical blanking interval in FIG. 11. [Figure 13] It is a diagram showing how luminance flashing occurs in the conventional VRR driving method. [Figure 14] It is a diagram showing that luminance flashing is prevented in the VRR driving method of the embodiment. [Figure 15] It is a diagram showing a feature regarding the interval between a plurality of gate-on intervals included in a sense signal in the VRR driving method of the embodiment.

Mode for Carrying Out the Invention

[0011] The advantages, features, and the methods for achieving them in this specification will become clear by referring to the embodiments described in detail below together with the attached drawings. However, this specification is not limited to the embodiments disclosed below, but is embodied in various different forms. Merely, these embodiments are provided so that the disclosure of this specification is complete and that those with ordinary knowledge in the technical field to which this specification belongs can fully know the scope of the invention. This specification is only defined by the scope of the claims.

[0012] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so this specification is not limited to the matters illustrated. The same reference numerals throughout the specification refer to the same components. When terms such as "including", "having", "being made" are used in this specification, unless "only" is used, other parts may be added. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0013] When interpreting components, it is interpreted as including an error range even without separate explicit description.

[0014] When it comes to the description of positional relationships, for example, when the positional relationships of both parts are described such as "above ~", "at the upper part of ~", "below ~", "beside ~", etc., unless "immediately" or "directly" is used, there may be one or more different parts located between the two parts.

[0015] The first, the second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below may be the second component within the technical concept of this specification.

[0016] Hereinafter, the embodiments of this specification will be described in detail with reference to the attached drawings. In the following description, if it is determined that the specific description of the notification function or configuration according to this specification may blur the gist of this specification unnecessarily, the detailed description thereof will be omitted.

[0017] FIG. 1 is a block diagram showing a frequency variable type display device according to this embodiment.

[0018] Referring to FIG. 1, the display panel 100 includes a screen AA on which an input image is displayed. The screen AA includes a pixel array on which pixel data (hereinafter referred to as "video data") DATA of the input image is displayed. The pixel array includes a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, a reference voltage line, and a plurality of pixels.

[0019] Pixels may be arranged on the screen AA in a matrix form defined by the data lines DL, the gate lines GL, and the reference voltage line. In addition to the matrix form, pixels may be arranged on the screen AA in various ways such as a stripe form, a diamond form, etc.

[0020] A pixel array includes a column of pixels and pixel rows L1 to Ln that intersect the column. A column of pixels contains pixels arranged along the y-axis. A pixel row contains pixels arranged along the x-axis. One vertical interval is the time required to write one frame's worth of image data DATA to all pixels on the screen. One horizontal interval is the time obtained by dividing one frame interval by the number of pixel rows L1 to Ln. One horizontal interval is the time required to write one pixel row's worth of image data DATA, which shares a gate line GL, to the pixels of that pixel row.

[0021] Each pixel may contain red (R) subpixels 101, green (G) subpixels 101, blue (B) subpixels 101, and white (W) subpixels 101 to embody a color.

[0022] The display device of this embodiment may be implemented as an organic light-emitting display device. In this case, the pixel circuit may include a light-emitting element, a driving element, one or more switching elements, and a capacitor. The light-emitting element may be implemented as an organic light-emitting diode (OLED). The driving current that causes the light-emitting element to emit light may be adjusted according to the gate-source voltage of the driving element. The driving element and the switching element may be implemented as transistors. The semiconductor layer of the transistor may include amorphous silicon or polysilicon. At least some of the semiconductor layers of the transistor may include oxide.

[0023] The pixel circuit is connected to the data line DL and the gate line GL. In Figure 1, "D1~D3" shown within the circle are data lines, and "Gn-2~Gn" are gate lines.

[0024] A touch sensor may be placed on the display panel 100. The touch sensor may be placed on the screen AA of the display panel 100 as an on-cell type or add-on type, or it may be implemented as an in-cell type touch sensor embedded in the pixel array. Touch input may be sensed via the touch sensor or sensed only via pixels without a touch sensor.

[0025] The source driver 110 converts the video data DATA received from the timing controller 130 into a gamma-compensated voltage using a digital-to-analog converter (DAC) to generate a data voltage. The source driver 110 supplies the data voltage to the data line DL. The data voltage is applied to the gate electrode of the driving element via the switch element of each sub-pixel 101. The source driver 110 supplies the initialization voltage VpreR received from the power supply circuit 200 to the reference voltage line connected to the sub-pixel. The initialization voltage VpreR is supplied to the reference voltage line and applied to the source electrode of the driving element via the switch element of each sub-pixel 101.

[0026] The source driver 110 may be implemented as one or more source drive integrated circuits. The source drive integrated circuit may be connected to the timing controller 130 via an internal interface circuit. The internal interface circuit may be implemented as an EPI (Embedded Clock Point to Point Interface). The source drive integrated circuit may further include a touch driver. The touch driver generates a touch sensor drive signal and converts changes in the charge amount of the touch sensor into touch raw data. The touch driver transmits the touch raw data to the host system via a separate interface circuit. The separate interface circuit may be implemented as an SPI (Serial Peripheral Interface).

[0027] The gate driver 120 may be formed in the bezel area BZ located outside the screen AA of the display panel 100. No image is displayed in the bezel area BZ. Under the control of the timing controller 130, the gate driver 120 sequentially supplies gate signals synchronized with the data voltage to the gate line GL. The gate signals simultaneously activate pixels in the same pixel row that are charged with the data voltage. The gate driver 120 outputs the gate signals using one or more shift registers and shifts those gate signals. The gate signals are sometimes called scan signals. The scan signals may have a gate-on voltage VON and a gate-off voltage VOFF received from the power supply circuit 200.

[0028] The timing controller 130 receives video data DATA and timing signals synchronized with this video data DATA from a host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync defines a vertical interval (i.e., one frame). The horizontal synchronization signal Hsync defines a horizontal interval. The data enable signal DE defines the time during which a data voltage is input to a subpixel in the vertical interval (i.e., the vertical active interval). The remaining time in the vertical interval excluding the vertical active interval is the vertical blank interval. The data enable signal DE swings during the vertical active interval and is non-swing during the vertical blank interval.

[0029] The timing controller 130 generates a source timing control signal DDC for controlling the operation timing of the source driver 110 and a gate timing control signal GDC for controlling the operation timing of the gate driver 120, using the timing signals Vsync, Hsync, and DE received from the host system.

[0030] The host system may be one of the following: a television, set-top box, navigation system, personal computer (PC), home theater, vehicle display system, mobile device, or wearable device. In mobile devices and wearable devices, the source driver 110, timing controller 130, level shifter 140, etc., may be integrated into a single drive integrated circuit.

[0031] The level shifter 140 shifts the logic voltage level of the gate timing control signal GDC output from the timing controller 130 to the gate-on voltage VON and gate-off voltage VOFF and supplies them to the gate driver 120. The low logic voltage of the gate timing control signal GDC is downshifted to the gate-off voltage VOFF, and the high logic voltage is upshifted to the gate-on voltage VON.

[0032] The power supply circuit 200 generates various power supply voltages used for panel driving. The power supply circuit 200 generates the gate-on voltage VON and gate-off voltage VOFF used for generating scan signals, generates the high-potential power supply voltage EVDD and low-potential power supply voltage EVSS supplied to sub-pixels, and generates the initialization voltage VpreR supplied to the reference voltage line.

[0033] Figure 2 shows the connection configuration of a single pixel according to this embodiment.

[0034] Referring to Figure 2, a single pixel PXL may include four subpixels SP1, SP2, SP3, and SP4 that share a reference voltage line RL. The four subpixels SP1, SP2, SP3, and SP4 may be R (red), G (green), B (blue), and W (white) subpixels to constitute the same pixel. Each of the subpixels SP1, SP2, SP3, and SP4 may include, as an example, a light-emitting element OLED, a driving transistor DT, first and second switching transistors ST1 and ST2, and a storage capacitor Cst.

[0035] The light-emitting element OLED emits light and expresses brightness in response to the drive current supplied by the drive transistor DT. The anode electrode of the light-emitting element OLED is connected to the second node N2, and the cathode electrode is connected to the input terminal of the low-potential power supply voltage EVSS.

[0036] The drive transistor DT is a drive element that generates a drive current corresponding to the voltage difference between the gate and source and supplies it to the light-emitting element OLED. The gate electrode of the drive transistor DT is connected to the first node N1, the drain electrode is connected to the input terminal of the high-potential power supply voltage EVDD, and the source electrode is connected to the second node N2.

[0037] The gate electrode of the first switch transistor ST1 is connected to the scan gate line GLa, the first electrode of the first switch transistor ST1 is connected to the data line DL, and the second electrode is connected to the first node N1. In response to the scan signal SCAN from the scan gate line GLa, the first switch transistor ST1 connects the first node N1 to the data line DL, which is supplied with the data voltage Vdata.

[0038] The gate electrode of the second switch transistor ST2 is connected to the sense gate line GLb. The first electrode of the second switch transistor ST2 is connected to the reference voltage line RL, and the second electrode is connected to the second node N2. The second switch transistor ST2 connects the second node N2 and the reference voltage line RL, which is supplied with an initialization voltage VpreR, in response to the sense signal SEN from the sense gate line GLb.

[0039] One electrode of the storage capacitor Cst is connected to the first node N1, and the other electrode is connected to the second node N2.

[0040] A first switch SW1 and a second switch SW2 may be further connected to the reference voltage line RL. The first switch SW1 connects the input terminal of the initialization voltage VpreR to the reference voltage line RL. The second switch SW2 connects a sensing circuit SU, which senses the electrical characteristics (threshold voltage or electron mobility) of the drive transistor DT, to the reference voltage line RL.

[0041] In the nth (where n is a natural number) frame, the first switch SW1 may be turned on so that the gate-source voltage difference of the drive transistor DT is programmed. While the second switch SW2 is turned on, the electrical connection between the input terminal of the initialization voltage VpreR and the reference voltage line RL is disconnected. The sensing circuit SU performs sampling while the second switch SW2 is on.

[0042] The first switch SW1, the second switch SW2, and the sensing circuit SU may be provided in the source driver 110. However, in models where sensing functionality is not required, the second switch SW2 and the sensing circuit SU may be omitted.

[0043] Figure 3 shows the vertical active section and vertical blank section that make up one frame interval. Figure 4 shows that the length of the vertical blank section included in the vertical blank section changes depending on the magnitude of the frame frequency.

[0044] Referring to Figure 3, a single frame interval (vertical interval) may be defined by the vertical synchronization signal Vsync. A single frame interval (vertical interval) may be defined as the time interval between adjacent polling edges (or rising edges) of the vertical synchronization signal Vsync.

[0045] Within a single frame interval (vertical interval), the vertical active interval ACT and the vertical blank interval BLK may be defined by the data enable signal DE. The vertical active interval ACT is the interval in which the data enable signal DE swings, and the vertical blank interval BLK is the interval in which the data enable signal DE does not swing.

[0046] The variable frequency display device of this embodiment operates in VRR mode, in which the length of one frame varies within a variable frequency range below a preset maximum frame frequency. In the following embodiment, the maximum frame frequency is exemplified at 240 Hz, but the technical concept is not limited to this. In VRR mode, the frame frequency may vary to A, B, and C Hz, as shown in Figure 4. When the frame frequency changes, the length of one frame interval also changes accordingly. In VRR mode, the length of the vertical active interval ACT is fixed to a constant value determined based on the maximum frame frequency, and the length of the vertical blank interval BLK changes according to the frame frequency. The length of the vertical blank interval may be BLK1 for a frame frequency of A Hz, BLK2 for a frame frequency of B Hz, and BLK3 for a frame frequency of C Hz. Here, when A > B > C, BLK1 <BLK2<BLK3である。

[0047] During the fixed-length vertical active interval ACT, the voltage difference between the data voltage corresponding to the image data DATA and the initialization voltage, i.e., the gate-source voltage difference of the drive transistor, is set at each subpixel. This setting operation is sometimes called the programming operation. Once the programming operation is complete, the gate-source voltage difference of the drive transistor set at the subpixel is maintained, while the source voltage of the drive transistor rises to the threshold voltage of the light-emitting element.

[0048] To reduce VRR flicker, additional copy programming operations may be performed during the variable-length vertical blank section (BLK). This will be described in detail later using Figures 9b, 10, 11, 12a-12d, 14, and 15.

[0049] Figure 5 shows that the perceived brightness differs depending on the magnitude of the frame frequency. Figure 6 shows VRR flicker that occurs under conditions of abrupt changes in frame frequency. Figures 7 and 8 show that VRR flicker is even more visible at low gradation than at high gradation.

[0050] The peak-low brightness points in Figures 5 and 6 represent the points where the programming operation takes place. During the programming operation, the light-emitting operation of the OLED light-emitting element stops, and after the programming operation is completed, the light-emitting operation of the OLED light-emitting element resumes.

[0051] Programming and illumination operations occur sequentially within a single frame. The more frames placed within a given time, i.e., the higher the frame frequency, the more programming operations occur, and the lower the perceived brightness. For example, the number of programming operations within a given time at a frame frequency of 240Hz may be 12, at a frame frequency of 120Hz it may be 6, and at a frame frequency of 60Hz it may be 3. As a result, the real-time brightness integral value (i.e., perceived brightness) at a frame frequency of 240Hz is L1, the real-time brightness integral value (i.e., perceived brightness) at a frame frequency of 120Hz is L2 (higher than L1), and the real-time brightness integral value (i.e., perceived brightness) at a frame frequency of 60Hz is L3 (higher than L2).

[0052] Thus, assuming that the grayscale of the displayed image is the same, the perceived brightness is relatively higher at lower frame frequencies compared to higher frame frequencies. Therefore, when the frame frequency changes from high to low frequencies, VRR flicker may occur due to fluctuations in perceived brightness.

[0053] VRR flicker can be relatively more noticeable in low-gradation sections compared to high-gradation sections, as shown in Figures 7 and 8. When defining luminance pass-through rate as the speed at which the target luminance saturation level is reached immediately after programming, the luminance pass-through rate of high-gradation images is relatively higher than that of low-gradation images. Therefore, VRR flicker due to frequency fluctuations is not a major problem in high-gradation images, but it can be easily noticed when displaying low-gradation images.

[0054] Figure 9a shows a conventional VRR drive system in which programming operations are performed only in the vertical active section. Figure 9b shows a VRR drive system in an embodiment in which programming operations are performed in the vertical active section and copy programming operations are performed in the vertical blank section.

[0055] As shown in Figure 9a, in the case of a VRR drive system where programming is performed only in the vertical active section (ACT), as explained in Figure 5, the real-time luminance integral value (i.e., cognitive luminance) increases as the frame frequency decreases. Therefore, if the frame frequency changes abruptly from high frequency to low frequency, VRR flicker may occur due to fluctuations in cognitive luminance.

[0056] In contrast, as shown in Figure 9(b), in a VRR drive system where programming is performed in the vertical active section (ACT) and copy programming is performed in the vertical blank section (BLK), fluctuations in perceived brightness due to frame frequency fluctuations can be minimized or reduced, and VRR flicker can be improved.

[0057] Referring to Figure 9b, the programming operation may be embodied by a scan signal SCAN and a sense signal SEN, which have gate-on intervals synchronized with the input of the data voltage Vdata during the vertical active interval ACT.

[0058] The copy programming operation may be embodied by at least one sense signal SEN having a gate-on interval in a vertical blank section BLK where there is no data voltage Vdata input. The gate-on interval may be defined as an interval maintained at a gate-on voltage that can turn on the first and second switch transistors in a subpixel. In the vertical blank section BLK, the scan signal SCAN does not have a gate-on interval and is maintained at a gate-off voltage. The gate-off voltage is a voltage that can turn off the first and second switch transistors in a subpixel.

[0059] During the vertical blank section (BLK), the gate electrode of the drive transistor is floating due to the gate-off voltage scan signal (SCAN), and an initialization voltage is applied to the source electrode by the gate-on voltage sense signal (SEN), thereby realizing copy programming operation. The initialization voltage applied to the source electrode may lower the source voltage of the drive transistor from the threshold voltage of the light-emitting element to the initialization voltage. At this time, since the gate electrode of the drive transistor is coupled to the source electrode via a storage capacitor, the gate voltage of the drive transistor also becomes lower. The gate-source voltage difference of the drive transistor due to this copy programming operation is substantially the same as that due to programming operation.

[0060] Similar to the programming section of the vertical active section (ACT), the source voltage of the drive transistor is lower than the threshold voltage of the light-emitting element during the copy programming section of the vertical blank section (BLK), causing the light-emitting element to not emit light. The longer the vertical blank section (BLK), the more copy programming sections it contains, thus improving the luminance flashing phenomenon that occurs in long vertical blank sections (BLK) of slow frames. As a result, VRR flicker that occurs when the frame frequency changes abruptly from a fast frame to a slow frame can be reduced.

[0061] The copy programming interval is not allocated within the vertical blank interval of the shortest frame interval corresponding to the maximum frame frequency within the variable frequency range. The copy programming interval is allocated within the vertical blank interval of a frame interval under frame frequency conditions lower than the maximum frame frequency.

[0062] A vertical blank section BLK can contain at least one copy programming section, and the number of programming sections allocated is proportional to the length of the vertical blank section BLK. Specifically, the number of copy programming sections in a vertical blank section BLK of a second length, which is longer than the first length, may be greater than the number of copy programming sections in a vertical blank section BLK of a first length.

[0063] Figure 10 shows the supply configuration of scan signals and sense signals in a VRR drive system of an embodiment that is distinguished from the conventional VRR drive system.

[0064] Referring to Figure 10, in the conventional VRR drive system, the scan signal SCAN and sense signal SEN are sequentially supplied to each pixel row in sync during the vertical active section ACT for programming operation. In both the 100Hz first and second frames, the length of the vertical active section ACT is determined based on the maximum frame frequency of 240Hz. On the other hand, the scan signal SCAN and sense signal SEN are not supplied to the pixel row during the vertical blank section BLK.

[0065] In contrast, in the VRR drive method of the embodiment, during the vertical active section ACT, the scan signal SCAN and the sense signal SEN are sequentially supplied in sync with each other on a pixel row basis for programming operation, and then during the vertical blank section BLK, the sense signal SEN is sequentially supplied on a pixel row basis for copy programming operation.

[0066] In both the first and second frames at 100Hz, the length of the vertical blank section (BLK) is greater than the length of the vertical active section (ACT). The copy programming operation in the vertical blank section (BLK) of both the first and second frames may be performed twice for each subpixel.

[0067] The length of the vertical blank section BLK may be a non-integer multiple greater than the length of the vertical active section ACT. In this case, the timing of supplying the sense signal SEN for the second copy programming operation of the first frame and the timing of supplying the sense signal SEN for the programming operation of the second frame may overlap by a certain overlap time OT. As a result, "SEN Multi Driving" may occur for a certain period of time OT. Unlike the programming operation, no data voltage is supplied during the copy programming operation, so "SEN Multi Driving" does not cause any operational problems.

[0068] Figure 11 shows the voltage difference between the gate and source of a subpixel using the VRR driving method of the embodiment in the vertical active section and the vertical blank section belonging to one frame interval. Figures 12a, 12b, 12c, and 12d show the operation of the subpixel in the programming section of the vertical active section, the emission section of the vertical active section, the copy programming section of the vertical blank section, and the emission section of the vertical blank section, respectively, in Figure 11.

[0069] Referring to Figure 11, for copy programming operation in the vertical blank section BLK, the sense signal SEN may have at least one gate-on section (hereinafter referred to as VON section) such that it may turn on the second switch transistor ST2 during the vertical blank section BLK at a frame frequency lower than the max frame frequency.

[0070] Referring to Figures 11 and 12a, during the programming section TA of the vertical active section ACT, the scan signal SCAN and sense signal SEN maintain the VON section, turning on both the first switch transistor ST1 and the second switch transistor ST2. The data voltage Vdata is applied to the first node N1, which is connected to the gate electrode of the drive transistor DT via the first switch transistor ST1, and becomes the gate voltage Vg of the drive transistor DT. The initialization voltage VpreR is applied to the second node N2, which is connected to the source electrode of the drive transistor DT via the second switch transistor ST2, and becomes the source voltage Vs of the drive transistor DT. As a result, the gate-source voltage difference W-Vgs set for the programming section TA of the vertical active section ACT is "Vdata-VpreR". The gate-source voltage difference W-Vgs is greater than the threshold voltage of the drive transistor DT.

[0071] In the boosting section TB1 of the vertical active section ACT, the first switch transistor ST1 and the second switch transistor ST2 are turned off by the scan signal SCAN and sense signal SEN of the gate off voltage VOFF. The gate-source voltage difference W-Vgs in the programming section TA is maintained, and a drive current corresponding to the gate-source voltage difference W-Vgs flows through the drive transistor DT. This drive current up-boostifies the source voltage Vs of the drive transistor DT to the turn-on voltage Vf of the light-emitting element OLED. At this time, the gate voltage Vg of the drive transistor DT also rises due to cap boosting by the storage capacitor Cst. However, due to the first cap boosting loss, the increase in gate voltage Vg may be smaller than the increase in source voltage Vs.

[0072] Referring to Figures 11 and 12b, in the light-emitting section TE1 of the vertically active section ACT, the cap boosting loss may set the gate-source voltage difference E-Vgs in the light-emitting section TE1 to be smaller than the gate-source voltage difference W-Vgs in the programming section TA. The cap boosting loss may be defined as "Cst capacitance / (Cst capacitance + parasitic capacitance Cx)". The parasitic capacitance Cx may be defined as the sum of the parasitic capacitances that affect the gate electrode of the drive transistor DT. The larger the parasitic capacitance Cx, the greater the cap boosting loss and the larger the difference between W-Vgs and E-Vgs. In the light-emitting section TE1 of the vertically active section ACT, a drive current Ids corresponding to the gate-source voltage difference E-Vgs is applied from the drive transistor DT to the light-emitting element OLED. This drive current causes the light-emitting element OLED to emit light.

[0073] Referring to Figures 11 and 12c, during the copy programming section TC of the vertical blank section BLK, the sense signal SEN maintains the VON section, turning on the second switch transistor ST2. At this time, the first switch transistor ST1 is turned off by the scan signal SCAN, which has a gate off voltage VOFF. The initialization voltage VpreR is applied to the second node N2, which is connected to the source electrode of the drive transistor DT via the second switch transistor ST2, causing the source voltage Vs of the drive transistor DT to down-boosted from the turn-on voltage Vf of the light-emitting element OLED to the initialization voltage VpreR. At this time, the gate voltage Vg of the drive transistor DT also decreases due to cap boosting by the storage capacitor Cst. However, due to the second cap boosting loss, the fall of the gate voltage Vg may be smaller than the fall of the source voltage Vs.

[0074] In the copy programming section TC of the vertical blank section BLK, the gate-source voltage difference B-Vgs of the copy programming section TC is sometimes set to be substantially equal to the gate-source voltage difference W-Vgs of the programming section TA. In both W-Vgs and B-Vgs, the gate voltage Vg is the data voltage Vdata, and the source voltage Vs is the initialization voltage VpreR.

[0075] The programming section TA of the vertical active section ACT and the copy programming section TC of the vertical blank section BLK have the same length. As a result, even if only the second switch transistor ST2 is turned on based on the sense signal SEN of the VON section from the copy programming section TC of the vertical blank section BLK, the same programming effect as if both the first and second switch transistors ST1 and ST2 were turned on in the programming section TA of the vertical active section ACT can be obtained. The gate-source voltage difference W-Vgs set in the programming section TA of the vertical active section ACT and the gate-source voltage difference B-Vgs set in the copy programming section TC of the vertical blank section BLK are equal to each other.

[0076] In the copy programming section TC of the vertical blank section BLK, the gate voltage Vg is affected only by cap boosting. Since the second cap boosting loss acts in the opposite direction to the first cap boosting loss, the gate voltage Vg of B-Vgs may recover to the data voltage Vdata set at the end of the programming section TA of the vertical active section ACT.

[0077] In the boosting section TB2 of the vertical blank section BLK, the first switch transistor ST1 and the second switch transistor ST2 are turned off by the scan signal SCAN and sense signal SEN of the gate off voltage VOFF. The gate-source voltage difference B-Vgs in the copy programming section TC is maintained, and a drive current corresponding to the gate-source voltage difference B-Vgs flows through the drive transistor DT. This drive current up-boostifies the source voltage Vs of the drive transistor DT to the turn-on voltage Vf of the light-emitting element OLED. At this time, the gate voltage Vg of the drive transistor DT also rises due to cap boosting by the storage capacitor Cst. However, due to the first cap boosting loss, the increase in gate voltage Vg may be smaller than the increase in source voltage Vs.

[0078] Referring to Figures 11 and 12d, in the light-emitting section TE2 of the vertical blank section BLK, the gate-source voltage difference E-Vgs of the light-emitting section TE2 may be set to be smaller than the gate-source voltage difference B-Vgs of the copy programming section TC due to cap boosting losses. In the light-emitting section TE2 of the vertical blank section BLK, a drive current corresponding to the gate-source voltage difference E-Vgs is applied from the drive transistor DT to the light-emitting element OLED. This drive current causes the light-emitting element OLED to emit light.

[0079] Figure 13 shows how brightness flashing occurs with a conventional VRR drive system. Figure 14 shows how brightness flashing is prevented with the VRR drive system of the embodiment.

[0080] Referring to Figure 13, in the case of a conventional VRR drive system in which programming is performed only during the vertical active section (ACT), the real-time luminance integral value (i.e., cognitive luminance) increases in the third and fourth frames, where the frame frequency of 70 Hz is relatively low, which can cause luminance flashing. As a result, when changing from the second frame to the third frame, that is, when the frame frequency changes abruptly from 240 Hz to 70 Hz, VRR flicker due to cognitive luminance fluctuations may occur.

[0081] In contrast, as shown in Figure 14, in the VRR drive method of the embodiment, a copy programming section, which is a non-emitting section, is further placed in each of the vertical blank sections BLK of the third and fourth frames, where the frame frequency of 70Hz is relatively low, thereby preventing luminance flashing in the vertical blank sections BLK of the third and fourth frames. According to the embodiment, even when the frame frequency changes abruptly from 240Hz to 70Hz, there is almost no luminance fluctuation and VRR flicker is not visible.

[0082] Because the third copy programming section of the third frame overlaps with the programming section of the fourth frame, the length of the light emission section due to the third copy programming section of the third frame becomes shorter, and the brightness level (XY) becomes lower compared to a light emission section of normal length.

[0083] Similarly, because the third copy programming section of the fourth frame overlaps with the programming section of the fifth frame, the length of the light emission section due to the third copy programming section of the fourth frame is shortened, and the brightness level XZ becomes lower compared to a light emission section of normal length.

[0084] By the way, within a single frame interval, the time during which luminance levels XY or XZ are represented is very short, and they overlap with the luminance levels of subsequent frames and are perceived as a single unit, so there is no problem.

[0085] Figure 15 shows the characteristics of the intervals between multiple gate-on intervals included in the sense signal in the VRR drive system of the embodiment.

[0086] Referring to Figure 15, for copy programming operation to reduce VRR flicker, the sense signal SEN of this embodiment has at least one VON section such that it may turn on the second switch transistor ST2 during the vertical blank section BLK at frame frequencies lower than the maximum frame frequency (240 Hz) (70 Hz). Of course, for programming operation at a frame frequency of 70 Hz, the scan signal SCAN of this embodiment has one VON section such that it may turn on the first switch transistor ST1 during the vertical active section ACT, and the sense signal SEN has one VON section such that it may turn on the second switch transistor ST2 during the vertical active section ACT.

[0087] To put it another way, at frame frequencies lower than the maximum frame frequency (240 Hz) (70 Hz), within a single frame interval, the scan signal SCAN supplied to one subpixel contains one VON interval, and the sense signal SEN supplied to one subpixel contains at least two VON intervals.

[0088] Here, the first VON interval of the sense signal SEN overlaps with the VON interval of the scan signal SCAN, and the first subsequent VON interval of the sense signal SEN overlaps with the VOFF interval of the scan signal SCAN.

[0089] Referring to Figure 15, within the nth (where n is a natural number) frame Fn, the intervals between multiple VON segments included in the sense signal SEN are equal to each other, forming a first interval INT1, which can minimize luminance distortion in a single programming operation and multiple copy programming operations.

[0090] Referring to Figure 15, the interval between the last VON section of the sense signal SEN located in the nth frame Fn and the first VON section of the sense signal SEN located in the (n+1)th frame Fn+1 may have a second interval INT2 that is smaller than the first interval INT1. Even with this configuration, there is no problem with the data voltage (Vdata)-based programming operation performed in the (n+1)th frame (Fn+1). This is because, in the last VON section of the sense signal SEN located in the nth frame Fn, the copy programming operation is performed with only the initialization voltage VpreR and no data voltage Vdata.

[0091] Thus, according to this embodiment, since the programming interval in the (n+1)th frame Fn+1 may start before the last copy programming interval in the nth frame Fn has finished, there is no output delay compared to the input from the viewpoint of programming operation, and therefore there is no need to provide memory for frame image copying.

[0092] From the above explanation, those skilled in the art will understand that various changes and modifications are possible without departing from the technical concept of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be defined by the claims. [Explanation of Symbols]

[0093] TA Programming Section TC copy programming section TB1, TB2 boosting section TE1, TE2 Illumination Section

Claims

1. A display panel including multiple subpixels, where each subpixel is A drive transistor having a gate electrode connected to a first node, a drain electrode connected to a high potential power supply voltage, and a source electrode connected to a second node. A first switch transistor connects the first node to a data line to which a data voltage is supplied, in response to a scan signal. A second switch transistor connects the second node to a reference voltage line to which an initialization voltage is supplied, in response to a sense signal. A storage capacitor connected between the first node and the second node, and A light-emitting element having an anode electrode connected to the second node and a cathode electrode connected to a low potential power supply voltage. A display panel including, A gate driver that supplies the scan signal to a scan gate line connected to the gate electrode of the first switch transistor and supplies the sense signal to a sense gate line connected to the gate electrode of the second switch transistor. A variable frequency display device comprising: One frame interval is, A vertical active interval in which the data voltage is input to the corresponding subpixel of the subpixel, The vertical active section is followed by a vertical blank section in which the data voltage is not input to the corresponding subpixel, and the section includes these: A variable-frequency display device, wherein in one frame of a display panel driven at a frame frequency lower than a preset maximum frame frequency within a variable frame frequency range, the sense signal has at least one or more gate-on intervals such that the second switch transistor is turned on during the vertical blank interval.

2. The length of the vertical active interval is fixed based on the maximum frame frequency. The variable frequency display device according to claim 1, wherein the length of the vertical blank section is variable and increases as the frame frequency becomes lower than the maximum frame frequency.

3. During the programming interval of the vertical active interval, the scan signal and the sense signal maintain a gate-on interval so that both the first switch transistor and the second switch transistor are turned on. The variable frequency display device according to claim 2, wherein during the copy programming interval of the vertical blank interval, the scan signal maintains a gate-off interval and the sense signal maintains a gate-on interval, causing the first switch transistor to be turned off and the second switch transistor to be turned on.

4. The variable frequency display device according to claim 3, wherein the programming section and the copy programming section have the same length.

5. The variable frequency display device according to claim 4, wherein the gate-source voltage difference of the drive transistor in the programming section is the same as the gate-source voltage difference of the drive transistor in the copy programming section.

6. The variable frequency display device according to claim 3, in a display panel driven at a frame frequency lower than the maximum frame frequency, wherein the vertical blank section includes one or more copy programming sections.

7. The variable frequency display device according to claim 6, wherein the number of copy programming sections included in the vertical blank section increases as the length of the vertical blank section increases.

8. Within the nth (where n is a natural number) frame, the intervals between the multiple gate-on intervals included in the sense signal are equal to each other, and the first interval is equal to each other. The variable frequency display device according to claim 1, wherein the interval between the last gate-on section of the sense signal in the nth frame and the first gate-on section of the sense signal in the (n+1)th frame is a second interval that is smaller than the first interval.

9. A display panel including multiple subpixels, where each subpixel is A drive transistor having a gate electrode connected to a first node, a drain electrode connected to a high potential power supply voltage, and a source electrode connected to a second node. A first switch transistor connects the first node to a data line to which a data voltage is supplied, in response to a scan signal. A second switch transistor connects the second node to a reference voltage line to which an initialization voltage is supplied in response to a sense signal. A storage capacitor connected between the first node and the second node, and A light-emitting element having an anode electrode connected to the second node and a cathode electrode connected to a low potential power supply voltage. A display panel including, A gate driver that supplies the scan signal to a scan gate line connected to the gate electrode of the first switch transistor and supplies the sense signal to a sense gate line connected to the gate electrode of the second switch transistor. A variable frequency display device comprising: A variable-frequency display device, wherein in one frame interval of a display panel driven at a frame frequency lower than a preset maximum frame frequency within a variable frame frequency range, the scan signal supplied to one of the subpixels includes one gate-on interval, and the sense signal supplied to one of the subpixels includes two or more gate-on intervals.

10. During one frame interval of a display panel driven at a frame frequency lower than the maximum frame frequency, The one gate-on interval of the sense signal overlaps with one of the two or more gate-on intervals of the scan signal. The variable frequency display device according to claim 9, wherein the gate-on sections following the two or more gate-on sections of the sense signal overlap with the gate-off sections of the scan signal.

11. The aforementioned single frame interval is, A vertical active interval in which the data voltage is input to the corresponding subpixel among the subpixels, The vertical active section is followed by a vertical blank section in which the data voltage is not input to the corresponding subpixel, and the section includes these: The length of the vertical active interval is fixed based on the maximum frame frequency. The variable frequency display device according to claim 9, wherein the length of the vertical blank section is variable and increases as the frame frequency becomes lower than the maximum frame frequency.

12. Within the nth (where n is a natural number) frame, the intervals between the two or more gate-on intervals included in the sense signal are equal to a first interval. The variable frequency display device according to claim 9, wherein the interval between the last of the two or more gate-on intervals of the sense signal in the nth frame and the first gate-on interval of the sense signal in the (n+1)th frame is a second interval that is smaller than the first interval.

13. A display panel configured to be driven at a variable frame frequency within a certain frequency range, wherein the display panel includes subpixels, and the subpixels are A drive transistor having a gate electrode connected to a first node and a first electrode connected to a second node, A first switch transistor having a gate electrode connected to a scan gate line, a first electrode connected to a data line configured to receive a data voltage, and a second electrode connected to the first node, A second switch transistor having a gate electrode connected to a sense gate line, a first electrode connected to a reference voltage line configured to receive an initialization voltage, and a second electrode connected to the second node, and Light-emitting element connected to the second node A display panel including, A data driver configured to supply the aforementioned data voltage to the aforementioned data line, A gate driver configured to supply a scan signal to the scan gate line and a sense signal to the sense gate line, A display device comprising, A display device in which, during the nth frame (where n is a natural number) of the display panel driven at a frame frequency lower than a preset maximum frame frequency within a certain frequency range, the scan signal has one gate-on interval and the sense signal has two or more gate-on intervals.

14. The aforementioned frame n, A vertical active interval in which the data voltage is input to the subpixel, Following the preceding vertical active section, there is a vertical blank section in which the data voltage is not input to the subpixel. The display device according to claim 13, including the following:

15. The length of the vertical active interval is fixed based on the preset maximum frame frequency. The display device according to claim 14, wherein the length of the vertical blank section is variable and increases as the frame frequency becomes lower than the preset maximum frame frequency.

16. The vertical active interval includes a programming interval configured such that the first switch transistor and the second switch transistor are turned on. The display device according to claim 14, wherein the vertical blank section includes one or more copy programming sections configured to turn off the first switch transistor and to turn on the second switch transistor.

17. The display device according to claim 16, wherein the programming section and the one or more copy programming sections each have the same length.

18. The display device according to claim 17, wherein the number of copy programming intervals included in the vertical blank interval increases as the length of the vertical blank interval increases and the frame frequency decreases.

19. During the previous frame, The one gate-on interval of the sense signal overlaps with one of the at least two gate-on intervals of the scan signal. The display device according to claim 13, wherein the gate-on sections following the two or more gate-on sections of the sense signal overlap with the gate-off sections of the scan signal.

20. The intervals between the two or more gate-on sections of the sense signal within the n frame are equal to a first interval, The display device according to claim 13, wherein the interval between the last of the two or more gate-on intervals of the sense signal in the nth frame and the first gate-on interval of the sense signal in the (n+1)th frame is equal to a second interval that is smaller than the first interval.

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