Voltage conversion circuit and image sensing device including the same

Abstract

In an image sensing device, noise is reduced while decreasing power consumption. [Solution] An image sensing device according to one embodiment of the present invention includes a pump circuit 300 that pumps a bias voltage VBIAS to generate a pumping voltage PO; and a regulator 310 that regulates the pumping voltage PO to generate an output voltage NPG. The pump circuit 300 can vary the pumping voltage PO by adjusting the pumping capacitances C1 to C4 based on a control signal PC corresponding to the light intensity.

Description

Technical Field

[0005] , ,

[0001] The present disclosure relates to an image sensing device that generates image data.

Background Art

[0002] Generally, a CMOS (Complementary Metal Oxide Semiconductor) image sensor (CIS) implemented by a CMOS process has been rapidly expanding in the market due to advantages such as low power consumption, low cost, and small size compared to other competing products. In particular, the CMOS image sensor has gradually expanded its application range to the video field that requires high resolution and high frame rate due to relatively insufficient image quality improvement compared to competing products.

[0003] In order to reduce the power consumption of CIS, the development of CIS using low voltages for pixels and analog circuits has been carried out. However, when using a large number of supply voltages at different levels (for example, analog power supply voltage (VDDA), input / output power supply voltage (VDDIO), digital logic power supply voltage (VDDD)), the power management system becomes complicated, and there may be difficulties in adaptively controlling the image sensor according to the situation.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention attempt to provide an image sensing device that can adaptively control the size of the pumping capacitor of a voltage conversion circuit according to the intensity of light, and reduce noise while reducing power consumption.

[0005] Embodiments of the present invention attempt to provide an image sensing device that can adjust the bias current of an analog-to-digital conversion circuit based on the analog gain of a pixel signal, secure a voltage margin due to the analog gain, and reduce temporal noise. [Means for solving the problem]

[0006] A voltage conversion circuit according to one embodiment of the present invention includes a pump circuit that pumps a bias voltage to generate a pumping voltage, and a regulator that regulates the pumping voltage to generate an output voltage, wherein the pump circuit can vary the pumping voltage by adjusting the pumping capacitance based on a control signal corresponding to the intensity of light.

[0007] An image sensing device according to one embodiment of the present invention may include: a pixel array that outputs a pixel signal corresponding to incident light; a voltage conversion circuit that generates a pumping voltage by charging and pumping a bias voltage and adjusts the pumping capacitance according to a control signal to vary the pumping voltage; an analog-to-digital conversion circuit that samples and holds the pixel signal and converts it into a digital signal for output; and an image signal processor that controls a control signal in accordance with the intensity of light. [Effects of the Invention]

[0008] Embodiments of the present invention provide an image sensing device that can adaptively control the size of the pumping capacitor of a voltage conversion circuit according to the intensity of light, thereby ensuring high driving force in bright environments and minimizing output ripple of the voltage conversion circuit in dark environments.

[0009] Embodiments of the present invention provide an image sensing device that can adjust the bias current of an analog-to-digital conversion circuit based on the analog gain of a pixel signal, thereby ensuring a transistor voltage margin at relatively low analog gains and reducing noise at relatively high analog gains.

[0010] Furthermore, the embodiments of the present invention are illustrative, and those skilled in the art can make various modifications, changes, substitutions, and additions based on the technical idea and scope of the appended claims, and such modifications and changes should be considered to fall within the scope of the following claims. [Brief explanation of the drawing]

[0011] [Figure 1] This is a configuration diagram of an image sensing device according to one embodiment of the present invention. [Figure 2] Figure 1 is an illustrative circuit diagram of a pixel. [Figure 3] Figure 1 is a detailed diagram of the voltage conversion circuit shown. [Figure 4a] Figure 3 is a detailed circuit diagram of the pump circuit shown. [Figure 4b] Figure 3 is a detailed circuit diagram of the pump circuit shown. [Figure 5] This graph shows the relationship between sensor output and noise in relation to light intensity. [Figure 6] This graph, according to one embodiment of the present invention, shows the relationship between the negative current and the intensity of light when light is incident on a sensor. [Figure 7] This graph shows the relationship between light intensity and the number of pumping capacitors in a present embodiment of the present invention, illustrating the relationship between negative voltage and these factors. [Figure 8] This diagram shows the configuration of an electronic device according to one embodiment of the present invention. [Figure 9a] Figure 8 shows the configuration of the analog-to-digital conversion circuit. [Figure 9b] Figure 9a is a detailed circuit diagram of the comparator shown. [Figure 10] Figure 8 is a diagram illustrating the configuration of the bias voltage generation circuit and the comparator circuit shown. [Figure 11] This graph shows the relationship between analog gain and time noise. [Figure 12] This graph shows the relationship between analog gain and counter output in one embodiment of the present invention.

Best Mode for Carrying Out the Invention

[0012] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, the present disclosure should not be limited to specific embodiments and should be understood to include various modifications, equivalents, and / or alternatives of the embodiments. Embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized through the present disclosure.

[0013] FIG. 1 is a configuration diagram of an image sensing device according to an embodiment of the present invention.

[0014] Referring to FIG. 1, the image sensing device 100 may include a stacked CMOS image sensor (e.g., CMOS image sensor, CIS). The image sensing device 100 may include an upper chip 110 and a lower chip 120. According to an embodiment, the upper chip 110 may be stacked on top of the lower chip 120.

[0015] While high-resolution and high-frame-rate image sensing devices 100 are widely adopted in mobile smartphone applications, they consume a lot of power. In order to reduce power consumption, a low voltage can be used for pixels and analog circuits.

[0016] As an example, the image sensing device 100 can use two values of power supply voltage. For example, the power supply voltage VDDA may be at a first voltage level, and the power supply voltage VDDIO may be at the first voltage level as well as VDDA. And the digital logic power supply voltage VDDD may be at a second voltage level different from the first voltage level (e.g., lower than the first voltage level). By using the same level of power supply voltage for VDDA and VDDIO, the complexity of power management can be reduced, and the power consumption of pixels and analog circuits can be decreased.

[0017] Further, the image sensing device 100 can use a negative voltage (negative pixel ground, NPG). For example, the negative voltage (NPG) may have a negative voltage level lower than 0V.

[0018] The upper chip 110 may include a pixel array 111. The pixel array 111 may include a plurality of pixels (PX) arranged in a plurality of rows and a plurality of columns.

[0019] As an example, the plurality of pixels (PX) may be arranged in a two-dimensional pixel array 111 including rows and columns. As another example, the plurality of unit image pixels may be arranged in a three-dimensional pixel array 111.

[0020] The plurality of pixels (PX) can convert an optical signal into an electrical signal in pixel units or pixel group units, and the pixels (PX) within a pixel group can share at least one internal circuit.

[0021] The pixel array 111 can receive drive signals including a row selection signal, a pixel reset signal, a transmission signal, etc. from the load driver 125. The pixels (PX) of the pixel array 111 can be activated to perform operations corresponding to the row selection signal, the pixel reset signal, and the transmission signal based on the drive signal.

[0022] The lower chip 120 may include an interface circuit 121, a voltage conversion circuit 122, a bias voltage generation circuit 123, an analog-to-digital conversion circuit 124 (analog to digital converter, ADC), a row driver 125, and an image signal processor 126 (image signal processor, ISP).

[0023] In this embodiment, several conceptual hardware configurations included in the lower chip 120 are illustrated, but the embodiments described in this document are not limited thereto, and other configurations are possible.

[0024] The interface circuit 121 can transmit data between each component within the image sensing device 100. The interface circuit 121 can transmit data generated or stored in the image sensing device 100 (e.g., pixel data, image data, etc.) to each component (e.g., ISP 126).

[0025] As an example, the interface circuit 121 can input and output data using a mobile industry processor interface (MIPI). MIPI is a federation of organizations aimed at standardizing mobile device interfaces, and it covers many subjects including cameras, displays, audio, and buses. In this disclosure, the interface circuit 121 can use a MIPI interface, but the scope of the present invention is not limited thereto, and a variety of interfaces can be used.

[0026] The voltage conversion circuit 122 can convert the input voltage based on the control signal of the ISP 126 to supply power voltage to each component of the image sensing device 100. The voltage conversion circuit 122 can convert the input voltage to generate a negative voltage (NPG). The negative voltage (NPG) generated by the voltage conversion circuit 122 can be supplied to the pixel array 111.

[0027] For example, the voltage conversion circuit 122 may include a DC-DC converter. A DC-DC converter can convert a relatively high input voltage into a relatively low output voltage and output it.

[0028] In this disclosure, in a voltage conversion circuit 122 that generates a negative voltage (NPG), the magnitude of the pumping capacitance can be adaptively changed according to the illuminance. The detailed configuration and operation of the voltage conversion circuit 122 will be described in more detail in the drawings described later.

[0029] The bias voltage generation circuit 123 can convert a reference bias current into a voltage. The bias voltage generation circuit 123 can provide the generated bias voltage to components included in the image sensing device 100 (for example, the voltage conversion circuit 122 and / or ADC 124).

[0030] The ADC124 can sample and hold the pixel signals for each column output from each column line of the pixel array 111, convert them into digital signals, and output them. In one embodiment, the ADC124 may include, but is not limited to, a single-slope ADC124 circuit. In one embodiment, the ADC124 can be implemented as a ramp-compare type ADC124 that uses the ramp signal from a ramp signal generator (a ramp signal generator 840 described later).

[0031] Depending on the embodiment, the image data generated by the ADC124 can correspond to at least two different sensitivities. Sensitivity may refer to the increase in image data (or the increase in response) in response to an increase in the intensity of incident light. That is, the higher the sensitivity, the greater the increase in image data in response to an increase in the intensity of incident light, and the lower the sensitivity, the smaller the increase in image data in response to an increase in the intensity of incident light.

[0032] In this disclosure, sensitivity may be determined by analog gain. Analog gain may mean the ratio of the voltage level of an analog form of the pixel signal, which varies with the intensity of incident light, to the size of the image data.

[0033] The low driver 125 can activate the pixel array 111 to perform a specific operation on the pixel (PX) corresponding to the low based on the control signal of the ISP 126 (and / or the control signal of the timing controller (not shown)).

[0034] The low driver 125 can select at least one pixel (PX) arranged in at least one row of the pixel array 111. The low driver 125 can generate a low selection signal to select at least one low from multiple lows.

[0035] The low driver 125 can sequentially enable a pixel reset signal and a transmission signal for the pixel corresponding to at least one selected low. This allows the analog reference signal and video signal generated from each pixel of the selected low to be sequentially transmitted to the ADC 124.

[0036] Here, the reference signal is an electrical signal generated and provided to the ADC124 when the pixel's sensing node (e.g., floating diffusion region) is reset, and the video signal may be an electrical signal generated and provided to the ADC124 when the photocharge generated by the pixel is accumulated in the sensing node. The reference signal, which indicates the pixel-specific reset noise, and the video signal, which indicates the intensity of the incident light, may be collectively referred to as the pixel signal.

[0037] ISP126 can perform video signal processing on image data. ISP126 can reduce noise in image data and perform video signal processing for image quality improvement, including interpolation, compositing, gamma correction, color filter array interpolation, color matrix, color correction, color enhancement, and lens distortion correction.

[0038] ISP126 can generate a video file by compressing image data generated through video signal processing for image quality improvement, or it can recover image data from the video file. The video compression format may be lossless or lossy. As an example of compression format, for still images, JPEG (Joint Photographic Experts Group) format or JPEG2000 format may be used. For moving images, a video file may be generated by compressing multiple frames according to the MPEG (Moving Picture Experts Group) standard. The video file may be generated according to, for example, the Exif (Exchangeable image file format) standard.

[0039] ISP126 can generate an HDR image by combining at least two images with different sensitivities. For example, image sensing device 100 can output a low-sensitivity image generated by a relatively low analog gain and a high-sensitivity image generated by a relatively high analog gain. ISP126 can generate an HDR image by combining the low-sensitivity image and the high-sensitivity image. For example, low sensitivity and high sensitivity are relative concepts, and image sensing device 100 can generate n (where n is an integer greater than or equal to 2) or more video data with different sensitivities, and ISP126 can use these to generate an HDR image.

[0040] ISP126 can transmit image data after image processing is complete to a host device (not shown). The host device (not shown) may include a processor (e.g., an application processor) for processing the image-processed image data received from ISP126, a memory (e.g., non-volatile memory) for storing the image data, or a display device (e.g., an LCD (liquid crystal display)) for visually outputting the image data.

[0041] The ISP126 can generate control signals to control the operation of the image sensing device 100 (such as operation status, operation timing, and operation mode). To generate such control signals, the ISP126 may include a timing controller. In this disclosure, the inclusion of a timing controller within the ISP126 is described as an example. However, this disclosure is not limited to this, and the timing controller may be located outside the ISP126 as a separate component.

[0042] The ISP126 can generate and transmit a control signal (e.g., a control signal for the pumping capacitance) to adjust the magnitude of the pumping capacitance of the pump circuit (the pump circuit 300 described later) of the voltage conversion circuit 122. For example, when the light intensity is relatively high (e.g., a high-illumination environment), the ISP126 can generate a control signal to increase the pumping capacitance of the pump circuit. When the light intensity is relatively low (e.g., a low-illumination environment), the ISP126 can generate a control signal to decrease the pumping capacitance of the pump circuit. For example, the ISP126 can control the control signal by estimating the light intensity based on at least one of the average value of the pixel signal, the exposure time, and / or the analog gain for the pixel signal.

[0043] ISP126 can generate and transmit a control signal (e.g., a bias current control signal) to the ADC124 to adjust the bias current of the comparator (comparator 835, described later) of the ADC124. For example, if the analog gain is set relatively high, ISP126 can generate a control signal to relatively increase the bias current of the comparator. For example, if the analog gain is set relatively low, ISP126 can generate a control signal to relatively decrease the bias current of the comparator.

[0044] The configuration of the image sensing device 100 is not limited to that shown in Figure 1, and at least some components may be omitted or at least one component may be added.

[0045] Figure 2 is an illustrative circuit diagram of the pixel shown in Figure 1.

[0046] Referring to Figure 2, a pixel (PX) may be any one of the multiple pixels (PX) included in the pixel array 111 shown in Figure 1. Although Figure 2 describes one pixel (PX), other pixels may have substantially the same structure and operation as pixel (PX).

[0047] A pixel (PX) may include a photoelectric converter (PD), a transmission transistor (TX), a reset transistor (RX), a floating diffusion region (FD), a pixel capacitor (Cp), a source follower transistor (SF), and a selection transistor (SX).

[0048] Figure 2 illustrates a pixel (PX) containing a single photoelectric converter (PD), but is not limited to this. For example, a pixel (PX) may include a shared pixel containing multiple photoelectric converters. A shared pixel (PX) may include multiple transmission transistors corresponding to multiple photoelectric converters.

[0049] A photoelectric element (PD) can generate and store photocharges corresponding to the intensity of incident light. For example, a photoelectric element (PD) can be embodied as a photodiode, phototransistor, photogate, pinned photodiode, or a combination thereof. For example, when the photoelectric element (PD) is embodied as a photodiode, it may be a region doped with an impurity of a second conductivity type (e.g., N-type) within a substrate having a first conductivity type (e.g., P-type).

[0050] A transmission transistor (TX) may be connected between a photoelectric converter (PD) and a floating diffusion region (FD). The transmission transistor (TX) may be turned on or turned off in response to a transmission signal (TG). The transmission transistor (TX) can be turned on by a logic high-level transmission signal (TG) and can transfer the photocharge accumulated in the photoelectric converter (PD) to the floating diffusion region (FD).

[0051] A reset transistor (RX) may be connected between the power supply voltage (VDDA) application terminal and the floating diffusion region (FD). The reset transistor (RX) can respond to a logic high-level reset signal (RG) to reset the voltage in the floating diffusion region (FD) to the power supply voltage (VDDA).

[0052] The floating diffusion region (FD) can store photocharges transferred from the transmission transistor (TX). The floating diffusion region (FD) can be connected to a pixel capacitor (Cp) connected to the ground terminal.

[0053] For example, a floating diffusion region (FD) may be a region doped with an impurity of a second conductivity type (e.g., N-type) within a substrate having a first conductivity type (e.g., P-type), and the substrate and the impurity-doped region may be modeled as a pixel capacitor (Cp) which is a junction capacitor. The floating diffusion region (FD) may be referred to as a sensing node.

[0054] In this disclosure, logic high level may mean a voltage level for activating (e.g., turning on) the element (e.g., a transistor), and logic low level may mean a voltage level for deactivating (e.g., turning off) the element (e.g., a transistor).

[0055] Figure 2 describes an embodiment in which the floating diffusion region (FD) has one capacitance, but the floating diffusion region (FD) may have two or more capacitances. For example, the floating diffusion region (FD) can have two capacitances by being connected to a DCG (dual conversion gain) transistor and selectively providing additional capacitance.

[0056] A source follower transistor (SF) can be connected between the power supply voltage (VDDA) application terminal and a selection transistor (SX). The source follower transistor (SF) can amplify the change in the electrical potential of the floating diffusion region (FD) to which the photocharge accumulated in the photoelectric conversion element (PD) is transferred and transmit it to the selection transistor (SX).

[0057] A selection transistor (SX) may be connected between the source follower transistor (SF) and the output terminal of the pixel signal (PS). The selection transistor (SX) can be turned on by a selection control signal (SEL) and output the electrical signal transmitted from the source follower transistor (SF) as the pixel signal (PS).

[0058] According to one embodiment, a photoelectric converter (PD) can generate electron (e)-hole (h) pairs in response to the intensity of light. The electrons (e) are stored in the photoelectric converter (PD), and the holes (h) can flow to the negative voltage (NPG) terminal and become the load current of the voltage conversion circuit 122. For example, the greater the light intensity (for example, the brighter the ambient light (illumination)), the greater the load current flowing into the voltage conversion circuit 122.

[0059] Figure 3 is a detailed diagram of the voltage conversion circuit shown in Figure 1.

[0060] Referring to Figure 3, the voltage conversion circuit 122 can pump (boost or buck) the input bias voltage (VBIAS) to generate the power supply voltages used by the image sensing device 100 (e.g., analog power supply voltage (VDDA), input / output power supply voltage (VDDIO), digital logic power supply voltage (VDDD), and / or negative voltage (NPG)).

[0061] The voltage conversion circuit 122 may include a pump circuit 300 and a regulator 310. The following explanation will omit or briefly describe any content that overlaps with Figures 1 and 2.

[0062] The pump circuit 300 can generate a pumping voltage (PO) by boosting or bucking the input bias voltage (VBIAS). For example, the pump circuit 300 may include a plurality of pumping capacitors (described later) and a plurality of switches for controlling the plurality of pumping capacitors (described later). The pumping capacitance of the pump circuit 300 can be adjusted by turning on or off at least some of the plurality of switches connected to the plurality of pumping capacitors in response to the control signal (PC) of ISP126.

[0063] For example, when the light intensity (e.g., external illuminance) is high (e.g., in a bright environment), the pumping capacitance of the pump circuit 300 can be adjusted to be relatively high. On the other hand, when the light intensity is low (e.g., in a dark environment), the pumping capacitance of the pump circuit 300 can be adjusted to be relatively low.

[0064] The regulator 310 can generate an output voltage that is the same level as or lower than the pumping voltage (PO) by regulating the pumping voltage (PO). For example, the regulator 310 can regulate the pumping voltage (PO) to output a negative voltage (NPG).

[0065] The pumping voltage (PO) applied from the pump circuit 300 can be stabilized. For example, the regulator 310 can reduce power supply voltage noise (e.g., readout noise, pixel pattern noise) and remove ripple noise from the output of the pump circuit 300. The regulator 310 may include, but is not limited to, a low drop-out (LDO) regulator.

[0066] The regulator 310 may include a comparison unit 311, a voltage distribution unit 312, and a switching element (T1).

[0067] The comparison unit 311 can compare the voltage of the voltage distribution unit 312 applied via the positive terminal (+) with a reference voltage (VREF) applied via the negative terminal (-). The voltage distribution unit 312 can then distribute the power supply voltage (VDDA). The voltage distribution unit 312 may include a plurality of resistors (R1, R2). The plurality of resistors (R1, R2) can be connected in series between the power supply voltage (VDDA) application terminal and the switching element (T1).

[0068] A switching element (T1) may be connected between the voltage distribution unit 312 and the application terminal of the pumping voltage (PO). The switching element (T1) is controlled by the output of the comparison unit 311 and can output a negative voltage (NPG) generated by the power supply voltage (VDDA) and the pumping voltage (PO) to a pad (PAD). Here, the pad (PAD) may be located outside the voltage conversion circuit 122 and may be connected to an external capacitor (Cex).

[0069] Figures 4a and 4b are detailed circuit diagrams of the pump circuit shown in Figure 3.

[0070] Figure 4a shows the charging operation of the pump circuit 300, and Figure 4b shows the pumping operation of the pump circuit 300.

[0071] Referring to Figures 4a and 4b, the pump circuit 300 may include a first switching unit (S1), a second switching unit (S2), a variable pumping voltage circuit 320, and a charging capacitor (C5). The pump circuit 300 may have a bias voltage (VBIAS) applied via an input node (ND1) and a pumping voltage (PO) output via an output node (ND4).

[0072] The first switching unit (S1) can selectively control its switching operation based on switching control signals (SC1, SC2). Here, the switching control signals (SC1, SC2) may be signals generated from ISP126. The switching control signals (SC1, SC2) can be independently activated or deactivated. The first switching unit (S1) can electrically connect the input node (ND1) to node (ND2) during the charging section and disconnect the electrical connection between the input node (ND1) and node (ND2) during the pumping section.

[0073] The first switching unit (S1) may include a plurality of switches (SW1, SW2). Switch (SW1) is connected between an input node (ND1) and a node (ND2) and may be controlled by a switching control signal (SC1). Switch (SW2) is connected between a ground voltage terminal and a node (ND2) and may be controlled by a switching control signal (SC2). For example, switches (SW1) and (SW2) can operate complementaryly to each other.

[0074] The second switching unit (S2) can selectively control its switching operation based on switching control signals (SC3, SC4). Here, the switching control signals (SC3, SC4) may be signals generated from ISP126. The switching control signals (SC3, SC4) can be independently activated or deactivated. The second switching unit (S2) can electrically connect node (ND3) to output node (ND4) during the pumping section and disconnect the electrical connection between node (ND3) and output node (ND4) during the charging section.

[0075] The second switching section (S2) may include a plurality of switches (SW6, SW7). Switch (SW6) is connected between a node (ND3) and an output node (ND4) and may be controlled by a switching control signal (SC3). Switch (SW7) is connected between a node (ND3) and a ground voltage terminal and may be controlled by a switching control signal (SC4). For example, switches (SW6) and (SW7) can operate complementaryly to each other.

[0076] A charging capacitor (C5) may be connected between the output node (ND4) and the ground voltage terminal. The charging capacitor (C5) can stabilize the pumping voltage (PO) output through the output node (ND4).

[0077] The pumping voltage variable circuit 320 can adjust the pumping capacitance based on a control signal (PC) to vary the pumping voltage (PO). Such a pumping voltage variable circuit 320 may include a switching unit 321 and a capacitance control unit 322.

[0078] The switching unit 321 may include a plurality of switches (SW3 to SW5) connected in parallel between the node (ND2) and the capacitance control unit 322, which are opened and closed by a control signal (PC). The capacitance control unit 322 may also include a plurality of pumping capacitors (C1 to C4) connected in parallel between the switching unit 321 and the node (ND3).

[0079] For example, pumping capacitor (C1) may be connected to switch (SW3), and pumping capacitor (C2) may be connected to switch (SW3). Then, pumping capacitor (C3) may be connected to switch (SW5), and pumping capacitor (C4) may be connected to node (ND2).

[0080] Figures 4a and 4b illustrate the case where each pumping capacitor (C1 to C3) is connected to a corresponding switch at one end, but the embodiments of the present invention are not limited to this. As another example, at least one switch may be connected to each end of the pumping capacitor (C1 to C3).

[0081] Furthermore, in Figures 4a and 4b, the number of switches shown in the switching unit 321 and the number of pumping capacitors shown in the capacitance control unit 322 are not limited to these and can be easily changed.

[0082] The pumping voltage variable circuit 320 allows adjustment of the number of pumping capacitors (C1~C4) that are charged by a control signal (PC). The number of pumping capacitors (C1~C4) used for charging and pumping can be adjusted by turning on or off multiple switches (SW3~SW5) by the control signal (PC).

[0083] The control signal (PC) may be determined based on the light intensity (e.g., ambient illuminance). For example, when the switching unit 321 is turned on, at least one pumping capacitor (C1-C4) connected to the switch may be charged by the bias voltage (VBIAS). When the switching unit 321 is turned off, the pumping capacitors (C1-C4) connected to the switch may float and not be charged by the bias voltage (VBIAS).

[0084] A control signal (PC) can be used to control the pumping capacitors (C1-C4) so ​​that as the light intensity increases, more switches (SW3-SW5) connected to them are turned on. For example, the voltage conversion circuit 122 can increase the pumping capacitance by increasing the number of pumping capacitors (C1-C4) that are charged as the light intensity increases, based on the control signal (PC). On the other hand, the voltage conversion circuit 122 can decrease the pumping capacitance by decreasing the number of pumping capacitors (C1-C4) that are charged as the light intensity decreases, based on the control signal (PC).

[0085] As shown in Figure 4a, in the charging section, the switch (SW1) of the first switching section (S1) is turned on, and the switch (SW2) is turned off, connecting the input node (ND1) and node (ND2). This allows the bias voltage (VBIAS) to be transmitted to node (ND2). Then, the switch (SW6) of the second switching section (S2) is turned off, and the switch (SW7) is turned on, allowing the ground voltage to be applied to node (ND3). As a result, the pumping voltage variable circuit 320 switches multiple switches (SW3~SW5) based on the control signal (PC), and the pumping capacitors (C1~C4) are charged by the bias voltage (VBIAS).

[0086] As shown in Figure 4b, during the pumping section, the switch (SW2) of the first switching section (S1) is turned on and the switch (SW1) is turned off, potentially disconnecting the connection between the input node (ND1) and node (ND2). Then, the switch (SW6) of the second switching section (S2) is turned on and the switch (SW7) is turned off. This allows the charging voltage of node (ND3) to be transmitted to the output node (ND4). As a result, the pumping voltage (PO) charged to the pumping capacitors (C1~C4) can be output via the output node (ND4).

[0087] Figure 5 is a graph showing the relationship between sensor output and noise in relation to light intensity.

[0088] Referring to Figure 5, in the graph, the horizontal axis represents the light intensity, and the vertical axis represents the sensor output.

[0089] In Figure 5, 501 can represent the signal output corresponding to the light intensity, 503 can represent the shot noise corresponding to the light intensity, and 505 can represent the readout noise corresponding to the light intensity.

[0090] When the intensity of light increases, the shot noise in the signal output from the sensor may increase. Here, shot noise can be caused by stochastic fluctuations in the arrival interval of charges (e.g., electrons, holes) due to the irregular flow of charges. When the intensity of light increases, the number of incident photons increases, which can increase the shot noise generated in the photoelectric converter (PD) (e.g., photodiode).

[0091] Readout noise is noise that occurs in the floating diffusion region (FD), pixels (PX), analog-to-digital conversion circuit 124, etc., during the process of reading a signal as digital data due to circuit factors, and can have a constant value regardless of the light intensity.

[0092] In bright environments with relatively high light intensity, shot noise can have a relatively greater impact on the performance of the image sensing device compared to readout noise. As a result, the image sensing device 100 according to this disclosure can be controlled to use a relatively large capacity capacitor (e.g., more pumping capacitors) in the pump circuit 300 to ensure high driving force in bright environments with relatively high light intensity.

[0093] On the other hand, in dark environments with relatively low light intensity, readout noise can have a relatively greater impact on the performance of the image sensing device compared to shot noise. As a result, the image sensing device 100 according to this disclosure can be controlled to use a relatively small capacitance capacitor (e.g., fewer pumping capacitors) in the pump circuit 300 to reduce ripple noise in dark environments with relatively low light intensity, where the load current is small.

[0094] Figure 6 is a graph showing the relationship between the negative current and the intensity of light when light is incident on the sensor, according to one embodiment of the present invention.

[0095] Referring to Figure 6, in the graph, the horizontal axis represents the intensity of light, and the vertical axis represents the amount of current flowing at the negative voltage terminal.

[0096] The dotted line 601 represents the current at the negative voltage terminal in an ideal (e.g., linear) state corresponding to the light intensity, while the solid line 603 represents the result of measuring the current at the negative voltage terminal in an image sensing device according to the light intensity. Here, the negative voltage terminal may refer to the output terminal where a negative voltage (NPG) is output in Figures 1 and 3 described above.

[0097] For example, in low-illumination areas, the current at the negative voltage terminal may decrease compared to the dotted line 601, while in high-illumination areas, there may be a portion where the current at the negative voltage terminal increases compared to the dotted line 601.

[0098] As a result, even when the image sensing device 100 according to this disclosure adaptively adjusts the pumping capacitance (e.g., the number of pumping capacitors) according to the light intensity, the current 603 at the negative voltage terminal corresponding to the light intensity can be measured similarly to the ideal current 601 at the negative voltage terminal corresponding to the light intensity.

[0099] Figure 7 is a graph showing the relationship between light intensity and the number of pumping capacitors in the negative voltage (NPG) according to one embodiment of the present invention.

[0100] Referring to Figure 7, in the graph, the horizontal axis represents the light intensity, and the vertical axis represents the negative voltage (NPG).

[0101] In Figure 7, 701 can show the change in negative voltage (NPG) in response to light intensity when the pumping capacitance is of a standard magnitude. 703 can show the change in negative voltage (NPG) in response to light intensity when the pumping capacitance is twice as large. 705 can show the change in negative voltage (NPG) in response to light intensity when the pumping capacitance is four times as large. When the pumping capacitance is increased, the negative voltage (NPG) can be maintained relatively stably even when the light intensity increases.

[0102] The image sensing device 100 according to this disclosure can variably adjust the pumping capacitance of the pump circuit 300 according to the light intensity. When the light intensity reaches a specified threshold, the ISP 126 can adjust the pumping capacitance of the pump circuit 300 to a value corresponding to the specified threshold. For example, the image sensing device 100 can maintain a stable negative voltage (NPG) even when the light intensity changes by increasing the pumping capacitance as the light intensity increases.

[0103] Figure 8 shows the configuration of an electronic device according to one embodiment of the present invention.

[0104] Referring to Figure 8, the electronic device (800) may include a processor (hereinafter referred to as an application processor (AP810)) and an image sensing device 100-1.

[0105] AP810 can receive image data processed by ISP870 via interface circuit 880. AP810 can identify the brightness of the image data. AP810 can determine the exposure time and analog gain of image sensing device 100-1 based on the brightness of the image data. AP810 can transmit exposure time information and analog gain information to image sensing device 100-1.

[0106] The image sensing device 100-1 may include a pixel array 820, a bias voltage generation circuit 830, a ramp signal generator 840, a comparator circuit 850, a counting circuit 860, an ISP 870, and an interface circuit 880. The comparator circuit 850 may include multiple comparators (COMP). The counting circuit 860 may include multiple counters (CNT).

[0107] Here, the pixel array 820 can correspond to the pixel array 111 in Figure 1 mentioned above. The bias voltage generation circuit 830 can correspond to the bias voltage generation circuit 123 in Figure 1 mentioned above. The comparator circuit 850 and the counting circuit 860 may be included in the ADC 124 in Figure 1 mentioned above. The ISP 870 can correspond to the ISP 126 in Figure 1 mentioned above. The interface circuit 880 can correspond to the interface circuit 121 in Figure 1 mentioned above. Accordingly, in Figure 8, explanations that overlap with Figures 1 to 7 are omitted or briefly explained.

[0108] The bias voltage generation circuit 830 can generate a bias voltage (VBIAS) by converting a bias current. For example, the bias voltage generation circuit 830 may receive a bias current from a bandgap reference circuit (BGR). The bias voltage generation circuit 830 can output the generated bias voltage (VBIAS) to the comparator circuit 850.

[0109] The ramp signal generator 840 can generate a ramp signal (RS) based on a control signal (CON) applied from the ISP 870 and transmit it to the comparator circuit 850. For example, the ramp signal (RS) may be a reference signal that is compared with the pixel signals (PS0, PS1, PS2, ... PSN) in the comparator circuit 850, and which decreases (or increases) over time.

[0110] The comparator circuit 850 can compare the pixel signals (PS0, PS1, PS2, ... PSN) output from the column lines of the pixel array 820 and the ramp signals (RS) applied from the ramp signal generator 840 to output a comparator signal (CS). For example, the comparator signal (CP) can be inverted (for example, its value changes from logic high to logic low or from logic low to logic high) when the pixel signals (PS0, PS1, PS2, ... PSN) and the ramp signals (RS) become identical. The comparator circuit 850 can then adjust the bias current based on the bias voltage (VBIAS) applied from the bias voltage generation circuit 830.

[0111] The counting circuit 860 can perform counting operations according to a specified clock from the time the ramp signal (RS) decreases (or increases) until the time the comparison signal (CS) is inverted. The counting circuit 860 can output a counting signal (CNS) corresponding to the counting result to the ISP 870. Here, the counting signal (CNS) can correspond to a value obtained by converting the analog pixel signal to a digital value. The counting circuit 860 can be initialized according to a reset control signal received from the ISP 870.

[0112] The ISP870 can control the overall operation of the image sensing device 100-1. For example, the ISP870 can transmit control signals (CON) to the bias voltage generation circuit 830, the ramp signal generator 840, the comparator circuit 850, and / or the counting circuit 860. The ISP870 can adjust the brightness of the image data based on the exposure time information and analog gain information transmitted from the AP810. For example, the ISP870 can drive the pixels of the pixel array 820 based on the exposure time information.

[0113] The ISP870 can generate at least one control signal (CON) based on analog gain information. The ISP870 can adjust the bias current of the comparator (COMP) via the control signal (CON). For example, the ISP870 can adjust the bias current of the comparator (COMP) to a relatively high value when the analog gain is relatively high. Conversely, the ISP870 can adjust the bias current of the comparator (COMP) to a relatively low value when the analog gain is relatively low.

[0114] The interface circuit 880 can transmit data (e.g., image data, exposure time information, and / or analog gain information) between the AP810 and the image sensing device 100-1.

[0115] The configuration of the image sensing device 100-1 is not limited to that shown in Figure 8, and at least some components may be omitted or at least one component may be added.

[0116] Figure 9a shows the configuration of the analog-to-digital conversion circuit shown in Figure 8.

[0117] Referring to Figure 9a, an analog-to-digital converter (ADC) circuit is shown, consisting of one comparator (COMP) and one counter (CNT).

[0118] The comparator (COMP) can compare the pixel signal (PS) and the ramp signal (RS). The comparator (COMP) can transmit a comparison signal (CS) indicating the comparison result of the pixel signal (PS) and the ramp signal (RS) to the counter (CNT).

[0119] Here, the ramp signals (RS) can exhibit different waveforms based on the analog gain (AG). That is, when the analog gain (AG) is large, the ramp signals (RS) can have a relatively gentle waveform, and when the analog gain (AG) is small, the ramp signals (RS) can have a relatively sharp waveform.

[0120] The comparator (COMP) can output the comparator signal (CS) at a logic low (or logic high) level if the pixel signal (PS) is greater than the ramp signal (RS). Conversely, the comparator (COMP) can output the comparator signal (CS) at a logic high (or low) level if the pixel signal (PS) is the same as the ramp signal (RS). If the pixel signal (PS) and the ramp signal (RS) are the same, the logic level of the comparator signal (CS) may be inverted. The structure of the comparator (COMP) included in the analog-to-digital converter (ADC) is not limited to Figure 9a, and can be replaced with comparators of various structures capable of distinguishing the difference between the pixel signal (PS) and the ramp signal (RS).

[0121] Furthermore, the counter (CNT) can perform counting according to a specified clock. The counter (CNT) can continue counting until the ramp signal (RS) is matched to the analog pixel signal (PS). The counter (CNT) can stop counting if the pixel signal (PS) becomes identical to the ramp signal (RS) based on the comparison signal (CS).

[0122] Figure 9b is a detailed circuit diagram of the comparator shown in Figure 9a.

[0123] Referring to Figure 9b, the comparator (COMP) may include a drive unit 911, a differential comparison unit 913, and a bias adjustment circuit 915.

[0124] Here, the drive unit 911 can selectively supply a power supply voltage (VDDA) based on the voltage level of the node (ND6). The drive unit 911 may include a plurality of PMOS transistors (P1, P2). The PMOS transistors (P1, P2) act as a load and can convert the current difference at the nodes (ND6, ND7) into a voltage. The PMOS transistors (P1, P2) are connected between the application terminal of the power supply voltage (VDDA) and the nodes (ND6, ND7), respectively, and a common gate terminal may be connected to the node (ND6).

[0125] The differential comparison unit 913 can perform a differential comparison of the ramp signal (RS) and the pixel signal (PS) and output a comparison signal (CS) corresponding to the comparison result via the node (ND7). The differential comparison unit 913 may include a plurality of NMOS transistors (N1, N2). NMOS transistor (N1) is connected between node (ND6) and node (ND8), and the ramp signal (RS) may be applied via its gate terminal. NMOS transistor (N2) is connected between node (ND7) and node (ND8), and the pixel signal (PS) may be applied via its gate terminal.

[0126] The bias adjustment circuit 915 can adjust the bias current corresponding to the bias voltage (VBIAS) based on the bias current control signal (BC) applied from the ISP870. Here, the bias current control signal (BC) can correspond to the aforementioned control signal (CON).

[0127] The bias adjustment circuit 915 may include multiple switches (SW10~SW12) and multiple NMOS transistors (N10~N13).

[0128] Here, multiple switches (SW10~SW12) can be connected in parallel between the node (ND8) and multiple NMOS transistors (N11~N13). The multiple switches (SW10~SW12) can be selectively switched based on a bias current control signal (BC). The NMOS transistor (N10) is connected between the node (ND8) and the ground voltage terminal, and a bias voltage (VBIAS) can be applied via its gate terminal. The multiple NMOS transistors (N11~N13) are connected between the switches (SW10~SW12) and the ground voltage terminal, and a bias voltage (VBIAS) can be applied via their gate terminals.

[0129] For example, when a switch (SW10~SW12) is turned on, the NMOS transistor connected to that switch can generate a bias current. On the other hand, when a switch is turned off, it may not be possible to generate a bias current through the NMOS transistor connected to that switch.

[0130] The bias current of the comparator (COMP) can be generated via NMOS transistors (N11-N13) corresponding to the number of switches (SW10-SW12) that are turned on. For example, based on the bias current control signal (BC), the comparator (COMP) can turn on more switches to generate a larger bias current in a relatively high analog gain environment, and turn on fewer switches to generate a smaller bias current in a relatively low analog gain environment.

[0131] Figure 10 is a diagram illustrating the configuration of the bias voltage generation circuit and comparator circuit shown in Figure 8. Content that overlaps with Figures 8, 9a, and 9b will be omitted or briefly explained below.

[0132] Referring to Figure 10, the bias voltage generation circuit 830 can generate a bias voltage (VBIAS) and output it to the comparator (COMP) of the analog-to-digital converter (ADC). The bias voltage generation circuit 830 may include a bandgap reference circuit (BGR) and an NMOS transistor (N4).

[0133] Here, a bandgap reference circuit (BGR) can generate a reference current (BGRC). An NMOS transistor (N4) is connected between the terminal to which the reference current (BGRC) is applied and the ground voltage terminal, and its gate terminal may be commonly connected to the drain terminal. The NMOS transistor (N4) can convert the reference current (BGRC) into a bias voltage (VBIAS). The bias voltage (VBIAS) can be output to each comparator (COMP) of the comparator circuit 850.

[0134] The bias current control signal (BC) of the comparator (COMP) can be determined based on the analog gain value. This allows the bias adjustment circuit 915 to adjust the bias current of the comparator (COMP) based on the analog gain. For example, the bias adjustment circuit 915 can increase the bias current when the analog gain (AG) increases and decrease the bias current when the analog gain decreases.

[0135] In other words, using a smaller bias current in a low analog gain environment than in a high analog gain environment ensures sufficient voltage margin for the transistor. Conversely, using a larger bias current in a high analog gain environment than in a low analog gain environment reduces noise generated in dark environments.

[0136] Figure 11 is a graph showing the relationship between analog gain and time noise.

[0137] Referring to Figure 11, the horizontal axis of the graph represents analog gain, and the vertical axis represents temporal noise.

[0138] For example, the noise components included in the image data generated by the image sensing device 100-1 may include fixed pattern noise and / or temporal noise.

[0139] Here, fixed pattern noise may refer to noise that has a certain pattern due to the hardware characteristics of the image sensing device 100-1 (e.g., lens shading). Temporal noise, on the other hand, is a concept distinct from fixed pattern noise and refers to noise that changes over time. That is, temporal noise is noise that occurs randomly without a fixed pattern and may include photon shot noise, dark current noise, and read noise. Photon shot noise occurs in the presence of light, and dark current noise occurs in the absence of light. Both photon shot noise and dark current noise may include noise generated by the readout operation within the image sensor.

[0140] Referring to the graph in Figure 11, it can be seen that increasing the analog gain reduces temporal noise, while decreasing the analog gain can increase temporal noise.

[0141] In situations where the analog gain is relatively low, the ramp signal (RS) swings significantly before being input to the comparator (COMP), which can make it difficult to ensure sufficient voltage margin for the transistor. On the other hand, in situations where the analog gain is relatively high, quantization noise becomes the dominant influence within the temporal noise, while thermal noise can have a relatively small impact.

[0142] In situations where the analog gain is relatively low, temporal noise may increase due to the effects of quantization noise. In this case, since the magnitude of the ramp step of the ramp signal (RS) is relatively large, the bandwidth requirement of the comparator (COMP) may also be lower. As a result, the image sensing device 100-1 according to this disclosure can ensure the voltage margin of the transistor by reducing the bias current of the comparator (COMP) in low analog gain environments compared to high analog gain environments.

[0143] On the other hand, the image sensing device 100-1 according to this disclosure can increase the bias current of the comparator (COMP) to reduce noise in dark environments (environments with low light intensity) when the analog gain is relatively high. The image sensing device 100-1 can reduce noise generated in dark environments by increasing the bias current of the comparator (COMP) in high analog gain environments compared to low analog gain environments.

[0144] Figure 12 is a graph showing the relationship between analog gain and counter output in one embodiment of the present invention.

[0145] Referring to Figure 12, the horizontal axis of the graph represents the analog gain, and the vertical axis represents the output of the counter (CNT) of the analog-to-digital conversion circuit. In Figure 12, the solid line 1201 shows the counter (CNT) output when the bias current of the comparator (COMP) is fixed, and the dotted line 1203 shows the counter (CNT) output when the bias current of the comparator (COMP) is adjusted by the analog gain.

[0146] In this disclosure, it can be confirmed that when the bias current of the comparator (COMP) is adaptively adjusted by analog gain, the output of the counter (CNT) increases compared to when the bias current of the comparator (COMP) is fixed.

[0147] The image sensing device 100-1 according to this disclosure can increase the bias current of the comparator (COMP) when the analog gain is relatively small, and decrease the bias current of the comparator (COMP) when the analog gain is relatively large. When the bias current of the comparator (COMP) is set to a relatively large value when the analog gain is relatively small, noise and / or counting time can be reduced. When the bias current of the comparator (COMP) is set to a relatively small value when the analog gain is relatively large, the power consumption of the image sensing device can be reduced. [Explanation of Symbols]

[0148] 100 Image Sensing Devices 110 Top tip 111 pixel array 120 Lower Chip 121 Interface Circuit 122 Voltage Conversion Circuit 123 Bias voltage generation circuit 124 Analog-to-Digital Conversion Circuit 125 Low Driver 126 Image Signal Processors 300 Pump Circuit 310 Regulator 311 Comparison Section 312 Voltage distribution section 320 Pumping Voltage Variable Circuit 321 Switching section 322 Capacitance Control Unit 800 Electronic equipment 820 pixel array 830 Bias Voltage Generation Circuit 835 Comparator 840 Lamp Signal Generator 850 comparison circuit 860 counting circuit 880 Interface Circuit 911 Drive Unit 913 Differential comparison section 915 Bias Adjustment Circuit

Claims

1. A pump circuit that generates a pumping voltage by pumping the bias voltage, Includes a regulator that regulates the pumping voltage to generate an output voltage, The aforementioned pump circuit is A voltage conversion circuit that varies the pumping voltage by adjusting the pumping capacitance based on a control signal corresponding to the intensity of light.

2. The aforementioned pump circuit is As the intensity of the light increases, the pumping capacitance increases. The voltage conversion circuit according to claim 1, wherein the pumping capacitance is controlled to decrease when the intensity of the light decreases.

3. The aforementioned pump circuit is A first switching unit selectively supplies the bias voltage to the first node based on a first switching control signal, A variable pumping voltage circuit that charges and pumps the bias voltage applied via the first node and outputs the pumping voltage to the second node, The voltage conversion circuit according to claim 1, further comprising a second switching unit that selectively controls the output of the pumping voltage based on a second switching control signal.

4. The voltage conversion circuit according to claim 3, wherein the control signal is controlled based on the intensity of the light.

5. The first switching unit is, A first switch connected between the bias voltage application terminal and the first node, The voltage conversion circuit according to claim 3, further comprising a second switch connected between the first node and the ground voltage terminal.

6. The first switching unit is, During the charging section, the first switch is turned on, the second switch is turned off, and the bias voltage is output to the first node. The voltage conversion circuit according to claim 5, wherein during the pumping section, the second switch is turned on, the first switch is turned off, and the connection between the bias voltage application terminal and the first node is interrupted.

7. The second switching unit described above is: A third switch connected between the second node and the output terminal of the pumping voltage, The voltage conversion circuit according to claim 5, further comprising a fourth switch connected between the second node and the ground voltage terminal.

8. The second switching unit described above is: During the charging section, the fourth switch is turned on, the third switch is turned off, and the connection between the second node and the output terminal of the pumping voltage is interrupted. The voltage conversion circuit according to claim 7, wherein in the pumping section, the third switch is turned on, the fourth switch is turned off, and the second node is connected to the output terminal of the pumping voltage.

9. The aforementioned pumping voltage variable circuit is A switching unit comprising a plurality of switches connected in parallel to the first node and selectively switched based on the control signal, The voltage conversion circuit according to claim 7, further comprising a capacitance control unit including a plurality of pumping capacitors connected between the plurality of switches and the second node.

10. The aforementioned pumping voltage variable circuit is The voltage conversion circuit according to claim 9, wherein the plurality of switches are selectively switched based on the control signal, and the number of pumping capacitors being charged among the plurality of pumping capacitors is adjusted.

11. The aforementioned pump circuit is The voltage conversion circuit according to claim 3, further comprising a charging capacitor connected between the output terminal of the pumping voltage and the ground voltage terminal.

12. A pixel array that outputs a pixel signal corresponding to the incident light, A voltage conversion circuit that generates a pumping voltage by charging and pumping a bias voltage, and adjusts the pumping capacitance according to a control signal to vary the pumping voltage, An analog-to-digital conversion circuit that samples and holds the aforementioned pixel signal, converts it into a digital signal, and outputs it. An image sensing device, comprising an image signal processor that controls the control signal in response to the intensity of light.

13. The aforementioned voltage conversion circuit is The image sensing apparatus according to claim 12, wherein a negative voltage is generated with the pumping voltage and provided to the pixel array.

14. The aforementioned image signal processor is The image sensing device according to claim 12, wherein the intensity of the light is estimated based on at least one of the average value of the pixel signal, the exposure time, and the analog gain for the pixel signal, and the control signal is controlled accordingly.

15. The aforementioned image signal processor is As the intensity of the light increases, the pumping capacitance increases. The image sensing device according to claim 12, wherein the pumping capacitance is controlled to decrease when the intensity of the light decreases.

16. The aforementioned image signal processor is The image sensing device according to claim 12, wherein the bias current of the analog-to-digital conversion circuit is adjusted based on the analog gain for the pixel signal.

17. The aforementioned image signal processor is The image sensing apparatus according to claim 16, wherein the analog-to-digital conversion circuit is controlled such that the bias current increases as the analog gain increases.

18. The aforementioned analog-to-digital conversion circuit is A comparator that compares a lamp signal with the pixel signal to generate a comparison signal, The image sensing apparatus according to claim 17, further comprising a counter that performs a counting operation based on the comparison signal.

19. The aforementioned comparator is A drive unit that selectively supplies power voltage based on the voltage level of the first node, A differential comparison unit that compares the lamp signal and the pixel signal and outputs the comparison signal to a second node, The image sensing apparatus according to claim 18, comprising a bias adjustment circuit in which the number of transistors is adjusted based on a bias current control signal to control the bias current.

20. The aforementioned image signal processor is The image sensing device according to claim 19, wherein the bias current control signal is controlled based on the analog gain.

Images