Method for measuring the deformation level of a chip and method for stacking semiconductor chips.

Abstract

This disclosure relates to a method for measuring the z-axis deformation level of a chip from a two-dimensional image of the chip. [Solution] In one embodiment, the steps include scanning the surface of a chip to obtain a two-dimensional image of the chip, extracting features of the chip surface from the two-dimensional image, and measuring the z-axis deformation level of the chip based on the extracted features.

Description

Technical Field

[0001] The present disclosure relates to a method for measuring the deformation level of a semiconductor chip and a method for stacking semiconductor chips.

Background Art

[0002] A semiconductor chip (hereinafter referred to as a chip) is manufactured by repeating unit processes such as film formation, etching, and metal wiring in order to form a fine pattern having electrical characteristics on a wafer. With the high integration of semiconductor devices and the acceleration of processes, inspections for defects in the manufacturing steps are also thoroughly carried out. This is because partial defects in the fine pattern directly lead to defects in semiconductor devices.

[0003] In the manufacturing and packaging processes of a semiconductor chip, z-axis deformation (bending or warpage) may occur due to various thermal and mechanical stresses. For example, chips that were attached to each other on a wafer may undergo deformation such as warpage during the process of being individually separated through a sawing process, and the level of such deformation may vary from chip to chip.

[0004] Since the deformation of a chip causes electrical contact failure, package lamination process failure, reduction in reliability, etc., a technique for quantitatively measuring the deformation level of the chip surface is industrially very important.

[0005] Conventionally, the deformation of a chip has been measured using a contact displacement meter, a three-dimensional shape measuring device, a device based on an interferometer, etc. However, such methods have high equipment costs, long measurement times, and are restricted in application to mass production lines.

[0006] Furthermore, in the case of a High Bandwidth Memory (HBM) formed by stacking semiconductor chips, when the deformation levels of the stacked chips are different from each other, there have been problems such as bonding failure during the process and reduction in reliability.

Summary of the Invention

[0007] According to one aspect of this disclosure, the z-axis deformation level of the chip can be estimated based on a two-dimensional image, and the total processing time can be reduced compared to three-dimensional scanning and three-dimensional image processing.

[0008] Furthermore, embodiments of the present invention can measure the z-axis deformation level using geometric or optical features that can reflect the z-axis deformation of the chip, thereby reducing processing time.

[0009] Furthermore, according to one aspect of this disclosure, the deformation level can be measured before the stacking process, and chips with similar deformation levels can be stacked to improve the reliability and productivity of the semiconductor process.

[0010] The problems addressed by the present invention are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0011] A method for measuring the deformation level of a chip according to one example of the present disclosure may include the steps of: scanning the surface of the chip to obtain a two-dimensional image of the chip; extracting features of the chip surface from the two-dimensional image; and measuring the z-axis deformation level of the chip based on the extracted features.

[0012] The step of extracting features of the chip surface may include the step of extracting geometric deformations of the chip surface from the two-dimensional image.

[0013] The step of extracting the features of the chip surface may include the step of calculating the displacement values ​​of a reference point in a reference image where no deformation exists and the reference point in the acquired two-dimensional image.

[0014] The step of extracting the features of the chip surface includes the step of extracting a planar deformation model from the displacement value and the step of calculating the mean curvature value or curvature energy value of the planar deformation model, and the z-axis deformation level of the chip can be measured based on the mean curvature value or curvature energy value.

[0015] The step of extracting the features of the chip surface includes setting the reference points to at least three or more boundaries of a specific region within the chip, and comparing the displacement values ​​of the reference points to calculate the area or shape change of the specific region, and the z-axis deformation level of the chip can be measured based on the area or shape change.

[0016] The step of extracting the features of the chip surface includes the step of extracting optical brightness values ​​for multiple regions constituting the chip surface, and the step of analyzing the contrast pattern of the chip surface based on the spatial distribution of the brightness values, wherein the spatial distribution of the brightness values ​​can change in accordance with changes in the surface gradient or reflected light caused by z-axis deformation of the chip.

[0017] The contrast pattern of the chip surface can be analyzed by comparing the brightness value of the central region of the chip with the brightness value of the peripheral region of the chip.

[0018] The z-axis deformation level is predicted by a deep learning model, which, upon receiving the acquired two-dimensional image as input, can predict and output the z-axis deformation value of the chip.

[0019] The deep learning model can be configured to use a training data pair consisting of a two-dimensional image of the chip and a deformation value related to the z-axis deformation level of the chip, and to adjust its parameters to minimize the error between the predicted and actual values ​​of the deformation value. The trained deep learning model can then be configured to generalize and predict the z-axis deformation value of the chip even for two-dimensional images of chips that were not used in training.

[0020] A chip deformation level measuring device according to one example of the present disclosure may include an image acquisition unit that scans the surface of the chip to acquire a two-dimensional image of the chip, a feature extraction unit that extracts features of the chip surface from the two-dimensional image, and a deformation calculation unit that calculates the z-axis deformation level of the chip using the extracted features.

[0021] A computer-readable recording medium according to an example of the present disclosure can, when executed by a processor, scan the surface of a chip to obtain a two-dimensional image of the chip, extract features of the chip surface from the two-dimensional image, and use the extracted features to measure the z-axis deformation level of the chip.

[0022] An example of a semiconductor chip stacking method according to this disclosure may include the steps of measuring the z-axis deformation level for each of a plurality of semiconductor chips, classifying semiconductor chips whose measured z-axis deformation levels are similar into groups, and stacking semiconductor chips belonging to the same group. [Effects of the Invention]

[0023] According to one embodiment of the present disclosure, the z-axis deformation level of the chip can be estimated based on a two-dimensional image, and the overall processing time can be reduced compared to three-dimensional scanning and three-dimensional image processing.

[0024] Furthermore, by measuring the deformation level before the stacking process and stacking chips with similar deformation levels, the reliability and productivity of the semiconductor process can be improved.

[0025] The effects of the present invention are not limited to the above-described effects, and the effects not mentioned can be clearly understood by those having ordinary knowledge in the technical field to which the present invention pertains from the present specification and the accompanying drawings.

Brief Description of the Drawings

[0026] [Figure 1a] It is a diagram showing a reference point P1 on a reference image for a chip 1 without deformation. [Figure 1b] It is a diagram showing a reference point P'1 on a two-dimensional image obtained by scanning a chip 1' with deformation. [Figure 1c] It is a diagram showing displacement values Δx and Δy of each reference point. [Figure 1d] It is a diagram showing a graph of an exemplary planar deformation model according to the present disclosure. [Figure 1e] It is a diagram showing that the z-axis deformation levels between a number of chips were compared based on average curvatures H1, H2, and H3 calculated by different planar deformation models Model 1, Model 2, and Model 3, respectively. [Figure 2] It is a diagram showing the change in brightness for three chips having different deformation levels. [Figure 3] It is a diagram schematically showing a state in which semiconductor chips are stacked.

Modes for Carrying Out the Invention

[0027] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings. However, this is merely exemplary and the present disclosure is not limited to the specific embodiments exemplarily described.

[0028] The method for measuring the deformation level of a chip according to the present disclosure can include a step (S100) of scanning the surface of the chip to obtain a two-dimensional image of the chip, a step (S200) of extracting features of the chip surface from the two-dimensional image, and a step (S300) of measuring the z-axis deformation level of the chip based on the extracted features.

[0029] According to this disclosure, the z-axis deformation level of the chip can be estimated based on a two-dimensional image obtained by scanning the surface of the chip, which has the advantage of reducing the total processing time compared to three-dimensional scanning and three-dimensional image processing.

[0030] Two-dimensional images of the chip used in this disclosure can be acquired by various image sensors, such as CCD / CMOS cameras, line scan cameras, and optical microscopes. The images can be acquired under predetermined lighting conditions, shooting distance, and shooting angle, which can be set so that changes in brightness and pattern reflect changes in the chip surface shape.

[0031] In this disclosure, "feature" can be defined as a geometric or optical feature that can reflect the z-axis deformation of the chip. Geometric features may include reference image relative displacement, deformation rate, curvature, etc., while optical features may include brightness, contrast contrast, reflection pattern, etc. Such features can be calculated using image processing techniques such as detecting the distribution of pixel values ​​in the image, edges, corners, and feature points.

[0032] The following explanation will be given with reference to Figures 1a and 2.

[0033] According to this disclosure, the step of extracting features from the chip surface includes the step of extracting geometric deformations of the chip surface from a two-dimensional image obtained by scanning the chip.

[0034] For example, the step of extracting features from the chip surface may include calculating the displacement between a reference point in a reference image where no deformation exists and a reference point in a two-dimensional image obtained by scanning the chip.

[0035] A reference image without deformation can be a two-dimensional image and can be constructed using an image taken in the initial manufacturing step or a pre-stored reference image. Reference points can be set to points detected via an image processing algorithm, such as corner points, feature points, or pattern intersections. It is preferable to set at least one reference point.

[0036] JPEG2026127064000002.jpg66170

[0037] JPEG2026127064000003.jpg38170

[0038] Furthermore, according to this disclosure, the step of extracting features of the chip surface may include the step of extracting a planar deformation model from displacement values ​​and the step of calculating the mean curvature or curvature energy value of the planar deformation model, and the z-axis deformation level of the chip may be measured based on the mean curvature or curvature energy value.

[0039] JPEG2026127064000004.jpg37170

[0040] By utilizing the reference point displacement, a two-dimensional displacement field of the chip surface can be constructed, and this can be approximated by a polynomial surface or a nonlinear function model to extract a planar deformation model.

[0041] For example, a plane deformation model can be expressed in the form of a quadratic polynomial, as follows:

[0042] f(x, y) = ax 2 +by 2 +cxy+dx+hole+f

[0043] Alternatively, to handle more complex deformations, models based on nonlinear functions can also be applied.

[0044] JPEG2026127064000005.jpg57170

[0045] Once the planar deformation model is calculated, the mean curvature or curvature energy can be calculated using the second derivative of f(x, y). This curvature-based index allows for quantitative evaluation of the z-axis deformation level of the chip surface or comparison of deformation levels between multiple chips or multiple measurement areas.

[0046] Figure 1d is a graph showing an exemplary planar deformation model according to this disclosure, and Figure 1e is a figure showing a comparison of the z-axis deformation levels between a number of chips using mean curvatures H1, H2, and H3 calculated for different planar deformation models Model 1, Model 2, and Model 3, respectively.

[0047] Thus, according to this disclosure, the overall degree of bending of the chip can be calculated using the displacement of a reference point based on a two-dimensional image, and thereby the z-axis deformation level can be evaluated.

[0048] On the other hand, this disclosure also allows for the evaluation of the z-axis deformation level of the chip based on the area or shape change of a specific region using the displacement of a reference point.

[0049] In this disclosure, the step of extracting features from the chip surface can be performed by setting reference points at least three or more boundaries of a specific region within the chip. Once the displacement value of each reference point is calculated, the area change or shape change of the specific region can be calculated by comparing the displacement values ​​of the reference points, and based on this, the z-axis deformation level of the chip can be measured.

[0050] For example, a specific region A can be defined using the area within the chip that does not contain a scribe line as a reference point. Here, the reference points constituting region A can be set to the periphery or corner points of the chip's internal region, and these can function as reference points that can be reliably tracked in chip images before and after sawing.

[0051] JPEG2026127064000006.jpg66170

[0052] Since such length changes related to the size of region A, or angle changes between each reference point, differ depending on the degree to which the tip is convex or concave, this value can be used as an indicator to quantitatively evaluate the z-axis deformation level of the tip.

[0053] For example, a pattern in which the width or height increases or decreases in a particular direction reflects the overall bending direction of the chip surface, and a change in the ratio of the distance between corner points can indicate the intensity and asymmetry of the deformation. Furthermore, the amount of shape change can reflect the amount of angle change calculated by extracting the degree to which the contour line of a particular region is inclined. The area change or shape change of a particular region defined in this way can be calculated using the individual displacement values ​​of reference points, the change in distance between reference points (width, height, diagonal, etc.), the angle change between reference points, etc., thereby measuring the level of deformation of the chip in the z-axis direction.

[0054] On the other hand, this disclosure allows for the evaluation of the z-axis deformation level of the chip using changes in brightness or contrast present in the chip image.

[0055] This can be based on the principle that optical changes occurring due to deformation of the chip surface, such as changes in incident light, shadows generated when the deformed chip portion blocks light from adjacent areas, or differences in the amount of reflected light due to changes in the surface gradient, cause changes in brightness in the image.

[0056] According to this disclosure, the step of extracting features of the chip surface may include the step of extracting optical brightness for multiple regions constituting the surface of the chip, and the step of analyzing the contrast pattern of the chip surface based on the spatial distribution of brightness values. As described above, the brightness values ​​for multiple regions may differ depending on the change in surface gradient or the change in reflected light caused by the z-axis deformation of the chip.

[0057] When a chip warps and undergoes z-axis deformation, the brightness of the entire image or parts of it may change. This can occur because the angle at which incident light reaches the surface changes, or because the edges or corners of the chip, which have moved away from their original position, block light and create localized shadows. Since the changes in brightness and contrast caused by deformation are related to the level of z-axis deformation of the chip, the level of deformation can be quantified using one or more values ​​that indicate this level, allowing for a comparison of the degree of deformation between chips.

[0058] Various metrics can be used to indicate changes in brightness or contrast. For example, these could include the width of the shaded area, the gradient of the brightness profile of the shaded area's cross-section, or the difference in relative brightness values ​​at the periphery relative to the center. Such metrics can be defined or selected by the user, or a deep learning model can be used to configure an algorithm to automatically extract brightness-based features.

[0059] On the other hand, the contrast pattern of the chip surface can be analyzed by comparing the brightness value of the central region of the chip with the brightness value of the peripheral region of the chip.

[0060] As a concrete example, let's assume a chip where the central part is in close contact with the reference surface, but the four corners curve upwards from the bottom.

[0061] In this case, if light is incident vertically from above, sufficient reflected light will reach the center of the chip, but as you move towards the corners, shading may occur due to changes in the surface gradient and light blocking effects, causing the image to gradually darken.

[0062] After setting a straight line path connecting the chip's center coordinates x_center and y_center with the corner points to be analyzed x_corner and y_corner in the acquired two-dimensional image, profiling the brightness values ​​(gray levels) of the pixels located along this path in a linear or curved form can yield a graph where the brightness decreases as you approach the corner points.

[0063] The location of the point where the brightness drops below a pre-set threshold in this brightness profile, the distance to the corner point, and the brightness gradient all reflect the change in contrast caused by chip deformation, and can therefore be used as values ​​to evaluate the level of z-axis deformation of the chip.

[0064] Figure 2 is a diagram illustrating the above example, showing the change in brightness for three chips with different levels of deformation. The left side shows a chip with no deformation, the center shows a chip with small deformation, and the right side shows a chip with large deformation.

[0065] The top three figures show a side view of how incident light reaches the surface of each chip, the middle three figures are two-dimensional images taken under the same optical conditions, and the bottom three figures are graphs showing the brightness profile along the path from the center to the corner of the image.

[0066] In the chip on the left, where no deformation exists, the incident light angles at the center and periphery are almost identical, resulting in almost no contrast pattern and virtually no graph gradient. On the other hand, in the chip with deformation, the incident light angles at the central and corner regions of the chip differ, and a contrast pattern is observed where the image gradually darkens from the center towards the corners. It can be confirmed that the more severe the deformation, the steeper the graph gradient.

[0067] The aforementioned graph allows us to check the distance between the point where the brightness drops below a predetermined threshold and the corner point, as well as the brightness gradient of the graph. This value represents the contrast change due to chip deformation and can be used to evaluate the level of deformation of the chip in the z-axis direction.

[0068] Thus, according to this disclosure, the z-axis deformation level can be quantitatively calculated by linking the optical changes of the chip with the changes in the contrast distribution within the image. This can be used not only in feature value-based methods but also in deep learning-based automatic feature extraction methods.

[0069] According to this disclosure, the z-axis deformation level of the chip can be directly predicted by a deep learning model. The deep learning model can receive an acquired two-dimensional image as input and predict and output the z-axis deformation value of the chip.

[0070] The method using deep learning involves training a deep learning model (hereinafter referred to as "the model") using a pair of training data consisting of a two-dimensional image of the chip and a value related to the deformation level of the chip. The trained model then receives a two-dimensional image of the chip as input and predicts and outputs the deformation level or a related value (hereinafter referred to as "deformation value").

[0071] During the training process, the model first receives chip images from the training data as input and predicts the deformation value. Then, it calculates the error between the predicted value and the actual deformation value of the chip, and iteratively adjusts the model's weights and parameters to reduce this error. Training can continue until the model reaches a performance criterion set by the user (e.g., loss value, accuracy, RMSE, etc.).

[0072] Through this process, the model learns patterns, correlations, and nonlinear changes that exist between images and deformation values, and ultimately forms a mapping within the model that extracts deformation values ​​from images.

[0073] By applying appropriate normalization or data augmentation to prevent overfitting, the model can generalize and accurately predict the deformation value of new chip images that were not used in the training process.

[0074] The generalization capability of such deep learning-based models allows for stable estimation of deformation levels even in environments with various lighting conditions, different chip patterns, and manufacturing deviations between chips.

[0075] As for the model structure, for example, a CNN-based network, a ResNet structure including residual learning, or a Vision Transformer (ViT)-based structure that simultaneously reflects the local pattern and overall contour of the deformed region can be applied.

[0076] The model's output values ​​can be defined in various forms of deformation values, such as the absolute value, relative value, curvature-based index, and displacement-based index of the z-axis deformation, and can be selected according to the form of the training data.

[0077] Furthermore, the loss function used in training the model can be L1 (Lasso), L2 (MSE), Huber loss, or other methods commonly used in image-based regression problems, and the model parameters can be updated in a direction that minimizes this loss function.

[0078] Therefore, prediction methods based on deep learning have the advantage of being able to estimate the level of chip deformation using the entire image, without the need for predefined feature extraction procedures such as feature points and brightness values.

[0079] On the other hand, the chip deformation level measurement according to this disclosure can be realized in an apparatus configuration that includes an image acquisition unit that scans the surface of the chip to acquire a two-dimensional image of the chip, a feature extraction unit that extracts features of the chip surface from the two-dimensional image, and a deformation calculation unit that uses the extracted features to calculate the z-axis deformation level of the chip.

[0080] Furthermore, the method for measuring the deformation level of a chip according to this disclosure can be stored in a computer-readable recording medium in the form of an instruction set, and a processor can execute this to acquire a chip image, extract features, and calculate deformation.

[0081] The above describes the method for measuring the deformation level of a chip according to this disclosure. The semiconductor chip stacking method will now be described with reference to Figure 3.

[0082] The semiconductor chip stacking method according to this disclosure uses the aforementioned deformation level measurement technology based on a two-dimensional image of the chip to consider the deformation level of the chip during the semiconductor chip stacking process, and enables stacking of chips having similar deformation levels.

[0083] As shown on the left side of Figure 3, in semiconductor packaging or 3D stacking processes, if there is a large difference in z-axis deformation (warpage) between chips, various reliability problems can occur, such as increased stress inside the package, imbalance in contact surfaces between chips, deformation of the stacked structure, and bonding failures. Therefore, as shown on the right side of Figure 3, measuring the z-axis deformation level of each chip before stacking, classifying chips with similar deformation levels into groups, and stacking chips within the same group is effective in ensuring the stability and reliability of the entire stacked structure.

[0084] According to this disclosure, the steps include measuring the z-axis deformation level for each of a plurality of semiconductor chips, classifying semiconductor chips with similar measured z-axis deformation levels into groups, and stacking semiconductor chips belonging to the same group.

[0085] The deformation value indicating the z-axis deformation level may be a single scalar value, or it may be composed of a feature vector containing various values ​​such as the average curvature value, curvature energy value, and graph gradient based on brightness for each chip.

[0086] Once the deformation values ​​of the chips are obtained, the difference or similarity in deformation levels between chips can be quantitatively compared. For example, if the difference in deformation values ​​between two chips is less than or equal to a predetermined threshold, they can be judged to have the same deformation characteristics. Alternatively, the similarity of deformation can be determined by applying various quantitative criteria, such as a criterion based on RMS (root mean square) or a criterion based on curvature gradient. Depending on the similarity of the deformation values, the chips can be classified into one or more groups, and chips with the same or similar deformation levels can form a single group.

[0087] The grouped chips are stacked according to their respective groups, and by arranging chips belonging to the same group consecutively, deformation imbalances within the stacked structure can be minimized.

[0088] For example, chips with large deformations can be stacked together in one group, or chips with small deformations can be stacked together to ensure uniform package flatness, or inappropriate combinations of chips with opposite deformation directions or large curvature differences can be avoided.

[0089] According to this disclosure, the flatness of the package surface can be improved, and the advantages of ensuring uniformity of the chip stress distribution and long-term reliability can be provided.

[0090] While embodiments of the present invention have been described above with reference to the attached drawings, a person with ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without altering its technical idea or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not limiting. [Explanation of Symbols]

[0091] 1. Reference image 1' Acquired 2D image

Claims

1. The steps include scanning the surface of the chip to obtain a two-dimensional image of the chip, The steps include extracting features of the chip surface from the two-dimensional image, A method for measuring the deformation level of a chip, comprising the step of measuring the z-axis deformation level of the chip based on the extracted features.

2. The step of extracting the features of the chip surface is: A method for measuring the deformation level of a chip according to claim 1, comprising the step of extracting geometric deformation of the chip surface from the two-dimensional image.

3. The step of extracting the features of the chip surface is: A method for measuring the deformation level of a chip according to claim 2, comprising the step of calculating the displacement values ​​of a reference point in a reference image in which no deformation exists and the reference point in the acquired two-dimensional image.

4. The step of extracting the features of the chip surface is: The steps include extracting a planar deformation model from the aforementioned displacement values, The steps include calculating the mean curvature value or curvature energy value of the planar deformation model, The method for measuring the deformation level of a chip according to claim 3, wherein the z-axis deformation level of the chip is measured based on the mean curvature value or the curvature energy value.

5. The step of extracting the features of the chip surface is: The steps include setting the aforementioned reference points at least three or more boundaries of a specific region within the chip, The step includes comparing the displacement values ​​of the aforementioned reference points to calculate the area or shape change of the specified region, The method for measuring the deformation level of a chip according to claim 3, wherein the z-axis deformation level of the chip is measured based on the area or the amount of change in shape.

6. The step of extracting the features of the chip surface is: The steps include extracting optical brightness values ​​for multiple regions constituting the surface of the chip, The step includes analyzing the contrast pattern of the chip surface based on the spatial distribution of the brightness values, The method for measuring the deformation level of a chip according to claim 1, wherein the spatial distribution of the brightness value changes in accordance with the change in surface gradient or the change in reflected light caused by the z-axis deformation of the chip.

7. The method for measuring the deformation level of a chip according to claim 6, wherein the contrast pattern of the chip surface is analyzed by comparing the brightness value of the central region of the chip with the brightness value of the peripheral region of the chip.

8. The aforementioned z-axis deformation level is predicted by a deep learning model. The method for measuring the deformation level of a chip according to claim 1, wherein the deep learning model receives the acquired two-dimensional image as input and predicts and outputs the z-axis deformation value of the chip.

9. The deep learning model uses training data pairs consisting of a two-dimensional image of the chip and deformation values ​​related to the z-axis deformation level of the chip, and its parameters are adjusted to minimize the error between the predicted and actual values ​​of the deformation values. The method for measuring the deformation level of a chip according to claim 8, wherein the trained deep learning model is configured to generalize and predict the z-axis deformation value of the chip even for two-dimensional images of the chip that were not used in training.

10. An image acquisition unit scans the surface of the chip to obtain a two-dimensional image of the chip, A feature extraction unit that extracts features of the chip surface from the two-dimensional image, A chip deformation level measuring device, comprising a deformation calculation unit that calculates the z-axis deformation level of the chip using the extracted features.

11. When executed by the processor, The surface of the chip is scanned to obtain a two-dimensional image of the chip. Features of the chip surface are extracted from the two-dimensional image, A computer-readable recording medium containing instruction words for measuring the z-axis deformation level of the chip using the extracted features.

12. A method for stacking semiconductor chips according to claim 1, A step of measuring the z-axis deformation level for each of multiple semiconductor chips, A method for stacking semiconductor chips, comprising the steps of classifying semiconductor chips whose measured z-axis deformation levels are similar to each other into groups, and stacking semiconductor chips belonging to the same group.

Images