Gaming machine

Abstract

To enable efficient and proper wiring between multiple circuit boards. [Solution] The gaming machine's wiring path includes a first wiring pattern formed on a first circuit board, a connector for connecting the path between the first circuit board and the second circuit board, and a second wiring pattern formed on the second circuit board. In the wiring path, a group of signals, which are multiple signals used for common processing, are transmitted between the first electronic component and the second electronic component. Multiple pattern lines that transmit the group of signals in the first wiring pattern are of approximately equal length to each other, and multiple pattern lines that transmit the group of signals in the second wiring pattern are of approximately equal length to each other. In the connector, the terminals assigned to the group of signals are terminals in the same row among multiple rows. The first wiring pattern is provided with a line length adjustment section on some of the pattern lines among the multiple pattern lines that transmit the group of signals.

Description

Technical Field

[0001] The present invention relates to a gaming machine.

Background Art

[0002] In pinball gaming machines and rotating gaming machines, various effects using a liquid crystal display screen, a speaker, LEDs, actuators, vibrators, blowers, etc. are performed to enliven the game. In the following patent documents, technologies for controlling various effect operations are disclosed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such gaming machines, as various and complex effects are performed, the configuration and arrangement of the boards for driving various effect devices are becoming complicated. In the present invention, in response to such circumstances, a suitable board configuration for a gaming machine is proposed.

Means for Solving the Problems

[0005] The gaming machine of the present invention has a first electronic component provided on a first circuit board, a second electronic component provided on a second circuit board, and a wiring path that electrically connects the first electronic component and the second electronic component, wherein the wiring path includes a first wiring pattern formed on the first circuit board, a connector for connecting the path between the first circuit board and the second circuit board, the connector having multiple rows of terminals, and a second wiring pattern formed on the second circuit board, wherein a group of signals, which are multiple signals used for common processing, are transmitted between the first electronic component and the second electronic component in the wiring path, and the first wiring pattern contains the group Multiple pattern lines that transmit the signals are of approximately equal length to each other, and in the second wiring pattern, multiple pattern lines that transmit the group of signals are of approximately equal length to each other, and in the connector, the terminals assigned to the group of signals are terminals in the same row of multiple rows, and in the first wiring pattern, a line length adjustment section is provided in some of the multiple pattern lines that transmit the group of signals, and the line length adjustment section in some of the pattern lines is provided on the first electronic component side of the center position on the pattern line between the first electronic component and the connector on the first substrate. Furthermore, the line length adjustment section is provided continuously with the pad to which the terminals of the first electronic component are connected, and after passing from the pad through the line length adjustment section, the multiple signal pattern wirings of the group may be wired in parallel. [Effects of the Invention]

[0006] According to the present invention, a circuit board configuration suitable for gaming machines that perform various effects can be realized. [Brief explanation of the drawing]

[0007] [Figure 1] This is a front perspective view showing the external appearance of a gaming machine according to an embodiment of the present invention. [Figure 2] This diagram shows the configuration of the game board of the gaming machine according to the embodiment. [Figure 3] This is a block diagram showing the control configuration of a gaming machine according to an embodiment. [Figure 4]It is an explanatory diagram of an example of a preview performance of an embodiment. [Figure 5] It is a perspective view of the door of the gaming machine of the embodiment in an open state. [Figure 6] It is a perspective view of the inner frame of the gaming machine of the embodiment in an open state. [Figure 7] It is an explanatory diagram of the substrate arrangement on the back side of the game board of the embodiment. [Figure 8] It is an explanatory diagram of the substrate arrangement of the door and the inner frame of the gaming machine of the embodiment. [Figure 9] It is an explanatory diagram of the substrate arrangement of the inner frame of the gaming machine of the embodiment. [Figure 10] It is an explanatory diagram of the arrangement of various devices. [Figure 11] It is a block diagram of the connection configuration of the substrate. [Figure 12] It is an explanatory diagram of the power supply substrate. [Figure 13] It is an explanatory diagram of the components mounted on the power supply substrate. [Figure 14] It is an explanatory diagram of a single-system transmission example in which transmission between the effect control substrate and the LED connection substrate is performed through one transmission path by a pair of connectors. [Figure 15] It is an explanatory diagram of a multi-system transmission example in which transmission between the effect control substrate and the LED connection substrate is performed through two transmission paths by two pairs of connectors. [Figure 16] It is an explanatory diagram of the assignment of two-row connector pins in the multi-system transmission example. [Figure 17] It is a block diagram of the configuration around the input connector of the LED connection substrate. [Figure 18] It is a block diagram of the configuration around the LED drive unit of the LED connection substrate. [Figure 19] It is a block diagram of the configuration around the motor drive unit of the LED connection substrate. [Figure 20] It is a circuit diagram of the periphery of the input connector of the LED connection substrate according to the single-system transmission example. [Figure 21] It is a circuit diagram of the periphery of the input connector of the LED connection substrate according to the multi-system transmission example. [Figure 22] It is a circuit diagram of the periphery of the LED driver of the LED connection substrate. [Figure 23] It is a circuit diagram around the LED driver of the LED connection board. [Figure 24] It is a circuit diagram around the output-side connector of the LED connection board. [Figure 25] It is a circuit diagram around the output-side connector of the LED connection board. [Figure 26] It is a circuit diagram of a part of the power supply system of the LED connection board. [Figure 27] It is an explanatory diagram of the connector in the case of a single-system transmission example. [Figure 28] It is an explanatory diagram of the connector in the case of a multi-system transmission example. [Figure 29] It is an explanatory diagram of the connector in the case of a multi-system transmission example. [Figure 30] It is an explanatory diagram of the connector arrangement example in the multi-system transmission example. [Figure 31] It is an explanatory diagram of the connector arrangement example in the multi-system transmission example. [Figure 32] It is an explanatory diagram of the connector arrangement example in the multi-system transmission example. [Figure 33] It is an explanatory diagram of the connector arrangement example in the multi-system transmission example. [Figure 34] It is an explanatory diagram of the assignment of two-row connector pins in the multi-system transmission example. [Figure 35] It is an explanatory diagram of the pattern of the surface layer of the LED connection board. [Figure 36] It is an explanatory diagram of the pattern of the back layer of the LED connection board. [Figure 37] It is an explanatory diagram of the pattern of the first inner layer of the LED connection board. [Figure 38] It is an explanatory diagram of the pattern of the second inner layer of the LED connection board. [Figure 39] It is an explanatory diagram with a partial enlargement of the pattern of the surface layer of the LED connection board. [Figure 40] It is an explanatory diagram of an example of a test point. [Figure 41] It is an explanatory diagram with a partial enlargement of the pattern of the surface layer of the LED connection board. [Figure 42]This is an explanatory diagram showing a magnified view of the pattern on the back layer of the LED connection board. [Figure 43] This is an explanatory diagram for chip-type fuses. [Figure 44] This is an explanatory diagram of the fuse arrangement in a series supply circuit for power supply voltage. [Figure 45] This is an explanatory diagram of the fuse arrangement in a series supply circuit for power supply voltage. [Figure 46] This is a diagram illustrating the terminal assignments for a two-row connector. [Figure 47] This is a diagram illustrating the connection between the performance control board and the LED connection board, as well as the assignment of connector terminals. [Figure 48] This is a diagram illustrating the wiring of the connector and CPU on the performance control board. [Figure 49] This is a diagram illustrating the placement of connectors and bypass capacitors. [Figure 50] This is an explanatory diagram of an example of the circuit board configuration from the performance control board onwards. [Figure 51] This is a diagram illustrating the case containing the performance control board and the performance interface board. [Figure 52] This is a circuit diagram relating to the performance control signals in the performance interface board. [Figure 53] This is an explanatory diagram illustrating an example configuration in which the performance interface board outputs to multiple boards. [Figure 54] This is a diagram illustrating the wiring of the pull-up resistors on the performance interface board. [Figure 55] This is an explanatory diagram of a performance control board equipped with a heatsink. [Figure 56] This is an explanatory diagram of a control board equipped with a fan. [Figure 57] This is an explanatory diagram of the performance control board with the heat dissipation mechanism removed. [Figure 58] This is an explanatory diagram of a performance control board with its outer edge line indicated. [Figure 59] This is an explanatory diagram of the lower range and the center point in the performance control board. [Figure 60] This diagram illustrates how the component information labeling area in the lower part of the heatsink is visible. [Figure 61] This is an explanatory diagram of the visible area in the lower part of the heatsink. [Figure 62] This is an explanatory diagram showing a situation where the component information labeling area is located on the outer edge of the electronic component. [Figure 63] This is an explanatory diagram illustrating an example where the correspondence between electronic components and component information labels is shown using leader lines. [Figure 64] This is an explanatory diagram illustrating an example where the correspondence between electronic components and component information labels is shown using leader lines. [Figure 65] This is an explanatory diagram illustrating an example where the component information labeling area is located outside the outer edge line. [Figure 66] This is an explanatory diagram illustrating an example where the component information display area is located across the outer edge line. [Figure 67] This is an explanatory diagram illustrating an example where an electronic component is located across the outer edge line. [Figure 68] This is an explanatory diagram illustrating an example where an electronic component is located across the outer edge line, and its correspondence is indicated by a leader line. [Figure 69] This is an explanatory diagram illustrating an example of how multiple electronic components are associated with component information display sections. [Figure 70] This is an explanatory diagram illustrating an example of how multiple electronic components are associated with component information display sections. [Figure 71] This is an explanatory diagram illustrating an example of how multiple electronic components are associated with component information display sections. [Figure 72] This is an explanatory diagram illustrating an example of how multiple electronic components are associated with component information display sections. [Figure 73] This is an explanatory diagram showing an electronic component adjacent to a component information display area outside the lower range. [Figure 74] This is an explanatory diagram illustrating the distance relationship between electronic components, component information labels, outer borders, and the CPU. [Figure 75] This is an explanatory diagram of an example of the circuit board configuration from the performance control board onwards. [Figure 76] This is an explanatory diagram of the case containing the performance control board, LCD control board, ROM board, and LCD interface board. [Figure 77] This is a circuit diagram of a portion of the liquid crystal control board. [Figure 78]This is a circuit diagram of a portion of a ROM board. [Figure 79] This is an explanatory diagram of the pattern on the liquid crystal control board. [Figure 80] This is an enlarged explanatory diagram of a portion of the pattern on a liquid crystal control board. [Figure 81] This is an explanatory diagram showing the extracted pattern of a liquid crystal control board. [Figure 82] This is an explanatory diagram of the ROM board pattern. [Figure 83] This is a diagram illustrating the connector on the LCD control board. [Figure 84] This is a diagram illustrating the connector on the ROM board. [Figure 85] This is a cross-sectional view of the connector in its connected state. [Figure 86] This is an explanatory diagram of the area around the pads in a parallel wiring pattern. [Figure 87] This is a circuit diagram of an LED board. [Figure 88] This is the circuit diagram for the downstream LED board. [Figure 89] This is a diagram illustrating the pattern of the surface layer of an LED substrate. [Figure 90] This is an explanatory diagram of the pattern on the back layer of the LED substrate. [Figure 91] This is an explanatory diagram of the patterns on the surface and back layers of the downstream LED substrate. [Figure 92] This is an explanatory diagram of the placement of the LED circuit board at the very end of the distribution chain. [Figure 93] This is an explanatory diagram of the arrangement of LEDs on the circuit board. [Figure 94] This is an explanatory diagram of the arrangement of LEDs on the circuit board. [Figure 95] This is an explanatory diagram of the connector's reinforcing plate. [Modes for carrying out the invention]

[0008] Hereinafter, embodiments of the present invention will be described in the following order with reference to the attached drawings. <1. Structure of a gaming machine> <2. Control Configuration of Gaming Machines> [2.1 Main Control Board] [2.2 Performance Control Board] <3. Overview of Operation> [3.1 Game Status] [3.2 Symbol Variation Display Game] [3.3 Regarding the amount per unit] [3.4 Regarding the direction / staging] <4. Opening / closing structure and circuit board arrangement> <5. Circuit board configuration> [5.1 Connection status of each board] [5.2 Transmission path between the performance control board and the LED connection board] [5.3 LED Connection Board] <6. Characteristic Configuration and Effects of the Embodiment> <7. Other>

[0009] <1. Structure of a gaming machine> The structure of a pachinko game machine 1 as an embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a front perspective view showing the external appearance of the pachinko game machine 1, and Figure 2 is a diagram showing the front side of the game board 3 of the pachinko game machine 1. In the case of the pachinko game machine 1, it has a frame member, a door member that is provided to the frame member so as to be openable and closable, and a replaceable member that is attached to the frame member so as to be replaceable. The pachinko game machine 1 described below has an inner frame 2 as a component corresponding to the frame member, a door 6 as a component corresponding to the door member, and a game board 3 as a component corresponding to the replaceable member.

[0010] The pachinko game machine 1 shown in Figure 1 (hereinafter sometimes abbreviated as "game machine 1") has a wooden outer frame 4, a picture frame-shaped inner frame 2 attached to the front so as to be openable and closable, a game board 3 (see Figure 2) mounted inside a game board storage frame (not shown) attached to the back of the inner frame 2, and a game area 3a formed on the surface of the game board 3 facing the opening of the inner frame 2. The game board 3 can be attached to and detached from the inner frame 2 in an interchangeable manner and can therefore be called an interchangeable component. A door 6 supported by transparent glass is provided at the front of the game area 3a. Various control boards (see Figure 3) for controlling game operation are located on the back side of the game board 3.

[0011] On the front side of the door 6 (the player's side), a side unit 10 is formed as a decorative unit that surrounds all or part of the game board 3. The side unit 10 is designed with a decorative shape that matches the theme of the gaming machine 1, and may also be equipped with LEDs, mechanical devices, and other performance elements inside, thereby conveying the atmosphere of the game to the player. This side unit 10 is a unit that can be interchangeably attached to the door 6.

[0012] A key cylinder (not shown) for unlocking the door is provided on the front side of the door 6. By inserting a key into this key cylinder and operating it in one direction, the lock on the door 6 to the inner frame 2 is released, allowing the door 6 to be opened forward. By operating it in the other direction, the lock on the inner frame 2 to the outer frame 4 is released, allowing the inner frame 2 to be opened forward.

[0013] A front control panel 7 is positioned on the lower side of the door 6, pivotally supported by a hinge (not shown) on the inner frame 2 so as to be able to open and close. The front control panel 7 is equipped with an upper receiving unit 8, and this upper receiving unit 8 has an upper receiving tray 9 formed therein for storing the dispensed game balls.

[0014] The upper tray unit 8 is also provided with a ball release button 14 for removing the game balls stored in the upper tray 9 to the bottom of the game machine 1, a ball dispensing button 11 for requesting game balls from a game ball dispensing device (not shown), and a card return button 12 for requesting the return of a valuable medium inserted into the game ball dispensing device. The upper tray unit 8 is also equipped with a performance button 13 (operating means) that can be operated by the player. This performance button 13 becomes operable (input accepted) when its built-in lamp (button LED 75) lights up during a predetermined input acceptance period, and by performing a predetermined operation (pressing, repeatedly pressing, holding, etc.) while the built-in lamp is lit, it is possible to change the performance. The upper tray unit 8 is also equipped with controls such as a directional pad 15a for players, hall staff, and other users to select various items and indicate directions, and a confirmation button 15b for confirming selected items.

[0015] Furthermore, a launch operation handle 15 for operating the launch device 32 (see Figure 3) is provided on the right end of the front control panel 7.

[0016] Furthermore, speakers 46 are provided on both sides of the upper part of the inner frame 2 and on the upper side of the firing operation handle 15 to produce sound effects. Figure 1 shows only the two speakers 46 on the upper part of the inner frame 2. Multiple speakers 46 are used to enable stereo sound reproduction and multi-channel sound reproduction for sounds related to the performance.

[0017] Furthermore, multiple decorative lamps 45 (for example, full-color LEDs for light effects: see Figure 3) are provided at appropriate locations on the door 6 to produce a light effect through illumination. Multiple full-color LEDs (light effect LEDs) serving as decorative lamps 45 are provided around the pachinko game machine 1, for example, around the periphery of the door 6 and within the side unit 10.

[0018] Referring to Figure 2, the configuration of the game board 3 will be explained. The game board 3 shown in the illustration has a ball guide rail 5 mounted in a ring shape as a board surface partitioning member to guide the launched game ball. The roughly circular area surrounded by this ball guide rail 5 is the game area 3a, and the four corners are non-game areas.

[0019] Approximately in the center of this game area 3a, a liquid crystal display (LCD) 36 is provided, which is capable of independently displaying variations (variation display and stop display) of multiple types of decorative symbols (for example, left symbol (corresponding to the left display area), middle symbol (corresponding to the middle display area), and right symbol (corresponding to the right display area)) in, for example, three display areas (symbol variation display areas) (left, middle, and right). This liquid crystal display device 36, under the control of the performance control board 30 described later, displays various effects as images, in addition to the changing display operation of decorative patterns.

[0020] Furthermore, a center ornament 48 is provided within the game area 3a, surrounding the display surface of the liquid crystal display device 36 at a distance. The center ornament 48 is provided along the front side of the game board 3, protecting the display surface of the liquid crystal display device 36 from surrounding game balls, and also functions as a path distribution means that allows the path of the game balls to be divided to the left or right depending on the force or stroke length of the launch of the game balls. In this embodiment, the center ornament 48 is positioned approximately in the center of the game area 3a so that the presence of the center ornament 48 forms a flow path for the game balls on both the upper sides (left and right) of the game area 3a. The game balls launched into the upper part of the game area 3a by the launching device 32 are distributed to the left and right at the upper part of the armor frame 48b and flow down either the left-downward flow path 3b on the left side of the center ornament 48 or the right-downward flow path 3c on the right side.

[0021] Furthermore, the non-game area at the bottom of the game board 3 serves as a display area for various functions, and is equipped with a special symbol display device 38a (first special symbol display means) and a special symbol display device 38b (second special symbol display means) using dot matrix displays. Figure 4 shows an enlarged view of the various function display units, including the special pattern display devices 38a and 38b.

[0022] In the special symbol display devices 38a and 38b, a special symbol variation display game is executed by the variation display operation of "special symbols" represented by dot displays. In the liquid crystal display device 36, in time synchronization with the variation display of special symbols by the special symbol display devices 38a and 38b, decorative symbols are displayed in a variation manner, and a decorative symbol variation display game is executed along with various pre-announcement effects (effect images) (details of these symbol variation display games will be explained later).

[0023] Furthermore, the various function display sections are equipped with a combined display device (LED display device for combined hold display) 38c, which, like the special symbol display devices 38a and 38b, consists of a dot display. The term "combined" is used because it is a combined hold, time-saving, and high-probability display device (hereinafter simply referred to as the "combined display device") that has five display functions: displaying the number of balls held for special symbols 1 and 2, the number of balls held for normal symbols, and notifying the state when the variable time reduction function is in operation (time-saving mode) and when the high-probability state is in operation (high-probability mode).

[0024] Furthermore, various function display units are equipped with a composite display device 38d, which is also a dot matrix display. This combined display device 38d displays the number of rounds, indicating the specified number of rounds (maximum number of rounds) related to a jackpot, based on the combination of the on / off states of the four LEDs. For example, the combination of the on / off states of the four LEDs indicates the specified number of rounds (maximum number of rounds) related to a jackpot. Furthermore, in the combined display device 38d, a game of displaying a regular symbol variation is executed by the variation display operation of a regular symbol represented by a single LED. Furthermore, the combined display device 38d uses three LEDs to indicate right-handed play.

[0025] Below the center ornament 48 in Figure 2, an opening 34 (first special symbol opening: first starting means) is provided inside. Inside the opening 34, a detection sensor 34a (opening sensor 34a, see Figure 3) is formed to detect the passage of a game ball. Furthermore, the rightward flow path 3c is provided with a start port 35 (second special symbol start port: second start means) that performs opening and closing operations, and a detection sensor 35a (start port sensor 35a: see Figure 3) that detects the passage of game balls is formed inside.

[0026] The starting opening 34, which is the first special symbol starting opening, is a prize-winning opening related to the starting conditions for the variable display operation of the first special symbol (hereinafter, the first special symbol will be referred to as "special symbol 1," and sometimes abbreviated as "special symbol 1") in the special symbol display device 38a, and is configured as a prize-winning device with a fixed winning rate that does not have a starting opening opening opening means (means that allow the starting opening to be opened or enlarged). In this embodiment, due to the action of the game ball falling direction changing members (for example, game pins, windmills 44, center decorations 48, etc.) in the game area 3a, the starting opening 34 is configured to be easy to enter (win) for game balls that have flowed down the left-down path 3b, while it is difficult or impossible to enter for game balls that have flowed down the right-down path 3c.

[0027] The starting port 35 is a prize entry port related to the starting conditions for the variable display operation of the second special symbol (hereinafter, the second special symbol will be referred to as "special symbol 2," and sometimes abbreviated as "special symbol 2") in the special symbol display device 38b, and the prize entry area of ​​this starting port 35 is configured to be open and close between an open state in which a prize can be won and a closed state in which a prize cannot be won.

[0028] The starting port 35 is a prize entry port related to the starting conditions for the variable display operation of special symbol 2 in the special symbol display device 38b, and is configured as a variable starting port whose opening and closing is controlled by the ordinary electric mechanism 41. The standard electric mechanism 41 is controlled to either an open state that allows game balls to enter the starting opening 35, or a closed state that makes it difficult or impossible for game balls to enter the starting opening 35.

[0029] Furthermore, two general prize entry points 43 are provided on the left and right lower sides of the game area 3a, and a general prize entry point sensor 43a for detecting the passage of game balls is formed inside each of them. Furthermore, within the game board area, movable mechanical devices (not shown) that provide visual effects are positioned so as not to obstruct the flow of game balls.

[0030] Furthermore, diagonally above the ordinary electric mechanism 41, that is, above the middle section of the rightward flow path 3c, is provided an ordinary symbol start opening 37 (third starting means) consisting of a passage gate (specific passage area) through which game balls can pass. This ordinary symbol start opening 37 is a prize entry point related to the variable display operation of the ordinary symbols of the composite display device 38d, and an ordinary symbol start opening sensor 37a (see Figure 3) for detecting passing game balls is formed inside it. In this embodiment, the ordinary symbol start opening 37 is formed only on the rightward flow path 3c side and not on the leftward flow path 3b side. However, the present invention is not limited to this, and it may be formed only on the leftward flow path 3b, or on both flow paths.

[0031] In the path from the normal symbol start opening 37 within the rightward flow path 3c, there is a special variable prize winning device 52 (special electric mechanism) configured to open or enlarge the large prize winning opening 50 by an opening door 52b, and a large prize winning opening sensor 52a (see Figure 3) is formed inside it to detect game balls that have entered the large prize winning opening 50. Around the large prize winning opening 50, there are guide sections 55 and windmills 53 that work to guide the flowing game balls towards the large prize winning opening 50.

[0032] The process of a game ball entering the large prize slot 50 is as follows: The game ball, after passing through the movable area between the upper surface of the center ornament 48 and the ball guidance rail 5 and proceeding along the rightward downward path 3c, is guided by the guide unit 55 towards the large prize opening 50. If the large prize opening 50 is open (large prize opening open state), the game ball is guided into the large prize opening 50.

[0033] In this embodiment of the gaming machine 1, if the player aims the launch position towards the special variable prize winning device 52 (i.e., aims so that the game ball passes through the rightward downward path 3c), the configuration makes it difficult or impossible for the game ball to be guided towards the starting opening 34. Therefore, if the "large prize winning opening is closed," it becomes difficult or impossible for the ball to enter the starting opening 34. Furthermore, when the game enters a state with electric support (described later), the starting port 35 operates with a more advantageous opening and closing pattern than in the normal state.

[0034] In this embodiment, the advantageous playing style for the player varies depending on the game state. Specifically, in a game state with "no electric support" (described later), "left-handed play," where the player aims to have the ball pass through the left-down path 3b, is advantageous. In a game state with "electric support" (described later), "right-handed play," where the player aims to have the ball pass through the right-down path 3c, is advantageous.

[0035] In the gaming machine 1 of this embodiment, when a ball enters one of the various prize-winning slots provided in the gaming area 3a, other than the regular symbol start slot 37, the number of prize balls awarded per winning ball for each prize-winning slot (for example, 3 balls for start slot 34 or start slot 35, 13 balls for the large prize slot 50, and 10 balls for the general prize slot 43) is dispensed from the gaming ball dispensing device 19 (see Figure 3). Gaming balls that do not enter any of the above prize-winning slots are discharged from the gaming area 3a via the out slot 49.

[0036] Here, "winning" refers to a game ball entering an entry point, or, if the entry point is not designed to take in game balls but consists of a pass-through gate (for example, the normal symbol start point 37), a game ball passing through that gate. In practice, if a game ball is detected by the entry detection switch formed for each entry point, it is treated as if a "winning" event has occurred at that entry point. The game ball involved in this winning is also called a "winning ball." Since a game ball entering an entry point will be detected by the entry detection switch, unless otherwise specified in this specification, the term "winning" may be used to include the case where a game ball enters an entry point, regardless of whether or not the game ball is detected by the entry detection switch.

[0037] <2. Control Configuration of Gaming Machines> Referring to the block diagram in Figure 3, the configuration (control configuration) for realizing the game operation control of the gaming machine 1 will be explained. The gaming machine 1 of this embodiment is configured to include a main control board (main control means) 20 that comprehensively controls the overall operation of the game (game operation control), an effect control board 30 (effect control means) that receives effect control commands from the main control board 20 and comprehensively controls the execution control of effects by the effect means (appearance control), a payout control board (payout control means) 29 that controls the payout of prize balls, and a power supply board (power supply control means (not shown)) that generates and supplies the necessary power to the gaming machine 1 from an external power supply (not shown). Note that the power supply routes to each component are omitted in Figure 3.

[0038] [2.1 Main Control Board] The main control board 20 is equipped with a microprocessor that incorporates a CPU (Central Processing Unit) 20a (main control CPU), a control program that describes the game operation control procedure, a ROM (Read Only Memory) 20b (main control ROM) that stores various data necessary for game operation control, and a RAM (Random Access Memory) 20c (main control RAM) that functions as a work area and buffer memory, thus forming a microcomputer as a whole.

[0039] Although not shown in the diagram, the main control board 20 also includes a CTC (Counter Timer Circuit) for implementing periodic interrupts, a function to create pulse outputs of a fixed period (bitrate generator), and a time measurement function; an interrupt controller circuit that provides interrupt enable / disable functions such as timer interrupts that supply interrupt signals to the main control CPU 20a; a reset circuit that can reset the main control CPU 20a by detecting power-on, power-off, or power supply abnormalities and outputting a system reset signal; a watchdog timer (WDT) circuit that monitors abnormal operation of the control program; an Intrusion Prevention of Travel Outside Designated Area (IAT) circuit that monitors whether the program is being executed correctly within a preset address range; and a counter circuit for generating random numbers within a certain range in hardware.

[0040] The counter circuit described above includes a random number generation circuit that generates random numbers and a sampling circuit that samples random numbers from the random number generation circuit at predetermined timings, and functions as a 16-bit counter as a whole. The main control CPU 20a sends instructions to the sampling circuit according to the processing state to obtain the value indicated by the random number generation circuit as an internal random number for lottery (random number for jackpot determination (magnitude of random number: 65536)), and uses this random number for jackpot lottery. The internal random number for lottery is obtained by adding a software random number generated by appropriate software processing and a hardware random number to prevent cheating such as targeting specific jackpots.

[0041] The main control board 20 is connected to a start-up sensor 34a that detects entry into the start-up opening 34, a start-up sensor 35a that detects entry into the start-up opening 35, a regular symbol start-up sensor 37a that detects passage through the regular symbol start-up opening 37, a large prize-winning opening sensor 52a that detects entry into the large prize-winning opening 50, a general prize-winning opening sensor 43a that detects entry into the general prize-winning opening 43, and an OUT monitoring switch 49a that detects game balls (out balls) discharged from the out-up opening 49. The main control board 20 is capable of receiving detection signals output from these sensors. Based on the detection signals from each sensor, the main control board 20 can determine which prize-winning opening a game ball has entered.

[0042] Furthermore, the main control board 20 is connected to a standard electric mechanism solenoid 41c for controlling the opening and closing of the movable blades of the start opening 35, and a large prize opening solenoid 52c for controlling the opening and closing of the opening door 52b of the large prize opening 50. The main control board 20 is capable of transmitting control signals to control these.

[0043] Furthermore, the main control board 20 is connected to special symbol display devices 38a and 38b, and the main control board 20 is capable of transmitting control signals for displaying and controlling special symbols 1 and 2. In addition, the main control board 20 is connected to a composite display device 38c, and is capable of transmitting control signals for controlling the display of the number of reserved symbols and the status display.

[0044] Furthermore, a combined display device 38d is connected to the main control board 20, and the main control board 20 is capable of transmitting control signals to control the display of normal symbols, right-hand shots, and rounds shown on the combined display device 38d.

[0045] Furthermore, the main control board 20 is connected to an external centralized terminal board 21 for the frame, and the main control board 20 is capable of transmitting predetermined game information (for example, jackpot information, prize ball count information, symbol change execution information, etc.) to a hall computer HC located outside the gaming machine via the external centralized terminal board 21 for the frame. The hall computer HC is an information processing device (computer device) that monitors game information from the main control board 20 and comprehensively manages the operating status of the gaming machines in the pachinko hall.

[0046] Furthermore, the main control board 20 is connected to a payout control board (payout control unit) 29, and when it is necessary to pay out prize balls, it is possible to send control commands related to payouts (payout control commands specifying the number of prize balls) to the payout control board 29.

[0047] The payout control board 29 is connected to a launch control board (launch control unit) 28 that controls the launching device 32 and a game ball payout device (game ball payout means) 19 that dispenses game balls. The main roles of this payout control board 29 are to receive payout control commands from the main control board 20, control the payout of prize balls by the game ball payout device 19 based on the payout control commands, and transmit status signals to the main control board 20.

[0048] The game ball dispensing device 19 is equipped with a supply shortage detection sensor 19a for detecting insufficient supply of game balls and a ball counting sensor 19b for detecting the number of game balls (prize balls) to be dispensed, and the dispensing control board 29 is capable of receiving these detection signals. The game ball dispensing device 19 is also equipped with a dispensing motor 19c for driving a ball dispensing mechanism (not shown) for dispensing game balls, and the dispensing control board 29 is capable of transmitting control signals to control the dispensing motor 19c.

[0049] Furthermore, the payout control board 29 is connected to a fullness detection sensor 60 (in this embodiment, a detection sensor that detects the storage state of game balls stored in the upper tray 9) which detects when the upper tray 9 is full of game balls, and a front door open sensor 61 (for example, a detection sensor that detects when the door 6 or inner frame 2 is open).

[0050] The payout control board 29 is capable of transmitting various status signals to the main control board 20 based on detection signals from the full-capacity detection sensor 60, the front door open sensor 61, the supply depletion detection sensor 19a, and the ball count sensor 19b. These status signals include a ball jam signal indicating a full-capacity state, a door open signal indicating that at least the inner frame 2 is open, a supply depletion signal indicating insufficient supply of game balls from the game ball payout device 19, a counting error signal indicating insufficient payout of prize balls or an abnormality in the ball count sensor 19b, and a payout completion signal indicating that the payout operation has been completed. The main control board 20 is configured to transmit a variety of status signals. Based on these status signals, the main control board 20 monitors the open state of the inner frame 2 (door open error), whether the payout operation of the game ball payout device 19 is normal or not (supply depletion error), and the full state of the upper tray 9 (ball jam error), etc.

[0051] Furthermore, a launch control board 28 is connected to the payout control board 29, and it is possible to send a permission signal to the launch control board 28 to allow launching. Based on the output of the permission signal from the payout control board 29, the launch control board 28 controls the power supply to the launch solenoid (not shown) provided on the launching device 32, thereby realizing the launching operation of the game ball by operating the launching operation handle 15. Specifically, the launching operation of the game ball is permitted under the following conditions: the payout control board 29 outputs a launch permission signal (launch permission signal ON state), a touch sensor provided on the launching operation handle 15 detects that the player is touching the handle, and the launch stop switch (not shown) provided on the launching operation handle 15 is not operated. Therefore, if the launch permission signal is not output (launch permission signal OFF state), the launching operation will not be performed even if the launching operation handle 15 is operated, and no game ball will be launched. In addition, the strength of the launch of the game ball can be changed according to the amount the launching operation handle 15 is operated. Furthermore, when the dispensing control board 29 detects the ball jam error, it sends a ball jam signal to the main control board 20 and stops outputting the launch permission signal to the launch control board 28 (launch permission signal OFF), and performs control to stop the launching operation until the upper tray 9 is cleared of its full state. Furthermore, the dispensing control board 29 outputs a launch permission signal to the launch control board 28 only when launch permission has been instructed by the main control board 20.

[0052] The main control board 20 is connected to a RAM clear switch 98, and is capable of receiving detection signals from these switches.

[0053] The RAM clear switch 98 is, for example, a push-button type switch used to input an instruction to initialize a predetermined area of ​​the main control RAM 20c.

[0054] The RAM clear switch 98 is turned ON / OFF in response to the operation of the RAM clear button, which is provided so that it can be operated when the inner frame 2 is open. The RAM clear switch 98 is located in an appropriate place inside the gaming machine 1. For example, it is placed on the main control board 20.

[0055] The main control board 20 is also connected to a performance indicator 97. The performance indicator 97 is configured, for example, with a 7-segment display and functions as a display means capable of displaying performance information (described later). The performance indicator 97 is mounted, for example, in an easily visible position on the main control board 20.

[0056] (Regarding performance specifications) The main control board 20 is capable of transmitting control signals to the performance indicator 97 to display predetermined performance information. Performance information refers to information that pachinko parlors and relevant government agencies want to verify. Typical examples include information on whether or not there are any fraudulent payout tactics such as excessive payouts on the gaming machine, and information on the machine's inherent payout performance. Therefore, unlike pre-announcement effects and other such information, performance information itself is not directly related to the progress of the game while the player is enjoying the game.

[0057] For this reason, the performance indicator 97 is installed inside the gaming machine 1, for example, on the main control board 20, payout control board 29, launch control board 28, the relay board, the performance control board 30, or on the board case (protective cover that protects the board), in a position where the display information can be seen when the inner frame 2 is open.

[0058] Here, the performance information can specifically include the following:

[0059] (1) Information based on the value obtained by dividing the total number of balls dispensed by winning during a specific state (total number of balls dispensed during the specific state: α) by the total number of balls that were ejected from the game area 3a during the specific state (number of balls ejected during the specific state: β) (α / β) (specific ratio information) can be adopted as performance information. The "total number of balls dispensed" mentioned above refers to the total number of game balls (prize balls) dispensed when a ball enters one of the prize winning slots (start slot 34, start slot 35, general prize slot 43, and big prize slot 50). In this embodiment, the number of balls dispensed is 3 for start slot 34 or start slot 35, 13 for big prize slot 50, and 10 for general prize slot 43. Furthermore, the specific state to be adopted can be appropriately determined depending on the performance information to be captured under what state. In this embodiment, any of the following states can be adopted: normal state, latent probability state, time-saving state, probability variation state, or during a big win game. In addition, multiple types of states may be measured. For example, the normal state and probability variation state, or all game states except during a win game, and the types to be measured can be appropriately determined. Furthermore, the period within a specific state may be defined as a period in which the probability of winning a jackpot is either low or high. Alternatively, the total number of payouts may be calculated by excluding one or more specific winning slots from the measurement (total payouts excluding specific winning slots). For example, the total number of payouts may be calculated by excluding the 50 major winning slots from the measurement.

[0060] (2) In addition, the total number of balls dispensed, the total number of balls dispensed excluding specific prize slots, or the total number of balls that go out may be measured, and the measurement results may be used as performance information.

[0061] In this embodiment, the total number of balls dispensed during normal operation (normal number of balls dispensed) and the total number of balls out during normal operation (normal number of balls out) are measured in real time, and the value obtained by dividing the normal number of balls dispensed by the normal number of balls out and multiplying the result by 100 (calculated as normal number of balls dispensed ÷ normal number of balls out × 100) is displayed as performance information (hereinafter referred to as "normal ratio information"). The displayed value in this case is rounded to the first decimal place. Therefore, data on the number of balls dispensed under normal conditions, the number of balls out under normal conditions, and the ratio information under normal conditions are stored in the corresponding areas of the main control RAM 20c (specific total prize ball storage area, specific ball out storage area, and specific ratio information storage area). However, instead of simply measuring and displaying performance information indefinitely, the measurement is terminated once the total number of balls out reaches a predetermined number (for example, 60,000 balls). This predetermined number is not the total number of balls out under normal conditions, but the total number of balls out during all game states (including during winning games) (hereinafter referred to as "total number of balls out under all conditions"). This total number of balls out under all conditions is also measured in real time and stored in the corresponding area of ​​the main control RAM 20c (total number of balls out under all conditions storage area). For the sake of explanation, the specific total prize ball storage area, specific ball out storage area, specific ratio information storage area, and total number of balls out under all conditions storage area will be abbreviated as "measurement information storage area" below.

[0062] Then, the normal ratio information at the end of the measurement is stored in a predetermined area (performance display storage area) of the main control RAM 20c (storing the current normal ratio information), and after that, the measurement information storage area (normal payout count, normal out count, and total out count) is cleared, and then measurement is started again (measurement of normal payout count, normal out count, normal ratio information, and total out count is started). The performance display unit 97 then displays the previous normal ratio information (measurement history information) and the normal ratio information currently being measured. Note that the system may be configured to display history not only for the previous information, but also for the time before last and the time before that (3 times ago), and the number of times back in time information to be displayed can be determined as appropriate.

[0063] (Performance control command) The main control board 20 is capable of transmitting various performance control commands, including information related to the special symbol variation display game and error information, to the performance control board 30, depending on the processing status. However, in order to prevent fraudulent activities such as cheating, the main control board 20 is configured for one-way communication, only transmitting signals to the performance control board 30 and not being able to receive signals from the performance control board 30.

[0064] Here, the performance control command defines its function using a two-byte configuration consisting of a one-byte mode and a one-byte event. To distinguish between MODE and EVENT, Bit 7 of MODE is set to ON and Bit 7 of EVENT is set to OFF. When this information is to be transmitted as valid, a strobe signal is output corresponding to each of the mode and event. That is, when the main control CPU 20a has a command to transmit, it sets and outputs mode information for transmitting the command to the performance control board 30, and transmits the first strobe signal after a predetermined time has elapsed since this setting. Furthermore, after a predetermined time has elapsed since the transmission of this strobe signal, it sets and outputs event information, and transmits the second strobe signal after a predetermined time has elapsed since this setting. The strobe signal is controlled to be active by the main control CPU 20a for a predetermined period to ensure that the performance control CPU 30a can reliably receive the command.

[0065] [2.2 Performance Control Board] The performance control board 30 is primarily composed of a microcomputer equipped with a microprocessor that incorporates a performance control CPU 30a, a performance control ROM 30b that stores performance data required for performance control processing, and a performance control RAM 30c that functions as a work area and buffer memory. In addition, it is equipped with an audio control unit (sound source IC), an RTC (Real Time Clock) function unit, a counter circuit, an interrupt controller circuit, a reset circuit, a WDT circuit, etc., to control the overall performance operation.

[0066] The performance control CPU 30a performs calculation processing for various performance operations and controls each performance means based on the performance control program and performance control commands received from the main control unit 20. In the case of the pachinko game machine 1 of this embodiment, the performance means are a liquid crystal display device 36 (main liquid crystal display device 36M, sub-liquid crystal display device 36S), an optical display device 45a, a sound generating device 46a, and a movable mechanism not shown in the figure.

[0067] The performance control ROM 30b stores the control program for performance operations performed by the performance control CPU 30a, as well as various data necessary for controlling performance operations. The performance control RAM 30c is used by the performance control CPU 30a as a work area for various calculation processes, a table data area, a buffer area for various input / output data and processing data, etc. The performance control board 30 is configured, for example, with a single-chip microcomputer and its peripheral circuits, but various configurations are possible for the performance control board 30. For example, in addition to the microcomputer, it may also include interface circuits to various parts, a random number generation circuit to generate random numbers for drawing for performances, a CTC for various time counting, a watchdog timer (WDT) circuit, and an interrupt controller circuit that provides interrupt signals to the performance control CPU 30a.

[0068] The main roles of this performance control board 30 are to receive performance control commands from the main control unit 20, to select and determine performances based on the performance control commands, to control the display of the liquid crystal display device 36 (supply of display data), to control the sound output of the sound generator 46a, to control the light emission of the light display device 45a (LED), and to control the operation of the movable mechanism (drive control of the movable mechanism motor 80c).

[0069] Since this performance control board 30 also functions as a control device for the liquid crystal display device 36, the performance control board 30 is equipped with functions as a so-called VDP (Video Display Processor), image ROM, and VRAM (Video RAM), and the performance control CPU 30a also functions as a liquid crystal control unit. VDP refers to a function that controls all aspects of video output processing, including image processing and image rendering. Image ROM refers to the memory where image data (animation image data) that the VDP uses for image processing is stored. VRAM is an image memory area that temporarily stores image data expanded by VDP.

[0070] Based on these configurations, the performance control board 30 generates various image data based on commands from the main control unit 20 and outputs it to the main liquid crystal display 36M and the sub-liquid crystal display 36S. As a result, various performance images are displayed on the main liquid crystal display 36M and the sub-liquid crystal display 36S. Here, the "liquid crystal display device 36" shown in Figure 2 is the "main liquid crystal display device 36M". The sub-liquid crystal display device 36S is not shown in Figure 2.

[0071] The performance control board 30 also has an acoustic control unit (for example, the sound controller 230 in Figure 4) for the sound generating device 46a which includes multiple speakers 46. The acoustic signal output by the acoustic control unit is amplified by the amplifier unit 46d and supplied to the speakers 46. Although the sound controller 230 is described as being built into the performance control board 30, the acoustic control unit may use a separate sound source IC. Furthermore, the performance control board 30 is connected to a lamp driver unit 45d, which functions as a light display control unit for the light display device 45a, including decorative lamps 45 and various LEDs, and a motor driver unit 80d (motor drive circuit), which functions as a drive control unit for the movable mechanism motor 80c that operates a movable body (not shown). The performance control board 30 issues instructions to these lamp driver unit 45d and motor driver unit 80d to control the light display operation of the light display device 45a and the operation of the movable mechanism motor 80c. For example, the performance control board 30 is equipped with a serial output circuit 30d that generates serial data to control the light display operation and the operation of the movable mechanism motor 80c and supplies it to the lamp driver unit 45d and motor driver unit 80d.

[0072] The performance control board 30 is also connected to an origin switch 81 and a position detection sensor 82 for monitoring the movement of the movable parts. The origin switch 81 is composed of, for example, a photointerrupter, and detects whether the movable mechanism motor 80c is in the origin position. The origin position is, for example, a position where the movable mechanism is not normally visible on the panel in Figure 2. The performance control board 30 is capable of determining whether the movable mechanism motor 80c is in the origin position based on the detection information from the origin switch 81. Furthermore, the performance control board 30 monitors the current operating position of the movable mechanism (for example, the amount of movement from the origin position) based on the detection information from the position detection sensor 82 and controls its operation. In addition, the performance control board 30 monitors for malfunctions in the operation of the movable mechanism based on the detection information from the position detection sensor 82, and if a malfunction occurs, it detects it as an error.

[0073] Furthermore, the performance control board 30 is connected to the switches for the performance buttons 13, the directional pad 15a, and the select button 15b, which are shown as the operation unit 17 in the figure. In other words, the operation detection switches for the performance buttons 13, the directional pad 15a, and the select button 15b are connected to the performance control board 30, and the performance control board 30 is capable of receiving operation detection signals from the performance buttons 13, the directional pad 15a, and the select button 15b, respectively.

[0074] Furthermore, the performance control board 30 is equipped with a handle sensor 83 (touch sensor) for detecting whether the firing operation handle 15 shown in Figure 1 is being touched by a user such as a player. Based on the detection information from this handle sensor 83, the performance control board 30 can determine whether or not the firing operation handle 15 is being touched by a user.

[0075] The performance control board 30, based on performance control commands sent from the main control unit 20, selects (determines) a performance pattern from a pre-prepared set of multiple types by lottery or uniquely, and controls various performance means at the necessary timing to produce the desired performance. This enables the display of performance images on the liquid crystal display device 36 corresponding to the performance pattern, the playback of sound from the speaker 46, and the operation of lighting and flashing decorative lamps 45 and LEDs. Various performance patterns (such as decorative pattern variation display operations and pre-announcement performances) unfold chronologically, realizing a "performance scenario" in a broad sense.

[0076] Here, regarding the performance control command, the performance control board 30 (performance control CPU 30a) generates an interrupt based on the input of the strobe signal transmitted by the main control unit 20 (main control CPU 20a) to receive and analyze it. Specifically, the performance control CPU 30a executes a control program for command reception interrupt processing based on the input of the strobe signal, and in the interrupt processing realized thereby, it acquires the performance control command and analyzes the command content. In this case, when an interrupt occurs based on the input of a strobe signal, the performance control CPU 30a interrupts the execution of an interrupt process based on another interrupt (a timer interrupt process that is executed periodically) and performs a command reception interrupt process, and even if other interrupts occur simultaneously, the command reception interrupt process is given priority.

[0077] <3. Overview of Operation> Next, we will explain the general operation of the gaming machine 1, which is realized by the control configuration described above (Figure 3).

[0078] [3.1 Game Status] In the gaming machine 1, in addition to the special game state of a jackpot game, multiple types of game states can be set. To facilitate understanding of this embodiment, the various game states will first be explained.

[0079] Game machine 1 proceeds in one of two game states, which is a combination of either a low probability state or a high probability state, and either a non-time-saving state or a time-saving state.

[0080] A low-probability state is a state where the probability of winning the jackpot lottery is relatively low, while a high-probability state is a state where the probability of winning the jackpot lottery is relatively high. In the non-shortened time state, it is relatively difficult for game balls to enter the starting opening 35, while in the shortened time state, it is relatively easy for game balls to enter the starting opening 35. For example, in the shortened time state, the opening time of the starting opening 35 when a regular symbol win is achieved is set to be longer than in the non-shortened time state. However, if it is easier for game balls to enter the starting opening 35 in the shortened time state than in the non-shortened time state, then in the shortened time state, for example, the probability of winning the regular symbol win lottery may be increased, or the variation time of the regular symbols may be shortened.

[0081] In this embodiment, "normal state" refers to the low-probability state and the non-time-saving state, and corresponds to the initial state.

[0082] [3.2 Symbol Variation Display Game] This explains the game that displays changing symbols.

[0083] (Special symbol variation display game) In the pachinko game machine 1 of this embodiment, a "jackpot lottery" is performed by random number generation on the main control board 20 based on predetermined starting conditions, specifically, when a game ball enters (wins) the starting port 34 or starting port 35. Based on the lottery result, the main control board 20 starts a special symbol variation display game by displaying special symbol 1 and special symbol 2 on the special symbol display devices 38a and 38b in a variable manner. After a predetermined time has elapsed, the result is displayed on the special symbol display device, thereby ending the special symbol variation display game.

[0084] In this embodiment, the jackpot lottery based on entry into the starting gate 34 and the jackpot lottery based on entry into the starting gate 35 are performed separately and independently. For this reason, the jackpot lottery result for the starting gate 34 is derived on the special symbol display device 38a side, and the jackpot lottery result for the starting gate 35 is derived on the special symbol display device 38b side. Specifically, on the special symbol display device 38a side, the first special symbol variation display game is started by displaying special symbol 1 in a variation manner when a game ball enters the starting gate 34, while on the special symbol display device 38b side, the second special symbol variation display game is started by displaying special symbol 2 in a variation manner when a game ball enters the starting gate 35. Then, when the special symbol variation display game is started on the special symbol display device 38a or the special symbol display device 38b, after a predetermined variation display time has elapsed, the special symbols that were being displayed in the variation display stop in a predetermined "jackpot" manner if the jackpot lottery result is "jackpot", or in a predetermined "miss" manner otherwise, and the game result (jackpot lottery result) is derived from this.

[0085] In this specification, for the sake of explanation, the first special symbol variation display game on the special symbol display device 38a side will be referred to as "Special Symbol Variation Display Game 1," and the second special symbol variation display game on the special symbol display device 38b side will be referred to as "Special Symbol Variation Display Game 2." Unless otherwise necessary, "Special Symbol 1" and "Special Symbol 2" will simply be referred to as "Special Symbol" (or abbreviated as "Special Symbol" in some cases), and "Special Symbol Variation Display Game 1" and "Special Symbol Variation Display Game 2" will simply be referred to as "Special Symbol Variation Display Game."

[0086] (A game where decorative patterns change) Furthermore, when the aforementioned special symbol variation display game is started, the decorative symbol variation display game is started by displaying decorative symbols (theatrical game symbols) in a variation manner on the main LCD display device 36M, and various effects are unfolded in conjunction with this. When the special symbol variation display game ends, the decorative symbol variation display game also ends, and a predetermined special symbol indicating the jackpot lottery result is displayed on the special symbol display device, and a decorative symbol reflecting the jackpot lottery result is displayed on the main LCD display device 36M. In other words, the theatrical decorative symbol variation display game, which includes the operation of displaying the variation of decorative symbols, reflects and displays the result of the special symbol variation display game.

[0087] Therefore, for example, if the result of the special symbol variation display game is a "jackpot" (if the jackpot lottery result is a "jackpot"), the decorative symbol variation display game will feature a performance that reflects that result. When the special symbol display device stops displaying a special symbol in a display mode indicating a jackpot (for example, the 7-segment display shows "7"), the main liquid crystal display device 36M stops displaying the decorative symbols in the "left," "center," and "right" display areas in a display mode that reflects a "jackpot" (for example, in the "left," "center," and "right" display areas, the three decorative symbols show "7," "7," and "7").

[0088] When a "jackpot" occurs, specifically, the special symbol variation display game ends, followed by the decorative symbol variation display game, and as a result, the "jackpot" symbol pattern is displayed. Then, the large prize slot solenoid 52c of the special variation prize device 52 activates, causing the opening door 52b to open and close in a predetermined pattern. This opens and closes the large prize slot 50, resulting in a special game state (jackpot game) that is more advantageous to the player than the normal game state. In this jackpot game, the opening door 52b keeps the large prize winning area open or expanded until a predetermined time (maximum opening time: for example, 29.8 seconds) has elapsed, or until the number of game balls that have entered the large prize winning area (the number of balls that have entered the large prize winning area 50) reaches a predetermined number (maximum number of balls that have entered: for example, 9 balls). Once either of these conditions is met, the large prize winning area is closed. This "round game" is repeated for a predetermined number of rounds (for example, a maximum of 16 rounds).

[0089] When the above-mentioned jackpot game begins, an opening sequence is played to announce that a jackpot has started. After the opening sequence ends, rounds of gameplay are played multiple times, up to a predetermined number of rounds. After the predetermined number of rounds is completed, an ending sequence is played to announce that the jackpot has ended, and the jackpot game concludes.

[0090] Regarding the information necessary to execute the above-mentioned decorative symbol variation display game, the main control board 20 first performs a jackpot lottery based on the fact that a game ball has entered (won) the start port 34 or start port 35, specifically, based on the fact that the game ball has been detected by the start port sensor 34a or start port sensor 35a and the start condition (start condition related to special symbols) has been met, which includes a 'win / lose lottery (win / lose type lottery)' to determine whether it is a "jackpot" or a "miss", and a 'symbol lottery (winning type (winning type) lottery)' to determine the type of jackpot if it is a "jackpot", and the type of miss if it is a "miss" (if there is only one type of miss, it is not necessary to perform a type lottery for the miss, so that lottery may be omitted), and based on the lottery result information, it determines the variation pattern of the special symbols and the special symbols to be displayed at the end according to the winning type (hereinafter referred to as "special stop symbols").

[0091] The main control board 20 then sends a "variation pattern specification command" to the performance control board 30 as a performance control command to identify the processing state, which includes at least information on the variation pattern of special symbols (for example, information on the jackpot lottery result and the variation time of the special symbols). This sends the basic information necessary for the decorative symbol variation display game to the performance control board 30. In this embodiment, in order to provide a wide variety of performances, a "decorative symbol specification command" including information on special stop symbols (symbol lottery result information (information on the type of win)) is also sent to the performance control board 30.

[0092] The variable pattern information of the special symbol can include information specifying the occurrence or non-occurrence of a specific pre-announcement effect (for example, the "reach effect" or "pseudo-consecutive effect" described later). Specifically, the variable pattern of the special symbol is broadly classified into a "winning variable pattern" in the case of a win and a "losing variable pattern" in the case of a loss according to the jackpot lottery result. These variable patterns include, for example, a "reach variable pattern" that specifies the occurrence of the reach effect described later, a "normal variable pattern" that does not specify the occurrence of the reach effect, a "pseudo-consecutive with reach variable pattern" that specifies the occurrence (duplicate occurrence) of the pseudo-consecutive effect and the reach effect, a "pseudo-consecutive with normal variable pattern" that specifies the occurrence of the pseudo-consecutive effect and does not specify the occurrence of the reach effect, and other multiple types of variable patterns. In view of ensuring the performance time of the reach effect and the pseudo-consecutive effect, usually, the variable patterns that specify the reach effect and the pseudo-consecutive effect are defined to have a longer variable time than the normal variable pattern.

[0093] Based on the information included in the effect control commands (here, the variable pattern specification command and the decorative symbol specification command) sent from the main control board 20, the effect control board 30 determines the effect content (effect scenario such as pre-announcement effect) to be developed in time series during the decorative symbol variable display game and the decorative symbol (decorative stop symbol) to be finally stopped and displayed, and variably displays the decorative symbol according to the time schedule based on the variable pattern of the special symbol to execute the decorative symbol variable display game. Thereby, in synchronization with the variable display of the special symbol by the special symbol display devices 38a and 38b, the decorative symbol is variably displayed by the main liquid crystal display device 36M, and the period of the special symbol variable display game and the period during the decorative symbol variable display game have substantially the same time width. Also, the effect control board 30 controls the main liquid crystal display device 36M, the light display device 45a, or the sound generation device 46a respectively so as to correspond to the effect scenario, and develops various effects in the decorative symbol variable display game. Thereby, the reproduction of the image (image effect) on the main liquid crystal display device 36M, the reproduction of the sound effect (sound effect), and the lighting and blinking drive of the decorative lamp 45, the LED, etc. (light effect) are realized.

[0094] Thus, the special symbol variation display game and the decorative symbol variation display game are inseparably related, and the results of the special symbol variation display game are reflected in the representations in the decorative symbol variation display game. Therefore, these two symbol variation display games can be considered equivalent symbol games. In this specification, unless otherwise necessary, the above two symbol variation display games may be simply referred to as "symbol variation display games."

[0095] (Normal symbol variation display game) In addition, in the gaming machine 1, based on the fact that a game ball has passed through (entered) the regular symbol starting opening 37, the main control board 20 performs an "auxiliary win lottery" using a random number lottery. Based on the result of this lottery, the regular symbols represented by LEDs are displayed in a variable manner on the composite display device 38d to start the regular symbol variable display game, and after a certain period of time has elapsed, the result is displayed by stopping the LEDs in a combination of lit and unlit states. For example, if the result of the regular symbol variable display game is an "auxiliary win", the regular symbol display section of the composite display device 38d is stopped and displayed in a specific lighting state (for example, both LEDs 39 are lit, or the LED representing "○" among the LEDs representing "○" and "×" is lit).

[0096] When this "auxiliary win" occurs, the standard electric mechanism solenoid 41c (see Figure 3) is activated, causing the movable blade to open and the starting opening 35 to open or enlarge, making it easier for game balls to flow in (starting opening open state), resulting in an auxiliary game state (hereinafter referred to as "standard electric opening game") that is more advantageous to the player than the normal game state. In this standard electric opening game, the starting opening 35 is opened or enlarged by the movable blade until a predetermined time (for example, 0.2 seconds) has elapsed or the number of game balls that have entered the starting opening 35 reaches a predetermined number (for example, 4 balls), and when either of these conditions is met, the starting opening 35 is closed. This operation is repeated a predetermined number of times (for example, up to 2 times).

[0097] (Regarding the hold) In this embodiment, during a special / decorative symbol variation display game, a normal symbol variation display game, a jackpot game, or a normal symbol starter game, if a ball enters the starter opening 34, starter opening 35, or normal symbol starter opening 37, that is, if a detection signal is received from the starter opening sensor 34a, starter opening sensor 35a, or normal symbol starter opening sensor 37a, and the corresponding start condition (symbol game start condition) is met, this is stored as data relating to the right to start the variation display game, up to a predetermined upper limit of the maximum number of reserved balls (for example, a maximum of 4), excluding those related to the variation display. Reserved data that is not used in the symbol variation display operation, or the game balls related to such reserved data, are also called "operated reserved balls." To make the number of these operated reserved balls clear to the player, a dedicated reserved ball indicator (not shown) is provided in an appropriate place on the game machine 1, or a reserved ball indicator provided as an icon image on the screen of the liquid crystal display device 36 (main liquid crystal display device 36M or sub-liquid crystal display device 36S) is lit up.

[0098] In this embodiment, up to four operational reserve balls for each of the special symbols 1, special symbol 2, and normal symbols are reserved and stored in the corresponding memory area of ​​the main control RAM 20c, and are reserved as the number of times the special symbol or normal symbol variation is confirmed. There is no particular limit on the maximum number of operational reserve balls that can be stored for each of the special symbols 1, special symbol 2, and normal symbols (maximum number of reserved balls). Furthermore, all or part of the maximum number of reserved balls for each symbol may be different, and the number can be appropriately determined according to the gameplay.

[0099] [3.3 Regarding the amount per unit] Next, we will explain what constitutes a "win" in gaming machine 1. In the gaming machine 1 of this embodiment, a jackpot lottery (winning lottery) is conducted for multiple types of wins. In this example, the types of wins include jackpots belonging to the jackpot types, such as "Normal 4R", "Normal 6R", "Probability Change 6R", and "Probability Change 10R". The "R" notation above indicates the number of rounds (maximum number of rounds).

[0100] The type of jackpot is the win that triggers the activation of the conditional device. Here, the "conditional device" refers to a device whose activation is a condition required for the continuous activation of the mechanism that allows for round play, and which is activated when a specific combination of special symbols is displayed or when a game ball passes through a specific area within the jackpot entry point.

[0101] The above-mentioned probability variation state is a so-called "count-limited probability variation machine (ST machine)" where, if the number of executions of the special symbol variation display game ends after a predetermined number of times (for example, 70 times: prescribed ST count) without winning a jackpot of any type, the high probability state ends and the machine transitions to a low probability state. When the prescribed ST count ends, the machine transitions to the normal state from the next game. However, it may also be a "general probability variation machine" that continues until the next jackpot is won.

[0102] Furthermore, the number of times the special symbol variation display game is executed may be the total number of executions of special symbol variation display game 1 and special symbol variation display game 2 (total number of variations for special symbol 1 and special symbol 2), or it may be the number of executions of either one (for example, the number of executions of special symbol variation display game 2). Also, the number of times the time-saving state is not limited to 60 or 100, but can be determined as appropriate according to the gameplay. In addition, there are no particular restrictions on the types of wins to be provided, and they can be determined as appropriate.

[0103] In this example, just like with the types of big wins, there are also multiple types of "misses." Specifically, there are three types of misses: "miss 1," "miss 2," and "miss 3." As mentioned above, if the result of the initial draw is a "loser," a draw for the losing type will be conducted in the subsequent design draw.

[0104] [3.4 Regarding the direction / staging] (Performance Mode) Next, the performance modes (performance states) will be explained. The gaming machine 1 of this embodiment is provided with multiple performance modes for displaying performances related to the game state, and is configured to allow switching between these performance modes. Specifically, there are normal performance modes, time-saving performance modes, hidden probability performance modes, and probability variation performance modes, corresponding to the normal state, time-saving state, hidden probability state, and probability variation state, respectively. In each performance mode, the background display, which serves as the background for the display screen of the changing decorative symbols, is displayed with different background performances, allowing the player to understand what game state they are currently in.

[0105] The performance control board 30 (performance control CPU 30a) has a function unit (performance state transition control means) that controls transitions between multiple types of performance modes. Based on specific performance control commands sent from the main control board 20 (main control CPU 20a), specifically performance control commands that include game state information managed on the main control board 20, the performance control board 30 (performance control CPU 30a) is configured to grasp the current game state in a manner consistent with the game state managed on the main control board 20 and to control transitions between multiple types of performance modes. Examples of such specific performance control commands include a variation pattern specification command, a decorative symbol specification command, and a game state specification command sent when a change occurs in the game state.

[0106] (Preview / Preview) Next, the pre-announcement effects will be explained. The effects control board 30 is configured to be able to control the appearance of various "pre-announcement effects" related to the current effects mode and the jackpot lottery result, based on the content of the effects control commands from the main control board 20, specifically, the variation pattern information included in at least the variation pattern specification command. Such pre-announcement effects suggest (predict) the expected probability of winning a jackpot type (hereinafter referred to as "winning probability") and act as "hype effects" to heighten the player's expectation of winning. Typical pre-announcement effects include "reach effects," "pseudo-consecutive effects," and "pre-read pre-announcement effects." The effects control board 30 functions as a pre-announcement effect control means capable of controlling the execution (appearance) of these effects.

[0107] A "reach animation" refers to an animation pattern that involves a reach state (a variation display pattern that involves a reach state: a reach variation pattern), and specifically refers to an animation pattern that leads to and displays the final game result via a reach state. Reach animations include multiple types of reach animations associated with the probability of winning. For example, there are some that have a relatively higher probability of winning compared to when a normal reach animation appears. Such reach animations are called "super reach animations." Many of these "super reaches" have a relatively longer animation time (variation time) than normal reaches in order to heighten the expectation of winning. Also, normal reaches and super reaches include multiple types of reach animations. In this example, super reaches include multiple types of reach animations called super reach 1, 2, 3, and 4, and the probability of winning for these super reaches 1 to 4 is given the relationship "super reach 1 < super reach 2 < super reach 3 < super reach 4".

[0108] "Pseudo-consecutive display" refers to a display method that involves a pseudo-continuous display state of decorative symbols (pseudo-consecutive display). "Pseudo-consecutive display" refers to a display method in which, during a game of displaying decorative symbols, some or all of the decorative symbols are temporarily stopped, and then the display operation of the decorative symbols is performed again from that temporarily stopped state, and this display operation is repeated once or multiple times. In this respect, it differs from the "pre-announcement display (continuous announcement display)" described later, which unfolds across multiple games of displaying symbols. The occurrence rate (appearance rate) of such "pseudo-consecutive" is basically set so that the probability of winning increases as the number of pseudo-displays increases. For example, depending on the number of pseudo-displays, displays that heighten the sense of anticipation, such as super reach, are more likely to be selected.

[0109] A "pre-announcement effect" (hereinafter sometimes abbreviated as "pre-announcement" or "pre-announcement effect") refers to an effect that, based on the result of a pre-announcement judgment, notifies the player of the possibility of being controlled to a favorable state before the change in the target symbol is displayed. A "favorable state" refers to a state that is advantageous to the player. Specifically, the pre-announcement effect in this example is performed in a manner that allows the player to be informed of the probability of winning before the activated reserved balls (unused activated reserved balls) are used in the symbol variation display game (special symbol variation display operation), mainly by utilizing the reserved ball display pattern and the background effects of the symbol variation display game that will be executed first. In addition to the "reach effect" mentioned above, various other effects such as the so-called "SU (step-up) notification effect," "timer notification effect," "revival effect," and "premium notification effect" occur in the symbol variation display game to enhance the game experience.

[0110] Now, referring to Figure 4, we will explain the "hold change notification effect" as an example of the above-mentioned pre-announcement effect. In the case of the gaming machine 1 of the present embodiment, in the upper display area within the screen of the main liquid crystal display device 36M, a display area (a display area for presenting a variable display effect or a preview effect of a decorative symbol) for presenting a decorative symbol variable display game is provided. Also, in the lower display area within the screen, a hold display area 76 (hold display units a1 to d1) for displaying the number of active hold balls on the special symbol 1 side and a hold display area 77 (hold display units a2 to d2) for displaying the number of active hold balls on the special symbol 2 side are provided. Regarding the presence or absence of active hold balls, that fact is notified by a predetermined hold display mode. In FIG. 5, an example is shown in which information regarding the current number of active hold balls is notified in a lit state (there is an active hold ball: the "○ (white circle mark)" shown in the figure) or an unlit state (there is no active hold ball: the broken-line circle mark shown in the figure).

[0111] The display (hold display) regarding the presence or absence of active hold balls is sequentially displayed in the order of their occurrence (winning order). In each hold display area 76, 77, the leftmost active hold ball is displayed as the active hold ball that occurred first (i.e., the oldest) on the time axis among all the active hold balls within the hold display. Also, on the left side of the hold display areas 76, 77, a variable display area 78 for indicating the active hold balls currently being used in the special symbol variable display game is provided. In the case of the present embodiment, the variable display area 78 is configured such that an image in which the icon of the in-game hold K currently being used in the game appears on the icon of the receiving seat J. That is, when the variable display of the special symbol 1 or the special symbol 2 is started, the icon (icon image) of the oldest hold a1 or a2 displayed in the hold display areas 76, 77 moves as the icon of the in-game hold K onto the icon of the receiving seat J in the variable display area 78, and that state is maintained for a predetermined display time.

[0112] When an active hold ball occurs, a "hold addition command" that specifies the prediction determination information related to the jackpot lottery result and the number of active hold balls at the time of prediction determination (including the currently generated active hold ball, the existing number of active hold balls) is transmitted from the main control board 20 to the effect control board 30 (see steps S1309 to S1312 in FIG. 28). In this embodiment, the hold-add command consists of two bytes: the upper byte data that allows for the identification of the number of balls to be held in operation at the time of the pre-read determination, and the lower byte data that allows for the identification of the pre-read determination information.

[0113] As can be understood from the above explanation, in this embodiment, based on the occurrence of a winning ball in the starting port 34 or starting port 35 and the creation of a new reserved ball, a jackpot lottery is performed for the symbol variation display game related to the reserved ball as a pre-read determination. As will be described later, the main control board 20 stores information representing the result of the jackpot lottery performed as such a pre-read determination in the corresponding memory area of ​​the main control RAM 20c. The information obtained during the pre-read determination of the jackpot lottery results is used to select (draw) a symbol variation pattern in the symbol variation display game, and can be rephrased as "variation pattern selection information." Therefore, it can be said that the main control board 20 performs a pre-read determination and stores the resulting "variation pattern selection information" in a predetermined area of ​​the main control RAM 20c.

[0114] When the performance control board 30 receives the above-mentioned hold addition command transmitted by the main control board 20, it performs performance control processing related to the "pre-announcement performance" as part of the display control processing related to the hold display, based on the pre-announcement judgment information contained therein. Specifically, it performs a "pre-announcement lottery" to determine whether or not the pre-announcement performance can be executed, and if it wins, it displays the pre-announcement performance.

[0115] Here, the pre-read judgment information specifically refers to game information obtained by the main control board 20 by pre-reading the jackpot lottery result (jackpot lottery result at the start of the variation) and the variation pattern at the start of the variation when the operating reserve ball is used in the symbol variation display game. In other words, this information includes at least information obtained by pre-reading the win / loss lottery result at the start of the variation (pre-read win / loss information), and can also include information obtained by pre-reading the symbol lottery result (pre-read symbol information) and information obtained by pre-reading the variation pattern at the start of the variation (pre-read variation pattern information). The information to be included in the reserve addition command sent to the performance control board 30 can be appropriately determined according to the content to be announced in the pre-read notification. In this example, the hold-add command is assumed to include pre-read win / loss information, pre-read symbol information, and pre-read variation pattern information.

[0116] Furthermore, the "pre-read variation pattern" obtained by the pre-read judgment when the activated reserve ball is generated does not necessarily have to be the same as the "variation pattern at the start of variation" obtained when the activated reserve ball is actually used for variation display operation. For example, if we take the case where the variation pattern at the start of variation is a variation pattern that specifies "Super Reach 1" as a representative example, in this case, the content specified by the pre-read variation pattern can be specified not as the type of reach effect "Super Reach 1" itself, but as the core "Super Reach type".

[0117] In this embodiment, if the pre-announcement lottery is won, a "hold display change type" pre-announcement effect (also referred to as "hold change announcement") is performed, in which the hold icon that is the target of the pre-announcement among the hold icons in the hold display units a1~d1 and a2~d2 may change from, for example, the white of the normal hold display (normal hold display mode) to the hold display with blue, green, red, danger pattern (or special colors or patterns such as rainbow) of the announcement display (special hold display mode). Figure 5 shows an example where the operating reserve ball in the hatched reserve display section b1 changes to a special reserve display. Here, the blue, green, red, and danger pattern of the reserve icons indicate increasing probability of winning, in that order. In particular, the danger pattern reserve icon is considered a premium reserve icon that indicates an extremely high probability of winning the jackpot.

[0118] (Direction means) Various effects in the gaming machine 1 are produced by effect means installed in the gaming machine 1. These effect means can be any stimulus transmission means that can produce an effect by appealing to human senses such as sight, hearing, and touch. Typical examples include light generating means such as decorative lamps 45 and LED devices (light display devices 45a: light effect means), sound generating devices such as speakers 46 (sound generating devices 46a: sound effect means), effect display devices (display means) such as the main liquid crystal display device 36M and the sub-liquid crystal display device 36S, pressure devices that transmit contact pressure to the operator's body, air pressure devices that apply air pressure to the player's body, and movable parts that produce a visual effect through their operation. Here, effect display devices are display devices that appeal to the sense of sight, just like image display devices, but they differ from image display devices in that they also include those that do not rely on images (for example, 7-segment displays). When referred to as image display devices, it mainly refers to types that produce effects by displaying images, and those that produce effects using means other than images, such as 7-segment displays, are included in the above concept of effect display devices.

[0119] <4. Opening / closing structure and circuit board arrangement> The configuration shown in Figure 3 above is actually realized through multiple circuit boards. Below, we will describe the arrangement of some of the circuit boards installed in the gaming machine 1. We will also explain the opening and closing structure of the gaming machine 1 in relation to the mounting positions of the circuit boards.

[0120] Figure 5 shows the door 6 in the open position. When door 6 is opened, the inner frame 2 and the game board 3 mounted on the inner frame 2 are directly exposed. Furthermore, the circuit board located on door 6 and the circuit board located on inner frame 2 are connected by a harness acting as transmission line H8.

[0121] Furthermore, the gaming machine 1 is configured so that the inner frame 2 can be opened relative to the outer frame 4. Figure 6 shows the inner frame 2 in the open position. When the inner frame 2 is opened, the game board 3 attached to the inner frame 2 is also freed from the outer frame 4. Figure 6 shows the back cover 18 attached to the back side of the game board 3. The game board 3 is not shown in Figure 6, but when the back cover 18 is removed (opened), the back side of the game board 3 is exposed. In reality, because the back cover 18 is transparent or semi-transparent, the back side of the game board 3 is visible in the state shown in Figure 6. Furthermore, the game board 3 can be removed from the inner frame 2.

[0122] Thus, the gaming machine 1 is broadly composed of an outer frame 4, an inner frame 2 attached to the outer frame 4, a game board 3 attached to the inner frame 2, and a door 6 located on the front side of the game board 3 and the inner frame 2. Various circuit boards are attached to either the game board 3, the inner frame 2, or the door 6.

[0123] Figure 7 shows the positions of some of the circuit boards that are attached to the game board 3. Note that Figure 7 shows the circuit boards mounted on the back of the game area 3a, as viewed from the rear of the game board 3. Therefore, the right side of the figure corresponds to the left side when the game board 3 is viewed from the front. For reference, the outline of the game board 3 frame is shown with a dashed line in the figure.

[0124] As shown in the diagram, on the back of the game board 3, the performance control board 30 is positioned slightly above the center, and the main control board 20 is positioned below it. The LCD control board 901 is positioned so as to overlap with the performance control board 30, and the ROM board 902 and LCD interface board 903 are positioned nearby.

[0125] On the left side of the back of the game board 3, the LED connection board 700 is located, and the power module board 904 is located near its upper part. Additionally, the upper connection board 905 is positioned above the game board 3.

[0126] Near the main control board 20, relay boards 800, frame LED relay board 840, power supply relay board 40, game board connection board 906, etc. are arranged. Although not shown in the diagram, there is also a circuit board that is mounted on a movable mechanism (not shown) attached to the game board 3.

[0127] Figure 8 shows the positions of some of the circuit boards attached to the door 6, as viewed from the front of the gaming machine 1. For reference, the door 6, the effect button 13, the firing operation handle 15, and the upper speaker 46 are indicated by dashed lines as part of the internal configuration of the gaming machine 1.

[0128] A relay board 550 is installed above door 6. Similarly, an upper LED board 630 for the side unit is provided above the door 6, an upper right LED board 600 for the side unit is provided above the upper right of the door 6, and a lower right LED board 620 for the side unit is provided below it. These upper right LED board 600, lower right LED board 620, and upper LED board 630 for the side unit are mounted inside the side unit 10 (see Figure 1), and each board is positioned as shown in Figure 8 when the side unit 10 is attached to the door 6.

[0129] The left-side LED board 907 is located at the upper left of door 6, and the lower-left LED board 908 is located below it. Furthermore, the front frame LED connection board 500 is positioned below door 6. Additionally, a button LED connection board 640 is located in the lower right, and a button LED board 660 is placed inside the performance button 13.

[0130] Next, the position of the circuit board to be attached to the inner frame 2 will be explained. Figure 9 is a view of the gaming machine 1 from the rear. The rear side of the gaming machine 1 is mostly protected by a transparent or translucent rear cover 18. The power supply board 300 and the dispensing control board 29 are positioned front to back on the lower rear side. Additionally, the inner frame LED relay board 400 is mounted on the lower right side when viewed from the rear.

[0131] Figure 10 shows the placement of various devices on the door 6 and the game board 3. The outlines of the game board 3 and door 6 are shown with dashed lines to give a general idea of ​​the location of each device.

[0132] In Figure 10, the devices installed inside the side unit 10 of the door 6 are the side unit device 101, the side unit lower right movable position detection switch 102, the side unit lower right movable motor 103, the side unit upper right movable motor 104, the side unit upper right movable solenoid 105, the blower 106, and the photocouplers PC1F, PC2F, and PC3F, which are arranged in the positions shown in the figure. The photocouplers PC1F, PC2F, and PC3F are attached to the side unit lower right LED board 620.

[0133] Furthermore, in Figure 10, the devices attached to the game board 3 include a lower-rear movable upper position detection switch 120, a lower-rear movable right position detection switch 121, a distribution position detection switch 122, a lower-front movable position detection switch 123, a lower-front movable motor 124, a lower-rear movable left position detection switch 125, a lower-rear movable left motor 126, a lower-rear movable lower-right position detection switch 127, a lower-rear movable lower-left position detection switch 128, an upper movable left motor 129, an upper movable left position detection switch 130, a left movable motor 131, an upper movable position detection switch 132, an upper movable right motor 133, a left movable position detection switch 134, and a lower-rear movable right motor 135, each positioned as shown in the figure.

[0134] Furthermore, the circuit boards shown in Figures 7, 8, and 9 represent only a portion of the circuit boards installed in the gaming machine 1. Similarly, the device shown in Figure 10 represents only a portion of the devices installed in the gaming machine 1.

[0135] <5. Circuit board configuration> [5.1 Connection status of each board] The connection configuration of each circuit board, as described above, will be explained, along with the power supply voltage path.

[0136] Figure 11 shows an example of circuit boards to be placed in the game board 3, inner frame 2, and door 6, respectively. The diagram shows the following circuit boards mounted on the game board 3: main control board 20, performance control board 30, power relay board 40, relay board 800, decorative board 820, frame LED relay board 840, LED board 850, and LED board 860. The circuit boards mounted in the inner frame 2 include the power supply board 300, the payout control board 29, and the inner frame LED relay board 400. The circuit boards mounted on door 6 include the front frame LED connection board 500, the relay board 550, the upper right LED board 600 of the side unit, the lower right LED board 620 of the side unit, the upper LED board 630 of the side unit, the button LED connection board 640, and the button LED board 660.

[0137] Each of these circuit boards is part of the circuit boards installed in the gaming machine 1. In addition to those shown, there are various other circuit boards installed in the gaming board 3, inner frame 2, and door 6. Figure 11 shows the connection system of the circuit boards extracted for use in explaining the technology as an embodiment, and does not show all circuit boards.

[0138] The power supply board 300 is the board that supplies the DC voltage that serves as the operating power to each component based on the AC input power. The main control board 20, the performance control board 30, and the payout control board 29 are as described in Figure 3.

[0139] The front frame LED connection board 500 is a board for supplying control signals and power supply voltage to the LEDs, movable motors, solenoids, blowers, and other performance elements provided on the door 6.

[0140] The LED board 600 on the upper right of the side unit, the LED board 620 on the lower right of the side unit, and the LED board 630 on the top of the side unit are boards located inside the side unit 10 and constitute the drive control system for the modes of the LEDs and movable parts. These boards also constitute a detection system that transmits detection signals from the motor position sensor, touch sensor, and various other sensors to the performance control board 30. As described above, a side unit 10 is attached to the door 6 as one of the decorative units, and the side unit 10 is detachable and replaceable from the door 6. The LED board 600 on the upper right of the side unit, the LED board 620 on the lower right of the side unit, and the LED board 630 on the top of the side unit are detachable together with the side unit 10. With the side unit 10 installed and the transmission line H10 connecting the relay board 550 and the LED board 600 on the upper right of the side unit, the electrical configuration is as shown in Figure 11.

[0141] The button LED board 660 comprises the LEDs and their light-emitting drive system within the performance button 13, and also includes a circuit for transferring detection signals from various detection sensors. The button LED connection board 640 relays control signals and power supply voltage to the button LED board 660, and also transfers detection signals from various sensors.

[0142] The inner frame LED relay board 400 relays signals between the frame LED relay board 840, which is connected to the performance control board 30, and the front frame LED connection board 500, performs necessary signal processing, and also generates and supplies power voltage. The frame LED relay board 840 relays the signal path between the inner frame LED relay board 400 and the performance control board 30.

[0143] The decorative board 820, LED boards 850, and 860 are equipped with LEDs on the game board 3 and are responsible for their illumination. The relay board 800 relays the LED illumination drive signals. In addition to those shown, several other LED boards are mounted on the game board 3. Some of these LED boards are attached to movable parts. For example, the relay board 800 and decorative board 820 are attached to movable parts. The decorative board 820 also has a circuit for supplying motor drive signals to the motor of the movable part, for example.

[0144] The LED connection board 700 performs various necessary signal processing for driving the light emission of performance elements such as LEDs and motors based on control signals from the performance control board 30.

[0145] These boards are electrically connected by transmission lines H consisting of harnesses and cables. "Transmission lines H" is a collective term for the transmission lines H1, H2, ... H41 shown in the diagram. Each transmission line H generally consists of individual wiring paths that transmit signals, power supply voltages, etc., and connectors connected to both ends thereof. In each transmission line H, when distinguishing the individual wiring paths that transmit signals, power voltages, etc., i.e., the wire portions, from the connectors, they are simply called "lines."

[0146] A transmission line H refers to a collection of one or more transmission lines. The transmission line H includes various forms such as flexible harnesses, flexible circuit boards, and wire harnesses. Furthermore, the transmission line H may consist of multiple lines integrated together, or individual lines bundled together with binders, tapes, etc. Furthermore, when connectors are directly connected to each other, the terminals of each connector become transmission line H. In other words, even when there are no wires such as harnesses, they are included in "transmission line H". In other words, transmission line H does not refer to a specific type or shape, but rather broadly refers to anything that forms electrical wiring between circuit boards, etc.

[0147] The power supply board 300 and the dispensing control board 29 are connected by a transmission line H1. Furthermore, the power supply board 300 and the inner frame LED relay board 400 are connected by transmission line H3. These transmission lines H1 and H3 will consist of harnesses and other components installed within the inner frame 2.

[0148] The power supply board 300 and the power supply relay board 40 are connected by transmission line H2, and the power supply relay board 40 and the performance control board 30 are connected by transmission line H18. The dispensing control board 29 and the main control board 20 are connected by a transmission line H4. The inner frame LED relay board 400 and the frame LED relay board 840 are connected by transmission line H7. Transmission lines H2, H4, and H7 are connected by harnesses or similar devices that span across the space between the inner frame 2 and the game board 3.

[0149] The main control board 20 and the performance control board 30 are connected by a transmission line H5. The performance control board 30 and the frame LED relay board 840 are connected by a transmission line H6. The performance control board 30 and the LED connection board 700 are connected by the transmission line H20. The LED connection board 700 and the relay board 800 are connected by the transmission line H30. The relay board 800 and the decorative board 820 are connected by the transmission line H31. LED connection board 700 and LED board 850 are connected by transmission line H40. LED connection board 700 and LED board 860 are connected by transmission line H41. These transmission lines H5, H6, H18, H20, H30, H31, H40, and H41 are provided by harnesses installed within the game board 3.

[0150] The inner frame LED relay board 400 and the front frame LED connection board 500 are connected by transmission line H8. This transmission line H8 will be connected by a harness or similar device that spans across the space between the inner frame 2 and the door 6.

[0151] The front frame LED connection board 500 and the relay board 550 are connected by the transmission line H9. The relay board 550 and the LED board 600 on the upper right of the side unit are connected by the transmission line H10. The LED board 600 on the upper right of the side unit and the LED board 620 on the lower right of the side unit are connected by transmission line H11. The LED board 600 on the upper right of the side unit and the LED board 630 on the top of the side unit are connected by transmission line H12. The front frame LED connection board 500 and the button LED connection board 640 are connected by transmission line H15. The button LED connection board 640 and the button LED board 660 are connected by transmission line H16. These transmission lines H9, H10, H11, H12, H15, and H16 will be provided by harnesses and the like, which will be installed inside door 6.

[0152] Between these circuit boards, the transmission lines described above are used to transmit control signals for effects such as LED illumination, the operation of movable parts by motors, and sound output, as well as sensor signals for controlling the effects, and even the power supply voltage.

[0153] In Figure 11, the serial output circuit 30d of the performance control board 30 is shown, which outputs light-emitting drive data as serial data, mainly for the purpose of performing LED light-emitting operations. Earlier, in Figure 3, we mentioned that the performance control board 30 generates serial data to control the operation of the light display and the movable part motor 80c, and supplies it to the lamp driver unit 45d and the motor driver unit 80d via the serial output circuit 30d. In Figure 11, this means that the serial output circuit 30d outputs two sets of serial data via transmission lines H20 and H6.

[0154] The serial output circuit 30d outputs drive data for effects to the LED connection board 700 via the transmission line H20, which is then supplied to the circuit board in the game board 3. The drive data for effects includes light drive data for controlling LED illumination and motor drive data for the operation of motors for movable parts and other components. Furthermore, the serial output circuit 30d outputs drive data for the effects, which is supplied to the circuit boards in the inner frame 2 and door 6 via the transmission line H6, to the frame LED relay board 840. In this way, the performance control board 30 outputs drive data via serial data, broadly divided into drive data to the game board 3 and drive data to the frame and door side.

[0155] The power supply board 300 shown in Figure 11 will be described below. The power supply board 300 supplies power voltage to each part via transmission lines H1, H2, and H3. Figure 12 shows the power supply input / output for the power supply board 300. The power supply board 300 is equipped with connectors CN1A to CN7A. Connectors CN5A, CN6A, and CN7A are the transmission line ends of transmission lines H40, H41, and H42, which are not shown in Figure 11.

[0156] Hereafter, connectors CN1A to CN7A, as well as any other connectors shown in other diagrams, will be collectively referred to as "connector CN". In this specification, "connector CN" refers to a connector terminal component provided on a circuit board. The connector CN formed at the end of a transmission line H may be referred to as the "transmission line end." In this case, the connector CN is generally formed by a socket housing side fixed to the circuit board and a contact housing side joined to the socket housing, and these socket housing and contact housing are collectively referred to as the "transmission line end."

[0157] The 3-terminal connector CN5A receives AC24V power from the power plug 301 of the gaming machine 1 via the transmission line H40 (AC-IN(A), AC-IN(B)). Furthermore, a frame ground (FG) path is formed via the ground terminal 302, transmission line H40, and connector CN5A. The ground terminal 302 is connected, for example, to the outside of the gaming machine body.

[0158] A transmission line H41 is connected to the two-terminal connector CN6A, forming an FG path (FG-1) via ground terminals 303 and 304. Ground terminals 303 and 304 are connected, for example, to a sheet metal portion of the gaming machine 1 that does not come into contact with the game balls. The 2-terminal connector CN7A is connected to the transmission line H42, and an FG path (FG-2) is formed via the ground terminals 305 and 306. The ground terminals 305 and 306 are connected to, for example, the sheet metal parts in the gaming machine 1 that come into contact with the game balls, such as the ball tank, the sheet metal of the upper tray, and the launch rail. This is intended to separate low-noise grounds from high-noise grounds.

[0159] On the power supply board, the AC24V power supply is input to the AC / DC converter 311, and an internal DC voltage V1 with a predetermined voltage value is output. The internal DC voltage V1 is then input to the DC / DC converter 312, which generates a 5V DC voltage (DC5V) as the output. Furthermore, the internal DC voltage V1 is input to the DC / DC converter 313, which generates a 12V DC voltage (DC12V) as its output. Furthermore, the internal DC voltage V1 is input to the DC / DC converter 314, which generates a 35V DC voltage (DC35V) as the output.

[0160] These generated 5V DC voltages (DC5V), 12V DC voltages (DC12V), and 35V DC voltages (DC35V) are then supplied to each component through connectors CN1A, CN2A, and CN3A. Specifically, it outputs a 5V DC voltage (DC5VA) (DC5VB) based on a 5V DC voltage (DC5V), a 12V DC voltage (DC12VA) (DC12VB) based on a 12V DC voltage (DC12V), and a 35V DC voltage (DC35VA) (DC35VB) based on a 35V DC voltage (DC35V).

[0161] The transmission line H1-1 is connected to the 14-terminal connector CN1A. The transmission line H1-1 is also connected to the 3-terminal connector CN4A. These two transmission lines H1-1 and H1-2, which function as harnesses, are shown as transmission line H1 in Figure 11 above. Transmission line H1-1 supplies 35V DC voltage (DC35VA), 12V DC voltage (DC12VA), and 5V DC voltage (DC5VA) to the dispensing control board 29, and also forms a ground path (GND). A 24V AC voltage (AC24VA, AC24VB) is supplied to the dispensing control board 29 via the transmission line H1-2, and an FG path (FG) is also formed.

[0162] The main control board 20 is supplied with 35V DC voltage (DC35VA), 12V DC voltage (DC12VA), and 5V DC voltage (DC5VA) via the dispensing control board 29, and a ground path (GND) is also formed.

[0163] The transmission line H2 is connected to the 20-pin connector CN2A. Transmission line H2 supplies 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), and 35V DC voltage (DC35VB) to the performance control board 30 via the power relay board 40, and also forms a ground path (GND).

[0164] Based on the power supply via this transmission line H2, 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), and 35V DC voltage (DC35VB) are supplied from the performance control board 30 to the LED connection board 700, and are used as operating power for the LED connection board 700 and each downstream board (relay board 800, decorative board 820, LED boards 850, 860, etc.). On the other hand, the frame LED relay board 840 is simply a board with relay wiring and does not require a power supply voltage; therefore, it is not supplied with a power supply voltage from the performance control board 30.

[0165] For the sake of explanation, the expressions "upstream" and "downstream" are used. Regarding data and control signals, the main control board 20 is the most upstream, followed by the effect control board 30, and it is considered "downstream" from the effect control board 30 towards the actual effect devices such as LEDs and motors. Regarding the power supply voltage, the power supply board 300 is the most upstream, and it is considered "downstream" towards the actual effect devices.

[0166] The transmission line H3 is connected to the 6-terminal connector CN3A. A 12V DC voltage (DC12VB) is supplied to the inner frame LED relay board 400 through the transmission line H3, and a ground path (GND) is formed. That is, the inner frame LED relay board 400 is a board controlled by the effect control board 30, but it is configured to receive a direct power supply voltage from the power supply board 300. Each board (such as the front frame LED connection board 500, etc.) provided on the door 6 downstream of the inner frame LED relay board 400 receives a power supply voltage from the inner frame LED relay board 400.

[0167] The components mounted on the power supply board 300 are schematically shown in Fig. 13. The connectors CN1A to CN7A shown in Fig. 12 are respectively arranged near the edges of the substantially rectangular board. Also, electrolytic capacitors C106, C201, C202, C203, C501, C502, C601, C701, C801, transformers L1A, coils L201, L501, L601, L701, L801, etc. are respectively arranged. Also, IC chips 201A, 202A, 501A, switches SW1, etc. are arranged. The IC chip 201A is a power factor correction circuit, the IC chip 202A is a full-wave rectification circuit, and the IC chip 501A is a DC / DC converter. Only some of the electronic components are mentioned above, and these are insertion-mounted components that insert lead wires into through-hole vias for mounting.

[0168] In addition, tubular fuses, such as glass tube type fuses FZ1A, FZ301, and FZ401, are arranged, and lead wires are inserted into through-hole vias and fixed as terminal insertion type, but lead wire type fuses FV501, FZ601, and FZ701 are also arranged. As for the tubular fuses, for example, there are those with a structure in which a fuse cartridge having a fuse element provided in a glass tube is held by a fuse holder fixed to a substrate, those with a structure in which a mounting portion connected to the base of the glass tube is fixed to the substrate with bolts, those with lead wires provided on the base of the glass tube and the lead wires are inserted into through-hole vias and soldered and fixed, etc. There are also those with a ceramic tube instead of a glass tube.

[0169] The terminal insertion type fuse is a fuse in which connection terminals are provided in a high heat-resistant exterior resin. In addition, those with lead wires provided on the base of the glass tube as described above can be said to be both tubular fuses and terminal insertion type fuses.

[0170] Generally, tubular and terminal insertion type fuses are used in places where the fuse current value is higher than that of chip type and surface mount type fuses, and the component size is also larger than that of chip type.

[0171] Although detailed description is omitted, surface mount components such as resistors and capacitors are also mounted on the surface layer shown in FIG. 13 and the back surface layer not shown.

[0172] [5.2 Transmission Path between Performance Control Substrate and LED Connection Substrate] Hereinafter, focusing on the transmission line H20 between the performance control substrate 30 and the LED connection substrate 700, a single-system transmission example and a multi-system transmission example will be described as the configuration of the transmission path.

[0173] First, the single-system transmission example will be described with reference to FIG. 14. The single-system transmission example is an example in which the transmission line H20 between the performance control substrate 30 and the LED connection substrate 700 is configured by a pair of connectors. Figure 14 shows examples of pin assignments for connector CNe1 on the performance control board 30 and connector CN1 on the LED connection board 700.

[0174] In this embodiment, the pins of the connector CN are considered to be approximately cylindrical, but other terminal shapes for the connector CN are also considered. In the case of approximately cylindrical pins, the cross-sectional size of the pin refers to the diameter of the pin, but if we also consider plate-shaped pins, elliptical pins, etc., the cross-sectional size of the pin can be considered to be the longest possible size of the pin's cross-section. Alternatively, since the pin cross-section affects the current capacity, the pin cross-sectional size can be considered as the area of ​​the cross-section.

[0175] Connectors CNe1 and CN1 are 40-pin connectors. Each of the 40 pins corresponds to a corresponding line, through which various signals are transmitted.

[0176] As shown in Figure 14, a total of 16 pins, pins 1, 2, 8, 9, 10, 16, 18, 19, 20, 22, 29, 32, 33, 34, 39, and 40, are assigned to ground (GND).

[0177] Pins 12, 14, 24, 26, 28, and 30 (a total of 6 pins) are assigned to the first power supply voltage, which is a 12V DC voltage (DC12VB). The 4th and 6th pins, a total of two pins, are assigned to the second power supply voltage, which is a 5V DC voltage (DC5VB). Pins 36 and 38, a total of two pins, are assigned to the third power supply voltage, which is a 35V DC voltage (DC35VB).

[0178] Furthermore, various performance control signals are transmitted through transmission line H20. "Performance control signals" refer to various signals used to operate the performance mechanisms, including, for example, light emission control signals for illuminating the LEDs of the performance mechanisms, motor drive control signals for driving the motors of the movable parts of the performance mechanisms, and drive control signals for driving blowers and vibration devices. In addition, signals transmitted to the performance control board 30 for performance control, such as detection signals from various sensors related to the performance, such as the origin sensor for the movable parts and sensors for detecting user operations, or signals that are serial data versions of detection signals, are also included in the performance control signals. This is because the performance control board determines the game state based on these detection signals and performs performance control.

[0179] These performance control signals are often transmitted as a set of multiple signals for a specific purpose in controlling the performance. For example, a set of light emission control signals, which is a type of performance control signal, may consist of a serial data light emission control data signal and a clock signal, or it may also include enable signals and reset signals in addition to these to form a single set.

[0180] In the example shown in Figure 14, four sets of signals are transmitted as performance control signals. The first set consists of the clock signal LED_CLK, the data signal LED_DATA, and the enable signal LED_ENABLE. The clock signal LED_CLK is assigned to pin 13, the data signal LED_DATA to pin 15, and the enable signal LED_ENABLE to pin 17.

[0181] The clock signal LED_CLK, data signal LED_DATA, and enable signal LED_ENABLE are performance control signals (light emission control signals) supplied to the LED connection board 700 and LED drivers on downstream boards. The data signal LED_DATA is a serial data signal for controlling the light emission brightness of LEDs connected to downstream LED drivers after the LED connection board 700 using PWM control.

[0182] The second set consists of the clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST. The clock signal LSI_CLK is assigned to pin 3, the serial data signal LSI_IN_DATA to pin 5, the enable signal LSI_ENABLE to pin 7, the data signal LSI_DATA to pin 35, and the reset signal LSI_RST to pin 37.

[0183] The clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST are the display control signals (motor drive control signals) supplied to the motor control IC on the LED connection board 700. The data signal LSI_DATA is a serial data signal containing control data for motor control. Furthermore, the IC for motor control is equipped with a function to convert various detection signals into serial data, which can be transmitted to the upstream performance control board 30 as the serial data signal LSI_IN_DATA.

[0184] The third set consists of the clear signal CLR_X, the data signal DATA_X, and the latch signal LATCH_X. The clear signal CLR_X is assigned to pin 21, the data signal DATA_X to pin 25, and the latch signal LATCH_X to pin 27. These clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X are considered unused signals in the configuration example of the LED connection board 700 described later. However, they can be used as performance control signals when using the performance control board 30 due to a change in model or other reasons.

[0185] As the fourth group, there is a set consisting of a load signal S_IN_LOAD, a clock signal S_IN_CLK, and a serial data signal S_IN_DATA. The load signal S_IN_LOAD is assigned to the 11th pin, the clock signal S_IN_CLK is assigned to the 23rd pin, and the serial data signal S_IN_DATA is assigned to the 31st pin, respectively. The LED connection board 700 includes a parallel / serial conversion circuit (P / S conversion circuit) and has a function of serializing various detection signals input in parallel. The P / S conversion circuit performs P / S conversion processing based on the load signal S_IN_LOAD and the clock signal S_IN_CLK supplied from the effect control board 30 to the LED connection board 700, and outputs a plurality of detection signals as a serial data signal S_IN_DATA. This serial data signal S_IN_DATA is transmitted to the upstream effect control board 30.

[0186] The above pin assignment is an example. For example, in the case of a single-system transmission example, as described above, each of various power supply voltages, grounds, and effect control signals is transmitted by a pair of connectors CNe1, CN1 and the line therebetween.

[0187] Next, a multi-system transmission example will be described. The multi-system transmission example is an example in which transmission lines H20a and H20b between the effect control board 30 and the LED connection board 700 are formed by two pairs of connectors. The transmission lines H20a and H20b replace the transmission line H20.

[0188] FIG. 15 shows an example of pin assignment for two connectors CNe1a and CNe1b mounted on the effect control board 30 and two connectors CN1a and CN1b mounted on the LED connection board 700. Between the effect control board 30 and the LED connection board 700, these two pairs of connectors are connected to form two transmission lines H20a and H20b. That is, the transmission line grouped in the single-system transmission example is divided into two.

[0189] In this case, for example, the transmission line H20a of connectors CNe1a, CN1a has a 16-pin configuration and 16 lines. Therefore, the transmission line H20b of connectors CNe1b, CN1b has a 24-pin configuration and 24 lines. This forms 40 lines, equivalent to the single-system transmission example.

[0190] The pin assignment for connector CNe1a,CN1a is as follows: a total of 7 pins, pins 1, 2, 4, 6, 8, 9, and 10, are assigned to ground (GND).

[0191] Additionally, the six pins from pin 11 to pin 16 are assigned to the first power supply voltage, which is a 12V DC voltage (DC12VB).

[0192] Furthermore, of the aforementioned control signals, the first set of signals—the clock signal LED_CLK, the data signal LED_DATA, and the enable signal LED_ENABLE—are transmitted on the connector CNe1a,CN1a side. The clock signal LED_CLK is assigned to pin 3, the data signal LED_DATA to pin 5, and the enable signal LED_ENABLE to pin 7.

[0193] The pin assignment for connector CNe1b,CN1b is as follows: a total of 8 pins, pins 5, 8, 10, 12, 14, 16, 17, and 18, are assigned to ground (GND).

[0194] Additionally, the first and third pins (a total of two pins) are assigned to the second power supply voltage, which is a 5V DC voltage (DC5VB). Additionally, the 2nd, 4th, and 6th pins (a total of 3 pins) are assigned to the third power supply voltage, which is a 35V DC voltage (DC35VB).

[0195] Furthermore, of the aforementioned performance control signals, the second, third, and fourth sets are transmitted on the connector CNe1b, CN1b side.

[0196] For the second set of control signals, the clock signal LSI_CLK is assigned to pin 7, the serial data signal LSI_IN_DATA to pin 9, the enable signal LSI_ENABLE to pin 11, the data signal LSI_DATA to pin 13, and the reset signal LSI_RST to pin 15.

[0197] For the third set of performance control signals, the clear signal CLR_X is assigned to pin 20, the data signal DATA_X to pin 22, and the latch signal LATCH_X to pin 24.

[0198] For the fourth set of performance control signals, the load signal S_IN_LOAD is assigned to pin 19, the clock signal S_IN_CLK to pin 21, and the serial data signal S_IN_DATA to pin 23.

[0199] For the sake of clarity, in the example of dual transmission, the transmission line H20a side with connectors CNe1a, CN1a as the transmission line ends will be referred to as "system a," and the transmission line H20b side with connectors CNe1b, CN1b as the transmission line ends will be referred to as "system b."

[0200] In the single-channel transmission example, connectors CNe1 and CN1 can use a 40-pin connector with two rows, as described later in Figure 27. In the example of dual transmission, the connectors CNe1a, CN1a of system a can use connectors with a 16-pin configuration in two rows, as will be described later in Figure 28. In the example of dual transmission, the connectors CNe1b, CN1b of system b can use a 24-pin connector with two rows, as will be described later in Figure 29.

[0201] By using connectors with this two-row configuration for the a-system connectors CNe1a, CN1a and the b-system connectors CNe1a, CN1a in the dual transmission example, the pin assignments on the connector will be as shown in Figure 16. In Figure 16, the left side shows the row of odd-numbered pins, and the right side shows the row of even-numbered pins.

[0202] In the CNe1a connector of system a, the odd-numbered pins of CN1a are arranged as follows: Ground (GND), Clock signal LED_CLK, Data signal LED_DATA, Enable signal LED_ENABLE, Ground, 12V DC voltage (DC12VB), 12V DC voltage, and 12V DC voltage. In the even-numbered pin sequences, the following pins are arranged: Ground (GND), Ground, Ground, Ground, Ground, 12V DC voltage (DC12VB), 12V DC voltage, and 12V DC voltage.

[0203] In the b-system connectors CNe1b, the odd-numbered pins of CN1b are arranged as follows: 5V DC voltage (DC5VB), 5V DC voltage, ground (GND), clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, reset signal LSI_RST, ground, load signal S_IN_LOAD, clock signal S_IN_CLK, and serial data signal S_IN_DATA. In the odd-numbered sequences, the following pins are arranged: 35V DC voltage (DC35VB), 35V DC voltage, 35V DC voltage, ground (GND), ground, ground, ground, ground, ground, clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X.

[0204] The ground for system a and the ground for system b share a common ground. In other words, they are connected to a common ground line for the performance control board 30 and the LED connection board 700. It would be possible to consolidate the ground into either system a or system b harness, but as a noise countermeasure, each harness is assigned its own ground.

[0205] In Figure 16, the first, second, third, and fourth sets of performance control signals are indicated by the symbols "GP1," "GP2," "GP3," and "GP4."

[0206] [5.3 LED Connection Board] Next, we will explain the LED connection board 700. First, Figures 17, 18, and 19 illustrate the general circuit configuration formed on the LED connection board 700 using block diagrams.

[0207] The LED connection board 700 transmits and receives power supply voltage and performance control signals to and from the performance control board 30. The performance control signals include signals that affect the operation of the performance means, such as control signals for performances such as light emission and various sensing signals. Figure 17 shows the configuration around the connector CN1 (or CN1a, CN1b) described above.

[0208] When a single-system transmission example is adopted, the connector CN1 constitutes the transmission line H20 between the device and the performance control board 30. When employing a dual-system transmission example, the connectors CN1a and CN1b form the transmission lines H20a and H20b between the performance control board 30 and the transmission lines.

[0209] The LED connection board 700 is supplied with a 12V DC voltage (DC12VB) from connector CN1 (or CN1a). Fuse FZ2 is positioned as the closest component in terms of wiring relative to the 12V DC voltage (DC12VB) terminal (pin) on connector CN1 (or CN1a).

[0210] Furthermore, the LED connection board 700 is supplied with a 5V DC voltage (DC5VB) and a 35V DC voltage (DC35VB) from connector CN1 (or CN1b). Fuse FZ1 is positioned as the closest component in terms of wiring relative to the 5V DC voltage (DC5VB) terminal (pin) on connector CN1 (or CN1b).

[0211] Furthermore, a ground connection is made between the device and the performance control board 30 via connector CN1 (or CN1a, CN1b). Note that in Figures 17, 18, and 19, the notation for ground connections other than connector CN1 (or CN1a, CN1b) is omitted.

[0212] The performance control signals transmitted through connector CN1 (or CN1a, CN1b) are input to buffer circuits 701 and 703, where buffer processing, or signal compensation through waveform shaping, is performed. In other words, buffer processing can be described as noise suppression processing for the signal. The buffer circuit 701 receives the performance control signals for the first set (GP1) and the second set (GP2), while the buffer circuit 703 receives the performance control signal for the fourth set (GP4).

[0213] Of the performance control signals buffered by buffer circuit 701, the first set (GP1), consisting of the clock signal LED_CLK and the data signal LED_DATA, is further buffered by buffer circuit 702 before being output as three sets of light emission control signals: SA (CLK_A, DATA_A), SB (CLK_B, DATA_B), and SC (CLK_C, DATA_C). In this example, the enable signal LED_ENABLE is not used in the first set.

[0214] Of the performance control signals buffered by the buffer circuit 701, the second set (GP2), consisting of the clock signal LSI_CLK, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST, is supplied to the motor drive unit 760 in Figure 19, as shown by the motor control signal LSIS. The serial data signal LSI_IN_DATA output from the motor drive unit 760 in Figure 19 is buffered by the buffer circuit 701 and transmitted to the performance control board 30 via connector CN1 (or CN1b).

[0215] The buffer circuit 703 buffers the load signal S_IN_LOAD and clock signal S_IN_CLK of the fourth set (GP4) of the performance control signals. After that, the load signal S_IN_LOAD and clock signal S_IN_CLK are supplied to the P / S conversion circuit 704.

[0216] The P / S conversion circuit 704 performs parallel / serial conversion based on the load signal S_IN_LOAD and the clock signal S_IN_CLK. Specifically, the P / S conversion circuit 704 receives the sense signals SENS0, SENS1, and SENS2 input from connectors CN3, CN4 and connector CN23 in Figure 19, and outputs a serial data signal S_IN_DATA which includes these signals. The serial data signal S_IN_DATA is buffered by the buffer circuit 703 and then transmitted from connector CN1 (or CN1b) to the performance control board 30.

[0217] The buffer circuits 701, 702, 703 and the P / S conversion circuit 704 shown in Figure 17 are supplied with a 5V DC voltage (DC5VB) as the operating power supply. A 12V DC voltage (DC12VB) is transmitted downstream from connectors CN3 and CN4.

[0218] Figure 18 shows the circuit portion of the LED connection board 700 where the light emission control signals SA and SB from the buffer circuit 702 are supplied. The LED drive unit 750 is a circuit unit that performs LED drive control, including an LED driver. The LED driver in the LED drive unit 750 generates a light-emitting drive current based on the light-emitting control signal SA (CLK_A, DATA_A).

[0219] The LED driver of the LED drive unit 750 is connected to the downstream LED board via connectors CN5, CN8, CN11, CN13, CN6, and connectors CN7, CN9, CN12, CN14, and supplies light-emitting drive current to the LEDs mounted on the downstream LED board. Examples of downstream LED substrates include LED substrates 850 and 860 shown in Figure 11.

[0220] The LED driver unit 750 is supplied with a 12V DC voltage (DC12VB) as the power supply voltage for the LED driver and other components. Additionally, a 12V DC voltage (DC12VB) is transmitted to the LED boards downstream from connectors CN5, CN8, CN11, CN13, CN6, and connectors CN7, CN9, CN12, CN14 as the power supply for the LED's light emission operation, i.e., the power supply for the light emission drive current.

[0221] The light emission control signals SB (CLK_B, DATA_B) from the buffer circuit 702 are buffered by buffer circuits 708, 717, and 718 before being transmitted to downstream boards via connectors CN10, CN25, and CN26. Downstream boards include, for example, LED drivers and boards equipped with LEDs.

[0222] Buffer circuits 708, 717, and 718 are supplied with a 5V DC voltage (DC5VB) as their operating power supply. A 12V DC voltage (DC12VB) is transmitted from connectors CN10, CN25, and CN26 to the downstream LED board, serving as the power supply voltage for the LED driver and the power supply for the light-emitting drive current flowing through the LEDs.

[0223] Figure 19 shows the circuit portion of the LED connection board 700 around the motor drive unit 760 to which the motor control signal LSIS from the buffer circuit 702 is supplied.

[0224] The motor drive unit 760 is a circuit section that includes a motor control IC (motor controller) and, for example, four motor drive ICs (motor drivers). The motor control IC operates based on the second set (GP2) of clock signals LSI_CLK, enable signals LSI_ENABLE, data signals LSI_DATA, and reset signals LSI_RST, which are input as motor control signals LSIS, and controls multiple motor drive ICs. Each motor drive IC generates motor drive signals MD1, MD2, MD3, and MD4 for its corresponding motor (e.g., the motor of a movable part). These motor drive signals MD1, MD2, MD3, and MD4 are transmitted from connectors CN21, CN22, CN23, and CN24 to the downstream motors and to the circuit boards that relay the wiring to the motors.

[0225] Connectors CN16, CN17, CN18, CN19, CN20 and connector CN23 receive sense signals SENS0, SENS1, SENS2, SENS3, SENS4, and SENS5 from various motor-related sensors (e.g., origin sensors). These sense signals SENS0, SENS1, SENS2, SENS3, SENS4, and SENS5 are buffered by buffer circuit 709 before being input to the motor control IC in motor drive unit 760.

[0226] The motor control IC has a function to serialize multiple sense signals SENS0, SENS1, SENS2, SENS3, SENS4, and SENS5 that are input in parallel, and performs P / S conversion to output the serial data signal LSI_IN_DATA. As described above, this serial data signal LSI_IN_DATA is input to the buffer circuit 701 in Figure 17.

[0227] The motor control IC and motor drive IC in the motor drive unit 760 are supplied with a 5V DC voltage (DC5VB) and a 35V DC voltage (DC35VB) as operating power supply voltages. The buffer circuit 709 is supplied with a 5V DC voltage (DC5VB) as its operating power supply voltage. Furthermore, a 12V DC voltage (DC12VB) is transmitted via connectors CN16, CN17, CN18, CN19, and CN20 as the operating power supply for downstream sensors and other devices.

[0228] The light emission control signal SC (CLK_C, DATA_C) from the buffer circuit 702 in Figure 17 is buffered by the buffer circuit 714 in Figure 19 and then transmitted to the downstream board via connector CN23. The downstream board is, for example, the relay board 800 in Figure 11. The relay board 800 and the decorative board 820 are boards that are attached to the movable mechanism. The decorative board 820 is equipped with an LED driver and LEDs, and also has a relay circuit for the motor of the movable mechanism.

[0229] Therefore, the connector CN23 transmits the light emission control signal SC (CLK_C, DATA_C) and the motor drive signal MD3 to the decorative board 820 via the relay board 800. Furthermore, the sense signal SENS2 from the origin sensor of the movable motor is input from connector CN23 via decorative board 820 and relay board 800. As described above, the sense signal SENS2 is input to the P / S conversion circuit 704 in Figure 17.

[0230] Connector CN23 transmits 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) as operating power to the relay board 800 and decorative board 820. In this case, a flexible flat cable is used for the transmission line H31 between the relay board 800 and the decorative board 820, which are attached to the movable component. In some cases, a flexible flat cable may be used in the transmission line H30 between the relay board 800 and the LED connection board 700.

[0231] In this case, fuse FZ7 is placed between the 12V DC voltage (DC12VB) terminal of connector CN23 and the 12V DC voltage (DC12VB) power line (12V power line), and fuse FZ8 is placed between the 5V DC voltage (DC5VB) terminal of connector CN23 and the 5V DC voltage (DC5VB) power line (5V power line). Fuses FZ7 and FZ8 are considered to be the components closest in terms of wiring to the power supply voltage terminal on connector CN23, respectively. The buffer circuit 714 is supplied with a 5V DC voltage (DC5VB) as its operating power supply voltage.

[0232] The circuit configuration of the LED connection board 700 shown in Figures 17, 18, and 19 above will be partially explained with a specific circuit diagram.

[0233] Figure 20 is a circuit diagram corresponding to the section shown in Figure 17. Here, it shows a circuit using a 40-pin connector CN1 as an example of single-channel transmission. The pin assignment of connector CN1 is as shown in Figure 14. The circuit diagram for a dual-channel transmission example will be described later in Figure 21.

[0234] The 12V DC voltage (DC12VB) transmitted from pins 12, 14, 24, 26, 28, and 30 of connector CN1 is supplied to the 12V power line on the board via fuse FZ2. Capacitors C1 and C4 are connected between the 12V power line and ground as a noise suppression measure. Test point TP51 ​​is formed at a position corresponding to the space between capacitors C1 and C4 and the terminal (pin) of the 12V DC voltage (DC12VB) of connector CN1.

[0235] The 5V DC voltage (DC5VB) transmitted from pins 4 and 6 of connector CN1 is supplied to the 5V power line on the board via fuse FZ1. Capacitors C2 and C3 are connected between the 5V power line and ground as a noise suppression measure. Test point TP50 is formed at a position corresponding to the space between capacitors C2 and C3 and the 5V DC voltage (DC5VB) terminal (pin) of connector CN1.

[0236] The 35V DC voltage (DC35VB) transmitted from pins 36 and 38 of connector CN1 is supplied to the 35V power line on the board.

[0237] Pins 1, 2, 8, 9, 10, 16, 18, 19, 20, 22, 29, 32, 33, 34, 39, and 40 of connector CN1 are each connected to the ground line on the circuit board.

[0238] The control signals input from connector CN1, namely the clock signal LED_CLK and data signal LED_DATA for the first set (GP1), and the clock signal LSI_CLK, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST for the second set (GP2), are input to buffer circuit 701. The load signal S_IN_LOAD and clock signal S_IN_CLK for the fourth group (GP4) are input to the buffer circuit 703.

[0239] Between connector CN1 and buffer circuits 701 and 703, test points TP1 to TP10 are formed on the signal paths (wiring patterns) of each of the above-mentioned control signals.

[0240] In connector CN1, the unused enable signal terminal LSI_ENABLE (pin 17) and the unused terminals for the third set (GP3) clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X (pins 21, 25, and 27) are left unconnected.

[0241] Buffer circuits 701, 702, and 703 (and buffer circuit 709 in Figure 19) use an IC that functions as an inverter when the CONT terminal of pin 1 is at a low level and as a buffer when it is at a high level. In this case, the buffer function is activated by applying a high level using a 5V DC voltage (DC5VB). Additionally, a 5V DC voltage (DC5VB) is applied to the VCC terminal of pin 20 as the operating power supply.

[0242] Buffer circuits 701, 702, 703, and 709 are Schmitt trigger buffers with CMOS8 circuits. They buffer, or rather compensate for, the signals input from pin 2 (terminal A1) to pin 9 (terminal A8), and output them from pin 18 (terminal Y1) to pin 11 (terminal Y8), respectively. In other words, the signal input to terminal A1 is buffered and output from terminal Y1, the signal input to terminal A2 is buffered and output from terminal Y2, ... the signal input to terminal A8 is buffered and output from terminal Y8.

[0243] The A1, A3, A4, and A5 terminals of the buffer circuit 701 receive the clock signal LSI_CLK, the enable signal LSI_ENABLE, the data signal LSI_DATA, and the reset signal LSI_RST. These signals are buffered by the buffer circuit 701 and output from the Y1, Y3, Y4, and Y5 terminals, and supplied to the motor control signal LSIS in Figure 19 via chip resistors RA1 or RA2.

[0244] Furthermore, the serial data signal LSI_IN_DATA from the motor drive unit 760 is input to the A2 terminal of the buffer circuit 701, buffered, output from the Y2 terminal, sent to the connector CN1 via the chip resistor RA1, and transmitted to the upstream performance control board 30.

[0245] The clock signal LED_CLK and data signal LED_DATA are input to terminals A6 and A7 of buffer circuit 701, buffered, output from terminals Y6 and Y7, and input to buffer circuit 702 via chip resistor RA2.

[0246] The clock signal CLK_CLK is branched and input to terminals A1, A3, and A5 of buffer circuit 702. The data signal LED_DATA is branched and input to terminals A2, A4, and A6 of buffer circuit 702.

[0247] These three separate clock signals, LED_CLK and LED_DATA, are buffered and output. The signals output from terminals Y1 and Y2 are designated as the light emission control signal SA (CLK_A, DATA_A), the signals output from terminals Y3 and Y4 are designated as the light emission control signal SB (CLK_B, DATA_B), and the signals output from terminals Y5 and Y6 are designated as the light emission control signal SC (CLK_C, DATA_C).

[0248] In the buffer circuit 703, the clock signal S_IN_CLK is input to terminal A2 and the load signal S_IN_LOAD is input to terminal A4. These signals are then buffered and output from terminals Y2 and Y4, and supplied to the P / S conversion circuit 704 via resistors R2 and R4.

[0249] The P / S conversion circuit 704 is, for example, a CMOS 8-bit shift register, which has 8 bits of parallel input / output, serial input, and serial output, and performs parallel-to-serial conversion of data. When the P / S CONT terminal is L, the eight terminals Q / D1 to Q / D8 become parallel outputs, and the data from the SI terminal is stored in each register on the rising edge of the input waveform at the CK terminal, and also output to the Q / D1 to Q / D8 terminals. Also, by setting the CLR / LOAD terminal to L, each register is reset asynchronously in response to the input at the CK terminal. When the P / S CONT terminal is H, the eight terminals Q / D1 to Q / D8 become parallel inputs, and when the CLR / LOAD terminal is L, the input data from Q / D1 to Q / D8 is stored asynchronously in each register at the CK terminal input.

[0250] In this example, the P / S conversion circuit 704 is configured such that a 5V DC voltage (DC5VB) is applied to the P / S CONT terminal, setting the P / S CONT terminal to H, and the eight terminals from Q / D1 to Q / D8 are treated as parallel inputs. Additionally, the clock signal S_IN_CLK input from buffer circuit 703 becomes the input to the CK terminal, and the load signal S_IN_LOAD becomes the input to the CLR / LOAD terminal.

[0251] At the parallel input terminals Q / D1 to Q / D8 of the P / S conversion circuit 704, the sense signal SENS0 is input to Q / D1, the sense signal SENS1 to Q / D2, and the sense signal SENS2 to Q / D3. Q / D4, Q / D5, Q / D6, Q / D7, and Q / D8 terminals are connected to ground. That is, each input is "0" (L level).

[0252] The sense signals SENS0, SENS1, and SENS2 are detection signals from sensors in downstream devices such as motors, including, for example, a home position sensor and a movement position sensor. The sense signal SENS0 is input from connector CN3. The sense signal SENS1 is also input from connector CN3. Connectors CN3 and CN4 are assigned a 12V DC voltage (DC12VB) to the first pin and ground (GND) to the second pin, respectively, supplying operating power to the connected sensor.

[0253] The signal line for the sense signal SENS0 is connected to the 5V power supply line via resistor R7 and is pulled up. The signal line for the sense signal SENS1 is connected to the 5V power supply line via resistor R8 and is pulled up.

[0254] The sense signal SENS2 is input from connector CN23, as shown in Figure 19 and Figure 25 described later. The signal line of the sense signal SENS2 is connected to the 5V power supply line via resistor R135 and is pulled up.

[0255] These sense signals SENS0, SENS1, and SENS2 are filtered to remove high-frequency noise by CR filter circuits (resistor R5 and capacitor C11, resistor R8 and capacitor C12, and resistor R11 and capacitor C14) and then input to the P / S conversion circuit 704.

[0256] The P / S conversion circuit 704 converts the input sense signals SENS0, SENS1, and SENS2 into serial data and outputs it as the serial data signal S_IN_DATA from the Q8 terminal. This serial data signal S_IN_DATA has high-frequency noise removed by a CR filter circuit consisting of resistor R3 and capacitor C10 and is input to the A7 terminal of the buffer circuit 703. It is then output from the Y7 terminal, and after passing through resistor R1, is transmitted to the upstream performance control board 30 from pin 31 of connector CN1.

[0257] Up to this point, Figure 20 has explained the circuit configuration using a single-channel transmission example, but Figure 21 shows the circuit configuration when a dual-channel transmission example is adopted. The only difference between Figure 21 and Figure 20 is the connectors CN1a and CN1b and the connection configuration of their respective terminals; the configurations of the buffer circuits 701, 702, and 703, the P / S conversion circuit 704, and the connectors CN3 and CN4 are the same as in Figure 20.

[0258] In the dual transmission example shown in Figure 21, a 16-pin connector CN1a and a 24-pin connector CN1b are used. The connector CN1a, which is part of system a, transmits a 12V DC voltage (DC12VB) and the first set of performance control signals (GP1). Furthermore, the b-system connector CN1b transmits 5V DC voltage (DC5VB) and 35V DC voltage (DC35VB), as well as the second set (GP2) and fourth set (GP4) of performance control signals.

[0259] The 12V DC voltage (DC12VB) transmitted from pins 11 through 16 of connector CN1a is supplied to the 12V power line on the board via fuse FZ2. Capacitors C2 and C3 are connected between the 12V power line and ground as a noise suppression measure. Test point TP51 ​​is formed at a position corresponding to the space between capacitors C2 and C3 and the 12V DC voltage (DC12VB) terminal (pin) of connector CN1a.

[0260] Pins 1, 2, 4, 6, 8, 9, and 10 of connector CN1a are each connected to the ground line on the circuit board.

[0261] The control signals for the effects input from connector CN1a, namely the clock signal LED_CLK (pin 3) and data signal LED_DATA (pin 5) of the first set (GP1), are input to buffer circuit 701. Note that in connector CN1a, the unused enable signal terminal (pin 7) for LSI_ENABLE is left unconnected.

[0262] On the other hand, the 5V DC voltage (DC5VB) transmitted from the first and third pins of connector CN1b is supplied to the 5V power line on the board via fuse FZ1. Capacitors C1 and C4 are connected between the 5V power line and ground as a noise suppression measure. Test point TP50 is formed at a position corresponding to the space between capacitors C1 and C4 and the terminals (pins) of the 5V DC voltage (DC5VB) on connector CN1b.

[0263] The 35V DC voltage (DC35VB) transmitted from the 2nd and 4th pins of connector CN1b is supplied to the 35V power line on the board.

[0264] Pins 5, 8, 10, 12, 14, 16, 17, and 18 of connector CN1b are each connected to the ground line on the circuit board.

[0265] The performance control signals input from connector CN1b, the clock signal LSI_CLK (pin 7), enable signal LSI_ENABLE (pin 11), data signal LSI_DATA (pin 13), and reset signal LSI_RST (pin 15) of the second set (GP2), are input to buffer circuit 701. The load signal S_IN_LOAD (pin 19) and clock signal S_IN_CLK (pin 21) of the fourth group (GP4) are input to the buffer circuit 703.

[0266] Between connectors CN1a and CN1b and buffer circuits 701 and 703, test points TP1 to TP10 are formed on the signal paths (wiring patterns) of the above-mentioned control signals.

[0267] In connector CN1b, the terminals for the unused third set (GP3) clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X (pins 20, 22, and 24) are left unconnected.

[0268] The serial data signal LSI_IN_DATA transmitted from the buffer circuit 701 via the chip resistor RA1 is transmitted from pin 9 of connector CN1b to the upstream performance control board 30. The serial data signal S_IN_DATA transmitted from the buffer circuit 703 via resistor R1 is transmitted from pin 23 of connector CN1b to the upstream performance control board 30.

[0269] In the example circuit for the dual transmission example shown in Figure 21, the above points differ from those in Figure 20, but these are due to differences in the pin assignments of connector CN1 and connectors CN1a and CN1b, and the circuits are the same in principle.

[0270] Next, Figures 22 and 23 show specific circuit examples of the LED driver unit 750 and the connector connected downstream, as shown in Figure 18.

[0271] The LED drive unit 750 in Figure 18 includes the LED driver 705 in Figure 22 and the LED driver 707 in Figure 23.

[0272] As shown in Figure 22, the light emission control signal SA (CLK_A, DATA_A) from the buffer circuit 702 in Figure 20 or Figure 21 is input to terminals 48 (SCLK) and 47 (SDATA) of the LED driver 705. Furthermore, a test point TP12 is formed on the wiring of the clock signal CLK_A from the buffer circuit 702 to the LED driver 705, and a test point TP11 is formed on the wiring of the data signal DATA_A from the buffer circuit 702 to the LED driver 705.

[0273] The LED driver 705 generates a light-emitting drive current in accordance with the clock signal CLK_A and the data signal DATA_A. The LED driver 705 has light-emitting drive current terminals LEDR1, LEDG1, LEDB1...LEDR8, LEDG8, LEDB8, and can control the drive current of 24 systems. In this case, all 24 light-emitting drive current terminals are used to execute light emission for 24 systems of LEDs.

[0274] The light-emitting drive current terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, and LEDB2 are connected to six LED circuits on a downstream board (not shown) that are electrically connected from connector CN5. One LED circuit is a circuit having one LED or multiple LEDs connected in series. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN5 as the power source, the terminal voltages of the light-emitting drive current terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, and LEDB2 in the LED driver 705 are controlled, and light-emitting drive currents 01-R1, 01-G1, 01-B1, 01-R2, 01-G2, and 01-B2 are flowed through each of the six LED circuits, causing each of the six LEDs to emit light.

[0275] The light-emitting drive current terminals LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4 ​​are connected to six LED circuits on a downstream board (not shown) that are electrically connected from connector CN8. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN8 as the power source, the terminal voltages of the light-emitting drive current terminals LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4 ​​in the LED driver 705 are controlled, and light-emitting drive currents 01-R3, 01-G3, 01-B3, 01-R4, 01-G4, and 01-B4 are flowed through each of the six LED circuits, causing each of the six LEDs to emit light.

[0276] The light-emitting drive current terminals LEDR5, LEDG5, and LEDB5 are connected to three LED circuits on a downstream board (not shown) that are electrically connected from connector CN11. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN11 as the power source, the terminal voltages of the light-emitting drive current terminals LEDR5, LEDG5, and LEDB5 in the LED driver 705 are controlled, and the light-emitting drive currents 01-R5, 01-G5, and 01-B5 are flowed through each of the three LED circuits, causing each of the three LEDs to emit light.

[0277] The light-emitting drive current terminals LEDR6, LEDG6, and LEDB6 are connected to three LED circuits on a downstream board (not shown) that are electrically connected from connector CN13. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN13 as the power source, the terminal voltages of the light-emitting drive current terminals LEDR6, LEDG6, and LEDB6 in the LED driver 705 are controlled, and the light-emitting drive currents 01-R6, 01-G6, and 01-B6 are flowed through each of the three LED circuits, causing each of the three LEDs to emit light.

[0278] The light-emitting drive current terminals LEDR7, LEDG7, LEDB7, LEDR8, LEDG8, and LEDB8 are connected to six LED circuits on a downstream board (not shown) that are electrically connected from connector CN6. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN13 as the power source, the terminal voltages of the light-emitting drive current terminals LEDR7, LEDG7, LEDB7, LEDR8, LEDG8, and LEDB8 in the LED driver 705 are controlled, and light-emitting drive currents 01-R7, 01-G7, 01-B7, 01-R8, 01-G8, and 01-B8 are flowed through each of the six LED circuits, causing each of the six LEDs to emit light. The lines for light-emitting drive currents 03-R8, 03-G8, and 03-B8 are connected to connector CN6 and connector CN10 shown in Figure 24. The light-emitting drive current terminals of the LED driver on a downstream board connected to either connector CN6 or connector CN10 are connected to three LED circuits on the other downstream board, and the light-emitting drive currents 03-R8, 03-G8, and 03-B8 are then supplied to these three LED circuits.

[0279] Next, as shown in Figure 23, the light emission control signal SA (CLK_A, DATA_A) from the buffer circuit 702 in Figure 20 or Figure 21 is also input to terminals 48 (SCLK) and 47 (SDATA) of the LED driver 707. Furthermore, a test point TP16 is formed on the wiring of the clock signal CLK_A from the buffer circuit 702 to the LED driver 707, and a test point TP15 is formed on the wiring of the data signal DATA_A from the buffer circuit 702 to the LED driver 707.

[0280] The LED driver 707 is the same IC chip as the LED driver 705 and generates a light-emitting drive current in response to the clock signal CLK_A and the data signal DATA_A. The LED driver 707 uses 23 light-emitting drive current terminals, excluding LEDB8, to control the illumination of 23 LEDs.

[0281] The light-emitting drive current terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, and LEDB2 are connected to six LED circuits on a downstream board (not shown) that are electrically connected from connector CN7 via current-limiting resistors R17, R18, R16, R20, R21, and R19. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN7 as the power source, the terminal voltages of the light-emitting drive current terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, and LEDB2 in the LED driver 707 are controlled, and light-emitting drive currents 10-R1, 10-G1, 10-B1, 10-R2, 10-G2, and 10-B2 are flowed through each of the six LED circuits, causing each of the six LEDs to emit light.

[0282] The light-emitting drive current terminals LEDR3, LEDG3, and LEDB3 are connected to three LED circuits on a downstream board (not shown) that are electrically connected from connector CN9 via current-limiting resistors R22, R23, and R24. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN9 as the power source, the terminal voltages of the light-emitting drive current terminals LEDR3, LEDG3, and LEDB3 in the LED driver 707 are controlled, causing the light-emitting drive currents 10-R3, 10-G3, and 10-B3 to flow through each of the three LED circuits, resulting in the illumination of each of the three LEDs.

[0283] The light-emitting drive current terminal LEDR4 is connected via a current-limiting resistor R27 to one LED circuit on a downstream board (not shown) that is electrically connected from connector CN12. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream circuit board via connector CN12 as the power source, the LED driver 707 controls the terminal voltage of the light-emitting drive current terminal LEDR4, causing the light-emitting drive current 10-R4 to flow through one LED circuit, thereby causing the LED to light up.

[0284] The light-emitting drive current terminals LEDG4, LEDB4, LEDR5, LEDG5, LEDB5, LEDR6, LEDG6, LEDB6, LEDR7, and LEDG7 are connected to 10 LED circuits on a downstream board (not shown) that are electrically connected from connector CN14 via current-limiting resistors R28, R29, R30, R31, R32, R33, R34, R35, R36, and R37. In addition, the light-emitting drive current terminals LEDB7, LEDR8, and LEDG8 are connected to 3 LED circuits on a downstream board that are electrically connected from connector CN14 without using current-limiting resistors. Then, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN14 as the power source, the terminal voltages of the light-emitting drive current terminals LEDG4, LEDB4, LEDR5, LEDG5, LEDB5, LEDR6, LEDG6, LEDB6, LEDR7, LEDG7, LEDB7, LEDR8, and LEDG8 in the LED driver 707 are controlled, and light-emitting drive currents 10-G4, 10-B4, 10-R5, 10-G5, 10-B5, 10-R6, 10-G6, 10-B6, 10-R7, 10-G7, 10-B7, 10-R8, and 10-G8 are flowed to each of the 13 LED circuits, causing each of the 13 LEDs to emit light.

[0285] Note that the LED driver 705 in Figure 22 and the LED driver 707 in Figure 23 have a 6-bit slave address set by address terminals A0 to A5. However, address terminal A5 is fixed to "0", and the 5-bit slave address is set by address terminals A0 to A4. Therefore, when each address terminal A0 to A4 is connected to terminal VREF, which outputs a reference voltage (5V), or to ground, each bit is set to "1" or "0".

[0286] This slave address is set to a different value for all LED drivers to which the first set of clock signals LED_CLK and data signals LED_DATA, i.e., light emission control signals SA, SB, and SC, are supplied. In other words, it is an address that distinguishes LED drivers on boards mounted on other boards (not shown) that are downstream from the LED connection board 700. In this way, in the clock signal LED_CLK and data signal LED_DATA systems, address terminal A5 is connected to ground as "0" for all bits, and the other 5 bits are used to set unique slave addresses.

[0287] Figure 24 shows the circuit where the light emission control signal SB (CLK_B, DATA_B) is output. The clock signal CLK_B and data signal DATA_B output from buffer circuit 702 in Figure 20 or Figure 21 are branched into three systems as shown in Figure 24 and input to buffer circuits 708, 717, and 718, which are dual Schmitt buffers. Buffer circuits 708, 717, and 718 are supplied with a 5V DC voltage (DC5VB) as their operating power supply.

[0288] The clock signal CLK_B and data signal DATA_B, buffered by buffer circuit 708, are supplied to pins 4 and 6 of the 12-pin connector CN10 via resistors R25 and R26, respectively. A 12V DC voltage (DC12VB) is supplied to pins 1, 2, and 3 of connector CN10. Pins 5, 7, 8, and 12 of connector CN10 are assigned to ground. Pins 9, 10, and 11 are assigned to the light emission drive currents 03-R8, 03-G8, and 03-B8 mentioned above. This transmits the light emission control signal SB and the 12V DC voltage (DC12VB) from connector CN10 to the downstream circuit board, controlling the operation of the downstream LED driver.

[0289] The clock signal CLK_B and data signal DATA_B, buffered by buffer circuit 717, are supplied to pins 4 and 6 of the 9-pin connector CN25 via resistors R136 and R137, respectively. A 12V DC voltage (DC12VB) is supplied to pins 1, 2, and 3 of connector CN25. Pins 5, 7, 8, and 9 of connector CN25 are assigned to ground. This transmits the light emission control signal SB and the 12V DC voltage (DC12VB) from connector CN25 to the downstream circuit board, controlling the operation of the downstream LED driver.

[0290] The clock signal CLK_B and data signal DATA_B, buffered by buffer circuit 718, are supplied to pins 4 and 6 of the 9-pin connector CN26 via resistors R138 and R112, respectively. A 12V DC voltage (DC12VB) is supplied to pins 1 and 2 of connector CN26. Pins 3, 5, 7, 8, and 9 of connector CN25 are assigned to ground. This transmits the light emission control signal SB and the 12V DC voltage (DC12VB) from connector CN26 to the downstream circuit board, controlling the operation of the downstream LED driver.

[0291] Figure 25 shows the circuit in the section where the light emission control signal SC (CLK_C, DATA_C) is output. The clock signal CLK_C and data signal DATA_C output from the buffer circuit 702 in Figure 20 or Figure 21 are input to the buffer circuit 714, which is a dual Schmitt buffer, as shown in Figure 25.

[0292] The clock signal CLK_C and data signal DATA_C, buffered by buffer circuit 714, are supplied to pins 8 and 12 of the 18-pin connector CN23, respectively, via resistors R109 and R110.

[0293] A 12V DC voltage (DC12VB) is supplied to pins 2, 4, and 6 of connector CN23. In this case, fuse FZ7 is placed between pins 2, 4, and 6 and the 12V power line. Additionally, a 5V DC voltage (DC5VB) is supplied to pin 9 of connector CN23. In this case, fuse FZ8 is placed between pin 9 and the 5V power line.

[0294] Pins 1, 3, 10, 11, 13, and 14 of connector CN23 are assigned to ground.

[0295] Pin 5 is assigned to the sense signal SENS4. The sense signal SENS4 is one of the sense signals input to the buffer circuit 709 in Figure 19. Pin 7 is assigned to the sense signal SENS2. The sense signal SENS2 is one of the sense signals input to the P / S conversion circuit 704 in Figure 17 (Figure 20 or Figure 21). Pins 15, 16, 17, and 18 are assigned to the motor drive signals MD3 (MOTzA+, MOTzB-, MOTzA-, MOTzB+) from the motor drive unit shown in Figure 19.

[0296] As a result, the light emission control signal SC, motor drive signal, 12V DC voltage (DC12VB), and 5V DC voltage (DC5VB) are transmitted from connector CN23 via transmission line H30 to the downstream board, in this case the relay board 800 mounted on the movable component, thereby controlling the operation of the downstream LED driver and motor. In addition, sense signals SENS2 and SENS4 from the downstream sensor are input to the LED connection board 700.

[0297] Figure 26 shows the circuit related to the 35V DC voltage (DC35VB) input from connector CN1 or CN1b. In particular, the motor drive unit 760 in Figure 19 is configured to obtain the motor drive power supply voltage from the 35V power supply line.

[0298] As shown in Figure 26, the 35V power supply line is connected to a protection circuit consisting of a Schottky barrier diode D10 and an electrolytic capacitor C57, and to another protection circuit consisting of a Schottky barrier diode D11 and an electrolytic capacitor C63.

[0299] Then, fuses FZ3 and FZ4 are connected to the connection point between the Schottky barrier diode D10 and the electrolytic capacitor C57, and the motor drive power supply voltages MOT35Vx and MOT35Vz are extracted. Furthermore, fuses FZ5 and FZ6 are connected to the connection point between the Schottky barrier diode D11 and the electrolytic capacitor C63, and the motor drive power supply voltages MOT35Vy and MOT35Vu are extracted. These motor drive power supply voltages, MOT35Vx, MOT35Vz, MOT35Vy, and MOT35Vu, are supplied to the four motor drive ICs in the motor drive unit 760 shown in Figure 19.

[0300] <6. Characteristic Configuration and Effects of the Embodiment> The gaming machine 1 of this embodiment may have the configurations described below from (Configuration A1-1) to (Configuration H5). These configurations will be explained mainly by taking as examples the transmission line H20 (H20a, H20b) between the performance control board 30 and the LED connection board 700, the configuration of the LED connection board 700, and the configuration of the performance control board 30.

[0301] (Composition A1-1) Gaming machine 1 is, A first control unit located at the first position, A second control unit located at the second position, The system includes a transmission line connecting the first control unit and the second control unit, By illuminating the light-emitting means and simultaneously driving a different performance means, a predetermined performance can be executed. The aforementioned transmission line is A first transmission means transmits, via a first connector, a light-emitting control signal for causing the light-emitting means to emit light and a first power supply voltage for driving the light-emitting mechanism. The system includes a second transmission means that transmits a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector separate from the first connector.

[0302] In this case (Configuration A1-1), the following corresponding example (Specific Example 1) can be assumed. (Specific example 1) • First control unit: Performance control board 30 • Second control unit: LED connection board 700 (configuration example shown in Figure 21) • First transmission means: Transmission line H20a • Second transmission means: transmission line H20b • First connector: Connectors CN1a, CNe1a • Second connector: Connectors CN1b, CNe1b • Light control signals for illuminating the light-emitting device: The first set of performance control signals consists of the data signal LED_DATA and the clock signal LED_CLK. • Primary power supply voltage for driving light emission: 12V DC voltage (DC12VB) • Control signals for controlling the performance means: The second set of performance control signals consists of the clock signal LSI_CLK, the enable signal LSI_ENABLE, the data signal LSI_DATA, and the reset signal LSI_RST. • Second power supply voltage for signal processing: 5V DC voltage (DC5VB)

[0303] The performance control board 30 is positioned at a specific first position on the game board 3 as shown in Figure 7, and the LED connection board 700 is also positioned at a specific first position on the game board 3 as shown in Figure 7, thus corresponding to the first control unit and the second control unit. As a means of illumination, this includes the light-emitting section using decorative LEDs. For example, this is the LED light-emitting section on the board downstream of the LED connection board 700, which is driven to emit light by LED drivers 705 and 707. As an example of a performance means other than illumination, there is the motor of a movable prop.

[0304] The 12V DC voltage (DC12VB) is the operating power supply for LED drivers 705 and 707, and is also used as the power supply voltage for the light emission drive current of LEDs mounted on downstream boards. In other words, it is the first power supply voltage for light emission drive.

[0305] The 5V DC voltage (DC5VB) is used in buffer circuits 701, 702, 703, and 709, the P / S conversion circuit 704, and the motor control IC in the motor drive unit 760. In other words, it is the power supply voltage for signal processing and is the second power supply voltage. Furthermore, since the 35V DC voltage (DC35VB) is the same as the motor drive power supply voltages MOT35Vx, MOT35Vz, MOT35Vy, and MOT35Vu used by the motor drive IC in the motor drive unit 760, the 35V DC voltage (DC35VB) can be said to correspond to the second power supply voltage for signal processing.

[0306] As explained in Figure 15, in transmission line H20a of system a, where connectors CN1a and CNe1a are the transmission line ends, the first set of data signals LED_DATA and clock signals LED_CLK of the performance control signals, which are the light emission control signals, are transmitted, and a 12V DC voltage (DC12VB) is transmitted. Furthermore, in transmission line H20b of system b, where connectors CN1b and CNe1b are at the transmission line ends, the second set of performance control signals—the clock signal LSI_CLK, the enable signal LSI_ENABLE, the data signal LSI_DATA, and the reset signal LSI_RST—along with 5V DC voltage (DC5VB) and 35V DC voltage (DC35VB) are transmitted.

[0307] In principle, as shown in the example of single-line transmission, a single transmission line H20 can be provided between the performance control board 30 and the LED connection board 700, with, for example, 40-pin connectors CN1 and CN1e as transmission line ends. By dividing this into system A and system B, the efficiency of the circuit board configuration can be improved.

[0308] For example, instead of the 40-pin connectors CN1 and CNe1, we can use 16-pin connectors CN1a and CNe1a, 24-pin connectors CN1b and CNe1b, and their respective harnesses. This allows us to use multiple relatively small connectors instead of one large connector, reducing the overall area occupied by connectors on the circuit board and improving placement flexibility.

[0309] For example, Figure 27 shows an example of a 40-pin connector that can be used as connectors CN1 and CNe1. Figure 28 shows examples of 16-pin connectors that can be used for connectors CN1a and CNe1a, and Figure 29 shows examples of 24-pin connectors that can be used for connectors CN1b and CNe1b.

[0310] In Figures 27, 28, and 29, a top-type connector is shown as an example, where the connector terminals are connected from above the circuit board. However, a side-type connector, where the connector terminals are connected parallel to the plane of the circuit board, is also acceptable.

[0311] Furthermore, the lower part of Figures 27, 28, and 29 shows the arrangement of pads Pd formed on the substrate corresponding to the connectors. The dashed line SCA corresponds to the outer shape of the connector where it is placed. Each pad Pd electrically corresponds to each terminal (pin) of the connector, and the pitch PW of the pad Pd corresponds to the pitch of the terminal (pin). To avoid complexity, only some of the symbols for pads, pins, and other components are shown in each diagram.

[0312] Each figure shows the contact housing 1000 and socket housing 1001 that make up the connector, with the socket housing 1001 shown mounted on the circuit board 2000. On the socket housing 1001 side, a predetermined number of pins 1002 are provided in two rows. On the contact housing 1000 side, wires 1003 are attached to which each pin 1002 will be electrically connected. The specifications for each connector are as follows:

[0313] Connector CN1 / CNe1 in Figure 27 • Socket housing 1001 width: Xs: 33.7mm • Socket housing 1001 vertical size Ys: 7.6mm • Socket housing 1001 height size Zs: 8.6mm • Contact housing 1000 width x c: 33.7mm • Vertical size of contact housing 1000: Yc: 7.6mm • Contact housing 1000 height size Zc: 5.7mm Terminal pitch PW: 1.5mm Pad width W1: 0.7mm • Pin diameter: 0.6mm ·Rated current: 1.5A • Applicable wire range / conductor size: AWG28 (diameter 0.3200mm / cross-sectional area 0.08046mm) 2 )from AWG24 (diameter 0.5105mm / cross-sectional area 0.2047mm 2 ) • Applicable wire range / insulation outer diameter: 0.76mm to 1.2mm

[0314] Connector CN1a / CNe1a in Figure 28 • Socket housing 1001 width Xs: 15.7mm • Socket housing 1001 vertical size Ys: 7.6mm • Socket housing 1001 height size Zs: 8.6mm • Contact housing 1000 width xc: 15.7mm • Vertical size of contact housing 1000: Yc: 7.6mm • Contact housing 1000 height size Zc: 5.7mm Terminal pitch PW: 1.5mm Pad width W1: 0.7mm • Pin diameter: 0.6mm ·Rated current: 2A • Applicable wire range / conductor size: From AWG28 (diameter 0.3200mm / cross-sectional area 0.08046mm2) AWG24 (diameter 0.5105mm / cross-sectional area 0.2047 mm2) • Applicable wire range / insulation outer diameter: 0.76mm to 1.2mm

[0315] Connectors CN1b / CNe1b in Figure 29 • Socket housing 1001 width: Xs: 13.2mm • Socket housing 1001 vertical size Ys: 5.6mm • Socket housing 1001 height size Zs: 6.8mm • Contact housing 1000 width xc: 14.2mm • Vertical size of contact housing 1000: Yc: 4.25mm • Contact housing 1000 height size Zc: 4.36mm Terminal pitch PW: 1.0mm Pad width W1: 0.6mm • Pin diameter: 0.5mm ·Rated current: 1A • Applicable wire range / conductor size: AWG32 (diameter 0.2032mm / cross-sectional area 0.03243mm) 2 )from AWG28 (diameter 0.3200mm / cross-sectional area 0.08046mm 2 ) • Applicable wire range / insulation outer diameter: 0.4mm~0.8mm

[0316] For example, in the case of single-channel transmission, the 40-pin connector shown in Figure 27 can be used, whereas in the case of dual-channel transmission, the 16-pin connector shown in Figure 28 and the 24-pin connector shown in Figure 29 can be used. In other words, in the case of dual-channel transmission, the smaller 16-pin and 24-pin connectors are used instead of the large 40-pin connector.

[0317] Figure 30 schematically shows that in a single-system transmission example, 40-pin connectors CN1 and CNe1 were used between the performance control board 30 and the LED connection board 700. Figures 31, 32, and 33 schematically show that in the dual transmission example, 16-pin connectors CN1a and CNe1a, and 24-pin connectors CN1b and CNe1b were used between the performance control board 30 and the LED connection board 700.

[0318] In the case of Figure 30, the connectors CN1 and CNe1, which are horizontally large (for example, 33.7 mm), are placed near a certain edge of the circuit board, occupying a relatively large area. Furthermore, the wiring patterns around the connectors become densely packed.

[0319] In contrast, in the case of dual-system transmission, as shown in Figures 31, 32, and 33, the degree of freedom in the placement of the two connectors is increased, which expands the degree of freedom in the circuit board pattern design and facilitates miniaturization of the circuit board through placement.

[0320] In the example in Figure 31, for example, connectors CN1a and CN1b are arranged along one side of the LED connection board 700, so the area occupied on one side is wider, similar to Figure 30, but it is still not as large as connector CN1 in Figure 30. For example, the horizontal dimensions of the socket housings 1001 of connectors CN1a and CN1b in Figures 28 and 29 are 15.7 mm and 13.2 mm, totaling 28.9 mm, and even including the space for placement, the occupied area is smaller than the horizontal dimension of connector CN1 in Figure 27, which is 33.7 mm.

[0321] In the example shown in Figure 32, by positioning connectors CN1a and CN1b separately on the LED connection board 700, the density of wiring patterns around the connectors can be reduced. Furthermore, by arranging various components according to the power supply voltage using the performance control signals transmitted by connectors CN1a and CN1b, efficient wiring and component placement can be easily achieved.

[0322] In particular, in the example shown in Figure 32, the spacing d2 between connectors CN1a and CN1b on the LED connection board 700 is wider than the spacing d1 between connectors CNe1a and CN1eb on the performance control board 30. On the performance control board 30 side, since each signal is output from a single CPU output port, it is more convenient for wiring if connectors CNe1a and CN1eb are close together. On the other hand, if the LED connection board 700 has separate circuits for each effect (for example, LED illumination and motor drive), it is easier to design the wiring pattern if connectors CN1a and CN1b are placed far apart. Furthermore, the fact that the LED-related light emission control signals and the 12V DC voltage (DC12VB) for driving the light emission are on the same circuit (a) is advantageous in terms of wiring on the LED connection board 700.

[0323] In the example shown in Figure 33, arranging connectors CN1a and CN1b along different sides of the LED connection board 700 is an effective arrangement when it is desirable to avoid occupying one side with connectors. For example, if arranging connectors CN1a and CN1b along one side becomes inefficient in terms of wiring patterns and component placement due to the arrangement of other connectors or ICs, or the shape of the board, then the arrangement of connectors CN1a and CN1b as shown in Figure 33 is useful.

[0324] The gaming machine 1 of this embodiment includes the following (configuration A1-2) in addition to the above (configuration A1-1).

[0325] (Composition A1-2) The first power supply voltage and the second power supply voltage are power supply voltages used to produce the predetermined effects.

[0326] For example, the first power supply voltage, 12V DC voltage (DC12VB), and the second power supply voltage, 5V DC voltage (DC5VB), are power supply voltages used to produce a certain predetermined effect. A predetermined performance refers to the performance of a certain means of performance.

[0327] In this case, one example of a designated effect is the use of decorative LEDs for illumination as a means of performance. For example, LED drivers 705 and 707 control the illumination of LEDs on downstream LED boards 850, 860, etc. In this case, a 12V DC voltage (DC12VB) is used as the power supply voltage for LED drivers 705 and 707 and as the power supply for the light-emitting drive current that flows to the LEDs. A 5V DC voltage (DC5VB) is used as the power supply voltage for buffer circuits 701 and 702, which process the light-emitting control signal SA supplied to LED drivers 705 and 707.

[0328] Thus, 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are used for the illumination effects of decorative LEDs. In the case of dual-system transmission, these 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are transmitted through different transmission lines, H20a for system a and H20b for system b, respectively.

[0329] Another example of a designated effect is the use of LEDs installed on movable parts of a game machine. Furthermore, the specified effects can also refer to the overall effects of a movable mechanism. For example, this could include the motor-driven operation of the movable mechanism and the illumination of LEDs mounted on it.

[0330] In this case, with respect to the first power supply voltage of 12V DC voltage (DC12VB), we can consider a second power supply voltage of 5V DC voltage (DC5VB) or 35V DC voltage (DC35VB). The relay board 800 and decorative board 820 shown in Figure 11 are mounted on the movable mechanism.

[0331] From connector CN23 (see Figures 19 and 25), a 12V DC voltage (DC12VB) is transmitted to the relay board 800 and the decorative board 820, for example, as the power supply voltage for the LED driver mounted on the decorative board 820 and as the power supply for the light-emitting drive current that flows to the LEDs.

[0332] Furthermore, the clock signal CLK_C and data signal DATA_C, which serve as the light emission control signal SC, are processed by buffer circuits 701, 702, and 714, and then transmitted from connector CN23 to the relay board 800 and decorative board 820, and supplied, for example, to the LED driver mounted on the decorative board 820. A 5V DC voltage (DC5VB) is used as the power supply voltage for processing in buffer circuits 701, 702, and 714.

[0333] Furthermore, the 35V DC voltage (DC35VB) is the power supply voltage for the motor drive unit 760, which corresponds to the MOT35Vx, MOT35Vz, MOT35Vy, and MOT35Vu power supplies (see Figures 19 and 26).

[0334] In other words, 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are used for the lighting effects of LEDs mounted on movable parts. Additionally, 12V DC voltage (DC12VB), 5V DC voltage (DC5VB), and 35V DC voltage (DC35VB) are used to drive the motors and LEDs of the movable parts, and are used for the overall presentation of the movable parts.

[0335] Thus, the 12V DC voltage (DC12VB) used for the LED lighting effects on the movable parts, or for the overall effects of the movable parts, as well as the 5V DC voltage (DC5VB) and 35V DC voltage (DC35VB), are transmitted via different transmission lines, H20a for system a and H20b for system b, respectively.

[0336] For example, as in each of the above examples, the first and second power supply voltages, which are necessary to produce the same "predetermined effect," are transmitted via separate systems, system a and system b, instead of the usual single transmission method. This achieves the effect of (configuration A1-1) described above. Furthermore, by separating the power supply voltages into systems a and b, it is possible to avoid the power supply voltage being concentrated on one side, thus preventing, for example, an excessive current capacity burden on only one of the transmission lines H20a or H20b.

[0337] In particular, if the current capacity load becomes excessive, it becomes necessary to use connectors and wiring (wires) with higher rated currents, which increases the diameter of the wiring (wire diameter) and the size of the connectors. By avoiding an excessive current capacity load, it is possible to avoid increasing the size of connectors CN1a and CN1b, which is advantageous for miniaturizing the connectors and circuit boards, and improving the efficiency of the patterns, as described in (Configuration A1-1).

[0338] (Configuration A2-1) Gaming machine 1 is, A first control unit located at the first position, A second control unit located at the second position, The system includes a transmission line connecting the first control unit and the second control unit, By illuminating the light-emitting means and simultaneously driving a different performance means, a predetermined performance can be executed. The aforementioned transmission line is A first transmission means transmits, via a first connector, a light-emitting control signal for causing the light-emitting means to emit light and a first power supply voltage for driving the light-emitting mechanism. The system includes a second transmission means that transmits a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector separate from the first connector, The amount of current supplied by the first power supply voltage is greater than the amount of current supplied by the second power supply voltage, and the first transmission means has fewer lines than the second transmission means.

[0339] Each component of this (Configuration A2-1) corresponds to the above-mentioned (Specific Example 1). Furthermore, in (Configuration A2-1), in addition to the effects described in (Configuration A1-1), the following effects are obtained.

[0340] The first power supply voltage, 12V DC voltage (DC12VB), is the power supply voltage used by many LEDs and their corresponding LED drivers. For example, the power supply from the performance control board 30 to the LED connection board 700 is designed to supply a maximum of approximately 9A of 12V DC voltage (DC12VB).

[0341] The second power supply voltage, 5V DC voltage (DC5VB), is used in buffer circuits 701, 702, 703, and 709 of the LED connection board 700, as well as in the P / S conversion circuit 704 and the motor control IC in the motor drive unit 760. It is also used in buffer circuits on boards downstream of the LED connection board 700. In short, this 5V DC voltage (DC5VB) is mainly used as the power supply voltage for ICs. For example, the 5V DC voltage (DC5VB) supplied from the performance control board 30 to the LED connection board 700 is designed to supply a maximum of approximately 2A.

[0342] Furthermore, the 35V DC voltage (DC35VB) is used by the motor drive IC in the motor drive unit 760, but for example, the 35V DC voltage (DC35VB) is designed to supply a maximum of approximately 3A from the performance control board 30 to the LED connection board 700.

[0343] Now, looking at the 12V DC voltage (DC12VB), transmission line H20a uses six lines for power transmission. The current capacity required per line of a 12V DC voltage (DC12VB) is 9A / 6 = 1.5A.

[0344] On the other hand, transmission line H20b uses two lines for 5V DC voltage (DC5VB) and three lines for 35V DC voltage. The current capacity required for one line with a 5V DC voltage (DC5VB) is 2A / 2 = 1A. The current capacity required per line with a 35V DC voltage (DC35VB) is 3A / 3 = 1A.

[0345] Therefore, connectors CN1b and CNe1b can be used with a lower rated current than connectors CN1a and CNe1a. The rated current of connectors CN1a and CNe1a shown in Figure 28 is 2A, and the rated current of connectors CN1b and CNe1b shown in Figure 29 is 1A. Furthermore, in the dual transmission example, systems A and B do not each have 20 lines, but rather 16 and 24 lines respectively.

[0346] In this embodiment, when the amount of current flowing through the first power supply voltage of 12V DC (DC12VB) is greater than the amount of current flowing through the second power supply voltage of 5V DC (DC5VB) or 35V DC (DC35VB), the number of lines in system a, which transmits the first power supply voltage, is reduced compared to system b, which transmits the second power supply voltage. In this case, harnesses and connectors with a higher rated current can be used for system a, which is the first transmission means, and harnesses and connectors with a lower rated current can be used for system b, which is the second transmission means.

[0347] Generally, to ensure sufficient current capacity, connectors CN have larger pin diameters and larger housings as the rated current increases.

[0348] For example, if we configure a single transmission system including connectors CN1 and CNe1 in a single-line transmission example, it would require a 40-pin connector and a 40-line harness. However, the rated current would need to be matched to the 12V side, requiring, for example, a connector with a rated current of 1.5A or more. In other words, a connector with at least the specifications shown in Figure 27 would be required, resulting in a larger connector.

[0349] In contrast, in the dual-system transmission example, system a, which transmits a 12V DC voltage (DC12VB), has a rated current of 1.5A or more, while system b can use a system with a rated current of 1A or more, as shown in Figure 29. In system A, by reducing the number of lines, even connectors with a rated current of 1.5A or more can be miniaturized by using a relatively small number of pins. In system B, smaller connectors can be used, allowing for a greater number of tracks. This facilitates miniaturization of connectors CN1a, CNe1a, and connectors CN1b, CNe1b.

[0350] For example, in the case of single-channel transmission, the 40-pin connector CN1 shown in Figure 27 occupies an area of ​​33.7 mm in width and 7.6 mm in height on the LED connection board 700. However, in the case of dual-channel transmission, the 16-pin connector CN1a shown in Figure 28 occupies an area of ​​15.7 mm in width and 7.6 mm in height, and the 24-pin connector CN1b shown in Figure 29 occupies an area of ​​13.2 mm in width and 5.6 mm in height. Thus, even when the two connectors CN1a and CN1b are combined, the area occupied is less than that of the 40-pin connector CN1.

[0351] As a result, for example, the LED connection board 700 has two connectors, a 16-pin connector CN1a and a 24-pin connector CN1b, but the area occupied by the connectors on the board is reduced compared to having a 40-pin connector CN1. In other words, the overall area occupied by connectors on the board can be reduced. This can also facilitate the miniaturization of circuit boards.

[0352] In the example of dual-system transmission, dividing the number of lines for system A and system B into 16 and 24 lines is just one example. Other divisions, such as 12 and 28 lines, are also acceptable. In particular, as can be seen by comparing the connectors in Figures 28 and 29, the connector in Figure 29 is smaller in size than the connector in Figure 28 despite having more lines. In that sense, it is possible to reduce the overall connector footprint even if the number of lines in connector CN1a is further reduced.

[0353] Furthermore, while Figure 28 shows an example of a connector with a rated current of 2A, any connector with a rated current of 1.5A or higher is acceptable, so a smaller connector can be used as connector CN1a. This makes it possible to further reduce the overall area occupied by the connector on the circuit board.

[0354] The gaming machine 1 of this embodiment includes the following (configuration A2-2) in addition to the above (configuration A2-1).

[0355] (Configuration A2-2) The number of transmission lines for the performance control signal in the second transmission means is greater than the number of transmission lines for the light emission control signal in the first transmission means.

[0356] As explained above, in the dual-system transmission example, system a transmits the first set (GP1) as the performance control signal (lighting control signal), while system b transmits the second set (GP2), third set (GP3), and fourth set (GP4) as the performance control signals. In other words, the first transmission means (connector and line of system a) has 3 lines for the performance control signals, and the second transmission means (connector and line of system b) has 11 lines for the performance control signals.

[0357] Even excluding the enable signal LED_ENABLE, clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X, which are not used as performance control signals on the LED connection board 700, the number of lines for performance control signals in the first transmission means (system a) is 2, and the number of lines for performance control signals in the second transmission means (system b) is 8.

[0358] In other words, in any case, the number of transmission lines for the performance control signal in the second transmission means is greater than the number of transmission lines for the light emission control signal in the first transmission means. The performance control signals (including serial data signals for light emission control signals and detection signals) are signals transmitted between ICs, and the current they draw is extremely small compared to LED illumination or motor drive signals. Considering this, each performance control signal can be transmitted through either system a or system b. Therefore, more performance control signals are assigned to the smaller connector with the lower current, thereby realizing the above configuration (A2-1). In other words, the distribution of performance control signals allows for appropriate setting of the number of pins.

[0359] (Configuration A3) Gaming machine 1 is, A first control unit located at the first position, A second control unit located at the second position, The system includes a transmission line connecting the first control unit and the second control unit, By illuminating the light-emitting means and simultaneously driving a different performance means, a predetermined performance can be executed. The aforementioned transmission line is A first transmission means transmits, via a first connector, a light-emitting control signal for causing the light-emitting means to emit light and a first power supply voltage for driving the light-emitting mechanism. The system includes a second transmission means that transmits a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector separate from the first connector, The second connector has more pins and a narrower pin pitch than the first connector.

[0360] Each component of this (Configuration A3) corresponds to (Specific Example 1) mentioned above. Furthermore, in (Configuration A3), in addition to the effects described in (Configuration A1-1), the following effects are obtained.

[0361] As described above, the connectors CN1a and CNe1a in the dual transmission example have a 16-pin configuration with a pin pitch of 1.5 mm. Furthermore, connectors CN1b and CNe1b have a 24-pin configuration with a pin pitch of 1.0 mm.

[0362] As in the example of dual transmission, when using a first transmission means (connector and line of system a) and a second transmission means (connector and line of system b), the connector with a narrower pitch should be used for the side with more transmission lines, i.e., the side with more connector pins. By using a narrower pitch connector for the side with more pins, it is possible to miniaturize the connector.

[0363] Although connectors CN1b and CNe1b have a narrower pitch and therefore lower rated current, the idea is to transmit the first power supply voltage, which requires a higher rated current, using the side with a wider pitch and higher rated current. This enables miniaturization of the connector on the second transmission means side. Furthermore, miniaturization of the connector can also be achieved on the first transmission means side by using a connector with fewer pins.

[0364] (Configuration A4) Gaming machine 1 is, A first control unit located at the first position, A second control unit located at the second position, The system includes a transmission line connecting the first control unit and the second control unit, By illuminating the light-emitting means and simultaneously driving a different performance means, a predetermined performance can be executed. The aforementioned transmission line is A first transmission means transmits, via a first connector, a light-emitting control signal for causing the light-emitting means to emit light and a first power supply voltage for driving the light-emitting mechanism. The system includes a second transmission means that transmits a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector separate from the first connector, The connector of the second transmission means has a lower rated current value than the connector of the first transmission means.

[0365] Each component of this (Configuration A4) corresponds to (Specific Example 1) mentioned above. Furthermore, in (Configuration A4), in addition to the effects described in (Configuration A1-1), the following effects are obtained.

[0366] As described above, in the dual-system transmission example, connectors CN1a and CNe1a have a rated current of 2A, while connectors CN1b and CNe1b have a rated current of 1A.

[0367] As explained in the above description of (Configuration A2-1), when using the first transmission means (connector and line of system a) and the second transmission means (connector and line of system b), it is no longer necessary to make both transmission means compatible with the one with the higher current between the first power supply voltage and the second power supply voltage. Therefore, the second transmission means will have a low rated current value and will transmit a power supply voltage with a small current. This will enable miniaturization of the connectors CN1b and CNe1b on the second transmission means side.

[0368] (Configuration A5-1) Gaming machine 1 is, A first control unit located at the first position, A second control unit located at the second position, The system includes a transmission line connecting the first control unit and the second control unit, By illuminating the light-emitting means and simultaneously driving a different performance means, a predetermined performance can be executed. The aforementioned transmission line is A first transmission means transmits, via a first connector, a light-emitting control signal for causing the light-emitting means to emit light and a first power supply voltage for driving the light-emitting mechanism. The system includes a second transmission means that transmits a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector separate from the first connector, The connector of the second transmission means has a smaller pin cross-sectional size than the connector of the first transmission means.

[0369] Each component of this (Configuration A5-1) corresponds to the above-mentioned (Specific Example 1). Furthermore, in (Configuration A5-1), in addition to the effects described in (Configuration A1-1), the following effects are obtained.

[0370] As mentioned above, the pin diameters of connectors CN1a and CNe1a are 0.6 mm, and the pin diameters of connectors CN1b and CNe1b are 0.5 mm. Since cylindrical pins are assumed, the cross-sectional size of the pins of connectors CN1b and CNe1b of the second transmission means is smaller than that of connectors CN1a and CNe1a of the first transmission means.

[0371] When transmitting the first power supply voltage and the second power supply voltage using the first and second transmission means, respectively, it becomes unnecessary to make both transmission means compatible with the one with the higher current of the two power supply voltages. Therefore, the connector of the second transmission means has smaller pin diameters than the connector of the first transmission means, i.e., a lower current capacity, and is used to transmit power supply voltages with lower currents. This makes it possible to miniaturize the connector of the second transmission means. In particular, connectors CN1a and CNe1a not only have a small current capacity, but also employ a smaller pin cross-sectional size, which allows for more reliable miniaturization and a reduction in the area occupied on the circuit board.

[0372] While connector CN terminals can be cylindrical pins, plate-shaped, or elliptical, considering the cross-sectional size in the direction in which the pins are aligned, and considering it in the direction of the pitch, is advantageous for miniaturizing the connector. Furthermore, considering the current capacity, the cross-sectional size of the pin can be thought of as the cross-sectional area or the maximum size of the cross-section.

[0373] The gaming machine 1 of this embodiment includes the following (configuration A5-2) in addition to the above (configuration A5-1).

[0374] (Configuration A5-2) The diameter of the line in the second transmission means is smaller than the diameter of the line in the first transmission means.

[0375] As shown above (Specific Example 1), the applicable wire range for the railway line wire material is indicated. Connectors CN1a and CNe1a have conductor sizes ranging from AWG28 to AWG24, and the outer diameter of the insulator is 0.76 mm to 1.2 mm. Connectors CN1b and CNe1b have conductor sizes ranging from AWG32 to AWG28, and an insulator outer diameter of 0.4mm to 0.8mm. Within these respective applicable wire ranges, the diameter of the line in the second transmission means can be smaller than the diameter of the line in the first transmission means. For example, the wire connected to connector CN1a may have a diameter of 0.8 mm, and the wire connected to connector CN1b may have a diameter of 0.6 mm.

[0376] As described above, the second transmission means can have a smaller current capacity than the first transmission means, and therefore the wire material for the transmission line can also be made of a smaller diameter. This allows for miniaturization of connectors CN1b and CNe1b, as well as reduction in wire diameter, making it easier to handle.

[0377] (Configuration A6-1) Gaming machine 1 is, A first control unit located at the first position, A second control unit located at the second position, The system includes a transmission line connecting the first control unit and the second control unit, By illuminating the light-emitting means and simultaneously driving a different performance means, a predetermined performance can be executed. The aforementioned transmission line is A first transmission means transmits, via a first connector, a light-emitting control signal for causing the light-emitting means to emit light and a first power supply voltage for driving the light-emitting mechanism. The system includes a second transmission means that transmits a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector separate from the first connector, The second transmission means has a greater number of ground transmission lines than the first transmission means. The aforementioned performance control signal is composed of multiple sets of signal lines, each set consisting of multiple signal lines. The connector of the second transmission means is configured such that some or all of the pins assigned to ground are located between the pins assigned to one set of performance control signals and the pins assigned to another set of performance control signals, when viewed in the longitudinal direction of the connector.

[0378] Each component of this (Configuration A6-1) corresponds to the above-mentioned (Specific Example 1). Furthermore, in (Configuration A6-1), in addition to the effects described in (Configuration A1-1), the following effects are obtained.

[0379] In the dual-system transmission example, the first transmission means (connector and line of system a) has 7 ground lines, and the second transmission means (connector and line of system b) has 8 ground lines.

[0380] The performance control signals are composed of multiple sets of signal lines, each consisting of multiple signal lines, as shown in sets 1 through 4 (GP1 through GP4).

[0381] Furthermore, the performance control signals transmitted through multiple signal lines that constitute a single set can be considered as a set of signals related to the same IC chip. Examples include multiple performance control signals that are input to the same IC chip and control that IC chip, or multiple performance control signals that become input and output signals for the same IC chip.

[0382] For example, the clock signal LED_CLK and data signal LED_DATA, which are the signals of the first pair (GP1), are input to the same chip such as the LED driver 705 or 707. Note that the enable signal LED_ENABLE is not used in LED drivers such as the 705 or 707 and is therefore considered unused. However, depending on the type of driver, the enable signal LED_ENABLE is also input to the same LED driver as the clock signal LED_CLK and data signal LED_DATA, so in terms of the transmission path, G can be treated as a pair.

[0383] Following a similar line of reasoning, the second set (GP2) of signals—the clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST—are a set of control signals for the motor control IC. Furthermore, the load signal S_IN_LOAD, clock signal S_IN_CLK, and serial data signal S_IN_DATA of the fourth set (GP4) are a set of control signals for the P / S conversion circuit 704. Although the third set (GP3) consisting of the clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X is not used in this embodiment, it can be considered as a set because it is used in some models and becomes a signal for a certain IC.

[0384] The connectors CN1b and CNe1b of the second transmission means are configured such that some of the pins assigned to ground are located between the pins assigned to one set of performance control signals and the pins assigned to the other set of performance control signals when viewed in the longitudinal direction of the connectors CN1b and CNe1b.

[0385] In other words, as shown in Figure 16, in the odd-numbered pin rows of connectors CN1b and CNe1b, the second set of performance control signals (GP2) are arranged from pin 7 to pin 15, and with the ground pin 17 in between, the fourth set of performance control signals (GP4) are arranged from pin 19 to pin 23.

[0386] By placing a ground pin between the pins of one set of performance control signals and the pins of another set of performance control signals, the sets of performance control signals can be separated via the ground, thereby reducing crosstalk noise between each set. For example, as shown in Figure 16, the presence of a ground pin between the second set (GP2), which is a set of control signals for motor LSIs, and the fourth set (GP4), which is a set of serial signals for transmitting detection signals from various sensors, can reduce crosstalk between these different sets of signals.

[0387] Furthermore, among the control signals for each set of signals, the clock signal has the greatest potential to affect other sets as high-frequency noise. Therefore, as shown in Figure 16, it is advisable to separate the clock signal LSI_CLK of the second set (GP2) from the fourth set, and the clock signal S_IN_CLK of the fourth set (GP4) from the second set (GP2), with a ground connection. In other words, it is desirable not to assign clock signals to pins 15 and 19, which are adjacent to the ground terminal of pin 17. This will greatly reduce crosstalk.

[0388] Furthermore, odd-numbered and even-numbered rows are physically sufficiently far apart. For example, looking at the pad arrangement in the lower part of Figure 29, it can be seen that the pins in the odd-numbered rows and the pins in the even-numbered rows are far apart. Therefore, crosstalk between adjacent terminals in odd-numbered and even-numbered rows is hardly a problem. It is only effective to place grounds between pairs of pins in the longitudinal direction.

[0389] In the example shown in Figure 16, one of the 17th pins is used as the ground terminal between the second pair (GP2) and the fourth pair (GP4). However, multiple pins can be used as ground terminals in the longitudinal direction to further separate the second pair (GP2) and the fourth pair (GP4).

[0390] By the way, Figures 34A and 34B show other assignment examples for the b-system connectors CN1b and CNe1b. This is an example where the third set (GP3) and the fourth set (GP4) in Figure 16 are swapped. Figure 34A shows the pin assignments from pin 1 to pin 24, and Figure 34B shows the actual arrangement in connectors CN1b and CNe1b.

[0391] For the third group (GP3), assign the clear signal CLR_X to pin 19, the data signal DATA_X to pin 21, and the latch signal LATCH_X to pin 23. For the fourth group (GP4), assign the load signal S_IN_LOAD to pin 20, the clock signal S_IN_CLK to pin 22, and the serial data signal S_IN_DATA to pin 24.

[0392] In this embodiment, the third set of clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X were left unused. However, a circuit configuration that utilizes these signals may be adopted, for example, in the LED connection board 700. For example, the third set of performance control signals may be used as motor drive control signals to a motor driver for motor control without using an LSI. In that case, if the second group (GP2) and the third group (GP3) are in the same row as shown in Figure 34B, it is effective to use pin 17 as the ground terminal to obtain a crosstalk reduction effect between the second group (GP2) and the third group (GP3).

[0393] Furthermore, in this embodiment, only the first set (GP1) is transmitted in system a. However, if multiple sets are to be transmitted in system a, it is advisable to interpose ground terminals between sets of performance control signals that are arranged longitudinally on the connector CN1a and CNe1a sides. As explained earlier in Figure 16, the ground for system a and the ground for system b are shared, and it is possible to consolidate the ground into either the system a or system b harness. However, by separating the ground for system a and the ground for system b, the above noise countermeasures can be implemented in both systems a and b. For example, in the example in Figure 16, only the first set (GP1) of performance control signals is transmitted in system a, but it may be assigned to transmit multiple sets of performance control signals. In that case, in system a as well, it is best to position some or all of the pins assigned to ground between the pins of the performance control signal sets when viewed along the longitudinal direction of the connector.

[0394] The gaming machine 1 of this embodiment includes the following (configuration A6-2) in addition to the above (configuration A6-1).

[0395] (Configuration A6-2) The number of transmission lines for the performance control signal in the second transmission means is greater than the number of transmission lines for the light emission control signal in the first transmission means.

[0396] As described above, in the dual-system transmission example, system a transmits the first set (GP1) as the performance control signal (lighting control signal), while system b transmits the second set (GP2), the third set (GP3), and the fourth set (GP4) as the performance control signals. In other words, the first transmission means (connector and line of system a) has 3 lines for the performance control signals, and the second transmission means (connector and line of system b) has 11 lines for the performance control signals. Even excluding unused signals, the first transmission means (system a) has 2 lines for performance control signals, and the second transmission means (system b) has 8 lines for performance control signals.

[0397] In such cases, it is highly effective to separate the performance control signals on the b system, which has many performance control signals, by using a ground connection.

[0398] The gaming machine 1 of this embodiment includes the following (configuration A6-3) in addition to the above-described (configuration A6-1) or (configuration A6-2).

[0399] (Configuration A6-3) The first power supply voltage and the second power supply voltage are power supply voltages used to produce the predetermined effects.

[0400] As explained above in (Configuration A1-2), one example of a predetermined effect in this case is the illumination effect of decorative LEDs as a means of effect. Another example of a designated effect is the use of LEDs installed on movable parts of a game machine. Furthermore, the specified effects can also refer to the overall effects of a movable mechanism. For example, this could include the motor-driven operation of the movable mechanism and the illumination of LEDs mounted on it.

[0401] While I will avoid repeating specific examples, as in each of the above examples, the first and second power supply voltages, which are necessary to produce the same "predetermined effect," are transmitted via separate systems, system a and system b, instead of the usual single transmission method. By separating the power supply voltages into systems a and b, it is possible to avoid the power supply voltage being concentrated on one side, thus preventing, for example, an excessive current capacity burden on only one of the transmission lines H20a or H20b. This is advantageous for miniaturizing connectors and circuit boards, and improving pattern efficiency.

[0402] (Configuration B1-1) Gaming machine 1 is, First circuit board and A second board to which a power supply voltage is supplied from the first board, It has, On the second substrate, the power supply voltage terminal of the connector that makes an electrical connection with the first substrate is connected to a noise suppression means, and a test point of the power supply voltage wiring pattern on the substrate is provided between the power supply voltage terminal and the noise suppression means.

[0403] In this case (configuration B1-1), the following corresponding example (specific example 2) can be assumed. (Specific example 2) • First circuit board: Performance control board 30 • Second board: LED connection board 700 • Connector: Connector CN1 • Power supply voltage: 12V DC (DC12VB), 5V DC (DC5VB) • Power supply voltage terminals: The 12V DC voltage (DC12VB) terminals (pins 12, 14, 24, 26, 28, and 30) and the 5V DC voltage (DC5VB) terminals (pins 4 and 6) of connector CN1 in Figure 14. • Noise suppression means: Capacitors C1, C4, Capacitors C2, C3 • Test points: Test points TP51, TP50

[0404] The LED connection board 700 is supplied with a power supply voltage of 12V DC (DC12VB) or 5V DC (DC5VB) from the performance control board 30. The 12V DC voltage (DC12VB) terminals on connector CN1 of the LED connection board 700, specifically pins 12, 14, 24, 26, 28, and 30, are connected to capacitor C4, and test point TP51 ​​is provided in the connection path. Furthermore, pins 4 and 6 of connector CN1, which are terminals for 5V DC voltage (DC5VB), are connected to capacitor C3, and test point TP50 is provided in the connection path.

[0405] The actual circuit board pattern for the circuit configuration shown in Figure 20 is explained. The wiring patterns of the LED connection board 700 are shown in Figure 35 for the surface layer, Figure 36 for the back layer, Figure 37 for the first inner layer, and Figure 38 for the second inner layer. Figure 39 is a magnified view of area AR1 in the surface layer of Figure 35, and Figure 41 is a magnified view of area AR2. Figure 42 is a magnified view of area AR3 in the back layer of Figure 36.

[0406] Furthermore, the wiring patterns of the back layer in Figure 36, the first inner layer in Figure 37, and the second inner layer in Figure 38 are all shown in a transparent view from the side of the front layer in Figure 35. Therefore, Figure 36 shows a mirror-reverse view of the back layer of the actual LED connection board 700 as it would appear when viewed.

[0407] In each of these diagrams, the gray-colored areas represent conductive pattern wiring, and the white-outlined squares represent pads where electronic component terminals are soldered. The uncolored areas other than the pads are insulating areas where no conductive pattern is formed. The black circles represent holes, such as through-holes or vias. Areas where the gray area surrounding a black circle indicate that the wiring pattern on that surface and the via (or through-hole) are electrically connected. Areas where the black circle has an uncolored area around it indicate that the surrounding conductive pattern and the via are insulated. Areas with circles drawn on a gray background represent conductive areas such as test points and pads.

[0408] Although through-holes and vias are strictly distinguished, in this embodiment, they are collectively referred to as "vias" in the sense of interlayer conductivity. "Vias" are a general term for through-hole vias, blind vias, pellet vias, etc.

[0409] Furthermore, the symbols in each figure are the same as those used in the circuit diagrams shown in Figures 20, 22 to 26, with "p" added before them to indicate the location of those components. For example, "pCN1" indicates the location where connector CN1 is located, and "p701" indicates the location where buffer circuit 701 is located. In the following text, the circuit diagrams shown in Figures 20, 22 through 26 will simply be referred to as "circuit diagrams."

[0410] As shown in Figure 35, the surface layer has connectors CN1, CN2, CN3, etc., positioned at pCN1, pCN2, pCN3, etc. Furthermore, the buffer circuits 701, 702, and 703 shown in Figure 20, the P / S conversion circuit 704, and the LED driver 707 shown in Figure 23 are arranged on the surface layer at positions p701, p702, p703, p704, and p707, respectively. Furthermore, the buffer circuits 708, 717, and 718 shown in Figure 24 are arranged on the surface layer at positions p708, p717, and p718, respectively. Furthermore, the buffer circuit 714 shown in Figure 25 is positioned at position p714 on the surface layer.

[0411] Although the circuit diagram is not shown on the back layer of Figure 36, the motor control IC (motor controller) in the motor drive unit 760 of Figure 19 is located at position p710, and the four motor drive ICs (motor drivers) are located at positions p712, p713, p715, and p716. In addition, the buffer circuit 709 shown in Figure 19 is located at position p709. Furthermore, on the back surface layer, the LED driver 705 shown in Figure 22 is positioned at position p705.

[0412] The first inner layer in Figure 37 is the layer on which the solid power supply pattern is formed, with the PT5V pattern for 5V DC voltage (DC5VB) and the PT12V pattern for 12V DC voltage (DC12VB) being formed. Additionally, the PT35Va and PT35Vb patterns for 35V DC voltage (DC35VB) are formed. The second inner layer in Figure 38 is a layer in which the ground pattern PTg was formed as a solid ground.

[0413] Figure 39 provides an enlarged view of area AR1, which surrounds connector CN1 (position pCN1). At position pCN1 in the lower center of Figure 39, 40 pads (20 in each of two rows) are formed, corresponding to each terminal of the 40-pin connector CN1. For the sake of explanation, the diagram shows numerical values ​​such as "1" to "40" corresponding to the pin numbers, placed near the 1st to 40th pins (see Figure 14 for the pin assignment of connector CN1).

[0414] First, let's explain the ground wiring. On the surface layer, a ground pattern PTg is formed as a solid ground plane, covering almost the entire surface of the substrate. The pads corresponding to pins 1, 2, 8, 9, 10, 16, 18, 19, 20, 22, 29, 32, 33, 34, 39, and 40 of connector CN1 are connected to the ground pattern PTg. The ground pattern PTg is connected to the ground pattern PTg of the second inner layer by numerous vias.

[0415] The pads at pins 12, 14, 24, 26, 28, and 30, which are supplied with a 12V DC voltage (DC12VB), are connected to the power supply pattern PT12V. The power supply pattern PT12V continues to the distant power supply pattern PT12V (also called power supply pattern PT12Va for distinction) via fuse FZ2 (position pFZ2). The power supply pattern PT12Va has pads formed where capacitors C1 and C4 are placed (positions pC1 and pC4). Additionally, pattern PT12Va is provided with four vias BR3, which are connected to the first inner layer power supply pattern PT12V in Figure 37. Additionally, in pattern PT12Va, a test point TP51 ​​is provided near via BR3.

[0416] The pads of pins 4 and 6 of connector CN1, which are supplied with a 5V DC voltage (DC5VB), are connected to power supply pattern PT5V. Power supply pattern PT5V continues to another power supply pattern PT5V (also called power supply pattern PT5Va for distinction) via fuse FZ1 (position pFZ1). Power supply pattern PT5Va has pads formed where capacitors C2 and C3 are placed (positions pC2, pC3). Additionally, power supply pattern PT5Va is provided with two vias BR1, which are connected to the first inner layer power supply pattern PT5V in Figure 37. Additionally, in the power supply pattern PT5Va, test point TP50 is provided near via BR1.

[0417] The pads of pins 36 and 38 of connector CN1, to which a 35V DC voltage (DC35VB) is supplied, are connected to the power supply pattern PT35V. Pads for Schottky barrier diodes D10 and D11, as shown in Figure 26, are formed on the power supply pattern PT35V (positions pD10, pD11). Power supply pattern PT35V is connected to two separate power supply patterns PT35V (PT35Va, PT35Vb) via Schottky barrier diodes D10 and D11.

[0418] The power supply pattern PT35Va has a pad for electrolytic capacitor C57 (position pC57) and four vias BR4. This power supply pattern PT35Va is connected to the first inner layer power supply pattern PT35Va in Figure 37 via the vias BR4. Furthermore, the power supply pattern PT35Vb in Figure 39 has a pad for an electrolytic capacitor C63 (position pC63) and four vias BR5. This power supply pattern PT35Vb is connected to the first inner layer power supply pattern PT35Vb in Figure 37 via the vias BR5.

[0419] The power supply pattern PT35Va, which reaches the first inner layer in Figure 37, is connected to fuses FZ3 and FZ4 shown in Figure 26. The power supply pattern PT35Vb is connected to fuses FZ5 and FZ6 in Figure 26. Specifically, as shown in Figures 37 and 35, vias BR6 and BR9 are formed in the power supply pattern PT35Va, and vias BR7 and BR8 are formed in the power supply pattern PT35Vb, and are connected to the surface layer, respectively. Then, as shown in Figure 35, fuses FZ3, FZ4, FZ5, and FZ6 are placed at positions pFZ3, pFZ4, pFZ5, and pFZ6, respectively, forming the circuit shown in Figure 26.

[0420] We have explained the wiring pattern of the LED connection board 700 up to this point. As can be seen from the circuit diagram and wiring pattern, a test point TP51 ​​is provided between the 12V DC voltage (DC12VB) terminal of connector CN1 and the noise suppression capacitors C1 and C4. Furthermore, a test point TP50 is provided between the 5V DC voltage (DC5VB) terminal of connector CN1 and the noise suppression capacitors C2 and C3.

[0421] Various test points are provided on the circuit board, and by providing test points for the power supply voltage wiring, the stability of the power supply voltage transmitted from other circuit boards can be checked. Ideally, the power supply voltage should be constant along the power supply pattern on the circuit board, but in reality, this is not always the case. Therefore, test points are set between the connector terminals and the noise suppression means for the 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) transmitted from the performance control board 30. This allows for the most accurate detection of the power supply voltage state at the input stage. Consequently, this is most suitable for checking the power supply voltage transmission status between boards.

[0422] In terms of circuitry, setting a test point between the connector terminals and the noise suppression means setting the test point at a location that does not involve electronic components such as resistors, capacitors, or IC chips, excluding fuses (FZ1, FZ2) that normally do not affect voltage or current, when viewed from the power terminals of the connector. The noise suppression means referred to here is the capacitor (C1, C4, or C2, C3) connected between the power line and ground. Therefore, test points TP51 ​​and TP50 are designed to detect the power supply voltage state at the input stage without being affected by electronic components.

[0423] Furthermore, if a fuse is placed between the connector terminal and the noise suppression means, it is more appropriate to set the test point closer to the noise suppression means than the fuse (FZ1, FZ2) in order to detect the state of the power supply voltage input stage that is actually applied to each circuit on the board.

[0424] While it is technically possible to set up a test point between the connector terminals and the noise suppression means in terms of circuitry, in terms of physical location on the circuit board, it is best to set up the test point as far away from the connector as possible on the wiring between the connector terminals and the noise suppression means.

[0425] For example, test point TP51, circuit-wise, would be placed somewhere on the power supply pattern PT12V (including PT12Va) between the connector terminal and the noise suppression means, but it is specifically placed on the power supply pattern PT12Va, away from connector CN1. Furthermore, while test point TP51 ​​can be placed anywhere on the power supply pattern PT5V (including PT5Va) circuit-wise, it is specifically placed on the power supply pattern PT5Va, away from connector CN1.

[0426] Connector CN is one of the taller electronic components mounted on a circuit board. If test points are placed too close to the connector CN, it can become difficult for the test equipment's probe to reach them. As shown in the example above, by placing test points TP51 ​​and TP50 as far away from connector CN1 as possible, it becomes easier to apply the probe. Specifically, for example, it is advisable to place test points at a distance of at least half the shortest straight-line distance between the connector and the furthest point of the pattern area where test points can be placed, relative to the connector CN. Test points TP51 ​​and TP50 in Figure 39 satisfy this condition.

[0427] By the way, a test point refers to a part of the circuit board where an insulating protective film is not formed and electrical conductivity with the wiring pattern is possible. Specific examples of test points include those formed as pads, those where a portion of a wiring pattern is a circular pad, those formed as conductive parts around vias, and those formed by building up solder. For example, the circular sections in the wiring leading to the pads such as the 3rd and 5th pins of connector CN1 in Figure 39 correspond to the test points TP1, TP2, etc. in Figure 20. Regardless of the form, any conductive area on a substrate with an insulating coating that can be tested by applying a probe can serve as a test point.

[0428] Note that the wiring patterns in Figures 35 to 39 correspond to the circuit in Figure 20. However, even in the case of the circuit in Figure 21, test points TP51 ​​and TP50 are similarly placed between the power supply voltage terminals of connectors CN1a and CN1b and the noise suppression capacitors (C1, C4, or C2, C3). Therefore, the same effect as described above can be obtained in the circuit example in Figure 21. The following configurations (B1-2) through (C7) will also be explained using the circuit and pattern examples in Figure 20, but they are also applicable to the circuit in Figure 21.

[0429] The gaming machine 1 of this embodiment includes the following (configuration B1-2) in addition to the above (configuration B1-1).

[0430] (Configuration B1-2) On the second substrate, the ground terminal of the connector is also connected to the noise suppression means, and a test point for the ground wiring pattern on the substrate is provided between the ground terminal and the noise suppression means.

[0431] The noise suppression capacitors (C1, C4) are placed between the power supply pattern PT12V and the ground pattern PTg. Furthermore, the capacitors (C2, C3), which serve as noise suppression measures, are placed between the power supply pattern PT5V and the ground pattern PTg. As described above, the ground terminal in connector CN1 is connected to the ground pattern PTg. In other words, on the LED connection board 700, the ground terminal of connector CN1 is also connected to the noise suppression means.

[0432] For example, as shown in the lower center of Figure 39, a test point TP30 is formed on the ground pattern PTg. This test point TP30 is located between the ground terminal of connector CN1 and the noise suppression means (C1, C4, or C2, C3).

[0433] This configuration allows for testing of the 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) transmitted from the performance control board 30 at the most suitable location for checking the transmitted power supply voltage, both on the power line side and the ground side.

[0434] The gaming machine 1 of this embodiment includes the following (configuration B1-3) in addition to the above-described (configuration B1-1) or (configuration B1-2).

[0435] (Configuration B1-3) The aforementioned test points are of the pad type and are located on the mounting surface of the connector.

[0436] In this context, "pad type" refers to a type formed on the surface of a circuit board in a circular, rectangular, or other shape, which serves as a conductive area to which a probe can be applied, and is not a hole such as a via.

[0437] Figure 40A shows an enlarged view of the test point TP50 in Figure 39. The test point TP50 in Figure 40A is a pad type. For example, a circular area is formed as a conductive portion on the substrate surface and does not form a via to another layer. Test point TP51 ​​in Figure 39 is also a similar pad type.

[0438] On the other hand, Figures 40B and 40C show an example where test point TP50 is a land-type structure around a via. Figure 40B shows an example where via BR1 and the surrounding land are used as test point TP50 as conductive areas without surface insulation treatment on the substrate surface. Figure 40C shows an example where only the land on the upper surface of via BR1 is left uninsulated, resulting in a conductive area designated as test point TP50. Figures 40B and 40C show examples of using vias to form test points.

[0439] As described above, the test points may be land-type or formed using the top surface of a via. However, in Figure 39, test points TP51 ​​and TP50 are shown as pad-type, as in Figure 40A, rather than being via-top type. In particular, the wiring around the connectors is densely packed, and there are many interlayer connections. By making test points TP51 ​​and TP50 pad-type, it is possible to avoid affecting the wiring patterns of the back layer and inner layers.

[0440] By the way, the test points TP1 to TP10 shown in Figures 20 and 21 are test points for each performance control signal, and as shown in Figure 39, they are provided as pads on the mounting side of connector CN1. Note that in Figure 39, only the symbols "TP1," "TP2," and "TP10" are shown to avoid making the diagram more complex. In the case of connector CN1, test points TP1 to TP10 are arranged in ascending order of the connector's terminal numbers, so please understand the positions of test points TP3 to TP9 as circular pad portions on the wiring path in the diagram. That is, test points TP3 to TP9 are the circular pad portions on the wiring following the pads for pins 7, 11, 13, 15, 23, 31, and 35.

[0441] These test points TP1 to TP10 are also pad-type, and when they are placed around the connector, using a pad type prevents them from affecting the wiring patterns on the back layer or inner layer.

[0442] Furthermore, test points TP1 to TP10 are located relatively close to the position pCN1 where connector CN1 is positioned. For example, they are located closer to connector CN1 than the center, based on the wiring length from the terminal pads of connector CN1 to buffer circuit 701 or 703. As mentioned earlier, the test point TP has the advantage of being easier to probe by being located away from the connector CN, which is a relatively tall component, but this is contradicted by the fact that it is located away from the connector CN.

[0443] This is because test points TP1 to TP10 are test points related to each effect control signal. By positioning the test points related to effect control signals as close to connector CN1 as possible, it becomes easier to understand the correspondence with the terminal numbers. In other words, it becomes easier for the operator to distinguish which effect control signals need to be tested. Furthermore, since power supply and ground patterns are easily identifiable on the circuit board, it is best to keep them away from connectors and other components as described above to make it easier to apply the probe.

[0444] Furthermore, by not providing test points for the unused terminals on connector CN1—pins 17, 21, 25, and 27—the complexity of the mounting pattern can be reduced.

[0445] (Configuration B2-1) Gaming machine 1 is, First circuit board and A second board to which control signals are supplied from the first board, It has, The second substrate is The IC chip to which the aforementioned control signal is input, One or more noise suppression means for the control signal, The system includes a test point formed in the wiring pattern between one or more of the noise suppression means, the one provided closest to the IC chip on the wiring path, and the input terminal of the control signal of the IC chip.

[0446] In this case (configuration B2-1), the following corresponding example (specific example 3) can be assumed. (Specific example 3) • First circuit board: Performance control board 30 • Second board: LED connection board 700 • Control signals: Clock signal LED_CLK (CLK_A), Data signal LED_DATA (DATA_A) • IC chip: LED driver 705, 707 • One or more noise suppression means: Buffer circuits 701, 702 • Noise suppression means located closest to the IC chip: Buffer circuit 702 • Input terminals: LED drivers 705 and 707, terminals 48 (SCLK) and 47 (SDATA) • Test points: Test points TP11, TP12, TP15, TP16

[0447] The clock signal LED_CLK and data signal LED_DATA are transmitted from the performance control board 30 to the LED connection board 700, where they are waveform-shaped by buffer circuits 701 and 702 and input to the LED drivers 705 and 707 as the clock signal CLK_A and data signal DATA_A, respectively. As can be seen from Figures 20 (or 21) and 22, test point TP11 is located on the wiring of the data signal DATA_A between the buffer circuit 702 and the LED driver 707. Test point TP12 is located on the wiring of the clock signal CLK_A between the buffer circuit 702 and the LED driver 707.

[0448] Furthermore, as can be seen from Figure 20 (or Figure 21) and Figure 23, test point TP15 is located on the wiring of the data signal DATA_A between the buffer circuit 702 and the LED driver 707. Test point TP16 is located on the wiring of the clock signal CLK_A between the buffer circuit 702 and the LED driver 707.

[0449] Figure 42 is an enlarged view of area AR3 on the back surface of Figure 36. As shown, at position p705 where the LED driver 705 is located, test point TP11 is formed on the wiring between pad Pd47, which corresponds to terminal 47 (SDATA), and via BR21, and test point TP12 is formed on the wiring between pad Pd48, which corresponds to terminal 48 (SCLK), and via BR22.

[0450] Figure 41 is an enlarged view of area AR2 in the surface layer of Figure 35. As shown, at position p707 where the LED driver 707 is located, test point TP15 is formed on the wiring between pad Pd47, which corresponds to terminal 47 (SDATA), and via BR25, and test point TP16 is formed on the wiring between pad Pd48, which corresponds to terminal 48 (SCLK), and via BR26.

[0451] Vias BR21 and BR25 are connected to terminal 17 (Y2) of buffer circuit 702, and vias BR22 and BR26 are connected to terminal 18 (Y1) of buffer circuit 702.

[0452] In other words, with this configuration, the data signal DATA_A and the clock signal CLK_A, which are input to the LED drivers 705 and 707 and whose waveforms have been shaped and noise suppressed by buffer circuits 701 and 702, can be observed at test points TP11, TP12, TP15, and TP16. This means that the signals themselves that are input to the IC chip can be inspected, making it the most suitable for checking control signals.

[0453] The gaming machine 1 of this embodiment includes the following (configuration B2-2) in addition to the above (configuration B2-1).

[0454] (Configuration B2-2) The aforementioned test points are of the pad type and are located on the mounting surface of the IC chip.

[0455] As shown in Figures 41 and 42, test points TP11, TP12, TP15, and TP16 are formed as pads. As explained in (Configuration B1-2), using pads prevents test points TP from affecting the wiring patterns of other layers. Pads are particularly suitable around IC chips such as LED drivers 705 and 707, where wiring is dense and there are many interlayer connections. Furthermore, by using the IC chip mounting surface, the relationship between the probe and the IC chip's terminals is easily visible when applying the probe.

[0456] The gaming machine 1 of this embodiment includes the following (configuration B2-3) in addition to the above-described (configuration B2-1) or (configuration B2-2).

[0457] (Configuration B2-3) The aforementioned control signals include a set of multiple control signals that are input to the same IC chip. In the second substrate, the test points for each of the multiple control signals that make up a set are arranged on the same plane.

[0458] As illustrated earlier with the first group (GP1), second group (GP2), and fourth group (GP4), multiple control signals are arranged in pairs. The control signals for the first set (GP1) are the clock signal LED_CLK and the data signal LED_DATA (in this embodiment, the enable signal LED_ENABLE is not used). For the clock signal LED_CLK, test point TP5 is provided on the wiring from pin 13 of connector CN1, and for the data signal LED_DATA, test point TP6 is provided on the wiring from pin 15. These test points TP5 and TP6 are provided on the surface layer of the LED connection board 700 as shown in Figure 39 (indicated by no sign in the figure).

[0459] Test points TP1, TP2, TP3, TP9, and TP10 for the control signals of the second set (GP2)—the clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST—are also provided on the surface layer of the LED connection board 700. Test points TP4, TP7, and TP8 for the load signal S_IN_LOAD, clock signal S_IN_CLK, and serial data signal S_IN_DATA, which are the control signals for the fourth set (GP4), are also provided on the surface layer of the LED connection board 700.

[0460] In this way, the test points for each of the multiple control signals in a set are located on the same plane. This makes it easier for the operator to check each control signal that makes up the same set. In this embodiment, test points TP1 to TP10 are all formed on the surface layer as shown in Figure 39. However, by forming them on the mounting surface of connector CN1, it becomes easier to distinguish each control signal in relation to the terminals. However, some or all of the sets may be formed on the back layer. Having test points for multiple performance control signals of the same set on the same surface makes the checking process easier.

[0461] (Composition B3-1) Gaming machine 1 is, The first substrate is a multilayer substrate having a surface layer, a back layer, and one or more inner layers. The aforementioned first substrate is The inner layer is provided with a power voltage pattern to which the power voltage terminals of a connector attached to the surface layer or the back layer are connected, and a ground pattern to which the ground terminal of the connector is connected. A test point in either the power supply voltage pattern or the ground pattern is provided in the surface layer or the back layer near an interlayer conductive portion for electrical connection with the inner layer.

[0462] In this case (configuration B3-1), the following corresponding example (specific example 4) can be assumed. (Specific example 4) • First board: LED connection board 700 • Connector: Connector CN1 • Power supply patterns: PT12V, PT5V • Ground pattern: Ground pattern PTg • Test points: Test points TP51, TP50

[0463] As described above, test point TP51 ​​is located on power supply pattern PT12V (PT12Va), and test point TP50 is located on power supply pattern PT5V (PT5Va). These are located on the surface layer shown in Figure 35. Note that although the surface in Figure 35 is referred to as the "surface layer" for explanatory purposes, this is simply one side of the LED connection substrate 700. If the surface in Figure 36 is called the "surface layer," then the surface in Figure 35 becomes the back layer. In that sense, "the surface layer or the back layer" in (Configuration B3-1) refers to the surface that becomes the surface of the substrate, and not an inner layer.

[0464] In Figure 37, the first inner layer has power supply patterns PT12V and PT5V formed on it, and in Figure 38, the second inner layer has a ground pattern PTg formed on it. Test point TP50 is located near via BR1, which is an interlayer conductive portion connecting the power supply pattern PT5V of the first inner layer and the power supply pattern PT5V of the surface layer (see Figures 39 and 40A). Furthermore, test point TP51 ​​is located near via BR3, which is an interlayer conductive portion connecting the power supply pattern PT12V of the first inner layer and the power supply pattern PT12V of the surface layer (see Figure 39).

[0465] With this configuration, test points TP50 and TP51 ​​are suitable for checking the power supply status on the inner layer side at the boundary between the surface layer (or back layer) and the inner layer.

[0466] In particular, test point TP50 is near via BR1, which connects the power supply pattern PT5V in the surface layer and the first inner layer. Furthermore, test point TP51 ​​is near via BR3, which connects the power supply pattern PT12V in the surface layer and the first inner layer. This eliminates the need to specifically create test point vias from the first inner layer for checking the first inner layer, thus streamlining the circuit board pattern configuration.

[0467] Regarding the ground, as shown in Figure 39, a test point TP30 is provided near via BR35. This allows the ground on the inner layer side to be checked at the boundary between the surface layer (or back layer) and the inner layer using test point TP30.

[0468] Furthermore, power and ground patterns are often made up of thick patterns or solid planes even in the surface layer. By placing test points near vias in a wide area of ​​these conductive pattern connections, the visibility of the test points is improved.

[0469] The gaming machine 1 of this embodiment includes the following (configuration B3-2) in addition to the above (configuration B3-1).

[0470] (Composition B3-2) The test points are either pad-type near the interlayer conductive portion or land-type around the interlayer conductive portion.

[0471] In the example shown in Figure 39, test point TP50 is provided as a pad type near via BR1, as shown in Figure 40A. This allows for the formation of a test point that does not affect the patterns of other layers. The same applies to test points TP51 ​​and TP30.

[0472] On the other hand, test point TP50 may be made by utilizing the land portion on the upper surface of via BR1, as shown in Figures 40B and 40C. This eliminates the need to provide test point TP50 separately from the via, and further streamlines the pattern configuration of the circuit board. Similarly, test point TP51 ​​may be formed on the land portion on the upper surface of via BR3. Furthermore, the test point TP30 of the ground pattern PTg may be formed using the land portion of via BR35, rather than being located near via BR35.

[0473] (Configuration C1) Gaming machine 1 is, First circuit board and A second board to which a power supply voltage is supplied from the first board, Equipped with, The second substrate is A connector that receives the power supply voltage from the first substrate, Chip-type fuses and It has, The fuse is the element closest in terms of wiring to the power supply voltage terminal in the connector.

[0474] In this case (configuration C1), the following corresponding example (specific example 5) can be assumed. (Specific example 5) • First circuit board: Performance control board 30 • Second board: LED connection board 700 • Connector: Connector CN1 • Power supply voltage: 12V DC (DC12VB), 5V DC (DC5VB) • Power supply voltage terminals: The 12V DC voltage (DC12VB) terminals (pins 12, 14, 24, 26, 28, and 30) and the 5V DC voltage (DC5VB) terminals (pins 4 and 6) of connector CN1 in Figure 14. • Fuses: FZ2, FZ1

[0475] In the LED connection board 700, fuses FZ1 and FZ2 are located at positions pFZ1 and pFZ2, respectively, as shown in Figure 39. As can be seen from the pads at positions pFZ1 and pFZ2, fuses FZ1 and FZ2 are surface-mount chip-type fuses.

[0476] For example, Figure 43 shows an example of the appearance of a rectangular chip fuse FZc that can be used as fuses FZ1 and FZ2. This rectangular chip fuse FZc has external electrodes 1101 and 1102 connected to a pad, and has a structure that contains a fuse-cutting element inside.

[0477] Furthermore, fuse FZ1 is considered to be the component closest in terms of wiring to the 5V DC voltage (DC5VB) terminal on connector CN1. Furthermore, fuse FZ2 is considered to be the component closest in terms of wiring to the 12V DC voltage (DC12VB) terminal on connector CN1.

[0478] Furthermore, the 5V DC voltage (DC5VB) and 12V DC voltage (DC12VB) are also transmitted from the LED connection board 700 to the downstream boards. On the other hand, the 35V DC voltage (DC35VB) is used by the motor drive unit 760 on the LED connection board 700, but it is not transmitted to downstream boards.

[0479] The fuses FZ1 and FZ2, which are positioned for 5V DC voltage (DC5VB) and 12V DC voltage (DC12VB), are located immediately after connector CN1 on the LED connection board 700. In other words, fuses FZ1 and FZ2 are located as far upstream as possible on the LED connection board 700, excluding connector CN1, and are electrically closest to the performance control board 30.

[0480] The LED connection board 700 is located directly below the performance control board 30 in the game board 3, and multiple performance control boards are connected downstream of the LED connection board 700. As a result, fuses FZ1 and FZ2 are located downstream of the performance control board 30, at the very top of the numerous boards in the performance system.

[0481] Therefore, it functions most appropriately as a protective circuit to protect the performance control board 30 in the event of a short circuit downstream of the LED connection board 700. This is because, in the game board 3, no matter where a short circuit occurs downstream of the LED connection board 700, the performance control board 30 will not be affected due to the blowing of fuses FZ1 and FZ2.

[0482] Since fuses FZ1 and FZ2 are chip type, if they blow, the LED connection board 700 itself will need to be replaced, but the expensive upstream performance control board 30 will not need to be replaced. Normally, in gaming machine 1, the performance control board 30 is housed inside a crimped board case, making it difficult to replace. Replacing the performance control board 30 requires destroying the board case. The LED connection board 700 is easy to replace because it can be removed without tools or is simply covered by a cover that can be removed without damage. In this respect, the protection of the performance control board 30 is also useful. Furthermore, some of the display boards downstream of the LED connection board 700 cannot be removed without disassembling them with tools. In that sense, replacing the LED connection board 700 is relatively easy, and it is suitable for using chip-type fuses in the LED connection board 700.

[0483] Furthermore, the fact that fuses FZ1 and FZ2 are chip-type significantly contributes to the miniaturization of circuit boards required for the downstream side of the effects system.

[0484] Furthermore, fuses FZ3, FZ4, FZ5, and FZ6 are provided for the 35V DC voltage (DC35VB) as shown in Figure 26. The 35V DC voltage (DC35VB) is not transmitted downstream of the LED connection board 700, and is branched into four motor drive power supply voltages MOT35Vx, MOT35Vz, MOT35Vy, and MOT35Vu. Additionally, a protection circuit using Schottky barrier diodes (D10, D11) and electrolytic capacitors (C57, C63) is provided, so it is not the closest component in terms of wiring relative to the power supply voltage terminal of connector CN1.

[0485] (Configuration C2) Gaming machine 1 is, First circuit board and A second board to which a power supply voltage is supplied from the first board, A plurality of third boards to which the power supply voltage is supplied from the second board, Equipped with, The second substrate is An input connector that receives the power supply voltage from the first board, Multiple output connectors, each supplying the power supply voltage to the third board, Chip-type fuses and It has, The fuse is the element closest in terms of wiring to the power supply voltage terminal in the input connector.

[0486] In this case (configuration C2), the following corresponding example (specific example 6) can be assumed. (Specific example 6) • First circuit board: Performance control board 30 • Second board: LED connection board 700 • Input connector: Connector CN1 Output connectors: Connectors CN3, CN4, CN5, CN8, CN11, CN13, CN6, CN7, CN9, CN12, CN14, CN10, CN25, CN26, etc. • Power supply voltage: 12V DC voltage (DC12VB) • Power supply voltage terminals: Terminals for 12V DC voltage (DC12VB) on connector CN1 (pins 12, 14, 24, 26, 28, and 30) • Fuse: Fuse FZ2 • Third board: The board connected to the output connector.

[0487] As explained in the circuit diagram, the LED connection board 700 receives a 12V DC voltage (DC12VB) at connector CN1 and transmits it to downstream boards via connectors CN3, CN4, CN5, CN8, CN11, CN13, CN6, CN7, CN9, CN12, CN14, CN10, CN25, CN26, etc., as power for the LED's illumination operation and the LED driver.

[0488] In this configuration, fuse FZ2 is located downstream of the performance control board 30, at the upstream end of the 12V DC voltage (DC12VB) line in the numerous performance system boards. Therefore, it functions most appropriately as a protection circuit to protect the upstream performance control board 30 in the event of a short circuit in either the LED connection board 700 or the third board. When the LED connection board 700 is configured to supply power to multiple third boards, the number of short-circuit locations that can be protected by the protection function increases, making it a suitable configuration for protecting the performance control board 30. Furthermore, because the FZ2 fuse is a chip type, it can contribute to the miniaturization of downstream circuit boards.

[0489] (Configuration C3) Gaming machine 1 is, First circuit board and A second board to which a power supply voltage is supplied from the first board, A third board from which the power supply voltage is supplied from the second board, Equipped with, The second substrate is An input connector that receives the power supply voltage from the first board, An output connector that supplies the power supply voltage to the third board, A fuse is provided on the wiring of the aforementioned power supply voltage, It has, Beyond the output connector, there is a transmission line using a flexible flat cable as the inter-board transmission line through which the power supply voltage is transmitted. The fuse is the element closest in terms of wiring to the power supply voltage terminal in the output connector.

[0490] In this case (configuration C3), the following corresponding example (specific example 7) can be assumed. (Specific example 7) • First circuit board: Performance control board 30 • Second board: LED connection board 700 • Third board: Relay board 800 • Power supply voltage: 12V DC (DC12VB), 5V DC (DC5VB) • Input connector: Connector CN1 • Output connector: Connector CN23 • Transmission line using flexible flat cable: Transmission line H31 • Fuses: Fuses FZ7, FZ8

[0491] As explained in Figure 25, the 12V DC voltage (DC12VB) and the 5V DC voltage (DC5VB) are transmitted from connector CN23 to the relay board 800 and decorative board 820. Furthermore, among the inter-board transmission lines that transmit 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) from connector CN23 onwards, the transmission line H31 between the relay board 800 and the decorative board 820 uses a flexible flat cable.

[0492] For example, Figures 45 and 46 show connectors CN101 and CN102, which connect the relay board 800 and the decorative board 820. These are connectors for connecting flexible flat cables (FFCs). Details regarding Figures 44 and 45 will be described later, but Figure 44 shows the series supply path from the power supply board 300 to a 5V DC voltage (DC5VB), and Figure 45 shows the series supply path from the power supply board 300 to a 12V DC voltage (DC12VB).

[0493] Furthermore, as shown in Figure 25, fuses FZ7 and FZ8 are attached to the LED connection board 700. Figure 39 shows the position pCN23 where connector CN23 is located, and terminal numbers are added to some of the pads for illustrative purposes. The pads for pins 2, 4, and 6, which are terminals for 12V DC voltage (DC12VB), are connected to the pad where fuse FZ7 is located (position pFZ7). The pad of pin 9, which is the terminal for the 5V DC voltage (DC5VB), is connected to the pad where fuse FZ8 is located (position pFZ8).

[0494] As can be seen from Figures 25 and 39, fuses FZ7 and FZ8 are considered to be the elements closest in terms of wiring to the power supply voltage terminals in connector CN23.

[0495] In the case of connectors such as connectors CN101 and CN102, where flexible flat cables are inserted and removed, short circuits can occur due to slanted insertion of the cable ends. In other words, the possibility of a short circuit occurring is relatively high. Therefore, fuses FZ7 and FZ8 are placed in the LED connection board 700 as the closest elements to connector CN23, which is the output connector upstream of the flexible flat cable. This minimizes the impact of short circuits occurring in the relay board 800, decorative board 820, or flexible flat cable. In other words, the blowing of fuses FZ7 or FZ8 protects the upstream performance control board 30 and other boards in parallel with the relay board 800 (e.g., LED boards 850, 860, etc.), resulting in an optimal fuse placement.

[0496] Figure 25 shows an example where the pads are formed using chip-type fuses FZ7 and FZ8. In the case of chip-type fuses, if fuse FZ7 or FZ8 blows, the LED connection board 700 also needs to be replaced. Fuses FZ7 and FZ8 could, for example, be replaced with glass tube type fuses. This would protect the LED connection board 700 even if a short circuit occurs in the flexible flat cable, and only the fuses would need to be replaced.

[0497] In some cases, a flexible flat cable may be used in the transmission line H30 between the LED connection board 700 and the relay board 800. That is, when connectors CN23 and CN100 are used as connectors for the flexible flat cable. In such cases, the output connector upstream of the flexible flat cable within the LED connection board 700 will be connector CN23. Therefore, by placing fuses FZ7 and FZ8 as the elements closest to connector CN23, the same effect as described above can be obtained. In other words, when transmitting power supply voltages such as 12V DC (DC12VB) and 5V DC (DC5VB) downstream from connector CN23, the configuration (configuration C3) becomes effective if a flexible flat cable is used after connector CN23.

[0498] (Configuration C4-1) Gaming machine 1 is, A power supply board that generates and outputs a first DC power supply voltage based on the AC input power supply, A plurality of boards having a series supply path for the first power supply voltage formed on them so as to sequentially receive the supply of the first power supply voltage from the power supply board, Equipped with, The aforementioned plurality of circuit boards include circuit boards that are attached to replaceable components. Multiple fuses are arranged on the aforementioned series supply path, One of the aforementioned plurality of fuses is a chip-type fuse that is the closest element in terms of wiring to the terminal of the first power supply voltage of the input connector on the board that is the highest-ranking board in the series relationship of the series supply path among the one or more boards arranged in the replaceable component.

[0499] In this case (configuration C4-1), the following corresponding example (specific example 8) can be assumed. (Specific example 8) • Power supply board: Power supply board 300 • First power supply voltage: 5V DC voltage (DC5VB), 12V DC voltage (DC12VB) • Multiple substrates forming a series supply path: Multiple substrates shown in Figures 44 and 45 • Circuit board to be attached to replaceable parts: Circuit board of game board 3 shown in Figures 44 and 45 • Multiple fuses: Multiple fuses as shown in Figures 44 and 45 • Input connector: Connector CN40 • One of several fuses: Fuse FZz in Figure 44, Fuse FZw in Figure 45

[0500] Figures 44 and 45 show the series supply path for the first power supply voltage in configuration C4-1 of the circuit board shown in Figure 11. Figure 44 shows the series supply path when the first power supply voltage is 5V DC (DC5VB), and Figure 45 shows the series supply path when the first power supply voltage is 12V DC (DC12VB). In the circuit boards shown in Figures 44 and 45, the power supply board 300 is placed in the inner frame 2, and the rest are placed in the game board 3. Although Figures 44 and 45 only show some of the connectors CN, it goes without saying that each circuit board is provided with connectors CN as transmission line ends.

[0501] Figure 44 describes the series supply path for a 5V DC voltage (DC5VB). As explained earlier in Figure 12, the 5V DC voltage (DC5VB) generated by the power supply board 300 based on the AC input power supply is sent from connector CN2A to the power relay board 40 via transmission line H2.

[0502] In the power supply board 300, the fuse FZx is connected to the 5V DC voltage (DC5VB) terminal of connector CN2A as the closest component in terms of wiring. That is, there is only wiring between the 5V DC voltage (DC5VB) terminal of connector CN2A and the fuse FZx, and no other electronic components are provided. Fuse FZx is mounted on the power supply board 300 as, for example, a tubular or terminal-insertion type fuse. For example, the terminal-insertion type fuse FZ601 or the tubular type fuse FZ301 shown in Figure 13 are considered to be fuse FZx in Figure 44. The fuse FZx has a blowing current value of, for example, 10A.

[0503] As shown in Figure 44, the power supply relay board 40 is provided with a connector CN40 which is the transmission line end of the transmission line H2. The fuse FZw is connected to the 5V DC voltage (DC5VB) terminal of the connector CN40 as the closest component in terms of wiring. That is, there is only wiring between the 5V DC voltage (DC5VB) terminal of the connector CN40 and the fuse FZw, and no other electronic components are provided. The fuse FZw is a chip-type fuse, and its blowing current value is specified as, for example, 5A.

[0504] From the power relay board 40, a 5V DC voltage (DC5VB) is transmitted to the performance control board 30 via transmission line H18, and then sent to the LED connection board 700 via transmission line H20 (or transmission line H20b). The LED connection board 700 receives a 5V DC voltage (DC5VB) input via connector CN1 (or connector CN1b). A fuse FZ1 is provided for this 5V DC voltage (DC5VB). As shown in Figures 20, 21, and 39, fuse FZ1 is connected to the 5V DC voltage (DC5VB) terminal of connector CN1 (or connector CN1b) as the closest element in terms of wiring. That is, there are no other electronic components between the 5V DC voltage (DC5VB) terminal of connector CN1 (or connector CN1b) and fuse FZ1, only wiring. Fuse FZ1 is a chip-type fuse, and its blowing current value is specified as, for example, 4A.

[0505] A 5V DC voltage (DC5VB) is transmitted from connector CN23 on LED connection board 700 to relay board 800 via transmission line H30. As can be seen in Figure 25, on the LED connection board 700, the fuse FZ8 is connected to the 5V DC voltage (DC5VB) terminal of connector CN23 as the closest component in terms of wiring. That is, there are no other electronic components between the 5V DC voltage (DC5VB) terminal of connector CN23 and fuse FZ8, only wiring. Fuse FZ8 is a chip-type fuse, and its blowing current value is specified as, for example, 2A.

[0506] The 5V DC voltage (DC5VB) is further transmitted from the relay board 800 to the decorative board 820 via the transmission line H31.

[0507] As described above, with the power supply board 300 as the upstream component, a series supply path of 5V DC voltage (DC5VB) is formed in the power supply relay board 40, the performance control board 30, the LED connection board 700, the relay board 800, and the decorative board 820.

[0508] Figure 45 illustrates a series supply circuit for 12V DC voltage (DC12VB). The 12V DC voltage (DC12VB) generated by the power supply board 300 based on the AC input power supply is sent to the power relay board 40 via the transmission line H2 from connector CN2A (see Figure 12).

[0509] In the power supply board 300, the fuse FZy is connected to the 12V DC voltage (DC12VB) terminal of connector CN2A as the closest component in terms of wiring. That is, there is only wiring between the 12V DC voltage (DC12VB) terminal of connector CN2A and the fuse FZy; no other electronic components are provided. Fuse FZy is mounted on the power supply board 300 as, for example, a tubular or terminal-insertion type fuse. For example, the terminal-insertion type fuse FZ501 or the tubular type fuse FZ401 shown in Figure 13 are considered to be fuse FZy in Figure 45. The fuse FZy is specified to have a blowing current of, for example, 15A.

[0510] In the power supply relay board 40, the fuse FZz is connected to the 12V DC voltage (DC12VB) terminal of connector CN40, which is the transmission line end of transmission line H2, as the closest component in terms of wiring. That is, there is only wiring between the 12V DC voltage (DC12VB) terminal of connector CN40 and fuse FZz; no other electronic components are provided. Fuse FZz is a chip-type fuse, and its blowing current value is, for example, 10A.

[0511] From the power relay board 40, a 12V DC voltage (DC12VB) is transmitted to the performance control board 30 via transmission line H18, and then sent to the LED connection board 700 via transmission line H20 (or transmission line H20a). The LED connection board 700 receives a 12V DC voltage (DC12VB) input via connector CN1 (or connector CN1a). A fuse FZ2 is provided for this 12V DC voltage (DC12VB). As shown in Figures 20, 21, and 39, fuse FZ2 is connected to the 12V DC voltage (DC12VB) terminal of connector CN1 (or connector CN1a) as the closest element in terms of wiring. That is, there are no other electronic components between the 12V DC voltage (DC12VB) terminal of connector CN1 (or connector CN1a) and fuse FZ2, only wiring. Fuse FZ2 is a chip-type fuse, and its blowing current value is specified as, for example, 8A.

[0512] A 12V DC voltage (DC12VB) is transmitted from the LED connection board 700 to several other boards. One example is that a 12V DC voltage (DC12VB) is transmitted from connector CN23 to relay board 800 via transmission line H30. As can be seen from Figure 25, the fuse FZ7 is connected to the 12V DC voltage (DC12VB) terminal of connector CN23 as the closest component in terms of wiring. In other words, there are no other electronic components between the 12V DC voltage (DC12VB) terminal of connector CN23 and fuse FZ7, only wiring. The FZ7 fuse is a chip-type fuse, and its blowing current is specified as, for example, 2A.

[0513] The 12V DC voltage (DC12VB) is further transmitted from the relay board 800 to the decorative board 820 via the transmission line H31. As described above, with the power supply board 300 as the upstream component, a series supply path of 12V DC voltage (DC12VB) is formed in the power supply relay board 40, the performance control board 30, the LED connection board 700, the relay board 800, and the decorative board 820.

[0514] Furthermore, a 12V DC voltage (DC12VB) is supplied from the LED connection board 700 to the LED board 850 via the transmission line H40, which includes the connector CNv. Therefore, with the power supply board 300 as the upstream terminal, a series supply path of 12V DC voltage (DC12VB) is formed in the power relay board 40, the performance control board 30, the LED connection board 700, and the LED board 850.

[0515] Furthermore, a 12V DC voltage (DC12VB) is supplied from the LED connection board 700 to the LED board 860 via the transmission line H41, which includes the connector CNu. Therefore, with the power supply board 300 as the upstream terminal, a series supply path of 12V DC voltage (DC12VB) is formed in the power relay board 40, the performance control board 30, the LED connection board 700, and the LED board 860.

[0516] Note that connectors CNv and CNu in Figure 45 correspond to, for example, connectors CN5, CN8, CN11, CN13, CN6 and connectors CN7, CN9, CN12, CN14 shown in Figure 18.

[0517] In the 5V DC voltage (DC5VB) series supply circuit shown in Figure 44, a fuse FZw is mounted on the power supply relay board 40. In the series supply circuit of 12V DC voltage (DC12VB) shown in Figure 45, a fuse FZz is mounted on the power supply relay board 40. Although the detailed circuit configuration is omitted, fuses FZw and FZz are on the 5V and 12V power lines, respectively, and are the upstream electrical components within the power supply relay board 40, excluding connector CN40.

[0518] Furthermore, the game board 3 is a replaceable component for the frame members, including the inner frame 2. In that case, the power supply relay board 40 is the highest-ranking board in the series relationship of the 5V DC voltage (DC5VB) or 12V DC voltage (DC12VB) series supply path among the one or more boards arranged in the replaceable component (for example, the game board 3).

[0519] By mounting fuses FZw and FZz on the power supply relay board 40 in this way, it becomes suitable for protecting the frame members. Even if a short circuit occurs in the 5V DC voltage (DC5VB) system or the 12V DC voltage (DC12VB) system in the components of the game board 3, the fuse FZw or FZz will blow, protecting the power supply board 300 side, that is, the inner frame 2 side. Protecting the circuitry on the frame component allows for the repair of the gaming machine 1 by replacing the game board 3. Alternatively, the frame component can be used in a different machine. In gaming machine 1, replacing the game board 3 with the frame component can create a new machine, so protecting the frame component is a significant advantage. Furthermore, it is environmentally friendly as it eliminates the need to discard the frame component unnecessarily.

[0520] Furthermore, fuses FZw and FZz are chip-type, making them suitable for miniaturizing the power supply relay board 40.

[0521] The gaming machine 1 of this embodiment includes the following (configuration C4-2) in addition to the above (configuration C4-1).

[0522] (Configuration C4-2) The power supply board is placed on the frame member, The aforementioned replaceable parts are parts that are interchangeable with respect to the frame member.

[0523] As described above, the power supply board 300 is located in the inner frame 2 (frame member), and the replaceable part is the game board 3, which is replaceable relative to the frame member. In the series power supply path, fuses FZw and FZz are connected to connector CN40 of the power relay board 40, which is the boundary between the inner frame 2 and the game board 3, making it extremely suitable for protecting the frame members.

[0524] (Configuration C5) Gaming machine 1 is, A power supply board that generates and outputs a first DC power supply voltage based on the AC input power supply, A plurality of boards having a series supply path for the first power supply voltage formed on them so as to sequentially receive the supply of the first power supply voltage from the power supply board, Equipped with, The plurality of boards include a performance control board that outputs performance control signals, and one or more boards that are lower in series relationship to the series supply path than the performance control board. Multiple fuses are arranged on the aforementioned series supply path, One of the aforementioned multiple fuses is a chip-type fuse that is the closest element in terms of wiring to the terminal of the first power supply voltage of the input connector on the board that is directly below the performance control board in the series relationship of the series supply path.

[0525] In this case (configuration C5), the following corresponding example (specific example 9) can be assumed. (Specific example 9) • Power supply board: Power supply board 300 • First power supply voltage: 5V DC voltage (DC5VB), 12V DC voltage (DC12VB) • Multiple substrates forming a series supply path: Multiple substrates shown in Figures 44 and 45 • Performance control board: Performance control board 30 • Board directly below the performance control board: LED connection board 700 • Multiple fuses: Multiple fuses as shown in Figures 44 and 45 • Input connector: Connector CN1 (or CN1a, or CN1b) • One of several fuses: Fuse FZ1, FZ2

[0526] As explained in Figures 44 and 45, both the 5V DC voltage (DC5VB) series supply circuit and the 12V DC voltage (DC12VB) series supply circuit have multiple fuses. Fuse FZ1, one of several fuses in the 5V DC (DC5VB) series supply circuit, is a chip-type fuse that is the closest element in terms of wiring to the power supply voltage terminal of connector CN1 (or CN1b) on the LED connection board 700, which is directly below the performance control board 30. Fuse FZ2, one of several fuses in the series supply circuit for 12V DC voltage (DC12VB), is a chip-type fuse that is the closest element in terms of wiring to the power supply voltage terminal of connector CN1 (or CN1a) on the LED connection board 700, which is directly below the performance control board 30.

[0527] As a result, fuses FZ1 and FZ2 are located downstream of the performance control board 30, at the very top of the numerous boards in the performance system. Therefore, it functions most appropriately as a protective circuit to protect the performance control board 30 in the event of a short circuit downstream of the LED connection board 700. This is because, in the game board 3, no matter where a short circuit occurs downstream of the LED connection board 700, the performance control board 30 will not be affected due to the blowing of fuses FZ1 and FZ2.

[0528] Since fuses FZ1 and FZ2 are chip type, if they blow, the LED connection board 700 itself will need to be replaced, but the expensive upstream performance control board 30 will not need to be replaced. Furthermore, in typical gaming machines 1, the performance control board 30 is housed in a crimped board case, making it difficult to replace. However, the LED connection board 700 is simply covered by a removable cover that can be taken off without tools, making it easy to replace. In this respect as well, protecting the performance control board 30 is useful. Furthermore, the fact that fuses FZ1 and FZ2 are chip-type significantly contributes to the miniaturization of circuit boards required for the downstream side of the effects system.

[0529] In the above (Configuration C5), the specific example of the "performance control board" is the performance control board 30, but in reality, this performance control board 30 may consist of a single board or be composed of multiple boards. In any case, the performance control board is housed in a board case in which one or more boards are crimped together. The term "performance control board" refers to one or more boards housed in a board case. Therefore, the "performance control board" in (Configuration C5) can be defined as "one or more boards housed in a board case," or "one or more boards housed in a board case and integrally attached to the gaming machine." Furthermore, by having the circuit board to which the fuse is installed be the circuit board directly below the "performance control board," that is, the circuit board directly below the circuit board case of the performance control board, it is possible to avoid having to replace the expensive performance control board 30, which consists of one or more circuit boards housed in a circuit board case, even if a short circuit occurs downstream.

[0530] (Configuration C6) Gaming machine 1 is, A power supply board that generates and outputs a DC power supply voltage based on the AC input power supply, The system includes multiple performance boards to which power voltage is supplied from the aforementioned power supply board, The aforementioned power supply board is a board on which through-hole components involved in generating the power supply voltage are mounted, and a tubular or terminal-insertion type fuse is mounted. The aforementioned multiple performance boards include a performance board in which all surface-mount components mounted on the board, excluding connectors, are chip components, and a chip-type fuse is mounted.

[0531] In this case (configuration C6), the following corresponding example (specific example 10) can be assumed. (Specific example 10) • Power supply board: Power supply board 300 • Power supply voltage: 5V DC (DC5VB), 12V DC (DC12VB) • Multiple circuit boards for performance effects: Multiple circuit boards shown in Figures 44 and 45. • A display board for LED connection board 700 in which all surface-mount components except for the connector are chip components and chip-type fuses are mounted.

[0532] The electrical components mounted on the LED connection board 700 include connector CN, IC chip, resistor, capacitor, diode, and fuse. The IC chip is, of course, a chip component, but the resistors, capacitors, and diodes used are chip-type resistors, chip-type capacitors, and chip-type diodes. Furthermore, fuses FZ1, FZ2 (see Figure 20 or Figure 21), FZ3, FZ4, FZ5, FZ6 (see Figure 26), FZ27, and FZ28 (see Figure 25) are all chip type. Figures 35 and 36 show the pads and wiring patterns for surface mounting these chip-type components.

[0533] On the other hand, as explained in Figure 13, the power supply board 300 is a board on which through-hole components involved in generating the power supply voltage are mounted, and tubular or terminal-insertion type fuses FZ301, FZ401, FZ501, FZ601, FZ701, and FZ1A are mounted.

[0534] The power supply board 300 requires a fuse with a high blowing current, so a tubular or terminal-insertion type fuse is used. However, the downstream effect board only needs a low blowing current. Therefore, a chip-type fuse is used for the board on which surface-mount components are mounted. This means that all electrical components except for connector CN are chip-type. This configuration is particularly suitable for miniaturizing the board area required for the downstream effect board. Furthermore, the fact that all surface-mount components, including fuses, are chip components offers a cost advantage.

[0535] (Configuration C7) Gaming machine 1 is, A power supply board that generates and outputs a first DC power supply voltage based on the AC input power supply, A plurality of boards having a series supply path for the first power supply voltage formed on them so as to sequentially receive the supply of the first power supply voltage from the power supply board, Equipped with, The aforementioned power supply board is a board on which through-hole components involved in generating the power supply voltage are mounted, and a tubular or terminal-insertion type fuse is mounted. The aforementioned multiple performance boards include a performance board in which all surface-mount components mounted, excluding connectors, are chip components and chip-type fuses are mounted. No boards with tubular or terminal-insertion type fuses are provided on boards that are downstream in the series supply path from the board on which the chip-type fuse is mounted.

[0536] In this case (configuration C7), the following corresponding example (specific example 11) can be assumed. (Specific example 11) • Power supply board: Power supply board 300 • First power supply voltage: 5V DC voltage (DC5VB), 12V DC voltage (DC12VB) • Multiple substrates: Multiple substrates shown in Figures 44 and 45 • A display board for LED connection board 700 in which all surface-mount components except for the connector are chip components and chip-type fuses are mounted. • Circuit boards with chip-type fuses: Power relay board 40, LED connection board 700

[0537] As previously described in the explanation of configuration C6, the LED connection board 700 is a display board in which all surface-mount components mounted on it, excluding the connector, are chip components, and chip-type fuses are also mounted. In the examples shown in Figures 44 and 45, chip-type fuses are mounted on the power relay board 40 and the LED connection board 700, but no boards with tubular or terminal-insertion type fuses are provided downstream of the power relay board 40.

[0538] The power supply board 300 requires a fuse with a high blowing current, so a tubular or terminal-insertion type fuse is used. However, the downstream performance board only needs a low blowing current. Therefore, a chip-type fuse is used on the board where surface-mount components are mounted. Furthermore, if a chip-type fuse is used on one board, all fuses installed downstream from that point should also be chip-type. This promotes the miniaturization required for the downstream boards.

[0539] (Configuration D1-1) Gaming machine 1 is, The first board has wiring formed to transmit performance control signals output from an IC chip component including an active circuit, and it receives the performance control signals from another board and / or outputs the performance control signals to another board. The first substrate has a connector located near the edge of the substrate, with two rows of terminals arranged, one row of terminals facing the edge of the substrate and the other row of terminals facing inward. The connector is configured such that all terminals of the performance control signals transmitted between the connector and another board are connected to the terminals of the other terminal array.

[0540] In this case (configuration D1-1), the following corresponding example (specific example 12) can be assumed. (Specific example 12) • First circuit board: Performance control board 30 • Connector: Connector CNe1 • Other boards: LED connection board 700

[0541] Furthermore, in the case of (Configuration D1-1), the following corresponding example (Specific Example 13) can also be considered. (Specific example 13) • First board: LED connection board 700 • Connector: Connector CN1 • Other boards: Performance control board 30

[0542] In these specific examples 12 and 13, the control signals output from the IC chip components including the active circuit are: the first set of clock signal LED_CLK, data signal LED_DATA, and enable signal LED_ENABLE; the second set of clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST; the third set of clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X; and the fourth set of load signal S_IN_LOAD, clock signal S_IN_CLK, and serial data signal S_IN_DATA.

[0543] The IC chip components that include active circuits include the performance control CPU 30a on the performance control board 30, and the buffer circuits 701, 702, and 703, LED drivers 705 and 707, and P / S conversion circuit 704 on the LED connection board 700. The above performance control signals are signals generated and output by the performance control CPU 30a, or signals generated and output by the P / S conversion circuit 704 on the LED connection board 700, or the motor driver of the motor drive unit 760, etc.

[0544] The terminal assignments for connectors CN1 and CNe1 are explained in Figure 14, and it was also explained that connectors CN1 and CNe1 have pins arranged in two rows, as shown in Figure 27. Figure 46 shows the pin assignments of connectors CN1 and CNe1, column by column. The diagram shows the terminal rows with odd-numbered pins on the left and the terminal rows with even-numbered pins on the right. The pins assigned to the "performance control signals" mentioned above are marked with diagonal lines.

[0545] As is clear from the diagram, all performance control signals are assigned to the pins in the odd-numbered terminal rows. The pins in the even-numbered terminal rows are assigned to 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), 35V DC voltage (DC35VB), or ground (GND), and no performance control signals are assigned to them.

[0546] Figure 47 schematically shows the connection between the performance control board 30 and the LED connection board 700 using connectors CN1 and CNe1, and the wiring of the performance control signals on each board. Connectors CN1 and CNe1 are separated by dashed lines, indicating pin numbers "1", "2", "39", and "40".

[0547] The above-mentioned (Specific Example 12) performance control board 30 will now be explained. On the performance control board 30, the wiring pattern is formed so that the above-mentioned performance control signals are transmitted between the performance control CPU 30a and the connector CNe1. Note that buffer circuits, filter circuits, etc. may be provided between the performance control CPU 30a and the connector CNe1, but these are omitted here. In any case, on the performance control board 30, the performance control signals generated and output by the performance control CPU 30a are sent to the connector CNe1 and transmitted to the LED connection board 700 via a harness which becomes the transmission line H20. The performance control signals transmitted from the LED connection board 700 are then sent from the connector CNe1 to the performance control CPU 30a.

[0548] Figure 48 shows the transmission signals between the performance control CPU 30a and connector CNe1. The performance control CPU 30a outputs the clock signal LED_CLK, data signal LED_DATA, enable signal LED_ENABLE, clock signal LSI_CLK, enable signal LSI_ENABLE, data signal LSI_DATA, reset signal LSI_RST, clear signal CLR_X, data signal DATA_X, latch signal LATCH_X, load signal S_IN_LOAD, and clock signal S_IN_CLK, which are sent to connector CNe1. Additionally, the serial data signals LSI_IN_DATA and S_IN_DATA transmitted from the LED connection board 700 are sent to the performance control CPU 30a via connector CNe1.

[0549] In this case, as shown in Figure 47, the connector CNe1 is positioned on the performance control board 30 near the board edge 30T, with its longer side aligned with the board edge 30T. Placing it near the board edge 30T can also be rephrased as a state where no other electronic components are placed between connector CNe1 and board edge 30T. The terminal rows with even-numbered pins are mounted facing the 30T side of the circuit board edge, while the terminal rows with odd-numbered pins face inwards. Therefore, all pins assigned to the performance control signals face inwards.

[0550] From the perspective of connector CNe1, which is located near the edge, the performance control CPU 30a is positioned towards the inside of the board. Furthermore, because the performance control CPU 30a requires numerous wires around it, it is generally positioned closer to the center of the board.

[0551] As a result, the performance control CPU 30a faces the odd-numbered terminal rows on connector CNe1. Therefore, the wiring pattern for the performance control signals between the performance control CPU 30a and connector CNe1 does not need to wrap around connector CNe1, and can be designed as a very simple and efficient pattern.

[0552] In addition, while buffer circuits and filter circuits may be provided between the performance control CPU 30a and connector CNe1 in terms of wiring, since connector CNe1 is located near the edge of the board, the odd-numbered terminal rows of connector CNe1 will always face the chips and electronic components that make up those circuits, so the wiring pattern can still be kept simple.

[0553] Furthermore, wiring patterns for 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), 35V DC voltage (DC35VB), and ground (GND) are required between connector CNe1 and edge 30T of the circuit board. These power supply voltage patterns and ground patterns are typically formed across almost the entire surface of the circuit board. For example, they are configured as solid power supply patterns and solid ground patterns. Each of these is also assigned to multiple terminals. Therefore, the wiring pattern between connector CNe1 and the edge of the circuit board does not need to be complex.

[0554] Next, we will describe the LED connection board 700 as (Specific Example 13) mentioned above. On the LED connection board 700, the wiring pattern is formed so that the above-mentioned performance control signals are transmitted between buffer circuits 701 and 703, as explained in Figure 20. Then, on the LED connection board 700, the performance control signals (serial data signal LSI_IN_DATA, serial data signal S_IN_DATA) output from buffer circuits 701 and 703 are sent to connector CN1 and transmitted to the performance control board 30 via a harness which becomes the transmission line H20. The performance control signals transmitted from the performance control board 30 are sent from connector CN1 to buffer circuits 701 and 703.

[0555] In this case, as shown in Figure 47, the connector CN1 is positioned near the board edge 700T on the LED connection board 700, with its longer side aligned with the board edge 700T. No other electronic components are placed between the connector CN1 and the board edge 700T. The terminal rows with even-numbered pins are mounted facing the 700T side of the circuit board edge, while the terminal rows with odd-numbered pins face inwards. Therefore, all pins assigned to the performance control signals face inwards.

[0556] From the perspective of connector CN1, which is located near the edge, buffer circuits 701 and 703 are positioned towards the inside of the board. As a result, buffer circuits 701 and 703 face the odd-numbered terminal rows on connector CN1. Therefore, the wiring pattern for the control signals between buffer circuits 701 and 703 and connector CNe1 does not need to wrap around connector CN1, and can be designed as a very simple and efficient pattern.

[0557] The specific wiring pattern is shown in Figure 39. The figure shows that the wiring between the positions p701 and p703 where the buffer circuits 701 and 703 are located and the position pCN1 of the connector CN1 is simple. The control signals transmitted between connector CN1 and buffer circuits 701 and 703 on the board are the clock signal LED_CLK, data signal LED_DATA, clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, reset signal LSI_RST, load signal S_IN_LOAD, clock signal S_IN_CLK, and serial data signal S_IN_DATA (see Figure 20).

[0558] Furthermore, because the wiring pattern can be simplified, the test points TP1 to TP10 for each of the aforementioned performance control signals can be formed with ample space.

[0559] Furthermore, wiring patterns for 5V DC (DC5VB), 12V DC (DC12VB), 35V DC (DC35VB), and ground (GND) are formed between connector CN1 and the edge of the circuit board. As is clear from Figure 39, these patterns are extremely simple. Moreover, because there are no wirings for performance control signals, it is easier to form wider solid traces than with normal wiring, resulting in a configuration th...

Claims

1. A first electronic component provided on the first substrate, A second electronic component is provided on the second substrate, A wiring path that electrically connects the first electronic component and the second electronic component, It has, The aforementioned wiring path is The first wiring pattern formed on the first substrate, A connector for connecting a path between the first substrate and the second substrate, wherein the connector has multiple rows of terminals, The second wiring pattern formed on the second substrate, Includes, In the aforementioned wiring path, a group of signals, which are multiple signals used for common processing, are transmitted between the first electronic component and the second electronic component. In the first wiring pattern, the multiple pattern lines that transmit the group of signals are approximately equal in length to each other. In the second wiring pattern, the multiple pattern lines that transmit the group of signals are approximately equal in length to each other. In the aforementioned connector, the terminals assigned to the group of signals are the terminals in the same row among multiple rows. The first wiring pattern is provided with a line length adjustment section in some of the pattern lines among the multiple pattern lines that transmit the group of signals. The line length adjustment section in some of the pattern lines is located on the first electronic component side of the pattern line between the first electronic component and the connector on the first substrate, rather than at the central position on the pattern line. Gaming machine.

2. The line length adjustment section is provided continuously with the pad to which the terminals of the first electronic component are connected, and after passing from the pad through the line length adjustment section, the multiple signal pattern wirings of the group become parallel wirings. The gaming machine according to claim 1.

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