Imaging device and camera system

Abstract

To provide an imaging device or the like that can improve image quality. [Solution] The imaging device 100 includes a first substrate 10 including a pixel array in which a plurality of pixels 31 are arranged, and a second substrate 20 stacked on the first substrate 10 and including peripheral circuits connected to the pixel array. Each of the plurality of pixels 31 includes a photoelectric conversion layer 73 that converts light into signal charges, a pixel electrode 71 that collects signal charges, and a counter electrode 72 that faces the pixel electrode 71 via the photoelectric conversion layer 73. The first substrate 10 includes a first portion 15 of an electrical path 90 for supplying voltage to the counter electrode 72. The second substrate 20 includes a second portion 23 of the electrical path 90. The peripheral circuits include an AD conversion circuit 53 that converts signals from the plurality of pixels 31 into digital signals. The second portion 23 does not overlap the AD conversion circuit 53 in a plan view.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and a camera system.

Background Art

[0002] In digital cameras and the like, imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used. These imaging devices have, for example, photodiodes formed on a semiconductor substrate as a photoelectric conversion unit. Further, Patent Document 1 discloses an imaging device having a structure in which a photoelectric conversion unit having a photoelectric conversion layer is disposed on the light incident side of a semiconductor substrate instead of a photodiode.

[0003] In recent years, due to the demand for miniaturization of imaging devices, an imaging device having a structure in which a substrate on which a pixel array composed of a plurality of pixels is formed and a substrate on which a circuit connected to the pixel array is formed are laminated has been proposed. For example, Patent Document 2 discloses a technique for miniaturizing an image sensor by laminating a substrate on which a pixel region is formed and a substrate on which a drive circuit or the like is formed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In an imaging device, higher image quality is required.

[0006] This disclosure provides an imaging device and the like that can improve image quality. [Means for solving the problem]

[0007] An imaging apparatus according to one aspect of the present disclosure comprises a first substrate including a pixel array in which a plurality of pixels are arranged, and a second substrate laminated on the first substrate and including peripheral circuits connected to the pixel array, wherein each of the plurality of pixels includes a photoelectric conversion layer that converts light into signal charges, a first electrode that collects the signal charges, and a second electrode that faces the first electrode via the photoelectric conversion layer, the first substrate includes a first portion of an electrical path for supplying voltage to the second electrode, the second substrate includes a second portion of the electrical path, and the peripheral circuits include an AD conversion circuit that converts signals from the plurality of pixels into digital signals, the second portion not overlapping the AD conversion circuit in a plan view.

[0008] A camera system according to one aspect of this disclosure includes the above-mentioned imaging device. [Effects of the Invention]

[0009] According to this disclosure, it is possible to provide an imaging device, etc., that can improve image quality. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of an imaging device according to Embodiment 1. [Figure 2] Figure 2 shows an example of the pixel circuit configuration according to Embodiment 1. [Figure 3] Figure 3 is a schematic cross-sectional view showing an example of the device structure of the imaging device according to Embodiment 1. [Figure 4] Figure 4 is a schematic plan view showing an example of the planar layout of the first substrate of the imaging device according to Embodiment 1. [Figure 5] Figure 5 is a schematic plan view showing an example of the planar layout of the second substrate of the imaging device according to Embodiment 1. [Figure 6]Figure 6 is an enlarged plan view of the vicinity of the corner of the first substrate of the imaging device according to Embodiment 1. [Figure 7] Figure 7 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to a modified example 1 of Embodiment 1. [Figure 8] Figure 8 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to a modified example 2 of Embodiment 1. [Figure 9] Figure 9 is a schematic plan view showing an example of a planar layout on the first substrate of an imaging device according to a modified example 2 of Embodiment 1. [Figure 10] Figure 10 is a schematic plan view showing an example of a planar layout on the second substrate of an imaging device according to a modified example 2 of Embodiment 1. [Figure 11] Figure 11 is an enlarged plan view of the vicinity of the corner of the second substrate of the imaging device according to a modified example 2 of Embodiment 1. [Figure 12] Figure 12 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to a modified example 3 of Embodiment 1. [Figure 13] Figure 13 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to a modified example 4 of Embodiment 1. [Figure 14] Figure 14 is a schematic plan view showing an example of a planar layout on the first substrate of an imaging device according to a modified example 4 of Embodiment 1. [Figure 15] Figure 15 is a schematic plan view showing an example of a planar layout on the second substrate of an imaging device according to a modified example 4 of Embodiment 1. [Figure 16] Figure 16 is an enlarged plan view of the vicinity of the corner of the second substrate of the imaging device according to a modified example 4 of Embodiment 1. [Figure 17] Figure 17 is a schematic cross-sectional view showing an example of the device structure of an imaging device according to a modified example 5 of Embodiment 1. [Figure 18] Figure 18 is a schematic plan view showing an example of the planar layout of the first substrate of the imaging device according to modified example 5 of Embodiment 1. [Figure 19]FIG. 19 is a plan view schematically showing an example of a planar layout on a second substrate of an imaging device according to Modification Example 5 of Embodiment 1. [Figure 20] FIG. 20 is an enlarged plan view of the vicinity of a corner of a second substrate of an imaging device according to Modification Example 5 of Embodiment 1. [Figure 21] FIG. 21 is a block diagram showing an example of the configuration of a camera system according to Embodiment 2.

MODE FOR CARRYING OUT THE INVENTION

[0011] (Background Leading to One Aspect of the Present Disclosure) In recent years, due to market demands such as higher resolution of imaging devices, the pixel size has been miniaturized. There is also a demand for miniaturization of imaging devices, and development of a substrate stacked type imaging device in which two or more substrates are stacked has been carried out. On the other hand, even when miniaturizing the pixel size and the imaging device, high image quality by reducing noise and the like is an important matter in the imaging device.

[0012] In a substrate stacked type imaging device, a pixel array for performing photoelectric conversion is arranged on a substrate including a semiconductor substrate arranged on the light incident side, and the pixel array is connected to a circuit of another substrate via a through electrode or a metal bonding portion or the like.

[0013] Further, in an imaging device having a structure in which a photoelectric conversion unit having a photoelectric conversion layer is arranged on the light incident side of a semiconductor substrate, like the imaging device disclosed in Patent Document 1, a control voltage for controlling the potential difference between two electrodes facing each other across the photoelectric conversion layer is supplied. The control voltage is applied to one of the two electrodes.

[0014] Furthermore, it is known that this control voltage can extend the functionality of the imaging device. For example, when the imaging device performs global shutter operation, as described in Patent Document 1, the control voltage applied to one of the two electrodes can be changed. The change in control voltage is a large voltage change, for example, about 10V. Therefore, if capacitive coupling or inductive coupling occurs between the power supply wiring and / or signal wiring of the surrounding circuitry and the electrical path that supplies the control voltage, crosstalk noise may propagate the voltage change of the control voltage to the power supply wiring and / or signal wiring of the surrounding circuitry. If this propagation occurs to the power supply wiring and / or signal wiring of the surrounding circuitry, there is a concern that glitches or voltage fluctuations may cause circuit malfunction, signal distortion, or compression of the dynamic range, leading to a decrease in image quality.

[0015] The inventors of this application focused on the fact that the electrical path for supplying the control voltage described above can be a factor in degrading image quality, and have come to obtain one aspect of this disclosure.

[0016] (Summary of this disclosure) As an overview of this disclosure, examples of imaging devices and camera systems related to this disclosure are shown below.

[0017] For example, an imaging apparatus according to a first aspect of the present disclosure includes a first substrate including a pixel array in which a plurality of pixels are arranged, and a second substrate laminated on the first substrate and including peripheral circuits connected to the pixel array, wherein each of the plurality of pixels includes a photoelectric conversion layer that converts light into signal charges, a first electrode that collects the signal charges, and a second electrode that faces the first electrode via the photoelectric conversion layer, the first substrate includes a first portion of an electrical path for supplying voltage to the second electrode, the second substrate includes a second portion of the electrical path, and the peripheral circuits include an AD conversion circuit that converts signals from the plurality of pixels into digital signals, the second portion not overlapping the AD conversion circuit in a plan view.

[0018] As a result, the second portion of the electrical path, located on the second substrate, is further away from the AD conversion circuit, thus suppressing noise applied to the AD conversion circuit by the voltage in the electrical path. Therefore, noise is suppressed in the AD conversion circuit where the signal from the pixels is input, improving the image quality of the imaging device.

[0019] Furthermore, for example, an imaging device according to a second aspect of this disclosure is an imaging device according to a first aspect, wherein the peripheral circuit includes a DAC (Digital to Analog Converter) that supplies a reference signal to the AD conversion circuit, and the second part does not overlap the DAC in a plan view.

[0020] This reduces noise in the reference signal supplied to the AD conversion circuit caused by voltage in the electrical path.

[0021] Furthermore, for example, an imaging device according to a third aspect of the present disclosure is an imaging device according to the first or second aspect, wherein the peripheral circuit includes a vertical scanning circuit that supplies control signals to the plurality of pixels, and the second portion does not overlap the vertical scanning circuit in a plan view.

[0022] This reduces noise in the control signals used to control pixel drive, which is caused by voltage in the electrical path.

[0023] Furthermore, for example, the imaging device according to the fourth aspect of this disclosure is an imaging device according to any one of the first to third aspects, wherein the second part does not overlap with the analog circuit included in the peripheral circuit in a plan view.

[0024] This reduces parasitic capacitance between the second section and the analog circuit wiring, reduces crosstalk noise between the second section and the analog circuit, and improves the image quality of the imaging device.

[0025] Furthermore, for example, an imaging apparatus according to a fifth aspect of the present disclosure is an imaging apparatus according to any one of the first to fourth aspects, wherein the first substrate includes a first semiconductor substrate and a first wiring layer laminated on the first semiconductor substrate, and the second substrate includes a second semiconductor substrate and a second wiring layer laminated on the second semiconductor substrate, and the first substrate and the second substrate are laminated such that the first wiring layer and the second wiring layer are located between the first semiconductor substrate and the second semiconductor substrate.

[0026] This makes it easier to connect the wiring of the first wiring layer with the wiring of the second wiring layer.

[0027] Furthermore, for example, an imaging apparatus according to a sixth aspect of the present disclosure is an imaging apparatus according to a fifth aspect, further comprising a metal joint that joins the first wiring layer and the second wiring layer, is electrically connected to the pixel array and the peripheral circuit, and is electrically insulated from the electrical path, wherein the second portion of the electrical path does not overlap the metal joint in a plan view.

[0028] This reduces noise caused by the second voltage in the signal between the pixel array and the peripheral circuitry passing through the metal junction.

[0029] Furthermore, for example, an imaging apparatus according to the seventh aspect of the present disclosure is an imaging apparatus according to any one of the first to fourth aspects, wherein the first substrate includes a first semiconductor substrate and a first wiring layer laminated on the first semiconductor substrate, and the second substrate includes a second semiconductor substrate and a second wiring layer laminated on the second semiconductor substrate, and the first substrate and the second substrate are laminated such that the first semiconductor substrate and the second wiring layer are positioned between the first wiring layer and the second semiconductor substrate.

[0030] This allows the first semiconductor substrate to suppress noise transmitted from the first portion of the electrical path passing through the first wiring layer to the surrounding circuit.

[0031] Furthermore, for example, an imaging apparatus according to the eighth aspect of the present disclosure is an imaging apparatus according to the seventh aspect, further comprising a through electrode that penetrates the first semiconductor substrate, is electrically connected to the pixel array and the peripheral circuit, and is electrically insulated from the electrical path, wherein the second portion of the electrical path does not overlap with the through electrode in a plan view.

[0032] This reduces noise caused by the voltage in the second part of the signal between the pixel array and the peripheral circuitry passing through the through-electrode.

[0033] Furthermore, for example, an imaging device according to the ninth aspect of the present disclosure is an imaging device according to any one of the first to eighth aspects, wherein the second substrate is arranged in the middle of the electrical path and further includes a switch circuit that switches the voltage supplied to the second electrode.

[0034] This allows for the reduction of transistors other than pixel transistors formed on the first substrate, such as limiting the number of transistors formed on the first substrate to only pixel transistors, while still having a switch circuit within the imaging device to switch the voltage supplied to the second electrode. As a result, it becomes possible to form transistors on the first substrate using process parameters specialized for pixel transistors, improving the characteristics of the transistors in the pixels. Furthermore, it becomes possible to reduce the number of masks used when manufacturing the first substrate, thereby lowering costs.

[0035] Furthermore, for example, the imaging device according to the tenth aspect of this disclosure is the imaging device according to the ninth aspect, wherein the switch circuit is located at the corner of the second substrate in a plan view.

[0036] This allows the switch circuit that performs the voltage switching to be separated from the pixel array, thereby reducing noise in the signals transmitted and received by the pixel array.

[0037] Furthermore, for example, an imaging device according to the 11th aspect of the present disclosure is an imaging device according to any one of the first to tenth aspects, wherein the second substrate includes a pad to which an external voltage is applied, and the electrical path connects the pad and the second electrode.

[0038] As a result, there is no need to form pads on the first substrate, eliminating the need to ensure sufficient thickness on the first substrate for pad formation. Therefore, for example, the length of the contact plug connected to the first electrode that collects signal charge can be shortened. Since the contact plug becomes part of the charge storage region that stores signal charge, shortening the contact plug reduces the capacitance of the charge storage region, thereby increasing the signal charge conversion gain. Consequently, the signal-to-noise ratio can be improved, and the image quality of the imaging device can be enhanced.

[0039] Furthermore, for example, the imaging device according to the twelfth aspect of this disclosure is the imaging device according to the eleventh aspect, wherein the pad is located at the corner of the second substrate in a plan view.

[0040] This allows the pads to which external voltage is applied to be separated from the pixel array, thereby reducing noise in the signals transmitted and received by the pixel array.

[0041] Furthermore, for example, a camera system according to the 13th aspect of this disclosure comprises an imaging device according to any one of the 1st to 12th aspects.

[0042] As a result, the camera system according to this embodiment, equipped with the above-mentioned imaging device, is capable of improving image quality.

[0043] Embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. The various embodiments described herein can be combined with each other as long as they do not conflict. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components. In each figure, components having substantially the same function are indicated by a common reference numeral, and redundant descriptions may be omitted or simplified.

[0044] Furthermore, the various elements shown in the drawings are for illustrative purposes only, and their dimensional ratios and appearance may differ from those of the actual object. In other words, each drawing is a schematic representation and not necessarily a strictly accurate depiction. Therefore, for example, the scale in each drawing may not necessarily match.

[0045] Furthermore, in this specification, terms indicating relationships between elements, such as perpendicular or parallel, terms indicating the shape of elements, such as circular or rectangular, and numerical ranges are not expressions that represent only strict meanings, but also expressions that include substantially equivalent ranges, such as differences of a few percent.

[0046] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Specifically, the light-receiving side of the imaging device is defined as "upper," and the side opposite the light-receiving side is defined as "lower." Similarly, for the "upper surface" and "lower surface" of each component, the light-receiving side of the imaging device is defined as the "upper surface," and the side opposite the light-receiving side is defined as the "lower surface." Note that terms such as "upper," "lower," "upper surface," and "lower surface" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device when in use. In addition, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other. Furthermore, in this specification, "planar view" refers to a view taken from a direction perpendicular to the semiconductor substrate (in other words, in the thickness direction of the semiconductor substrate).

[0047] Furthermore, in this specification and the drawings, the X, Y, and Z axes represent the three axes of a three-dimensional Cartesian coordinate system. In the following embodiments, the Z-axis direction is the thickness direction of the semiconductor substrate and the stacking direction of the semiconductor substrate. Also, the negative side of the Z-axis is defined as "downward," and the positive side of the Z-axis is defined as "upward."

[0048] Furthermore, in this specification, "connection" means an electrical connection unless otherwise specified.

[0049] Furthermore, in this specification, for convenience, not only visible light but also invisible light such as ultraviolet light and near-infrared light will be referred to as "light."

[0050] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., unless otherwise specified, do not refer to the number or order of constituent elements, etc., but are used for the purpose of avoiding confusion and distinguishing similar constituent elements, etc.

[0051] (Embodiment 1) The imaging device according to Embodiment 1 will now be described.

[0052] [composition] First, an overview of the configuration of the imaging device according to this embodiment will be described. Figure 1 is a block diagram showing an example of the configuration of the imaging device 100 according to this embodiment.

[0053] As shown in Figure 1, the imaging device 100 includes a first substrate 10 including a pixel array 30 composed of a plurality of pixels 31, a second substrate 20 including peripheral circuits 51 connected to the pixel array 30, and a group of metal junctions 40 consisting of a plurality of metal junctions 41 for electrically connecting the pixel array 30 and the peripheral circuits 51 between the first substrate 10 and the second substrate 20. The peripheral circuits 51 include circuits for driving the plurality of pixels 31 and circuits for processing signals output by the plurality of pixels 31, which are directly or indirectly connected to the pixel array 30. In the example shown in Figure 1, the peripheral circuits 51 include a vertical scanning circuit 52, an AD (Analog to Digital) conversion circuit 53, a DAC (Digital to Analog Converter) 54, a memory 55, a logic circuit 56, and an output circuit 59. As will be described later, the peripheral circuits 51 may also include circuits not shown in Figure 1. Furthermore, some of the peripheral circuits 51 may be located on the first substrate 10.

[0054] As will be described in detail later, the first substrate 10 and the second substrate 20 are stacked on top of each other. The electrical connection between the pixel array 30 and the peripheral circuit 51 between the first substrate 10 and the second substrate 20 is made via multiple metal junctions 41 of the metal junction group 40. Depending on the arrangement of the peripheral circuit 51, some of the connections made via the metal junctions 41 described below may be made without using the metal junctions 41.

[0055] The pixel array 30 includes a plurality of pixels 31 arranged in two dimensions. The plurality of pixels 31 are arranged, for example, along the row and column directions in a planar view. Each of the plurality of pixels 31 includes a photoelectric converter that converts light into electric charge and outputs a signal corresponding to the incidence of light on the photoelectric converter. In the example shown in Figure 1, the plurality of pixels 31 are depicted as being spatially separated from each other, but this is merely for illustrative purposes, and the plurality of pixels 31 may also be arranged continuously without any spacing between them.

[0056] Multiple pixels 31 are connected to a voltage line Lv. Although Figure 1 shows one voltage line Lv, multiple pixels 31 may be connected to multiple voltage lines Lv. The voltage line Lv is connected via a metal junction 41 to an external power supply that provides voltages such as the power supply voltage VDD and reset voltage VR, which will be described later. At least a portion of the power supply may be provided in the imaging device 100. Alternatively, the voltage line Lv may be connected to the external power supply without going through the metal junction 41.

[0057] The vertical scanning circuit 52 is connected to the multiple pixels 31 via control signal lines Lcon provided for each row of pixels 31, and performs signal reading and resetting of the pixels 31 for each row of pixels 31. The vertical scanning circuit 52 supplies control signals to the multiple pixels 31 via the control signal lines Lcon to control the driving of the multiple pixels 31. Figure 1 shows a diagram in which one control signal line Lcon is provided for each row of pixels 31, but multiple control signal lines Lcon may be provided for each row of pixels 31. The control signal lines Lcon are connected to the vertical scanning circuit 52 via metal joints 41.

[0058] The AD conversion circuit 53 converts signals from multiple pixels 31 into digital signals. Specifically, the AD conversion circuit 53 is connected to the multiple pixels 31 via vertical signal lines 77 provided for each row of pixels 31, and converts the analog signals output for each row of pixels 31 into digital signals. The vertical signal lines 77 are connected to the AD conversion circuit 53 via metal junctions 41. The AD conversion circuit 53 may perform noise suppression signal processing, such as correlated double sampling, before AD conversion.

[0059] The AD conversion circuit 53 includes, for example, a sample-and-hold circuit, a comparator, and a counter circuit. The sample-and-hold circuit temporarily holds the analog signal output from the pixel 31 to the vertical signal line 77 and outputs it to the comparator. The comparator compares the output from the sample-and-hold circuit with a reference signal from the DAC 54. The counter circuit counts the time until the comparison result from the comparator inverts and generates a digital signal as the count result. The DAC 54 generates a reference signal with a ramp waveform as an analog signal and supplies the generated reference signal to the AD conversion circuit 53. The configuration of the AD conversion circuit 53 is not limited to the above configuration. For example, the AD conversion circuit 53 may include an amplifier circuit that amplifies the pixel signal, and an attenuator that reduces the pixel signal or the reference signal. Also, a successive approximation ADC (SAR-ADC) or a delta-sigma ADC may be used in the AD conversion circuit 53.

[0060] Memory 55 temporarily stores, for example, the digital signal converted by the AD conversion circuit 53. Memory 55 may also temporarily store the digital signal processed by the signal processing circuit 58.

[0061] The logic circuit 56 is a digital circuit that processes digital signals. In the example shown in Figure 1, the logic circuit 56 includes a control circuit 57 and a signal processing circuit 58. The logic circuit 56 can be implemented, for example, by a microcontroller or one or more processors. The functions of the logic circuit 56 may be implemented by a combination of general-purpose processing circuits and software, or by hardware specialized for such processing. The logic circuit 56 is composed, for example, of a plurality of standard cells formed on a semiconductor substrate. A standard cell is a circuit block having a specific function, such as a logic gate, flip-flop, or multiplexer. Although the control circuit 57 and the signal processing circuit 58 are shown as separate blocks, the control circuit 57 and the signal processing circuit 58 may be implemented by a single processor or the like.

[0062] The control circuit 57 controls the drive of the imaging device 100. For example, the control circuit 57 controls the drive of at least one of the circuits included in the peripheral circuit 51.

[0063] The signal processing circuit 58 processes the digital signal converted by the AD conversion circuit 53. For example, the signal processing circuit 58 processes the data stored in the memory 55 as needed and outputs it to the outside via the output circuit 59 at the appropriate timing.

[0064] The output circuit 59 outputs the data from the signal processing circuit 58 to the outside.

[0065] Next, the circuit configuration of the pixel 31 according to this embodiment will be described. Figure 2 is a diagram showing an example of the circuit configuration of the pixel 31 according to this embodiment. Each of the plurality of pixels 31 has, for example, the circuit configuration shown in Figure 2.

[0066] As shown in Figure 2, the pixel 31 includes a photoelectric conversion unit 70 and a detection circuit 32 which includes an amplification transistor 33, a selection transistor 34, and a reset transistor 35.

[0067] The photoelectric conversion unit 70 generates positive and negative charges upon the incidence of light. In other words, the photoelectric conversion unit 70 converts light into electric charge. Positive and negative charges are typically hole-electron pairs. As will be described in detail later, the photoelectric conversion unit 70 includes a pixel electrode 71, a counter electrode 72 facing the pixel electrode 71, and a photoelectric conversion layer 73 located between the pixel electrode 71 and the counter electrode 72.

[0068] The counter electrode 72 of the photoelectric conversion unit 70 is connected to the connecting electrode 75, and a control voltage Vp is applied to the counter electrode 72 when the imaging device 100 is in operation. By applying the control voltage Vp to the counter electrode 72, one of the positive and negative charges generated in the photoelectric conversion layer 73 by photoelectric conversion can be selectively stored in the charge storage region as a signal charge. In the following description, unless otherwise specified, the example will be that of the positive charges, i.e., holes, generated by photoelectric conversion are used as the signal charge.

[0069] The detection circuit 32 is connected to the pixel electrode 71 of the photoelectric conversion unit 70 and detects the signal charge generated by the photoelectric conversion unit 70.

[0070] The amplification transistor 33, the selection transistor 34, and the reset transistor 35 are, for example, field-effect transistors (FETs) formed on a semiconductor substrate supporting the photoelectric conversion unit 70. In the example shown in Figure 2, each of the amplification transistor 33, the selection transistor 34, and the reset transistor 35 is an N-channel MOSFET (Metal Oxide Semiconductor FET). Note that which of the two diffusion regions of the FET corresponds to the source and which corresponds to the drain is determined by the polarity of the FET and the potential level at that time. Therefore, which is the source and which is the drain may vary depending on the operating state of the FET.

[0071] The gate of the amplification transistor 33 is connected to the charge storage node FD, which is connected to the pixel electrode 71 of the photoelectric conversion unit 70. The charge storage node FD is at least a part of the charge storage region where the signal charge generated by the photoelectric conversion unit 70 is stored, and the potential of the charge storage node FD is substantially the same as the potential of the charge storage region. The potential of the charge storage node FD of the pixel 31 after the exposure period corresponds to the amount of signal charge stored in the charge storage region of the pixel 31 during the exposure period.

[0072] The power supply voltage VDD is applied to the drain of the amplification transistor 33 via a metal junction 41. The power supply voltage VDD is, for example, about 3.3V. The wiring connecting the drain of the amplification transistor 33 and the metal junction 41 corresponds to one of the voltage lines Lv described above. The metal junction 41 connected to the drain of the amplification transistor 33 is shared by, for example, multiple pixels 31. The source of the amplification transistor 33 is connected to the corresponding vertical signal line 77 via a selection transistor 34. The drain of the amplification transistor 33 outputs an analog signal corresponding to the potential of the charge storage node FD to the corresponding vertical signal line 77 via the selection transistor 34. When the selection transistor 34 is ON, the amplification transistor 33 forms a source follower circuit together with a current source (not shown) connected to the vertical signal line 77. The current source is, for example, one of the circuits included in the peripheral circuit 51.

[0073] A row selection signal SEL is supplied to the gate of the selection transistor 34 from the vertical scanning circuit 52 via a metal junction 41. The row selection signal SEL controls the on and off states of the selection transistor 34. The wiring connecting the gate of the selection transistor 34 to the metal junction 41 corresponds to one of the control signal lines Lcon described above. The metal junction 41 connected to the gate of the selection transistor 34 is provided, for example, for each row of multiple pixels 31. By controlling the on and off states of the selection transistor 34, the vertical scanning circuit 52 can read the output of the amplification transistor 33 of the selected pixel 31 to the corresponding vertical signal line 77. The analog signal from the amplification transistor 33 output to the vertical signal line 77 is input to the AD conversion circuit 53 via the metal junction 41. The metal junction 41 connected to the vertical signal line 77 is provided, for example, for each column of multiple pixels 31 corresponding to the vertical signal line 77.

[0074] One of the drains and sources of the reset transistor 35 is connected to the charge storage node FD. A reset voltage VR is applied to the other drain and source of the reset transistor 35 via a metal junction 41. The reset voltage VR is, for example, a voltage of 0V or near 0V. The wiring connecting the other drain and source of the reset transistor 35 to the metal junction 41 corresponds to one of the other voltage lines Lv described above. The metal junction 41 connected to the other drain and source of the reset transistor 35 is shared, for example, by multiple pixels 31.

[0075] A reset signal RST is supplied to the gate of the reset transistor 35 from the vertical scanning circuit 52 via a metal junction 41. The reset signal RST controls the on and off states of the reset transistor 35. The wiring connecting the gate of the reset transistor 35 to the metal junction 41 corresponds to one of the control signal lines Lcon described above. When the reset transistor 35 is turned on, the potential of the charge storage node FD is reset to the reset voltage VR. The metal junction 41 connected to the gate of the reset transistor 35 is provided, for example, for each row of pixels 31.

[0076] Next, the detailed device configuration of the imaging device 100 according to this embodiment will be described with reference to Figures 3 to 6.

[0077] Figure 3 is a schematic cross-sectional view showing an example of the device structure of the imaging device 100 according to this embodiment. Figure 4 is a schematic plan view showing an example of the planar layout of the first substrate 10 of the imaging device 100 according to this embodiment. Figure 5 is a schematic plan view showing an example of the planar layout of the second substrate 20 of the imaging device 100 according to this embodiment. Figure 6 is an enlarged plan view of the vicinity of the corner 7 of the first substrate 10 of the imaging device 100 according to this embodiment. Figure 3 is a cross-sectional view when the imaging device 100 is cut in a crank shape and unfolded in region III in Figures 4 and 5, passing through the pad 92, control voltage supply line 5, connecting electrode 75, AD conversion circuit 53, and pixel array 30 in a plan view. Note that in the cross-sectional views of the imaging device according to this disclosure, such as Figure 3, for ease of viewing, the shading indicating the cross-section is omitted for parts composed of insulating materials such as insulating layers 13, 14, 80 and 81 and protective layer 83. Furthermore, in Figure 3, metal joints 41 that do not appear in the cross-section (for example, metal joints 41 located on the near side of the cross-section) are shown by dashed lines. Also, in the plan views of the first and second substrates according to this disclosure, such as Figures 4 to 6, patterns are added to the areas where the metal joint groups 40 are located for clarity. In addition, in Figure 5, the positions of the pads 92 placed on the first substrate 10 are shown by dashed lines.

[0078] As shown in Figure 3, the first substrate 10 and the second substrate 20 are stacked on top of each other. The first substrate 10 and the second substrate 20 have the same shape and size, for example, in a plan view, and their outer edges coincide. The first substrate 10 and the second substrate 20 are joined at the interface s1 between the first substrate 10 and the second substrate 20.

[0079] As shown in Figure 3, the first substrate 10 includes a semiconductor substrate 11 and a wiring layer 12 located below the semiconductor substrate 11 and laminated on the semiconductor substrate 11. In the example shown in Figure 3, the wiring layer 12 is located on the lower surface of the semiconductor substrate 11. In the example shown in Figure 3, the first substrate 10 further includes a detection circuit 32, insulating layers 13, 14, 80 and 81, a photoelectric conversion unit 70, a connecting electrode 75, a light-shielding layer 82, a protective layer 83, a color filter 84, a microlens 86, and a pad 92. The detection circuit 32, the photoelectric conversion unit 70, the color filter 84, and the microlens 86 are included in each pixel 31.

[0080] The second substrate 20 includes a semiconductor substrate 21 and a wiring layer 22 located above the semiconductor substrate 21 and laminated on the semiconductor substrate 21. In the example shown in Figure 3, the wiring layer 22 is located on the upper surface of the semiconductor substrate 21.

[0081] The first substrate 10 and the second substrate 20 are stacked such that the wiring layers 12 and 22 are located between the semiconductor substrate 11 and the semiconductor substrate 21. This makes it easier to connect the wiring of wiring layer 12 and wiring layer 22. Wiring layer 12 and wiring layer 22 are joined at interface s1. Semiconductor substrate 11 is an example of a first semiconductor substrate, and semiconductor substrate 21 is an example of a second semiconductor substrate. Also, wiring layer 12 is an example of a first wiring layer, and wiring layer 22 is an example of a second wiring layer.

[0082] The semiconductor substrates 11 and 21 are, for example, p-type or n-type semiconductor substrates in which various impurity regions are formed.

[0083] A detection circuit 32 for each pixel 31 is formed on the lower surface of the semiconductor substrate 11. Figure 3 shows some of the transistors in the detection circuit 32. The first substrate 10 may have a stacked structure in which multiple semiconductor substrates, including the semiconductor substrate 11, are stacked. In this case, each transistor in the detection circuit 32 is formed separately on multiple semiconductor substrates.

[0084] The wiring layer 12 includes, for example, a plurality of wires, an interlayer insulating layer between the wires, a plurality of vias for electrical connection of the wires spanning the interlayer insulating layer, and a plurality of contact plugs for connecting the wires to the semiconductor substrate 11. The wiring layer 12 also includes the gate electrodes of transistors formed on the semiconductor substrate 11.

[0085] Peripheral circuits 51 are formed on the upper surface of the semiconductor substrate 21. Figure 3 shows a part of the AD conversion circuit 53 included in the peripheral circuit 51. The second substrate 20 may have a laminated structure in which multiple semiconductor substrates, including the semiconductor substrate 21, are stacked. In this case, each circuit of the peripheral circuit 51 is formed separately on multiple semiconductor substrates.

[0086] The wiring layer 22 includes, for example, a plurality of wirings, an interlayer insulating layer between the wirings, a plurality of vias for electrical connection of wirings spanning the interlayer insulating layer, and a plurality of contact plugs for connecting the wirings to the semiconductor substrate 21. The wiring layer 22 also includes the gate electrodes of transistors formed on the semiconductor substrate 21.

[0087] The photoelectric conversion unit 70 is positioned above the semiconductor substrate 11. The photoelectric conversion unit 70 faces the wiring layer 12 via the semiconductor substrate 11. The photoelectric conversion unit 70 is laminated on the semiconductor substrate 11 via insulating layers 13 and 14. The insulating layer 13 is laminated on the upper side of the semiconductor substrate 11. The insulating layer 14 is laminated on the upper side of the insulating layer 13. The insulating layers 13 and 14 are formed of an insulating material such as silicon dioxide.

[0088] As described above, the photoelectric conversion unit 70 includes a pixel electrode 71, a counter electrode 72, and a photoelectric conversion layer 73. The pixel electrode 71 is an example of a first electrode, and the counter electrode 72 is an example of a second electrode. The photoelectric conversion unit 70 may further include other layers such as a charge blocking layer, a buffer layer, or a charge transport layer in at least one of the spaces between the pixel electrode 71 and the photoelectric conversion layer 73, and between the photoelectric conversion layer 73 and the counter electrode 72.

[0089] The pixel electrode 71 is located on the upper surface of the insulating layer 14. The pixel electrode 71 is a film-like electrode. The pixel electrode 71 may include at least one selected from metals, metal compounds, and polysilicon doped with impurities to impart conductivity. Examples of metals include copper, titanium, tantalum, and aluminum. Examples of metal compounds include metal nitrides. Examples of metal nitrides include titanium nitride and tantalum nitride. The pixel electrode 71 collects one of the positive and negative charges generated in the photoelectric conversion layer 73 as a signal charge. The pixel electrode 71 is electrically isolated from the pixel electrodes 71 of other adjacent pixels 31 by being spatially separated from them. The pixel electrode 71 is connected to a contact plug 76 and connected to a detection circuit 32 via the contact plug 76 and wiring in the wiring layer 12. The contact plug 76 is in contact with the lower surface of the pixel electrode 71. The contact plug 76 extends from the lower surface of the pixel electrode 71, through the insulating layers 13 and 14 and the semiconductor substrate 11, into the wiring layer 12. The contact plug 76 is separated from the semiconductor substrate 11 by an insulating film covering the sides of the contact plug 76.

[0090] The photoelectric conversion layer 73 is located above the pixel electrode 71 and covers the pixel electrode 71. The photoelectric conversion layer 73 contains an organic semiconductor material or an inorganic semiconductor material such as amorphous silicon, and receives light incident through the counter electrode 72 to generate positive and negative charges by photoelectric conversion. The photoelectric conversion layer 73 converts light into signal charges. The positive and negative charges are, for example, hole-electron pairs. The photoelectric conversion layer 73 is formed continuously, for example, across multiple pixels 31. The photoelectric conversion layer 73 is shared by multiple pixels 31. The photoelectric conversion layer 73 may be provided separately for each pixel 31 or for each block of two or more pixels 31.

[0091] The counter electrode 72 is located above the photoelectric conversion layer 73 and covers the photoelectric conversion layer 73. The counter electrode 72 faces the pixel electrode 71 via the photoelectric conversion layer 73. The counter electrode 72 is a film-like electrode. In the example shown in Figure 3, the counter electrode 72 and the photoelectric conversion layer 73 are aligned in terms of their side positions in a plan view. The counter electrode 72 is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is positioned on the light-receiving surface side of the photoelectric conversion layer 73. The counter electrode 72 is formed continuously across multiple pixels 31, for example, similar to the photoelectric conversion layer 73. That is, the counter electrodes 72 of multiple pixels 31 are electrically connected to each other. The counter electrodes 72 may be provided separately for each pixel 31 or for each block of two or more pixels 31.

[0092] During the operation of the imaging device 100, the potential of the counter electrode 72 is controlled to make the potential of the counter electrode 72 different from the potential of the pixel electrode 71, thereby allowing the signal charge generated by photoelectric conversion to be collected by the pixel electrode 71. For example, the potential of the counter electrode 72 is controlled so that its potential is higher than the potential of the pixel electrode 71. Specifically, during the operation of the imaging device 100, a first voltage V1, which is different from the reset voltage VR, is applied to the counter electrode 72 as a control voltage Vp supplied by the electrical path 90. The first voltage V1 is a fixed voltage that does not change in magnitude during the operation of the imaging device 100. A specific example of the first voltage V1 is a positive voltage of about 10V. As a result, holes from the hole-electron pairs generated in the photoelectric conversion layer 73 can be collected as signal charges by the pixel electrode 71. The signal charges collected by the pixel electrode 71 are stored in a charge storage region connected to the pixel electrode 71 and detected by the detection circuit 32. When electrons are used as the signal charge, a first voltage V1 is applied to the counter electrode 72 such that the potential of the counter electrode 72 is lower than the potential of the pixel electrode 71.

[0093] The imaging device 100 may perform a global shutter operation during operation. In this case, for example, a first voltage V1 is applied to the counter electrode 72 during the exposure period of all pixels 31 at once, which moves the signal charge generated in the photoelectric conversion layer 73 to the pixel electrode 71. In addition, a second voltage V2 is applied to the counter electrode 72 during the non-exposure period such that substantially no movement of the signal charge generated in the photoelectric conversion layer 73 occurs. By pulse driving of such a control voltage Vp, signal charge is not collected on the pixel electrode 71 during the non-exposure period, and the signal charge collected on the pixel electrode 71 during the exposure period can be detected. The second voltage V2 is, for example, a fixed voltage whose magnitude does not change during the operation of the imaging device 100. The second voltage V2 is, for example, a voltage such that the potential difference between the counter electrode 72 and the pixel electrode 71 is 0V or near 0V. Furthermore, during the exposure period of the imaging device 100, the control voltage Vp may be pulsed, such that a first voltage V1 and a second voltage V2 are repeatedly applied alternately to the counter electrode 72. This allows the sensitivity of the imaging device 100 to be adjusted. Thus, in the imaging device 100, the control voltage Vp supplied to the counter electrode 72 can fluctuate with an amplitude of about 10V.

[0094] The color filter 84 is located above the counter electrode 72 and faces the counter electrode 72 via an insulating layer 81 and a protective layer 83. The color filter 84 is formed, for example, as an on-chip color filter by patterning, and a photosensitive resin in which dyes or pigments are dispersed is used. The microlens 86 is located above the color filter 84. The microlens 86 is formed, for example, as an on-chip microlens, and an ultraviolet photosensitive material is used. The insulating layer 81 and the protective layer 83 are formed, for example, from an insulating material such as silicon dioxide.

[0095] As shown in Figure 4, the first substrate 10 includes a pixel array 30, a connecting electrode 75, and a pad group 91 composed of multiple pads including a pad 92. Also, as shown in Figure 5, the second substrate 20 includes peripheral circuits 51. Furthermore, a group of metal joints 40, composed of multiple metal joints 41, is formed on both the first substrate 10 and the second substrate 20. The multiple metal joints 41 of the group of metal joints 40 are formed spanning both the first substrate 10 and the second substrate 20. In a plan view, the connecting electrode 75, the group of metal joints 40, and the pad group 91 are arranged in the region surrounding the pixel array 30.

[0096] The connecting electrode 75 is elongated in a plan view, extending along the outer periphery of the pixel array 30. In the example shown in Figure 4, the connecting electrode 75 is elongated rectangular in a plan view. In a plan view, the connecting electrode 75 is located on the outer periphery of the first substrate 10, relative to the pixel array 30. In the example shown in Figure 4, in a plan view, four connecting electrodes 75 are arranged along each of the four sides of the rectangle of the pixel array 30, surrounding the pixel array 30. Note that the number of connecting electrodes 75 is not limited to the example shown in Figure 4; for example, there may be one, two, or three.

[0097] As shown in Figure 3, the connecting electrode 75 is located on the upper surface of the insulating layer 14. The connecting electrode 75 is a film-like electrode. In the example shown in Figure 3, the connecting electrode 75 is located in the same layer as the pixel electrode 71. This allows the connecting electrode 75 to be formed using the same process as the pixel electrode 71, thereby simplifying the manufacturing process of the imaging device 100. In this specification, "located in the same layer" means that the distance from the semiconductor substrate 11 is the same.

[0098] The material used for the connecting electrode 75 can be the same material used for the pixel electrode 71. The connecting electrode 75 may contain the same material as the material used for the pixel electrode 71, or the material used for the connecting electrode 75 may be the same as the material used for the pixel electrode 71. This allows for the use of common materials for the pixel electrode 71 and the connecting electrode 75, thereby reducing the number of materials used in the manufacture of the imaging device 100.

[0099] In the example shown in Figure 3, the connecting electrode 75 is electrically connected to the counter electrode 72 via a conductive light-shielding layer 82. Specifically, the connecting electrode 75 is electrically connected to the light-shielding layer 82 on its upper surface, and the counter electrode 72 is electrically connected to the light-shielding layer 82 on its side facing the connecting electrode 75. The light-shielding layer 82 is in contact with the upper surface of the connecting electrode 75 and the side of the counter electrode 72. The connecting electrode 75 may also be connected to the counter electrode 72 via a conductor other than the light-shielding layer 82, as long as it is electrically connected to the counter electrode 72. Alternatively, the counter electrode 72 may extend over the connecting electrode 75 so that it can be directly connected to the connecting electrode 75.

[0100] The light-shielding layer 82 covers the connecting electrode 75 and the counter electrode 72 from above. In a portion of the area where the pixel array 30 is arranged, the light-shielding layer 82 is located between the insulating layer 81 and the protective layer 83 and faces the counter electrode 72. The light-shielding layer 82 shields the light incident on the photoelectric conversion unit 70 of some of the pixels 31, specifically the pixels 31 located at the ends of the pixel array 30. Therefore, pixels 31 whose photoelectric conversion unit 70 is covered by the light-shielding layer 82 become OB (Optical Black) pixels. In Figure 3, pixels 31 located at the ends of the pixel array 30 are shown, which are OB pixels whose photoelectric conversion unit 70 is covered by the light-shielding layer 82. However, in pixels 31 other than those at the ends of the pixel array 30, the photoelectric conversion unit 70 is not covered by the light-shielding layer 82, and the protective layer 83 is placed instead of the light-shielding layer 82, allowing light to be incident on the photoelectric conversion unit 70. In multiple pixels 31, the structure of the OB pixels and the non-OB pixels is the same in parts other than the light-shielding layer 82.

[0101] The light-shielding layer 82 includes at least one selected from the group consisting of metals and metal compounds. For example, the light-shielding layer 82 includes at least one selected from the group consisting of titanium, titanium nitride, aluminum, silicon, copper-added aluminum, copper, and tungsten. The light-shielding layer 82 may also include an alloy containing at least two of the above-mentioned materials.

[0102] The multiple metal joints 41 constituting the metal joint group 40 are arranged in a predetermined pattern in a plan view. Figure 4 shows the area in which the multiple metal joints 41 are arranged as the metal joint group 40. As shown in Figure 4, the metal joint group 40 is elongated in shape in a plan view, extending along the outer circumference of the pixel array 30. In other words, the multiple metal joints 41 constituting the metal joint group 40 are arranged along the outer circumference of the pixel array 30. In the example shown in Figure 4, the metal joint group 40 is located on the outer circumference side of the first substrate 10, further than the connecting electrode 75, in a plan view. Also, in the example shown in Figure 4, in a plan view, two metal joint groups 40 are arranged together with the connecting electrode 75 along each of two adjacent sides of the rectangle of the pixel array 30. The number of metal joint groups 40 is not limited to the example shown in Figure 4, and may be, for example, one, three, or four. Furthermore, as shown in Figure 5, the metal bonding group 40 is positioned on the outer periphery of the second substrate 20, relative to the peripheral circuitry 51, in a plan view. A portion of the peripheral circuitry 51 may also be positioned on the outer periphery of the second substrate 20, relative to the metal bonding group 40, in a plan view. The imaging device 100 may include one or more metal bonding groups 41 positioned to overlap with at least one of the pixel array 30, the connecting electrodes 75, and the peripheral circuitry 51 in a plan view.

[0103] As shown in Figure 3, the metal joint 41 joins the wiring layer 12 and the wiring layer 22 at interface s1. The metal joint 41 includes, for example, pad wirings arranged on the wiring layer 12 and the wiring layer 22, and the pad wirings form a metal joint with each other. The metal joint is, for example, a Cu-Cu joint, but it may be a joint between metals other than Cu. The joint between the wiring layer 12 and the wiring layer 22 is a hybrid joint including a metal joint and an insulating film joint. The metal joint 41 is electrically insulated from the electrical path 90 for supplying a control voltage Vp to the counter electrode 72 in the first substrate 10 and the second substrate 20. In Figure 3, two of the multiple metal joints 41 are shown representatively. As described above, the metal joint 41 is electrically connected to the pixel array 30 and the peripheral circuit 51.

[0104] The multiple pads constituting the pad group 91 are plate-shaped metal terminals for sending and receiving power and signals from outside the imaging device 100. In a plan view, the pad group 91 is located on the outer periphery of the first substrate 10, further than the pixel array 30 and peripheral circuits 51. In the example shown in Figure 4, the multiple pads constituting the pad group 91 are arranged along the outer periphery at the edge of the first substrate 10 in a plan view. The pad group 91 includes a pad 92 to which a control voltage Vp is applied from the outside. As shown in Figure 3, the pad 92 is located above the semiconductor substrate 11. The pad 92 is placed within an insulating layer 14. An insulating layer 13 is placed between the pad 92 and the semiconductor substrate 11. The upper surface of the pad 92 is exposed and is connected to an external voltage supply circuit by wire bonding or the like on the upper surface of the pad 92. The voltage supply circuit supplies the pad 92 with, for example, a first voltage V1 and a second voltage V2 as described above, as control voltage Vp. The pad 92 is connected to an electrical path 90 for supplying a control voltage Vp to the counter electrode 72.

[0105] As shown in Figure 6, the pad 92 is located at the corner 7 of the first substrate 10 in a plan view. The corner 7 is an area outside the extended lines of each side of the pixel array 30 on the first substrate 10 (the dashed lines shown in Figure 6) in a plan view. Therefore, in a plan view, the pad 92 does not overlap with the pixel array 30 and the metal junction group 40, and is not located in an area where the pixel array 30 is extended in the direction of the arrangement of the multiple pixels 31 (in the illustrated example, the X-axis direction, which is the row direction, and the Y-axis direction, which is the column direction). By positioning the pad 92 at the corner 7 of the first substrate 10 in a plan view, the pad 92 to which the control voltage Vp is applied from the outside can be separated from the pixel array 30, thereby reducing noise in the signals transmitted and received by the pixel array 30. Furthermore, the pad 92 can also be separated from the multiple metal junctions 41 arranged along the outer circumference of the pixel array 30, thereby reducing noise in the signals flowing through the multiple metal junctions 41. The pads 92 are, for example, positioned at the corners 7 at each of the four corners of the first substrate 10. The electrical paths 90 are provided at four locations, for example, corresponding to each of the four corner pads 92.

[0106] In the example shown in Figure 5, the peripheral circuit 51 includes, in addition to the vertical scanning circuit 52, AD conversion circuit 53, DAC 54, memory 55, logic circuit 56, and output circuit 59 described above, a PLL (Phase Locked Loop) 60, a ring oscillator 61, a reference circuit 62, and a bias circuit 63.

[0107] Of the circuits included in the peripheral circuit 51, the vertical scanning circuit 52, AD conversion circuit 53, DAC 54, memory 55, PLL 60, ring oscillator 61, reference circuit 62, and bias circuit 63 are all analog circuits through which analog signals flow.

[0108] The PLL60 performs frequency synthesis and clock generation. The PLL60 compares the phase of the input signal with the phase of the output signal and adjusts the difference between these phases through a feedback loop. This synchronizes the frequency of the output signal with the input signal. The PLL60 outputs a clock to, for example, the logic circuit 56 and the output circuit 59. In the example shown in Figure 5, the PLL60 is positioned adjacent to the logic circuit 56 and the output circuit 59 in a plan view.

[0109] The ring oscillator 61 generates high-frequency signals used in digital circuits. In the example shown in Figure 5, the ring oscillator 61 is positioned adjacent to the PLL 60 and logic circuit 56 in a plan view. The reference circuit 62 supplies a reference voltage to other circuits such as the AD conversion circuit 53. The bias circuit 63 supplies a bias voltage to each circuit.

[0110] Furthermore, in the example shown in Figure 5, the AD conversion circuit 53 is positioned adjacent to the DAC 54 and the memory 55 in a plan view. The memory 55 is positioned adjacent to the AD conversion circuit 53 and the logic circuit 56. Note that the plan view layout of each circuit in the peripheral circuit 51 shown in Figure 5 is just one example and is not limited to the example shown in Figure 5. Also, the circuits included in the peripheral circuit 51 are not limited to the example shown in Figure 5.

[0111] [Electrical path to the counter electrode] Next, the details of the electrical path 90 for supplying a control voltage Vp to the counter electrode 72 will be described. As shown in Figure 3, the electrical path 90 connects the pad 92 and the counter electrode 72. The electrical path 90 includes a first portion 15, which is the part of the electrical path 90 located within the first substrate 10, and a second portion 23, which is the part of the electrical path 90 located within the second substrate 20. In other words, the first substrate 10 contains the first portion 15 of the electrical path 90, and the second substrate 20 contains the second portion 23 of the electrical path 90.

[0112] The electrical path 90 includes a portion of the light-shielding layer 82, a connecting electrode 75, and a control voltage supply line 5 connecting the connecting electrode 75 and the pad 92. In the example shown in Figure 3, the control voltage supply line 5 includes through electrodes 16 and 17, two metal joints 45, and wiring 24. The through electrodes 16 and 17, portions of each of the two metal joints 45, the connecting electrode 75, and a portion of the light-shielding layer 82 are included in the first portion 15. The remaining portions of each of the two metal joints 45 and the wiring 24 are included in the second portion 23. The control voltage Vp applied to the pad 92 is supplied to the opposing electrode 72 by passing through the through electrode 16, one metal joint 45, wiring 24, the other metal joint 45, the through electrode 17, the connecting electrode 75, and a portion of the light-shielding layer 82 in that order. Note that the configuration of the electrical path 90 shown in Figure 3 is an example and is not limited to the example shown in Figure 3. For example, the pad 92 and the counter electrode 72 may be connected via further wiring and vias, etc., not shown in Figure 3, in at least one of the wiring layers 12 and 22.

[0113] The through electrodes 16 and 17 penetrate the semiconductor substrate 11 and extend into the wiring layer 12. The through electrodes 16 and 17 are separated from the semiconductor substrate 11 by an insulating film covering the sides of the through electrodes 16 and 17. The through electrode 16 connects the pad 92 to one metal junction 45 in the first substrate 10. The through electrode 17 connects the connecting electrode 75 to the other metal junction 45 in the first substrate 10. The wiring 24 is wiring included in the wiring layer 22. The wiring 24 connects the two metal junctions 45 in the wiring layer 22. The two metal junctions 45 are the parts that connect the first part 15 and the second part 23 in the electrical path 90. The metal junctions 45, like the metal junction 41, include pad wirings arranged in the wiring layer 12 and the wiring layer 22 respectively, and the pad wirings form metal junctions with each other.

[0114] As shown in Figures 3 and 5, the second portion 23 of the electrical path 90 does not overlap with the AD conversion circuit 53 in a plan view. Therefore, although the control voltage Vp fluctuates in the electrical path 90, the noise applied to the AD conversion circuit 53 due to the fluctuation of the control voltage Vp in the electrical path 90 can be suppressed. Thus, noise is suppressed in the AD conversion circuit 53 to which the signal from the pixel 31 is input, and the image quality of the imaging device 100 can be improved.

[0115] In the example shown in Figure 5, the second part 23 does not overlap with the analog circuits included in the peripheral circuit 51 in a plan view. In Figure 5, the analog circuits are, as described above, the vertical scanning circuit 52, the AD conversion circuit 53, the DAC 54, the memory 55, the PLL 60, the ring oscillator 61, the reference circuit 62, and the bias circuit 63. This reduces the parasitic capacitance between the second part 23 and the wiring of the analog circuits, reduces crosstalk noise between the second part 23 and the analog circuits, and improves the image quality of the imaging device 100. For example, by not overlapping the DAC 54, the noise of the reference signal supplied to the AD conversion circuit 53 can be reduced. Also, for example, by not overlapping the vertical scanning circuit 52, the noise of the control signal for controlling the driving of the pixels 31 can be reduced. In the example shown in Figure 5, the second part 23 does not overlap with all of the peripheral circuit 51 in a plan view, but it may overlap with some of the circuits of the peripheral circuit 51. For example, the second part 23 may overlap with the logic circuit 56 in a plan view.

[0116] Furthermore, as shown in Figures 3 and 5, the second portion 23 does not overlap with the multiple metal joints 41 that constitute the metal joint group 40 in a plan view. This allows the second portion 23 to be separated from the metal joints 41, thereby reducing noise in the signals passing through the metal joints 41. For example, in a plan view, the second portion 23 does not overlap with all the metal joints 41 electrically connected to the pixel array 30 and the peripheral circuit 51. Also, for example, in a plan view, the second portion 23 does not overlap with the wiring connecting the pixel array 30 and the multiple metal joints 41, and the wiring connecting the peripheral circuit 51 and the multiple metal joints 41.

[0117] Furthermore, in the examples shown in Figures 3 and 5, the entire electrical path 90 does not overlap with the multiple metal joints 41 that constitute the metal joint group 40 in a plan view. However, at least one of the first portion 15 and the second portion 23 of the electrical path 90 may overlap with one or more of the multiple metal joints 41 in a plan view. In this case, shield wiring may be placed between at least one of the first portion 15 and the second portion 23 of the electrical path 90 and the one or more metal joints 41. This also reduces noise in the signal passing through the metal joints 41. In addition, if the electrical path 90 and the one or more metal joints 41 overlap, it becomes possible to reduce the area of ​​the imaging device 100.

[0118] [Example 1] Next, we will describe a modified example of Embodiment 1. In the following, we will focus on the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0119] Figure 7 is a schematic cross-sectional view showing an example of the device structure of the imaging device 100A according to this modified example. Figure 7 shows a cross-section of the imaging device 100A at the position corresponding to Figure 3. In Figure 7, through electrodes 43 that do not appear in the cross-section (for example, through electrodes 43 located in front of the cross-section) and wiring connected to the through electrodes 43 are shown by dashed lines.

[0120] As shown in Figure 7, the imaging device 100A according to this modified example differs from the imaging device 100 according to Embodiment 1 mainly in that it includes a first substrate 10A instead of the first substrate 10, and includes a through-electrode group 42 composed of multiple through-electrodes 43 instead of a group of metal joints 40 composed of multiple metal joints 41.

[0121] In the imaging device 100A, the planar layout of the first substrate 10A is, for example, the same as the planar layout of the first substrate 10 of the imaging device 100 shown in Figure 4, but with the metal bonding group 40 replaced by the through-electrode group 42. Similarly, in the imaging device 100A, the planar layout of the second substrate 20 is, for example, the same as the planar layout of the second substrate 20 of the imaging device 100 shown in Figure 5, but with the metal bonding group 40 replaced by the through-electrode group 42.

[0122] As shown in Figure 7, the first substrate 10A has a structure in which the positions of the semiconductor substrate 11 and the wiring layer 12 are swapped on the first substrate 10. In the imaging device 100A, the first substrate 10A and the second substrate 20 are stacked such that the semiconductor substrate 11 and the wiring layer 22 are located between the wiring layer 12 and the semiconductor substrate 21.

[0123] In the first substrate 10A, a detection circuit 32 for each pixel 31 is formed on the upper surface of the semiconductor substrate 11. Figure 7 shows some of the transistors in the detection circuit 32. In the first substrate 10A, the wiring layer 12 is located above the semiconductor substrate 11. In the example shown in Figure 7, the wiring layer 12 is located on the upper surface of the semiconductor substrate 11.

[0124] In the first substrate 10A, the photoelectric conversion unit 70 faces the semiconductor substrate 11 via the wiring layer 12. The photoelectric conversion unit 70 is laminated on the wiring layer 12 via insulating layers 13 and 14. The insulating layer 13 is laminated on the upper surface side of the wiring layer 12. Note that the first substrate 10A does not necessarily include the insulating layer 13, and the insulating layer 14 may be located on the upper surface of the wiring layer 12.

[0125] In the first substrate 10A, the contact plug 76 extends from the lower surface of the pixel electrode 71, through the insulating layers 13 and 14, into the wiring layer 12.

[0126] Multiple through electrodes 43 are electrically connected to the pixel array 30 and the peripheral circuit 51. In the imaging device 100A, the electrical connection between the pixel array 30 and the peripheral circuit 51 between the first substrate 10A and the second substrate 20 is made via the multiple through electrodes 43. In the imaging device 100A, for example, the electrical connection between the pixel array 30 and the peripheral circuit 51 made by multiple metal joints 41 as described using Figures 1 and 2 is made by multiple through electrodes 43. Therefore, by replacing the metal joints 41 with through electrodes 43 in the explanation using Figures 1 and 2 above, it is possible to explain the electrical connection by the through electrodes 43.

[0127] As shown in Figure 7, the through-electrode 43 is a via that penetrates the semiconductor substrate 11. The through-electrode 43 is electrically insulated from the electrical path 90A for supplying a control voltage Vp to the counter electrode 72 in the first substrate 10A and the second substrate 20. The through-electrode 43 is also separated from the semiconductor substrate 11 by an insulating film covering the sides of the through-electrode 43. In Figure 7, two of the multiple through-electrodes 43 are shown representatively.

[0128] The through electrode 43 may include a metal. For example, the through electrode 43 includes at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum.

[0129] As shown in Figure 7, in the imaging device 100A, a control voltage Vp is supplied to the counter electrode 72 by an electrical path 90A. The electrical path 90A connects the pad 92 and the counter electrode 72. The electrical path 90A includes a first portion 15A, which is located within the first substrate 10A, and a second portion 23A, which is located within the second substrate 20.

[0130] The electrical path 90A includes a portion of the light-shielding layer 82, a connecting electrode 75, and a control voltage supply line 5A connecting the connecting electrode 75 to the pad 92. In the example shown in Figure 7, the control voltage supply line 5A includes through electrodes 16 and 17 and wiring 24 and 18. Wiring 18 is wiring included in the wiring layer 12. The through electrode 17 and the connecting electrode 75 are connected via wiring 18. Portions of each of the through electrodes 16 and 17, the connecting electrode 75, a portion of the light-shielding layer 82, and wiring 18 are included in the first portion 15A. The remaining portions of each of the through electrodes 16 and 17, and wiring 24 are included in the second portion 23A. The control voltage Vp applied to the pad 92 is supplied to the counter electrode 72 through the through electrode 16, wiring 24, through electrode 17, wiring 18, connecting electrode 75, and a portion of the light-shielding layer 82 in that order. Note that the configuration of the 90A electrical circuit shown in Figure 7 is just one example and is not limited to the example shown in Figure 7.

[0131] The second portion 23A of the electrical path 90A for supplying the control voltage Vp to the counter electrode 72 does not overlap with the analog circuits of peripheral circuits 51 such as the AD conversion circuit 53 in a plan view, similar to the second portion 23 of the electrical path 90 described above. Therefore, noise in the analog circuits of peripheral circuits 51 can be suppressed, and the image quality of the imaging device 100A can be improved.

[0132] Furthermore, in a plan view, the second portion 23A does not overlap with the multiple through electrodes 43 that constitute the through electrode group 42. This allows the second portion 23 to be separated from the through electrodes 43, thereby reducing noise in the signals passing through the through electrodes 43. For example, in a plan view, the second portion 23A does not overlap with all the through electrodes 43 that are electrically connected to the pixel array 30 and the peripheral circuit 51. Also, in a plan view, the second portion 23A does not overlap with the wiring connecting the pixel array 30 and the multiple through electrodes 43, and the wiring connecting the peripheral circuit 51 and the multiple through electrodes 43.

[0133] Furthermore, in the example shown in Figure 7, the entire electrical path 90A does not overlap with the multiple through electrodes 43 that constitute the through electrode group 42 in a plan view. However, at least one of the first portion 15A and the second portion 23A of the electrical path 90A may overlap with one or more of the multiple through electrodes 43 in a plan view. In this case, a shielded wiring may be placed between at least one of the first portion 15A and the second portion 23A of the electrical path 90A and the one or more through electrodes 43. This also reduces noise in the signal passing through the through electrodes 43. In addition, if the electrical path 90A overlaps with the one or more through electrodes 43, it becomes possible to reduce the area of ​​the imaging device 100A.

[0134] Furthermore, in the imaging device 100A, the semiconductor substrate 11 and the wiring layer 22 are located between the wiring layer 12 and the semiconductor substrate 21. Therefore, the semiconductor substrate 11 can suppress noise transmitted from the first portion 15A of the electrical path 90A passing through the wiring layer 12 to the analog circuits of peripheral circuits 51 such as the AD conversion circuit 53.

[0135] [Differentiation 2] Next, we will describe a modified example of Embodiment 1, Part 2. In the following, we will focus on the differences between Embodiment 1 and Modified Example 1 of Embodiment 1, and will omit or simplify the explanation of the common points.

[0136] Figure 8 is a schematic cross-sectional view showing an example of the device structure of the imaging device 100B according to this modified example. Figure 9 is a schematic plan view showing an example of the planar layout of the first substrate 10 of the imaging device 100B according to this modified example. Figure 10 is a schematic plan view showing an example of the planar layout of the second substrate 20 of the imaging device 100B according to this modified example. Figure 11 is an enlarged plan view of the vicinity of the corner 8 of the second substrate 20 of the imaging device 100B according to this modified example. Figure 8 is a cross-sectional view when the imaging device 100B is cut in a crank shape and unfolded in region VIII in Figures 9 and 10 so as to pass through the pad 92, through hole 94, control voltage supply line 5B, connecting electrode 75, AD conversion circuit 53 and pixel array 30 in a plan view. Note that in Figure 8, metal joints 41 that do not appear in the cross-section (for example, metal joints 41 located on the near side of the cross-section) are shown with dashed lines. Furthermore, in Figure 11, the peripheral circuitry 51 is not shown, and the positions of the pixel array 30 and connecting electrodes 75 arranged on the first substrate 10 are indicated by dashed lines.

[0137] As shown in Figures 8 to 11, the imaging device 100B according to this modified example differs from the imaging device 100 according to Embodiment 1 mainly in that the pad group 91 is included in the second substrate 20 instead of the first substrate 10, and the first substrate 10 further includes a group of through holes 93.

[0138] As shown in Figures 8 and 9, in the imaging device 100B, the first substrate 10 includes through holes 94 and a group of through holes 93 consisting of multiple through holes penetrating the first substrate 10. Also, as shown in Figures 8 and 10, in the imaging device 100B, the second substrate 20 includes a group of pads 91 consisting of multiple pads, including a pad 92. In a plan view, the group of pads 91 is located on the outer periphery of the second substrate 20, relative to the pixel array 30 and peripheral circuits 51.

[0139] The multiple through-holes constituting the through-hole group 93 are provided in correspondence with the multiple pads constituting the pad group 91, exposing the multiple pads. In a plan view, the arrangement of the through-hole group 93 is the same as, for example, the arrangement of the pad group 91 in the imaging device 100. As shown in Figure 8, the through-hole 94 penetrates the first substrate 10 and exposes the pad 92. Although not shown in Figure 8, an insulating film may be formed on the surface of the semiconductor substrate 11 in the portion of the through-hole 94 that penetrates the semiconductor substrate 11. Although not shown in Figure 8, the through-holes in the through-hole group 93 other than the through-hole 94 have a similar structure to the through-hole 94 and expose the pads other than the pad 92 in the pad group 91. As shown in Figure 10, in the imaging device 100B, the multiple pads constituting the pad group 91 are arranged along the outer circumference at the edge of the second substrate 20 in a plan view. As shown in Figure 8, in the imaging device 100B, the pad 92 is located at the top of the wiring layer 22. The pad 92 may be located below the top of the wiring layer 22, and the through hole 94 may extend into a portion of the wiring layer 22.

[0140] As shown in Figure 11, the pad 92 is located at the corner 8 of the second substrate 20 in a plan view. The corner 8 is an area outside the extended lines of each side of the pixel array 30 on the first substrate 10 (the dashed lines shown in Figure 11) in a plan view. Therefore, the pad 92 does not overlap with the pixel array 30 and the metal junction group 40 in a plan view, and is not located in an area where the pixel array 30 is extended in the direction of the arrangement of the multiple pixels 31. By positioning the pad 92 at the corner 8 of the second substrate 20 in a plan view, the pad 92 to which the control voltage Vp is applied from the outside can be separated from the pixel array 30, thereby reducing noise in the signals transmitted and received by the pixel array 30. Furthermore, the pad 92 can also be separated from the multiple metal junctions 41 arranged along the outer circumference of the pixel array 30, thereby reducing noise in the signals flowing through the multiple metal junctions 41. The pad 92 is located at the corner 8 at each of the four corners of the second substrate 20, for example.

[0141] As shown in Figure 8, in the imaging device 100B, a control voltage Vp is supplied to the counter electrode 72 by an electrical path 90B. The electrical path 90B connects the pad 92 and the counter electrode 72. The electrical path 90B includes a first portion 15B, which is the part of the electrical path 90B located within the first substrate 10, and a second portion 23B, which is the part of the electrical path 90B located within the second substrate 20.

[0142] The electrical path 90B includes a portion of the light-shielding layer 82, a connecting electrode 75, and a control voltage supply line 5B connecting the connecting electrode 75 and the pad 92. In the example shown in Figure 8, the control voltage supply line 5B includes a through electrode 17, a metal joint 45, and wiring 24. The through electrode 17, a portion of the metal joint 45, the connecting electrode 75, and a portion of the light-shielding layer 82 are included in the first portion 15B. The remaining portion of the metal joint 45 and the wiring 24 are included in the second portion 23B. The control voltage Vp applied to the pad 92 is supplied to the counter electrode 72 by passing through the wiring 24, the metal joint 45, the through electrode 17, the connecting electrode 75, and a portion of the light-shielding layer 82 in that order. Note that the configuration of the electrical path 90B shown in Figure 8 is just one example and is not limited to the example shown in Figure 8.

[0143] The second portion 23B of the electrical path 90B for supplying the control voltage Vp to the counter electrode 72 does not overlap with the analog circuits of peripheral circuits 51 such as the AD conversion circuit 53 in a plan view, similar to the second portion 23 of the electrical path 90 described above. Therefore, noise in the analog circuits of peripheral circuits 51 can be suppressed, and the image quality of the imaging device 100B can be improved.

[0144] Furthermore, in the imaging device 100B, since the pad 92 is formed on the second substrate 20, the pad 92 is not placed within the insulating layer 14 as in the imaging device 100. Therefore, the thickness of the insulating layer 14, which had to be the same thickness as the pad 92 in the imaging device 100, can be reduced. As a result, the contact plug 76 that penetrates the insulating layer 14 and connects the pixel electrode 71 and the detection circuit 32 can be shortened. Since the contact plug 76 is part of the charge storage region that stores the signal charge generated by the photoelectric conversion unit 70, shortening the contact plug 76 reduces the capacitance of the charge storage region and increases the signal charge conversion gain. Therefore, the signal-to-noise ratio can be improved, and the image quality of the imaging device 100B can be improved. Note that in the imaging device 100B, the first substrate 10 does not need to include the insulating layer 14.

[0145] [Difference 3] Next, we will describe a modified example of Embodiment 1, Part 3. In the following, we will focus on the differences between Embodiment 1 and Modified Examples 1 and 2 of Embodiment 1, and will omit or simplify the explanation of the common points.

[0146] Figure 12 is a schematic cross-sectional view showing an example of the device structure of the imaging device 100C according to this modified example. Figure 12 shows a cross-section of the imaging device 100C at the position corresponding to Figure 8. In Figure 12, through electrodes 43 that do not appear in the cross-section (for example, through electrodes 43 located in front of the cross-section) and wiring connected to the through electrodes 43 are shown by dashed lines.

[0147] As shown in Figure 12, the imaging device 100C according to this modified example differs from the imaging device 100B according to Modification 2 of Embodiment 1 mainly in that it includes a first substrate 10A instead of the first substrate 10, and includes a through-electrode group 42 composed of multiple through electrodes 43 instead of a group of metal joints 40 composed of multiple metal joints 41. Furthermore, the imaging device 100C according to this modified example differs from the imaging device 100A according to Modification 1 of Embodiment 1 mainly in that the pad group 91 is included in the second substrate 20 instead of the first substrate 10A, and the first substrate 10A further includes a group of through holes 93. In other words, the imaging device 100C has a structure that combines the imaging device 100A and the imaging device 100B.

[0148] In the imaging device 100C, the planar layout of the first substrate 10A is, for example, the same as the planar layout of the first substrate 10 of the imaging device 100B shown in Figure 9, but with the metal joint group 40 replaced by the through electrode group 42. Also, in the imaging device 100C, the planar layout of the second substrate 20 is, for example, the same as the planar layout of the second substrate 20 of the imaging device 100B shown in Figure 10, but with the metal joint group 40 replaced by the through electrode group 42.

[0149] As shown in Figure 12, in the imaging device 100C, a control voltage Vp is supplied to the counter electrode 72 by an electrical path 90C. The electrical path 90C connects the pad 92 and the counter electrode 72. The electrical path 90C includes a first portion 15C, which is located within the first substrate 10A, and a second portion 23C, which is located within the second substrate 20.

[0150] The electrical path 90C includes a portion of the light-shielding layer 82, a connecting electrode 75, and a control voltage supply line 5C connecting the connecting electrode 75 and the pad 92. In the example shown in Figure 12, the control voltage supply line 5C includes a through electrode 17 and wirings 24 and 18. The through electrode 17 and the connecting electrode 75 are connected via wiring 18 in the wiring layer 12. A portion of the through electrode 17, the connecting electrode 75, a portion of the light-shielding layer 82, and wiring 18 are included in the first portion 15C. The remaining portion of the through electrode 17 and wiring 24 are included in the second portion 23C. The control voltage Vp applied to the pad 92 is supplied to the counter electrode 72 by passing through wiring 24, the through electrode 17, wiring 18, the connecting electrode 75, and a portion of the light-shielding layer 82 in that order. Note that the configuration of the electrical path 90C shown in Figure 12 is an example and is not limited to the example shown in Figure 12.

[0151] The second portion 23C of the electrical path 90C for supplying the control voltage Vp to the counter electrode 72 does not overlap with the analog circuits of peripheral circuits 51 such as the AD conversion circuit 53 in a plan view, similar to the second portion 23 of the electrical path 90 described above. Therefore, noise in the analog circuits of peripheral circuits 51 can be suppressed, and the image quality of the imaging device 100C can be improved.

[0152] Furthermore, the fact that the second portion 23C does not overlap with the multiple through electrodes 43 constituting the through electrode group 42 in a plan view is the same as the second portion 23A of the electrical path 90A described above. Therefore, noise in the signal passing through the through electrodes 43 can be reduced. Note that the second portion 23C may overlap with one or more of the multiple through electrodes 43 in a plan view.

[0153] Furthermore, in the imaging device 100C, similar to the imaging device 100A, the semiconductor substrate 11 and the wiring layer 22 are located between the wiring layer 12 and the semiconductor substrate 21. Therefore, the semiconductor substrate 11 can suppress noise transmitted from the first portion 15C of the electrical path 90C passing through the wiring layer 12 to the analog circuits of peripheral circuits 51 such as the AD conversion circuit 53.

[0154] In the imaging device 100C, similar to the imaging device 100B, the pad 92 is formed on the second substrate 20. This shortens the contact plug 76, reducing the capacitance of the charge storage region and increasing the signal charge conversion gain. As a result, the signal-to-noise ratio can be improved, and the image quality of the imaging device 100C can be enhanced.

[0155] [Differentiation Example 4] Next, we will describe Modification 4 of Embodiment 1. In the following, we will focus on the differences between Embodiment 1 and Modifications 1 to 3 of Embodiment 1, and will omit or simplify the explanation of the common points.

[0156] Figure 13 is a schematic cross-sectional view showing an example of the device structure of the imaging device 100D according to this modified example. Figure 14 is a schematic plan view showing an example of the planar layout of the first substrate 10 of the imaging device 100D according to this modified example. Figure 15 is a schematic plan view showing an example of the planar layout of the second substrate 20 of the imaging device 100D according to this modified example. Figure 16 is an enlarged plan view of the vicinity of the corner 8 of the second substrate 20 of the imaging device 100D according to this modified example. Figure 13 is a cross-sectional view when the imaging device 100D is cut in a crank shape and unfolded in region XIII in Figures 14 and 15, passing through the pad 92, control voltage supply line 5D, switch circuit 65, connecting electrode 75, AD conversion circuit 53, and pixel array 30 in a plan view. Note that in Figure 13, metal joints 41 that do not appear in the cross-section (for example, metal joints 41 located on the near side of the cross-section) are shown with dashed lines. Furthermore, in Figure 15, the positions of pads 92 and 95 located on the first substrate 10 are indicated by dashed lines. Also, in Figure 16, the peripheral circuit 51 is omitted from the illustration, and the positions of pads 92 and 95, the pixel array 30, and the connecting electrodes 75 located on the first substrate 10 are indicated by dashed lines.

[0157] As shown in Figures 13 to 16, the imaging device 100D according to this modified example differs from the imaging device 100 according to Embodiment 1 mainly in that the second substrate 20 further includes a switch circuit 65.

[0158] As shown in Figure 13, the switch circuit 65 is formed on the upper surface of the semiconductor substrate 21. The switch circuit 65 is also positioned in the middle of the electrical path 90D for supplying a control voltage Vp to the counter electrode 72. The switch circuit 65 is supplied with a first voltage V1 and a second voltage V2, and the switch circuit 65 switches the control voltage Vp supplied to the counter electrode 72 between the first voltage V1 and the second voltage V2. Alternatively, the switch circuit 65 may be supplied with three or more different voltages, and the switch circuit 65 may switch the control voltage Vp with three or more different voltages.

[0159] As shown in Figure 16, the switch circuit 65 is located at the corner 8 of the second substrate 20 in a plan view. Therefore, in a plan view, the switch circuit 65 does not overlap with the pixel array 30 and the metal junction group 40, and is not located in the region where the pixel array 30 is extended in the direction of the arrangement of the multiple pixels 31. By positioning the switch circuit 65 at the corner 8 of the second substrate 20 in a plan view, the switch circuit 65 that switches the control voltage Vp can be separated from the pixel array 30, thereby reducing noise in the signals transmitted and received by the pixel array 30. Furthermore, the switch circuit 65 can also be separated from the multiple metal junctions 41 arranged along the outer circumference of the pixel array 30, thereby reducing noise in the signals flowing through the multiple metal junctions 41. The switch circuit 65 is located at the corner 8 at each of the four corners of the second substrate 20, for example.

[0160] In the imaging device 100D, the pads constituting the pad group 91 include a pad 92 to which a first voltage V1 is applied externally, and a pad 95 to which a second voltage V2 is applied externally. The switch circuit 65 is supplied with the first voltage V1 via pad 92 and the second voltage V2 via pad 95, for example. Although not shown in Figure 13, pad 95 is also located within the insulating layer 14, similar to pad 92. In the example shown in Figure 14, pads 92 and 95 are adjacent to each other in the pad group 91. Also, pad 95 is located at a corner 7 of the first substrate 10 in a plan view, for example, but may be located in a region other than the corner 7 of the first substrate 10.

[0161] As shown in Figure 13, in the imaging device 100D, a control voltage Vp is supplied to the counter electrode 72 by an electrical path 90D. The electrical path 90D connects the pad 92 and the counter electrode 72. Although not shown in Figure 13, the electrical path 90D further connects the pad 95 and the counter electrode 72. The electrical path 90D includes a first portion 15, which is located within the first substrate 10, and a second portion 23D, which is located within the second substrate 20.

[0162] The electrical path 90D includes a portion of the light-shielding layer 82, a connecting electrode 75, a control voltage supply line 5D connecting the connecting electrode 75 to the pads 92 and 95, and a conductive path in the switch circuit 65 located in the middle of the control voltage supply line 5D. In the example shown in Figure 13, the control voltage supply line 5D includes through electrodes 16 and 17, two metal joints 45, wiring 25a and 25b, and a conductive structure (not shown in Figure 13) connecting the pads 95 to the switch circuit 65. The through electrodes 16 and 17, portions of each of the two metal joints 45, the connecting electrode 75, and a portion of the light-shielding layer 82 are included in the first portion 15. The remaining portions of each of the two metal joints 45, wiring 25a and 25b, and the conductive path in the switch circuit 65 are included in the second portion 23D. The first voltage V1 applied to the pad 92 is supplied to the switch circuit 65 by passing through the through electrode 16, one metal junction 45, and the wiring 25a in that order. The second voltage V2 applied to the pad 95 is supplied to the switch circuit 65 by passing through a conductive structure not shown in Figure 13. The switch circuit 65 supplies a control voltage Vp, which is switched between the first voltage V1 and the second voltage V2, to the counter electrode 72 by passing through the wiring 25b, the other metal junction 45, the through electrode 17, the connecting electrode 75, and a portion of the light-shielding layer 82 in that order. Note that the configuration of the electrical path 90D shown in Figure 13 is an example and is not limited to the example shown in Figure 13.

[0163] The second portion 23D of the electrical path 90D for supplying the control voltage Vp to the counter electrode 72 does not overlap with the analog circuits of peripheral circuits 51 such as the AD conversion circuit 53 in a plan view, similar to the second portion 23 of the electrical path 90 described above. Therefore, noise in the analog circuits of peripheral circuits 51 can be suppressed, and the image quality of the imaging device 100D can be improved.

[0164] Furthermore, in the imaging device 100D, since the second substrate 20 includes a switch circuit 65, it becomes possible to switch the control voltage Vp within the imaging device 100D. Therefore, for example, the pulse driving of the control voltage Vp applied to the counter electrode 72 can be flexibly performed. Also, since the switch circuit 65 is formed on the semiconductor substrate 21 of the second substrate 20, it becomes possible to reduce the number of transistors other than the pixel 31 transistors formed on the semiconductor substrate 11 of the first substrate 10, such as limiting the transistors formed on the semiconductor substrate 11 of the first substrate 10 to only the transistors for the pixels 31. Therefore, it becomes possible to form transistors on the semiconductor substrate 11 with process parameters specialized for the transistors of the pixels 31, and it becomes possible to improve the characteristics of the transistors in the pixels 31. In addition, it becomes possible to reduce the number of masks when manufacturing the first substrate 10, thereby reducing costs.

[0165] Furthermore, the imaging device 100D may include a first substrate 10A instead of the first substrate 10, and a through-electrode group 42 composed of multiple through-electrodes 43 instead of a group of metal joints 40 composed of multiple metal joints 41. In other words, in the imaging device 100A described above, the second substrate 20 may further include a switch circuit 65 positioned in the middle of the electrical path 90A.

[0166] [Difference 5] Next, we will describe Modification 5 of Embodiment 1. In the following, we will focus on the differences between Embodiment 1 and Modifications 1 to 4 of Embodiment 1, and will omit or simplify the explanation of the common points.

[0167] Figure 17 is a schematic cross-sectional view showing an example of the device structure of the imaging device 100E according to this modified example. Figure 18 is a schematic plan view showing an example of the planar layout of the first substrate 10 of the imaging device 100E according to this modified example. Figure 19 is a schematic plan view showing an example of the planar layout of the second substrate 20 of the imaging device 100E according to this modified example. Figure 20 is an enlarged plan view of the vicinity of the corner 8 of the second substrate 20 of the imaging device 100E according to this modified example. Figure 17 is a cross-sectional view when the imaging device 100E is cut in a crank shape and unfolded in region XVII in Figures 18 and 19 so as to pass through the pad 92, through hole 94, control voltage supply line 5E, switch circuit 65, connecting electrode 75, AD conversion circuit 53 and pixel array 30 in a plan view. Note that in Figure 17, metal joints 41 that do not appear in the cross-section (for example, metal joints 41 located on the near side of the cross-section) are shown with dashed lines. Furthermore, in Figure 20, the peripheral circuitry 51 is omitted from the illustration, and the positions of the pixel array 30 and connecting electrodes 75 are indicated by dashed lines.

[0168] As shown in Figures 17 to 20, the imaging device 100E according to this modified example differs from the imaging device 100B according to Modification 2 of Embodiment 1 mainly in that the second substrate 20 further includes a switch circuit 65. Furthermore, the imaging device 100E according to this modified example differs from the imaging device 100D according to Modification 4 of Embodiment 1 mainly in that the pad group 91 is included in the second substrate 20 instead of the first substrate 10, and the first substrate 10 further includes a through-hole group 93. In other words, the imaging device 100E has a structure that combines the features of the imaging device 100B and the imaging device 100D.

[0169] As shown in Figure 17, the switch circuit 65 is formed on the upper surface of the semiconductor substrate 21. The switch circuit 65 is also positioned in the middle of the electrical path 90E for supplying a control voltage Vp to the counter electrode 72. Furthermore, as shown in Figure 20, the switch circuit 65 is located at the corner 8 of the second substrate 20 in a plan view.

[0170] In the imaging device 100E, the pads constituting the pad group 91 include a pad 92 to which a first voltage V1 is applied externally, and a pad 95 to which a second voltage V2 is applied externally. The through-hole group 93 includes a through-hole 94 that exposes the pad 92 and a through-hole 96 that exposes the pad 95. Although not shown in Figure 17, the pad 95 is located at the top of the wiring layer 22, similar to the pad 92. The pad 95 may be located below the top of the wiring layer 22, with the through-hole 96 extending into a part of the wiring layer 22. Furthermore, the pad 95 is located, for example, at a corner 8 of the second substrate 20 in a plan view, but may be located in a region other than the corner 8 of the second substrate 20.

[0171] As shown in Figure 17, in the imaging device 100E, a control voltage Vp is supplied to the counter electrode 72 by an electrical path 90E. The electrical path 90E connects the pad 92 and the counter electrode 72. Although not shown in Figure 17, the electrical path 90E further connects the pad 95 and the counter electrode 72. The electrical path 90E includes a first portion 15B, which is located within the first substrate 10, and a second portion 23E, which is located within the second substrate 20.

[0172] The electrical path 90E includes a portion of the light-shielding layer 82, a connecting electrode 75, a control voltage supply line 5E connecting the connecting electrode 75 to the pads 92 and 95, and a conductive path in the switch circuit 65 located in the middle of the control voltage supply line 5E. In the example shown in Figure 17, the control voltage supply line 5E includes a through electrode 17, a metal joint 45, wiring 25a and 25b, and a conductive structure (not shown in Figure 17) connecting the pads 95 to the switch circuit 65. Wiring 25a and 25b are wiring included in the wiring layer 22. The through electrode 17, a portion of the metal joint 45, the connecting electrode 75, and a portion of the light-shielding layer 82 are included in the first portion 15B. The remaining portion of the metal joint 45, wiring 25a and 25b, the conductive path in the switch circuit 65, and the conductive structure (not shown in Figure 17) connecting the pads 95 to the switch circuit 65 are included in the second portion 23E. The first voltage V1 applied to pad 92 is supplied to the switch circuit 65 through wiring 25a. The second voltage V2 applied to pad 95 is supplied to the switch circuit 65 through a conductive structure not shown in Figure 17. The switch circuit 65 supplies a control voltage Vp, which is switched between the first voltage V1 and the second voltage V2, to the counter electrode 72 via wiring 25b, the other metal junction 45, the through electrode 17, the connecting electrode 75, and a portion of the light-shielding layer 82 in that order. Note that the configuration of the electrical path 90E shown in Figure 17 is an example and is not limited to the example shown in Figure 17.

[0173] The second portion 23E of the electrical path 90E for supplying the control voltage Vp to the counter electrode 72 does not overlap with the analog circuits of peripheral circuits 51 such as the AD conversion circuit 53 in a plan view, similar to the second portion 23 of the electrical path 90 described above. Therefore, noise in the analog circuits of peripheral circuits 51 can be suppressed, and the image quality of the imaging device 100E can be improved.

[0174] In the imaging device 100E, similar to the imaging device 100B, the pad 92 is formed on the second substrate 20. This shortens the contact plug 76, reducing the capacitance of the charge storage region and increasing the signal charge conversion gain. As a result, the signal-to-noise ratio can be improved, and the image quality of the imaging device 100E can be enhanced.

[0175] Furthermore, in the imaging device 100E, since the second substrate 20 includes a switch circuit 65, it becomes possible to switch the control voltage Vp within the imaging device 100E. Also, similar to the imaging device 100D, since the switch circuit 65 is formed on the semiconductor substrate 21 of the second substrate 20, it becomes possible to reduce the number of transistors other than those for the pixels 31 formed on the semiconductor substrate 11 of the first substrate 10, such as limiting the transistors formed on the semiconductor substrate 11 to only those for the pixels 31. As a result, it becomes possible to form transistors on the semiconductor substrate 11 with process parameters specialized for the transistors of the pixels 31, thereby improving the characteristics of the transistors in the pixels 31. In addition, it becomes possible to reduce the number of masks used when manufacturing the first substrate 10, thereby reducing costs.

[0176] Furthermore, the imaging device 100E may include a first substrate 10A instead of the first substrate 10, and a through-electrode group 42 composed of multiple through-electrodes 43 instead of a group of metal joints 40 composed of multiple metal joints 41. In other words, in the imaging device 100C described above, the second substrate 20 may further include a switch circuit 65 located in the middle of the electrical path 90C.

[0177] (Embodiment 2) Next, Embodiment 2 will be described. Embodiment 2 describes a camera system equipped with an imaging device according to the present disclosure.

[0178] Figure 21 is a block diagram showing an example of the configuration of the camera system 400 according to this embodiment.

[0179] As shown in Figure 21, the camera system 400 according to this embodiment comprises a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing circuit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0180] The lens optical system 601 focuses light onto the imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. As the imaging device 602, for example, an imaging device according to any of the above-described embodiments 1 and 1 to 5 of embodiment 1 may be used.

[0181] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0182] The camera signal processing circuit 604 has the function of processing the output signal from the imaging device 602. The camera signal processing circuit 604 receives output data from the imaging device 602 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The imaging device 602 and the camera signal processing circuit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device that includes the imaging device 602 as part can be made smaller.

[0183] (Other embodiments) The imaging apparatus and camera system relating to this disclosure have been described above based on embodiments, but this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to the embodiments that a person skilled in the art could conceive, as well as other forms constructed by combining some of the components of the embodiments, are also included in the scope of this disclosure.

[0184] For example, in modifications 4 and 5 of Embodiment 1 described above, the second substrate 20 was equipped with a switch circuit 65, but this is not limited to this. For example, in Embodiment 1 and any of modifications 1 to 3 of Embodiment 1, the first substrate 10 or 10A may be equipped with a switch circuit 65 located in the middle of an electrical path for supplying a control voltage Vp to the counter electrode 72.

[0185] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents. [Industrial applicability]

[0186] The imaging device and camera system described herein are useful for, for example, image sensors, digital cameras, etc. The imaging device and camera system described herein can be used for medical cameras, robot cameras, security cameras, cameras mounted on vehicles, etc. [Explanation of Symbols]

[0187] 5, 5A, 5B, 5C, 5D, 5E Control voltage supply lines 7, 8 corners 10, 10A First board 11, 21 Semiconductor substrates 12, 22 wiring layer 13, 14, 80, 81 Insulating layer 15, 15A, 15B, 15C Part 1 16, 17, 43 Through electrode Wiring 18, 24, 25a, 25b 20 Second board 23, 23A, 23B, 23C, 23D, 23E 2nd part 30-pixel array 31 pixels 32 Detection Circuit 33 Amplifying Transistors 34 Selective Transistors 35 Reset transistor 40 Metal joint group 41, 45 Metal joints 42 Through electrode group 51 Peripheral Circuits 52 Vertical scanning circuit 53 AD conversion circuit 54 DAC 55 memory 56 Logic Circuits 57 Control circuits 58 Signal Processing Circuits 59 Output Circuit 60 PLL 61 Ring Oscillator 62 Reference Circuit 63 Bias Circuit 65 Switch Circuits 70 Photoelectric conversion unit 71 Pixel electrodes 72 Counter electrode 73 Photoelectric conversion layer 75 Connecting electrodes 76 Contact plug 77 Vertical signal line 82 Light blocking layer 83 Protective layer 84 Color Filters 86 Microlenses 90, 90A, 90B, 90C, 90D, 90E Electrical Paths 91 pads 92, 95 pads 93 Through hole group 94, 96 Through holes 100, 100A, 100B, 100C, 100D, 100E, 602 Imaging device 400 Camera System 601 Lens Optics 603 System Controller 604 Camera signal processing circuit FD charge storage node Lcon control signal line Lv voltage line s1 interface

Claims

1. A first substrate including a pixel array in which multiple pixels are arranged, A second substrate is laminated on the first substrate and includes peripheral circuits connected to the pixel array, Equipped with, Each of the plurality of pixels includes a photoelectric conversion layer that converts light into signal charges, a first electrode that collects the signal charges, and a second electrode that faces the first electrode via the photoelectric conversion layer. The first substrate includes a first portion of an electrical path for supplying voltage to the second electrode, The second substrate includes the second portion of the electrical path, The peripheral circuit includes an AD conversion circuit that converts signals from the plurality of pixels into digital signals. The second part described above does not overlap with the AD conversion circuit in a plan view. Imaging device.

2. The aforementioned peripheral circuit includes a DAC (Digital to Analog Converter) that supplies a reference signal to the AD conversion circuit. The second portion does not overlap the DAC in plan view. The imaging apparatus according to claim 1.

3. The peripheral circuit includes a vertical scanning circuit that supplies control signals to the plurality of pixels. The second portion does not overlap the vertical scanning circuit in a plan view. The imaging apparatus according to claim 1.

4. The second part, in a plan view, does not overlap with the analog circuits included in the peripheral circuits. The imaging apparatus according to claim 1.

5. The first substrate includes a first semiconductor substrate and a first wiring layer laminated on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer laminated on the second semiconductor substrate. The first substrate and the second substrate are stacked such that the first wiring layer and the second wiring layer are located between the first semiconductor substrate and the second semiconductor substrate. The imaging apparatus according to claim 1.

6. The first wiring layer and the second wiring layer are joined together, and the pixel array and the peripheral circuit are electrically connected, and the metal joint is electrically insulated from the electrical path. The second portion of the electrical path does not overlap the metal joint in a plan view. The imaging apparatus according to claim 5.

7. The first substrate includes a first semiconductor substrate and a first wiring layer laminated on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer laminated on the second semiconductor substrate. The first substrate and the second substrate are stacked such that the first semiconductor substrate and the second semiconductor substrate are positioned between the first wiring layer and the second semiconductor substrate. The imaging apparatus according to claim 1.

8. The invention further comprises a through electrode that penetrates the first semiconductor substrate, is electrically connected to the pixel array and the peripheral circuit, and is electrically insulated from the electrical path, The second portion of the electrical path does not overlap with the through electrode in a plan view. The imaging apparatus according to claim 7.

9. The second substrate is positioned in the middle of the electrical path and further includes a switch circuit that switches the voltage supplied to the second electrode. The imaging apparatus according to claim 1.

10. The switch circuit is located at the corner of the second substrate in a plan view. The imaging device according to claim 9.

11. The second substrate includes a pad to which an external voltage is applied, The aforementioned electrical path connects the pad and the second electrode. The imaging apparatus according to claim 1.

12. The aforementioned pad is located at the corner of the second substrate in a plan view. The imaging apparatus according to claim 11.

13. The imaging device comprises the imaging device described in any one of claims 1 to 12. Camera system.

Images