Semiconductor equipment

Abstract

To improve the characteristics of semiconductor devices. [Solution] The semiconductor device of the embodiment includes a substrate 40 including lead terminals 401 and 402, a semiconductor chip 10 provided on the lead terminal 401 and including a switching element TR, a connector 60 extending from the surface of the semiconductor chip 10 to the lead terminal 402, and a semiconductor chip 20 provided on the connector 60 above the semiconductor chip 10, including a resistor 202 and a capacitance 201A. The semiconductor chip 10 includes a first electrode 102 on the surface of the semiconductor chip 10 and a second electrode 103 on the back surface of the semiconductor chip 10. The semiconductor chip 20 includes third and fourth electrodes 204 and 205. The first electrode 102 is connected to the lead terminal 402, the second electrode 103 is connected to the lead terminal 401, the third electrode 204 is connected to the lead terminal 401, and the fourth electrode 205 is connected to the lead terminal 402.

Description

Technical Field

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[0003] ,

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[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] A snubber circuit is used in a power module to stabilize the operation of a switching element.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the characteristics of semiconductor devices.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment comprises a package substrate including a first lead terminal and a second lead terminal; a first semiconductor chip provided on the first lead terminal and including a switching element; a connector extending from the surface of the first semiconductor chip to the second lead terminal; a resistor; and a second semiconductor chip provided on the connector above the first semiconductor chip, including a resistor and a first capacitance provided in the semiconductor substrate; the first semiconductor chip includes a first electrode provided on the surface of the first semiconductor chip and a second electrode provided on the back surface of the first semiconductor chip; the second semiconductor chip includes a third electrode and a fourth electrode, the first electrode being electrically connected to the second lead terminal, the second electrode being electrically connected to the first lead terminal, the third electrode being electrically connected to the first lead terminal, and the fourth electrode being electrically connected to the second lead terminal. [Brief explanation of the drawing]

[0006] [Figure 1] A circuit diagram showing an example configuration of a semiconductor device according to the first embodiment. [Figure 2] A bird's-eye view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 3] A plan view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 4] A cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 5] A cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 6] A flowchart illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 7] A graph showing the characteristics of the mechanism of the first embodiment. [Figure 8] A graph showing the characteristics of the mechanism of the first embodiment. [Figure 9] A plan view showing an example of the structure of a semiconductor device according to the second embodiment. [Figure 10] A cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. [Figure 11] Cross-sectional view showing a structural example of a semiconductor device according to the second embodiment. [Figure 12] Planar view showing a structural example of a semiconductor device according to the third embodiment. [Figure 13] Cross-sectional view showing a structural example of a semiconductor device according to the third embodiment. [Figure 14] Cross-sectional view showing a structural example of a semiconductor device according to the third embodiment. [Figure 15] Planar view showing a structural example of a semiconductor device according to the fourth embodiment. [Figure 16] Cross-sectional view showing a structural example of a semiconductor device according to the fourth embodiment. [Figure 17] Cross-sectional view showing a structural example of a semiconductor device according to the fourth embodiment. [Figure 18] Circuit diagram showing a configuration example of a semiconductor device according to the fifth embodiment. [Figure 19] Cross-sectional view showing a structural example of a semiconductor device according to the fifth embodiment.

Embodiments for Carrying Out the Invention

[0007] Referring to FIGS. 1 to 19, a semiconductor device and a method of manufacturing the semiconductor device according to the embodiments will be described. In the following description, elements having the same function and configuration are denoted by the same reference numerals. Further, in each of the following embodiments, when components (for example, circuits, wirings, various voltages and signals, etc.) denoted by reference numerals with numbers / letters at the end for differentiation do not need to be distinguished from each other, descriptions (reference numerals) in which the numbers / letters at the end are omitted are used.

[0008] (Embodiment) (1) First Embodiment Referring to FIGS. 1 to 8, a semiconductor device and a method of manufacturing the semiconductor device according to the first embodiment will be described.

[0009] (a) Configuration Example Referring to FIGS. 1 to 5, a configuration example of the semiconductor device according to the present embodiment will be described.

[0010] Figure 1 is a circuit diagram showing the circuit configuration of the semiconductor device 1 of this embodiment.

[0011] As shown in Figure 1, the semiconductor device 1 of this embodiment is a power device (power module) including a transistor TR and a snubber circuit SNB.

[0012] A transistor (TR) is a switching element. A transistor (TR) is a field-effect transistor (MOS) with a Metal-Oxide-Semiconductor (MOS) structure. For example, a transistor (TR) is an N-channel MOSFET. A transistor (TR) includes semiconductors such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). A transistor (TR) is a low-voltage MOSFET (with a voltage rating of approximately 12V to 300V), and is driven by an operating voltage of, for example, 6V to 300V. Hereafter, a transistor (TR) will also be referred to as an LVMOS.

[0013] The transistor TR may be a P-channel field-effect transistor or an IGBT (Insulated Gate Bipolar Transistor).

[0014] Transistor TR is connected to a DC power supply 900. One end of the current path of transistor TR (e.g., drain) is connected to the high-potential terminal of the DC power supply 900 via inductor 909. The other end of the current path of transistor TR (e.g., source) is connected to the low-potential terminal of the DC power supply 900. The control terminal (gate) of transistor TR is connected to a signal source (e.g., driver circuit) 901. Transistor TR is turned on or off in response to a pulse signal (control signal, gate voltage) from the signal source 901. Note that inductor 909 may be a device for adjusting the operating characteristics of transistor TR, or it may be a parasitic component included in the wiring between transistor TR and the DC power supply 900.

[0015] The snubber circuit (SNB) suppresses surge voltages generated during the switching operation of the transistor (TR). The snubber circuit (SNB) includes a capacitor (capacitive element, capacitor) 201A and a resistor (resistive element) 202.

[0016] The snubber circuit SNB is connected in parallel to the current path of the transistor TR. One end of capacitor 201A is connected to one end of the current path of transistor TR. The other end of capacitor 201A is connected to one end of resistor 202. The other end of resistor 202 is connected to the other end of the current path of transistor TR. Depending on the circuit configuration of the snubber circuit SNB, one end of resistor 202 may be connected to one end of the current path of transistor TR, the other end of resistor 202 may be connected to one end of capacitor 201A, and the other end of capacitor 201A may be connected to the other end of the current path of transistor TR.

[0017] For example, the semiconductor device 1 of this embodiment, with the configuration shown in Figure 1, functions as a switching device for power conversion in an external device (e.g., an inverter or converter) of the semiconductor device 1.

[0018] Figures 2 to 5 show examples of the structure of the semiconductor device 1 according to this embodiment.

[0019] Figure 2 is a bird's-eye view showing an example of the structure of the semiconductor device 1 of this embodiment. Figure 3 is a top view showing an example of the planar structure of the semiconductor device 1 of this embodiment. Figure 4 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 1 of this embodiment along line AA in Figure 3. Figure 5 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 1 of this embodiment along line BB in Figure 4.

[0020] In the following, a direction parallel to a certain plane is called the X direction, and a direction parallel to a certain plane and intersecting the X direction is called the Y direction. A direction perpendicular to the plane formed by the X and Y directions is called the Z direction.

[0021] As shown in Figures 2 to 5, in the semiconductor device 1 of this embodiment, the semiconductor chip 20 of the snubber circuit SNB is stacked on the semiconductor chip 10 of the transistor TR. The two stacked semiconductor chips 10 and 20 are provided on a package substrate 40. The two semiconductor chips 10 and 20 are covered with a sealing member 90 on the package substrate 40. The semiconductor chips 10 and 20 are connected to terminals 401, 402, and 403 of the package substrate 40. In this way, the semiconductor chips 10 and 20 are electrically connected to an external device of the semiconductor device 1.

[0022] The package substrate 40 is a lead frame 40. The lead frame 40 includes lead terminals 401, 402, 403 and an insulator 409.

[0023] Each of the lead terminals 401, 402, and 403 is a metal plate containing copper (Cu). Each of the lead terminals 401, 402, and 403 is spaced apart from one another. The lead terminals 401, 402, and 403 are housed within an insulator 409. The lead terminals 401, 402, and 403 are electrically insulated from each other by the insulator 409.

[0024] For example, lead terminal 401 has a flat shape. For example, one end of each lead terminal 402, 403 is raised in the Z direction so that it is located above the surface of lead terminal 401. The position of one end of lead terminals 402, 403 in the Z direction is substantially aligned with the position of the surface of the semiconductor chip 10 in the Z direction. Lead terminal 402 has a portion that is inclined with respect to the XY plane between one end of lead terminal 402 in the X direction and the other end of lead terminal 402 in the X direction. One end of lead terminal 402 in the X direction is located above the other end of lead terminal 402 in the X direction in the Z direction. Lead terminal 403 has a portion that is inclined with respect to the XY plane between one end of lead terminal 403 in the X direction and the other end of lead terminal 403 in the X direction. One end of lead terminal 403 in the X direction is located above the other end of lead terminal 403 in the X direction in the Z direction.

[0025] Lead terminal 401 is connected to electrode 103 at one end of the current path of transistor TR via conductor 80. Lead terminal 402 is electrically connected to electrode 102 at the other end of the current path of transistor TR via connector 60 (described later). Lead terminal 403 is electrically connected to electrode 105 of the control terminal of transistor TR via connector 62 (described later).

[0026] The package substrate 40 may have various structures, such as an SOP (Small Outline Package) structure or a QFP (Quad Flat Package) structure.

[0027] The transistor TR is formed within the semiconductor chip 10. Hereinafter, the semiconductor chip 10 containing the transistor TR will be referred to as the transistor chip 10.

[0028] The transistor chip 10 is mounted on the lead frame 40. More specifically, for example, the transistor chip 10 is mounted on the lead terminals 401 of the lead frame 40.

[0029] The transistor chip 10 includes a substrate 100, an element portion 101, and electrodes 102, 103, and 105.

[0030] The substrate 100 is a silicon (Si) substrate, silicon carbide (SiC) substrate, gallium nitride (GaN) substrate, zinc oxide (ZnO) substrate, gallium oxide (Ga2O3) substrate, aluminum nitride (AlN) substrate, or diamond substrate (carbon (C) substrate).

[0031] The element unit 101 is provided within the substrate 100. The element unit 101 includes various semiconductor layers and conductive layers as components of a transistor TR. Each of the semiconductor layers and conductive layers of the element unit 101 is electrically connected to the corresponding electrodes 102, 103, and 105 via contact plugs (not shown) and wiring (not shown).

[0032] Electrode 102 is located on the surface of the substrate 100. Electrode 102 is, for example, the source electrode 102 of transistor TR. Electrode 103 is located on the back surface of the substrate 100. Electrode 103 faces electrode 102 in the direction perpendicular to the surface of the substrate 100 (Z direction). Electrode 103 is, for example, the drain electrode 103 of transistor TR. Electrode 105 is located on the surface of the substrate 100. Electrode 105 is adjacent to electrode 102 in the directions parallel to the surface of the substrate 100 (X and Y directions). Electrode 105 is, for example, the gate electrode 105 of transistor TR. Thus, when transistor TR is a vertical transistor, the source electrode 102 of transistor TR overlaps with the drain electrode 103 of transistor TR in the Z direction.

[0033] Electrode 102 is electrically connected to connector 60 via a conductor 81A such as solder or conductive paste. Electrode 103 is electrically connected to lead terminal 401 via a conductor 80 such as solder or conductive paste. Electrode 105 is electrically connected to connector 62 via a conductor (not shown) such as solder or conductive paste.

[0034] The connector 60 is a metal plate containing copper (Cu). The connector 60 is provided on the lead terminals 402 of the lead frame 40 and on the surface of the transistor chip 10. The connector 60 extends in the X direction, for example, spanning between the lead terminals 402 and the transistor chip 10. The connector 60 has, for example, a bridge shape. The central part of the connector 60 is located above in the Z direction from one end and the other end of the connector 60 in the X direction. One end of the connector 60 in the X direction is electrically connected to one end of the lead terminal 402 in the X direction via a conductor 81B, such as solder or conductive paste. The other end of the connector 60 in the X direction is electrically connected to the electrode 102 of the transistor chip 10 via a conductor 81A. The conductor 81A is provided between the connector 60 and the electrode 102. The conductor 81B is provided between the connector 60 and the lead terminal 402.

[0035] The connector 62 is a metal plate containing copper. The connector 62 is provided on the lead terminals 403 of the lead frame 40 and on the surface of the transistor chip 10. The connector 62 extends in the X direction so as to span between the lead terminals 403 and the transistor chip 10. The connector 62 has, for example, a bridge shape. The central part of the connector 62 is located above in the Z direction from one end and the other end of the connector 62 in the X direction. One end of the connector 62 in the X direction is electrically connected to one end of the lead terminal 403 in the X direction via a conductor (not shown). The other end of the connector 62 in the X direction is electrically connected to the electrode 105 of the transistor chip 10 via a conductor (not shown).

[0036] One end (electrode 102) of the current path of transistor TR is connected to lead terminal 402 via connector 60. The other end (electrode 103) of the current path of transistor TR is electrically connected to lead terminal 401. The control terminal of transistor TR is connected to lead terminal 403 via connector 62.

[0037] The package substrate 40 may have a clip structure that includes a component (hereinafter referred to as a clip) that integrates the connector 60 and the lead terminal 402, and a component (clip) that integrates the connector 62 and the lead terminal 403. When the transistor chip 10 is mounted on the package substrate 40 with the clip structure, the transistor chip 10 is sandwiched between two clips corresponding to the lead terminals 402, 402 and the lead terminal 401. In this case, the clip corresponding to the lead terminal 402 is electrically connected to the electrode 102 of the transistor chip 10 without the conductor 81B being provided on the electrode 102. Also, the clip corresponding to the lead terminal 403 is electrically connected to the electrode 105 of the transistor chip 10 without the use of a conductor.

[0038] A semiconductor chip 20 including a capacitor (capacitance portion) 201A is provided on a connector 60. This semiconductor chip 20 is provided above the transistor chip 10 in the Z direction. The semiconductor chip 20 includes a silicon substrate 200. The capacitor 201A is formed using the silicon substrate 200. For example, the silicon substrate 200 functions as one electrode of the capacitor 201A. The thickness of the semiconductor chip 20 in the Z direction is, for example, 10 μm or more and 250 μm or less. Hereinafter, the capacitor 201A formed from the silicon substrate 200 will be referred to as a Si capacitor (or Si capacitor) 201A.

[0039] The Si capacitor 201A has a structure in which a dielectric film is sandwiched between a silicon substrate, which serves as one electrode, and the other electrode. For example, in the Si capacitor 201A, the facing area between two opposing electrodes is increased by trenches formed in the silicon substrate 200. The trenches in the silicon substrate 200 in the Si capacitor 201A are formed by etching the silicon substrate 200 using techniques such as RIE (Reactive ion etching) or Mac (Metal assisted chemical) etching using a noble metal catalyst.

[0040] For example, a resistor (resistor) 202 is provided in (or on) a silicon substrate 200 together with a Si capacitor 201A. The resistor 202 is formed using a semiconductor such as polysilicon, and / or a metal (or conductive compound) containing copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), or tungsten (W). For example, the resistor 202 includes one or more of the following: a thin-film resistor, a wiring resistor, a silicon resistor, and a via resistor.

[0041] When the capacitor 201A and the resistor 202 are provided within a single semiconductor chip 20, the single semiconductor chip 20 functions as a snubber circuit (SNB).

[0042] In the following, the semiconductor chip 20, which includes electronic components (e.g., passive elements) such as the capacitor 201A and the resistor 202, will be referred to as the component chip 20 or snubber chip 20.

[0043] The component chip 20 includes two electrodes 204 and 205. Electrode 204 is one terminal of the current path of the snubber circuit SNB. Electrode 205 is the other terminal of the current path of the snubber circuit SNB. Electrode 204 is located on the surface of the silicon substrate 200. Electrode 204 is electrically connected to the lead terminal 401 via a bonding wire 65. The bonding wire 65 is, for example, a gold (Au) or copper wire. Electrode 205 is located on the back surface of the silicon substrate 200. Electrode 205 is electrically connected to the connector 60 via a conductor 85 such as solder or conductive paste. Electrode 205 is electrically connected to the electrode 102 and lead terminal 402 of the transistor chip 10 via the connector 60. Between the two electrodes 204 and 205, the Si capacitor 201A is connected in series with the resistor 202. For example, one end of the Si capacitor 201A is electrically connected to electrode 204. The other end of the Si capacitor 201A is electrically connected to one end of the resistor 202. The other end of the resistor 202 is connected to electrode 205. However, the connection relationships between the Si capacitor 201A and the resistor 202 and electrodes 204 and 205 may be changed depending on the circuit configuration of the snubber circuit (SNB).

[0044] For example, the capacitance (capacitance value) of Si capacitor 201A is between 1.0 nF and 10.0 nF. The resistance value of resistor 202 is between 1.0 Ω and 10.0 Ω. Note that the capacitance of Si capacitor 201A may also be between 0.1 nF and 20.0 nF. Also, the resistance value of resistor 202 may be between 0.1 Ω and 10.0 Ω.

[0045] The resistor 202 may be provided in a semiconductor chip separate from the component chip 20. In this case, two semiconductor chips for the snubber circuit (SNB) are provided above the transistor chip 10 via the connector 60.

[0046] A sealing member (package material) 90 is provided on the lead frame 40 so as to cover the two stacked chips 10, 20 and connectors 60, 62. The sealing member 90 is an insulator such as epoxy resin. In this way, the two chips 10, 20 sealed within one package (sealing member 90) are provided as one semiconductor device 1. The insulator 409 may be made of the same material as the sealing member 90. In this case, the insulator 409 is continuous with the sealing member 90.

[0047] As shown in Figures 2 to 5, the semiconductor chip 20, which includes a capacitor 201A and a resistor 202, is stacked on the semiconductor chip 10, which includes a transistor TR, within the encapsulating member 90. The capacitor 201A and resistor 202 of the semiconductor chip 20 are connected in parallel to the current path of the transistor chip 10. The semiconductor chip 20, which functions as a snubber circuit (SNB), suppresses the surge voltage generated when the transistor TR is operating.

[0048] (b) Manufacturing method The manufacturing method of the semiconductor device 1 of this embodiment will be described with reference to Figure 6. In addition to Figure 6, Figures 2 to 5 will also be referred to as appropriate in order to explain the manufacturing method of the semiconductor device 1 of this embodiment.

[0049] Figure 6 is a flowchart illustrating the manufacturing method of the semiconductor device 1 according to this embodiment.

[0050] As shown in Figure 6, in step S1, a conductive material 80, such as solder, is applied to each of the multiple lead frames 40 provided within the metal plate.

[0051] In step S2, the transistor chip 10 is mounted on the lead frame 40 with the coated conductive material 80 in between.

[0052] In step S3, conductive materials 81A and 81B, such as solder, are applied to the surface of the transistor chip 10 and to the lead frame 40.

[0053] In step S4, connectors 60 and 62 are mounted on the transistor chip 10 and lead frame 40.

[0054] In step S5, a reflow process is performed on the transistor chip 10 and the lead frame 40. As a result, the transistor chip 10, the lead frame 40, and the connectors 60, 62 are connected (joined) to each other via the molten conductors 80, 81A, 81B.

[0055] In step S6, a conductive material (conductive paste) 85, such as silver (Ag) paste, is applied to the connector 60. When a conductive paste is used as the conductive material 85, the conductive material 85 of the conductive paste dries (solidifies) at a lower temperature compared to reflow soldering.

[0056] In step S7, a component chip 20 including a Si capacitor 201A and a resistor 202 is mounted on a conductive material 85 applied to the connector 60. The component chip 20 is stacked on the transistor chip 10 via the connector 60 and the conductive material 85. In the manufacturing process of the component chip 20, trenches in the silicon substrate 200 of the Si capacitor 201A are formed by RIE or Mac etching using a precious metal.

[0057] Note that the conductor 85 may be a material (for example, solder) with a melting point below that of the conductor 80 applied on the lead frame 40 and the conductors 81A and 81B applied on the transistor chip 10. In this case, before the reflow process in step S5, the component chip 20 is placed on the conductor 85 applied to the connector 60. A single reflow process is performed on the conductor 85 and the conductors 80, 81A, and 81B. As a result, the transistor chip 10, the lead frame 40, and the connectors 60 and 62 are joined together, and the component chip 20 is joined to the connector 60 via the molten conductor 85 by the reflow process.

[0058] In step S8, the paste-like conductive material 85 is cured. This bonds the component chip 20 to the connector 60. The component chip 20 is electrically connected to the transistor chip 10 via the conductive paste 85 and the connector 60.

[0059] In step S9, a bonding process is performed on the component chip 20. The component chip 20 is connected to the lead terminals 401 of the lead frame 40 by bonding wires 65.

[0060] In step S10, after the cleaning process with nitrogen plasma, a sealing process is performed on the chips 10 and 20 and the lead frame 40. As a result, the two chips 10 and 20 on the lead frame 40 are sealed within the sealing member 90.

[0061] In step S11, surface treatments such as deburring, exterior plating, and marking are performed on the sealing member 90 and lead frame 40 that cover the chips 10 and 20.

[0062] In step S12, a lead cutting process is performed on the metal plate containing multiple lead frames 40. As a result, multiple semiconductor devices 1 are cut out from the metal plate.

[0063] In step S13, a test process is performed on each semiconductor device 1. The test process measures the electrical characteristics and cosmetic defects of the semiconductor device 1.

[0064] The semiconductor device 1 of this embodiment is completed through the manufacturing process described above.

[0065] (c) Characteristics The characteristics of the semiconductor device 1 of this embodiment will be described with reference to Figures 7 and 8.

[0066] Figure 7 is a graph showing the drain-source voltage characteristics of the semiconductor device 1 of this embodiment when the transistor TR is turned off. In Figure 7, the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to the drain-source voltage (Vds).

[0067] The capacitance (capacitance value) of Si capacitor 201A is set to 0.5nF, 1.0nF, 4.4nF, 8.7nF, and 17.4nF. Figure 7 also shows an example where Si capacitor 201A is not provided in the semiconductor device. The resistance value of resistor 202 is set to 1.0Ω.

[0068] Line L1 in Figure 7 shows the characteristics of a semiconductor device without a Si capacitor. Line L2 in Figure 7 shows the characteristics of semiconductor device 1 when the capacitance of Si capacitor 201A is 0.5 nF. Line L3 in Figure 7 shows the characteristics of semiconductor device 1 when the capacitance of Si capacitor 201A is 1.0 nF. Line L4 in Figure 7 shows the characteristics of semiconductor device 1 when the capacitance of Si capacitor 201A is 4.4 nF. Line L5 in Figure 7 shows the characteristics of semiconductor device 1 when the capacitance of Si capacitor 201A is 8.7 nF. Line L6 in Figure 7 shows the characteristics of semiconductor device 1 when the capacitance of Si capacitor 201A is 17.4 nF.

[0069] As shown in Figure 7, when transistor TR is turned off, the voltage Vds includes a peak due to the surge voltage.

[0070] When Si capacitor 201A has a capacitance of 4.4 nF or more, the peak voltage Vds is reduced compared to when the capacitance of Si capacitor 201A is less than 1.0 nF.

[0071] Furthermore, as the capacitance of the Si capacitor 201A increases, the ringing phenomenon of the voltage Vds in the transistor TR is suppressed.

[0072] Thus, the semiconductor device 1 of this embodiment can suppress large surge voltages and ringing phenomena.

[0073] Figure 8 is a graph showing the characteristics of the loss and drain-source voltage change with respect to the capacitance of the Si capacitor 201A of the semiconductor device 1 in this embodiment. In Figure 7, the horizontal axis of the graph corresponds to the capacitance value of the Si capacitor 201A, one vertical axis of the graph corresponds to the turn-off loss of the transistor TR, and the other vertical axis corresponds to the peak value of the drain-source voltage. In this example, the turn-off loss of the transistor TR is the loss (Vds × Id) that occurs during the period from when the drain-source voltage reaches its peak value until the ringing phenomenon subsides. The resistance value of resistor 202 is set to 1.0Ω.

[0074] As shown in Figure 8, the peak value of the source voltage decreases as the capacitance value of the Si capacitor 201A increases. In other words, the semiconductor device 1 of this embodiment can suppress the surge voltage when the semiconductor device 1 (transistor TR) is turned off.

[0075] Regarding the losses of semiconductor device 1 during turn-off, as the capacitance of Si capacitor 201A increases, the period from when the ringing phenomenon subsides until transistor TR turns off becomes longer. In this case, the amount of loss during turn-off increases due to the prolonged turn-off period.

[0076] When the capacitance value of the Si capacitor 201A is between 1.0 nF and 10.0 nF, the turn-off period of the semiconductor device 1 is controlled to a more suitable value. As a result, the semiconductor device 1 of this embodiment can achieve low turn-off loss.

[0077] Furthermore, if the capacitance value of the Si capacitor 201A is 1.0 nF or more and 10.0 nF or less, the semiconductor device 1 of this embodiment can obtain substantially the same effect if the resistance value of the resistor 202 is in the range of 1.0 Ω to 10.0 Ω.

[0078] As in this embodiment, when the Si capacitor 201A and resistor 202 are built into the same sealing member 90 as the transistor TR, the semiconductor device 1 of this embodiment can reduce surge voltage and turn-off loss compared to when the Si capacitor and resistor are provided outside the transistor package.

[0079] As in the semiconductor device 1 of this embodiment, by integrating the components including the Si capacitor 201A and resistor 202 within the same package as the transistor TR, the wiring length between the transistor TR and components 201A and 202 is shortened. Therefore, the parasitic inductance between the transistor TR and components 201A and 202 is reduced.

[0080] As a result, the semiconductor device 1 of this embodiment can reduce the turn-off loss of the transistor TR.

[0081] For example, as the switching speed of a transistor (TR) increases, the effect of suppressing the adverse effects of parasitic inductance becomes more pronounced.

[0082] (d) Summary In semiconductor devices that control current, a spike-like voltage overshoot occurs during the switching operation (mainly during turn-off) of a transistor (e.g., a MOSFET). This spike-like voltage overshoot is called a surge voltage.

[0083] When selecting transistors for use in power devices, it is desirable that the surge voltage does not exceed the transistor's maximum rating.

[0084] However, generally speaking, MOSFETs with high voltage ratings have high on-resistance (Ron). This high on-resistance was a cause of losses during the switching operation of the MOSFET.

[0085] Snubber circuits are known as circuits for suppressing surge voltages. Snubber circuits include C snubber circuits, RC snubber circuits, charge / discharge RCD snubber circuits, and discharge-prevention RCD snubber circuits. A C snubber circuit is a circuit that includes a capacitive element (C) connected in parallel between the drain terminal and source terminal of a MOSFET. An RC snubber circuit is a circuit that uses a resistive element (R) and a capacitive element. Charge / discharge type and discharge-prevention RCD snubber circuits are circuits that use a diode (D). These snubber circuits are connected between the drain terminal and source terminal of a MOSFET. In this way, the snubber circuit absorbs and suppresses the surge voltage when the MOSFET is turned off.

[0086] When an RC snubber circuit is mounted on a circuit board, one set of RC snubber circuits is provided for each MOSFET. If long wires are used to connect the MOSFET and the RC snubber circuit, these wires contain parasitic inductance. This parasitic inductance in the wires can cause noise during the switching operation of the MOSFET.

[0087] For example, technologies have been proposed in which resistive and capacitive elements are integrated into the semiconductor chip of a MOSFET, or in which chip components such as resistive and capacitive elements are integrated into the package of a MOSFET.

[0088] In a structure where resistive and capacitive elements are integrated into a semiconductor chip, the area of ​​the resistive and capacitive elements is large, while the area of ​​the MOSFET (switching element) within the semiconductor chip becomes relatively small. Therefore, a structure in which resistive and capacitive elements are integrated into a semiconductor chip may result in problems with operating efficiency per chip area and cost.

[0089] In structures where chip components are embedded within a package, the large size of the chip components can lead to problems with the size of the semiconductor package and the reliability of the chip components.

[0090] The semiconductor device 1 of this embodiment includes a transistor chip 10 and a component chip 20 containing a Si capacitor 201A and a resistor 202, all contained within a sealing member 90. The component chip 20 is stacked on top of the transistor chip 10 via a connector 60. The Si capacitor 201A and resistor 202 of the component chip 20 are connected in parallel to the current path of the transistor TR of the transistor chip 10. The component chip 20 functions as a snubber circuit SNB.

[0091] As a result, the semiconductor device 1 of this embodiment can reduce the peak value of the surge voltage generated when the transistor TR is turned off. Furthermore, the semiconductor device 1 of this embodiment can suppress the ringing phenomenon of the transistor TR during turn-off.

[0092] In this embodiment, the semiconductor device 1 can be configured to use a transistor TR having low on-resistance and low breakdown voltage, depending on the reduction of surge voltage.

[0093] In the semiconductor device 1 of this embodiment, the Si capacitor 201A is used in a snubber circuit (SNB).

[0094] Generally, multilayer ceramic capacitors (MLCCs) exhibit unstable performance under high-temperature conditions. Therefore, integrating multilayer ceramic capacitors into the same package as power devices that generate relatively high temperatures is difficult from the standpoint of ensuring the stability of the semiconductor device's performance.

[0095] Si capacitor 201A has high heat resistance and maintains stable performance even under high-temperature conditions. Therefore, Si capacitor 201A can operate stably with almost no change in capacitance due to the heat generated by transistor TR.

[0096] In this embodiment, the semiconductor device 1 uses a Si capacitor 201A as the capacitive element of the snubber circuit SNB, thereby allowing the snubber circuit SNB to be built into the same sealing member 90 as the transistor TR.

[0097] As a result, the semiconductor device 1 of this embodiment can reduce the wiring length between the snubber circuit components 201A and 202 and the transistor TR. Therefore, the semiconductor device 1 of this embodiment can reduce the parasitic inductance contained in the wiring between components 201A and 202 and the transistor TR. Consequently, the semiconductor device 1 of this embodiment can reduce losses during the turn-off of the semiconductor device 1.

[0098] Furthermore, the semiconductor device 1 of this embodiment can achieve noise performance in which the influence of the operating temperature of the transistor TR on the capacitive elements of the snubber circuit SNB is suppressed by the application of the Si capacitor 201A. As a result, the semiconductor device 1 of this embodiment can improve switching efficiency.

[0099] In the semiconductor device 1 of this embodiment, a snubber circuit SNB is stacked on a transistor TR within a single sealing member 90. This allows the semiconductor device 1 of this embodiment to reduce the area of ​​the package substrate. Therefore, the semiconductor device 1 of this embodiment can reduce the package size.

[0100] When the semiconductor device 1 of this embodiment is applied to a power module, the number of components on the wiring board can be reduced by providing the snubber circuit components 201A and 202 of the SNB in ​​the same package as the transistor TR.

[0101] By reducing the size of the semiconductor device and decreasing the number of components on the wiring board, the semiconductor device 1 and the power module including the semiconductor device 1 of this embodiment can reduce manufacturing costs.

[0102] Furthermore, in this embodiment, a copper connector 60 is provided between the transistor chip 10 and the component chip 20. The connector 60 improves the heat dissipation performance of the transistor chip 10 and the component chip 20. As a result, the semiconductor device 1 of this embodiment can further stabilize the operation of the transistor TR and the snubber circuit SNB.

[0103] As described above, the semiconductor device 1 of this embodiment can improve the characteristics of the semiconductor device.

[0104] (2) Second embodiment A semiconductor device of the second embodiment will be described with reference to Figures 9 to 11.

[0105] Figure 9 is a top view showing an example of the planar structure of the semiconductor device 1 of this embodiment. Figure 10 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 1 of this embodiment, along line BB in Figure 9.

[0106] As shown in Figures 9 and 10, multiple Si capacitors 201A and 201B may be provided within a single semiconductor chip (component chip) 20.

[0107] The component chip 20 includes, for example, two Si capacitors 201A and 201B. Of the two Si capacitors 201A and 201B, Si capacitor 201B is used selectively as an option.

[0108] One terminal of the Si capacitor 201A is connected to the resistor 202 and also to the electrode 207A on the surface of the component chip 20.

[0109] When Si capacitor 201B is used, for example, Si capacitor 201B is electrically connected to Si capacitor 201A via bonding wire 69. One terminal of Si capacitor 201B is connected to electrode 207B on the surface of component chip 20. The other terminal of Si capacitor 201B is connected to electrode 205 on the back surface of component chip 20. Electrode 207B is connected to electrode 207A by bonding wire 69. This electrically connects Si capacitor 201B to Si capacitor 201A.

[0110] If Si capacitor 201B is not used, electrode 207B is not connected to electrode 207A. This electrically isolates Si capacitor 201B from the current path of the snubber circuit SNB.

[0111] Figure 11 is a circuit diagram showing the circuit configuration of the semiconductor device 1 of this embodiment when the optional Si capacitor 201B is used.

[0112] As shown in Figure 11, when Si capacitor 201B is used, Si capacitor 201B is connected in parallel with Si capacitor 201A.

[0113] Thus, when the Si capacitor 201B is used according to the electrical characteristics of the snubber circuit SNB, the capacitance of the snubber circuit SNB can be adjusted.

[0114] Multiple resistors 202 may be provided within a single component chip 20.

[0115] As described above, the semiconductor device 1 of this embodiment can improve the characteristics of the semiconductor device.

[0116] (3) Third Embodiment A semiconductor device of a third embodiment will be described with reference to Figures 12 to 14.

[0117] Figure 12 is a top view showing an example of the planar structure of the semiconductor device of this embodiment. Figure 13 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device of this embodiment along line AA in Figure 12. Figure 14 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device of this embodiment along line BB in Figure 12.

[0118] As shown in Figures 12 to 14, the terminals of the Si capacitor 201A on the component chip 20 may be electrically connected to the corresponding lead terminals 402 of the lead frame 40 by bonding wires 66.

[0119] In this embodiment, the component chip 20 does not have electrodes on its back surface. An insulator 89, such as an adhesive, is provided between the back surface of the component chip 20 and the connector 60. The component chip 20 is fixed onto the connector 60 by the insulator 89.

[0120] The component chip 20 includes two electrodes 204 and 209 provided on its surface. The Si capacitor 201A and the resistor 202 are connected in series between electrodes 204 and 209.

[0121] Electrode 209 is connected to the other terminal of Si capacitor 201A. Electrode 209 is electrically connected to connector 60 by bonding wire 66. This electrically connects the other terminal of Si capacitor 201A to electrode 102 and lead terminal 402 of transistor TR.

[0122] As described above, in this embodiment, the Si capacitor 201A and resistor 202 that form the snubber circuit SNB are connected in parallel to the current path of the transistor TR by bonding wires 65 and 69.

[0123] Even when the connection between the Si capacitor 201A and the lead frame 40 is made by bonding wires 65, as in this embodiment, the semiconductor device 1 of this embodiment can reduce surge voltage and suppress ringing substantially in the same manner as in the first embodiment.

[0124] Therefore, the semiconductor device 1 of this embodiment can improve the characteristics of the semiconductor device.

[0125] (4) Fourth Embodiment A semiconductor device of the fourth embodiment will be described with reference to Figures 15 to 17.

[0126] Figure 15 is a top view showing an example of the planar structure of the semiconductor device 1 of this embodiment. Figure 16 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 1 of this embodiment along line AA in Figure 15. Figure 17 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 1 of this embodiment along line BB in Figure 15.

[0127] As shown in Figures 15 to 17, in the semiconductor device 1 of this embodiment, the component chip 20 including the Si capacitor 201A is provided on a lead frame 40. The component chip 20 is adjacent to the transistor chip 10 on the lead frame 40 in a direction parallel to the surface of the lead frame 40 (in this example, the X direction).

[0128] The transistor chip 10 and the component chip 20 are covered by a sealing member 90 on the lead frame 40.

[0129] The component chip 20 is located between the connector 60 and the lead terminal 401 in the Z direction.

[0130] The electrodes 204 on the surface of the component chip 20 are electrically connected to the connector 60 via the conductor 87. The electrodes 204 are electrically connected to the lead terminals 402 by the connector 60. The electrodes 205 on the back surface of the component chip 20 are electrically connected to the lead terminals 401 via the conductor 88. This connects the snubber circuit SNB in ​​parallel to the current path of the transistor TR. The conductors 87 and 88 are, for example, solder or conductive paste.

[0131] The electrode 204 may also be electrically connected to the lead terminal 402 by a bonding wire without going through the connector 60.

[0132] Note that the connector 60 does not necessarily have to extend onto the surface of the component chip 20. In this case, the component chip 20 is provided on the lead terminal 401 without being sandwiched between the connector 60 and the lead terminal 401. The electrodes 204 of the component chip 20 are electrically connected to the lead terminal 402 by bonding wires.

[0133] The transistor chip 10 and the component chip 20 may be laid out on the lead frame 40 such that the component chip 20 is adjacent to the transistor chip 10 in the Y direction.

[0134] As in this embodiment, even if the semiconductor device 1 has a structure in which the transistor chip 10 and the component chip 20 are adjacent to each other on the lead frame 40 in the X direction (or Y direction), the semiconductor device 1 of this embodiment can obtain substantially the same effects as the embodiment described above.

[0135] The semiconductor device 1 of this embodiment has a structure in which a component chip 20 including a Si capacitor 201A and a resistor 202 is sandwiched between two metal plates (for example, copper plates) 60 and 401. With this structure, the component chip 20, which acts as a snubber circuit (SNB), is cooled by the metal plates 60 and 401.

[0136] As a result, the semiconductor device 1 of this embodiment can mitigate the effects of heat generated during operation.

[0137] Therefore, the semiconductor device 1 of this embodiment can improve the characteristics of the semiconductor device.

[0138] (5) Fifth embodiment A semiconductor device of the fifth embodiment will be described with reference to Figures 18 and 19.

[0139] Figure 18 is a circuit diagram showing the circuit configuration of the semiconductor device 1 of this embodiment.

[0140] As shown in Figure 18, in the semiconductor device 1 of this embodiment, the snubber circuit SNB may be an RCD snubber circuit. In addition to the Si capacitor 201A and the resistor 202, the snubber circuit SNB further includes a diode 208.

[0141] Diode 208 is connected in parallel with resistor 202. One end of diode 208 (e.g., anode) is connected to one end of resistor 202 (and the other end of Si capacitor 201). The other end of diode 208 (e.g., cathode) is connected to the other end of resistor 202 (and the other end of the current path of transistor TR). For example, diode 208 is a PN junction diode.

[0142] Figure 19 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 1 of this embodiment.

[0143] As shown in Figure 19, the diode 208 is provided within the component chip 20 together with the Si capacitor 201A and the resistor 202. The diode 208 is provided, for example, on the back side of the silicon substrate 200 in the component chip 20.

[0144] For example, one end of the diode 208 is connected to one end of the resistor 202 via a component (not shown) within the component chip 20. For example, the other end of the diode 208 is electrically connected to the connector 60 via an electrode 205 and a conductor 85. In this case, the other end of the resistor 202 is electrically connected to the connector 60 via, for example, an additional electrode (not shown) and a bonding wire (not shown). The other end of the resistor 202 may also be connected to the other end of the diode 208 (or electrode 205) via a component (not shown) within the component chip 20.

[0145] Thus, in the component chip 20, the diode 208 is connected in parallel with the resistor 202.

[0146] Note that the diode 208 may be provided on a semiconductor chip different from the component chip 20.

[0147] As described above, the semiconductor device 1 of this embodiment includes a component chip 20 for the RCD snubber circuit. This allows the semiconductor device 1 of this embodiment to suppress surge voltages generated during the switching operation of the transistor TR.

[0148] Therefore, the semiconductor device 1 of this embodiment can improve the characteristics of the semiconductor device.

[0149] (6) Others While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0150] 1: Semiconductor device, 10: Transistor chip, TR: Transistor, 20: Component chip, SNB: Snubber circuit, 201A, 201B: Si capacitor, 202: Resistor, 40: Lead frame, 401, 402, 403: Lead terminals, 60, 62: Connector, 90: Encapsulation material.

Claims

1. A package substrate including a first lead terminal and a second lead terminal, A first semiconductor chip, including a switching element, is provided on the first lead terminal, A connector extending from the surface of the first semiconductor chip to the second lead terminal, A resistive portion and a first capacitive portion provided in a semiconductor substrate are included, and a second semiconductor chip is provided on the connector above the first semiconductor chip. It is equipped with, The first semiconductor chip includes a first electrode provided on the surface of the first semiconductor chip and a second electrode provided on the back surface of the first semiconductor chip. The aforementioned second semiconductor chip includes a third electrode and a fourth electrode, The first electrode is electrically connected to the second lead terminal. The second electrode is electrically connected to the first lead terminal. The third electrode is electrically connected to the first lead terminal. The fourth electrode is electrically connected to the second lead terminal. Semiconductor equipment.

2. The semiconductor substrate is a silicon substrate, The first capacitance unit is a silicon capacitor. The semiconductor device according to claim 1.

3. The capacitance section is connected in series with the resistor section. The series-connected capacitance and resistor are connected in parallel to the current path of the switching element between the first electrode and the second electrode. The semiconductor device according to claim 1.

4. The second semiconductor chip further includes a second capacitance portion provided within the semiconductor substrate, The second capacitance unit is electrically connected to the first capacitance unit via the first wire. The semiconductor device according to claim 1.

5. The third electrode is provided on the surface of the second semiconductor chip, The fourth electrode is provided on the back surface of the second semiconductor chip. The first electrode is electrically connected to the second lead terminal via the connector. The second electrode is electrically connected to the first lead terminal via a conductor provided between the back surface of the first semiconductor chip and the first lead terminal. The third electrode is electrically connected to the first lead terminal via the second wire. The fourth electrode is electrically connected to the first electrode and the second lead terminal via the connector. The semiconductor device according to claim 1.

6. The third electrode and the fourth electrode are provided on the surface of the second semiconductor chip. The first electrode is electrically connected to the second lead terminal via the connector. The second electrode is electrically connected to the first lead terminal via a conductor provided between the back surface of the first semiconductor chip and the first lead terminal. The third electrode is electrically connected to the first lead terminal via a third wire. The fourth electrode is electrically connected to the connector via a fourth wire. The semiconductor device according to claim 1.

7. The capacitance of the aforementioned capacitive section is 0.1 nF or more and 20.0 nF or less. The semiconductor device according to claim 1.

8. The resistance value of the aforementioned resistor is 0.1Ω or more and 10.0Ω or less. The semiconductor device according to claim 7.

9. The switching element includes a transistor, The aforementioned transistor operates using a voltage of 6V or more and 300V or less. The semiconductor device according to claim 7.

10. Each of the first lead terminal, the second lead terminal, and the connector contains copper. The semiconductor device according to claim 1.

11. A sealing member provided on the package substrate and covering the first semiconductor chip and the second semiconductor chip, The semiconductor device according to claim 1, further comprising:

12. A package substrate including a first lead terminal and a second lead terminal, A connector provided above the aforementioned package substrate, A first semiconductor chip including a switching element is provided between the first lead terminal and the connector, A resistive portion and a first capacitive portion provided within a semiconductor substrate are included, and a second semiconductor chip is provided adjacent to the first semiconductor chip and between the first lead terminal and the connector, It is equipped with, The first semiconductor chip includes a first electrode provided on the surface of the first semiconductor chip and a second electrode provided on the back surface of the first semiconductor chip. The aforementioned second semiconductor chip includes a third electrode and a fourth electrode, The first electrode is electrically connected to the second lead terminal via the connector. The second electrode is electrically connected to the first lead terminal. The third electrode is electrically connected to the second lead terminal via the connector. The fourth electrode is electrically connected to the first lead terminal. Semiconductor equipment.

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