Semiconductor wafers, semiconductor wafer groups, and semiconductor devices

Abstract

To shorten the carrier lifetime within the epitaxial layer. [Solution] The technical concept of this disclosure is that a carrier lifetime distribution, which includes carrier lifetimes within an epitaxial layer measured at multiple measurement points, has the following characteristics: (1) The average value of the carrier lifetime is τ m In that case, τ m (2) The standard deviation of the carrier lifetime distribution is σ τ In that case, σ τ ≤0.5τ m That is the case.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor wafers, semiconductor wafer groups, and semiconductor devices. This disclosure relates, for example, to semiconductor wafers, semiconductor wafer groups, and semiconductor devices in which an epitaxial layer is formed on a silicon carbide substrate having a 4H-SiC crystal structure. [Background technology]

[0002] Japanese Patent Publication No. 7113882 (Patent Document 1) and Japanese Patent Publication No. 7298294 (Patent Document 2) describe techniques for reducing conduction losses when an IGBT (Insulated Gate Bipolar Transistor) has a withstand voltage of 10kV or more.

[0003] Specifically, Patent Documents 1 and 2 describe techniques for extending the carrier lifetime within the epitaxial layer in order to reduce conduction loss.

[0004] Non-patent document 1 describes a technology for shortening career lifetime. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Patent No. 7113882 [Patent Document 2] Patent No. 7298294 [Non-patent literature]

[0006] [Non-Patent Document 1] Seiji Ishikawa et al., "Characterization of 1.2kV SiC Trench-Type MOSFETs Using Bonded SiC Substrates," Advanced Power Semiconductor Subcommittee (2023) IIB-21 [Overview of the project] [Problems that the invention aims to solve]

[0007] In a single power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), current flows but almost no voltage is applied when it is in the ON state. Conversely, when it is in the OFF state, almost no current flows but a voltage is applied. Therefore, when the power MOSFET is in the ON state, the voltage is small. In contrast, when the power MOSFET is in the OFF state, the current is small. Consequently, the power generated in the steady state, whether ON or OFF, is small. This is because power is expressed as the product of current and voltage. That is, the voltage is small in the ON state and the current is small in the OFF state. From this, the product of current and voltage is small in both the ON and OFF states. In contrast, during the switching operation of the power MOSFET, a larger power loss occurs than in the ON or OFF state.

[0008] The following explains this point. The operation of switching between the on and off states of a power MOSFET by changing its gate voltage is called switching operation. During switching operation, the power MOSFET consumes a large amount of power because high voltage and high current are generated simultaneously. This power consumption is called switching loss.

[0009] The higher the switching frequency, defined by the frequency of the power MOSFET's on / off signal, the better the output quality of inverters, one of its applications. On the other hand, a higher switching frequency increases the number of switching losses that occur per unit time, thus increasing the switching loss. For this reason, reducing the switching loss is desirable.

[0010] Therefore, this disclosure aims to reduce switching losses in semiconductor devices. [Means for solving the problem]

[0011] A semiconductor wafer according to an embodiment includes a silicon carbide substrate having a 4H-SiC crystal structure and an epitaxial layer formed on the silicon carbide substrate. In a carrier lifetime distribution including carrier lifetimes in the epitaxial layer measured at a plurality of measurement points, when the average value of the carrier lifetimes is τ , , m ,

[0014] and m τ ≤ 0.4 μs, and when the standard deviation of the carrier lifetime distribution is σ τ and τ σ ≤ 0.5τ m is satisfied.

[0012] A semiconductor wafer according to an embodiment includes a silicon carbide substrate having a 4H-SiC crystal structure and an epitaxial layer formed on the silicon carbide substrate. In a carrier lifetime distribution including carrier lifetimes in the epitaxial layer measured at a plurality of measurement points, when the average value of the carrier lifetimes is τ m and m τ ≤ 0.2 μs, and when the standard deviation of the carrier lifetime distribution is σ τ and τ σ ≤ 0.05τ m is satisfied.

[0013] A semiconductor device according to an embodiment includes a silicon carbide substrate having a 4H-SiC crystal structure and an epitaxial layer formed on the silicon carbide substrate. In a carrier lifetime distribution including carrier lifetimes in the epitaxial layer measured at a plurality of measurement points, when the average value of the carrier lifetimes is τ m and m τ ≤ 0.4 μs, and when the standard deviation of the carrier lifetime distribution is σ τ and τ σ ≤ 0.5τ m is satisfied.

[0014] One embodiment of a semiconductor device comprises a silicon carbide substrate having a 4H-SiC crystal structure and an epitaxial layer formed on the silicon carbide substrate. In a carrier lifetime distribution that includes the carrier lifetimes in the epitaxial layer measured at multiple measurement points as elements, the average value of the carrier lifetimes is given by τ m In that case, τ m ≤0.2μs, and the standard deviation of the carrier lifetime distribution is σ τ In that case, σ τ ≤0.05τ m That is the case. [Effects of the Invention]

[0015] According to one embodiment, the carrier lifetime within the epitaxial layer of a semiconductor wafer can be shortened. As a result, the switching loss of semiconductor devices manufactured using the semiconductor wafer can be reduced. [Brief explanation of the drawing]

[0016] [Figure 1] This diagram shows the circuit configuration of a step-down DC / DC converter. [Figure 2] This figure shows the timing charts for high-side MOSFETs and low-side MOSFETs. [Figure 3] This diagram shows the configuration of a motor circuit including an inverter and a three-phase brushless motor. [Figure 4] This is a cross-sectional view showing a semiconductor device including a power MOSFET. [Figure 5] This diagram shows the voltage waveform, current waveform, and power loss waveform in relation to each other during the switching operation of a single power MOSFET used as a switching element. [Figure 6] This is a plan view showing a semiconductor wafer in Embodiment 1. [Figure 7] This is a cross-sectional view showing a semiconductor wafer in Embodiment 1. [Figure 8]This is a diagram for explaining that the inclusion of hydrogen chloride in the carrier gas can shorten the carrier lifetime and reduce the variation. [Figure 9] This is a diagram showing a schematic configuration of a film-forming apparatus in Embodiment 1. [Figure 10] This is a diagram showing a schematic configuration of a film-forming apparatus in a study example. [Figure 11] This is a diagram showing a carrier lifetime distribution obtained from carrier lifetimes in an epitaxial layer measured at a plurality of measurement points. [Figure 12] This is a diagram showing a Weibull distribution based on FIG. 11. [Figure 13] This is a diagram showing a carrier lifetime distribution obtained from carrier lifetimes in an epitaxial layer measured at a plurality of measurement points. [Figure 14] This is a diagram showing a Weibull distribution based on FIG. 13. [Figure 15] This is a cross-sectional view showing a manufacturing process of a semiconductor device in Embodiment 2. [Figure 16] This is a cross-sectional view showing a semiconductor device in Embodiment .

Embodiments of the Invention

[0017] In all the diagrams for explaining the embodiments, the same members are generally denoted by the same reference numerals, and repeated explanations thereof are omitted. Note that, for the sake of clarity of the drawings, hatching may be added even to a plan view.

[0018] First, a power conversion device using a power transistor will be described. Examples of the power conversion device include a DC / DC converter, an inverter, and the like. Hereinafter, as an example of the power conversion device, a DC / DC converter and an inverter will be described.

[0019] <Configuration of DC / DC Converter> DC / DC converters include buck DC / DC converters and boost DC / DC converters. Here, we will focus on and explain buck DC / DC converters.

[0020] Figure 1 shows the circuit configuration of a step-down DC / DC converter.

[0021] A step-down DC / DC converter has a control circuit CC, a high-side MOSFET 10, a low-side MOSFET 20, an inductor L, and a capacitor C. Both the high-side MOSFET 10 and the low-side MOSFET 20 are power MOSFETs. A power MOSFET is a type of power transistor.

[0022] In a step-down DC / DC converter, a high-side MOSFET 10 and a low-side MOSFET 20 are connected in series between the input terminal TE1 and ground (reference potential) GND. An inductor L and a load RL are connected in series between node NA, which is between the high-side MOSFET 10 and the low-side MOSFET 20, and ground GND, which is connected to the load RL. A capacitor C is connected in parallel with the load RL.

[0023] The gate electrode of the high-side MOSFET 10 is connected to the control circuit CC. The gate electrode of the low-side MOSFET 20 is also connected to the control circuit CC. The control circuit CC controls the on / off operation of the high-side MOSFET 10. In addition, the control circuit CC controls the on / off operation of the low-side MOSFET 20.

[0024] Specifically, when the control circuit CC turns on the high-side MOSFET 10, it turns off the low-side MOSFET 20. Conversely, when the control circuit CC turns off the high-side MOSFET 10, it turns on the low-side MOSFET 20.

[0025] For example, when the high-side MOSFET 10 is on and the low-side MOSFET 20 is off, current flows from the input terminal TE1 through the high-side MOSFET 10 and inductor L to the load RL. Then, when the high-side MOSFET 10 is turned off and the low-side MOSFET 20 is turned on, the high-side MOSFET 10 is turned off first. As a result, the current flowing from the input terminal TE1 through the high-side MOSFET 10 and inductor L to the load RL is interrupted. That is, the current flowing through inductor L is interrupted. However, when the current decreases (is interrupted) in inductor L, it tries to maintain the current flowing through inductor L. At this time, since the low-side MOSFET 20 is on, current now flows from ground GND through the low-side MOSFET 20 and inductor L to the load RL. After that, the high-side MOSFET 10 is turned on again and the low-side MOSFET 20 is turned off.

[0026] This switching operation of the high-side MOSFET 10 and the low-side MOSFET 20 is repeated. As a result, in a step-down DC / DC converter, when an input voltage Vin is input to the input terminal TE1, an output voltage Vout lower than the input voltage Vin is output across the load RL. In other words, the step-down DC / DC converter outputs an output voltage Vout lower than the input voltage Vin through switching operation.

[0027] The following explains why, by repeating the switching operation described above, when an input voltage Vin is applied to input terminal TE1, an output voltage Vout lower than the input voltage Vin is output across the load RL.

[0028] In the following explanation, we will assume that the current flowing through the inductor L is continuous.

[0029] The high-side MOSFET 10 is controlled by the control circuit CC, and during the on-period T ON and off period T OFFThe switching operation is performed as follows: The switching frequency in this switching operation is f = 1 / (T ON +T OFF )

[0030] For example, in Figure 1, capacitor C has the function of preventing large fluctuations in the output voltage Vout over a short period of time. In other words, in a step-down DC / DC converter, a capacitor C with a relatively large capacitance value is inserted in parallel with the load RL. Therefore, in a steady state, the ripple voltage included in the output voltage Vout is small compared to the output voltage Vout. Consequently, fluctuations in the output voltage Vout within one cycle of switching operation can be ignored.

[0031] First, let's consider the case where the high-side MOSFET 10 is ON.

[0032] Assuming that the output voltage Vout does not fluctuate within one period, the voltage across the inductor L can be considered constant as (Vin - Vout). As a result, if the inductance of the inductor L is L1, the on-period T ON The increase in current ΔI ON This is given by (Equation 1).

[0033] ΔI ON =(Vin-Vout) / L1×T ON ...(Equation 1) Next, let's consider the case where the high-side MOSFET 10 is off.

[0034] In this case, the low-side MOSFET 20 is ON. Therefore, the voltage across the inductor L is 0 - Vout = -Vout. Consequently, the off period T OFF The increase in current ΔI OFF This is given by (Equation 2).

[0035] ΔI OFF = -Vout / L1 × T OFF ...(Equation 2) When in the steady state, the current flowing through the inductor L does not increase or decrease during one cycle of the switching operation. In other words, if the current flowing through the inductor L increases or decreases during one cycle, the steady state has not been reached yet. Therefore, in the steady state, (Equation 3) holds.

[0036] ΔI ON +ΔI OFF =0 ···(Equation 3)

[0037] Substituting (Equation 1) and (Equation 2) into (Equation 3) gives (Equation 4).

[0038] Vout = Vin×T ON / (T ON +T OFF ) ···(Equation 4)

[0039] In (Equation 4), T ON ≧0, and T OFF ≧0. From this, Vout < Vin. That is, the step-down DC / DC converter is a circuit that outputs an output voltage Vout lower than the input voltage Vin.

[0040] By controlling the switching operation by the control circuit CC from (Equation 4), the on-time T ON and the off-time T OFF are changed. Thereby, an arbitrary output voltage Vout lower than the input voltage Vin can be obtained. In particular, if the on-time T ON and the off-time T OFF are controlled to be constant, a constant output voltage Vout can be obtained.

[0041] As described above, the step-down DC / DC converter controls the on / off operation (switching operation) of the high-side MOSFET 10 and the on / off operation (switching operation) of the low-side MOSFET 20 by the control circuit CC. Thereby, the step-down DC / DC converter can output an output voltage Vout lower than the input voltage Vin.

[0042] Figure 2 shows the timing chart for high-side MOSFET 10 and low-side MOSFET 20. ON period T ON This indicates the time when the high-side MOSFET 10 is ON. Off period T OFF This indicates the time when the high-side MOSFET 10 is off. When the high-side MOSFET 10 is on, the low-side MOSFET 20 is off. When the high-side MOSFET 10 is off, the low-side MOSFET 20 is on. Therefore, the on period T ON This indicates the time when the low-side MOSFET 20 is off. Off period T OFF This indicates the time that the low-side MOSFET 20 is ON.

[0043] As described above, a buck DC / DC converter is a type of switching converter that uses the switching operations of the high-side MOSFET 10 and the low-side MOSFET 20, respectively. For example, the switching frequency of a buck DC / DC converter is approximately 100 kHz. Therefore, in order to reduce the power loss of a buck DC / DC converter, it is important to reduce the switching losses caused by the switching operation.

[0044] <Inverter Configuration> In the following explanation, we will use a three-phase inverter as an example.

[0045] An inverter has the function of converting direct current (DC) power into alternating current (AC) power.

[0046] Figure 3 shows the configuration of a motor circuit including an inverter and a three-phase brushless motor. The motor circuit has a three-phase brushless motor MT and an inverter INV. The three-phase brushless motor MT is driven by three phases of voltage with different phases. Specifically, the three-phase brushless motor MT uses three phases of alternating current called U-phase, V-phase, and W-phase, which are 120 degrees apart in phase, to generate a rotating magnetic field inside the stator ST, which is a soft magnetic material. In this case, the magnetic field rotates around the rotor RT. This changes the magnetic flux that crosses the rotor RT, which is a conductor. As a result, a magnetic force is applied to the rotor RT, and the rotor RT rotates. In this way, the three-phase brushless motor MT can rotate the rotor RT by using three phases of alternating current. In other words, the three-phase brushless motor MT requires three phases of alternating current. Therefore, the motor circuit uses an inverter INV, which generates alternating current from direct current, to supply three phases of alternating current to the three-phase brushless motor.

[0047] The following describes an example of an inverter (INV) configuration.

[0048] As shown in Figure 3, for example, the inverter INV has switching elements 30 and diodes FWD corresponding to the three phases. The switching elements 30 and diodes FWD are connected in antiparallel. In Figure 3, the upper and lower arms of the first leg LG1 include a configuration in which the switching elements 30 and diodes FWD are connected in antiparallel. The upper and lower arms of the second leg LG2 include a configuration in which the switching elements 30 and diodes FWD are connected in antiparallel. The upper and lower arms of the third leg LG3 include a configuration in which the switching elements 30 and diodes FWD are connected in antiparallel. The diodes FWD connected in antiparallel to the switching elements 30 are freewheeling diodes.

[0049] Thus, the inverter INV has a configuration in which switching elements 30 and diodes FWD are connected in antiparallel between the positive potential terminal PT and each phase (U phase, V phase, W phase) of the 3-phase brushless motor MT. The inverter INV also has a configuration in which switching elements 30 and diodes FWD are connected in antiparallel between each phase of the 3-phase brushless motor MT and the negative potential terminal NT. In other words, two switching elements 30 and two diodes FWD are provided for each single phase. Therefore, a total of six switching elements 30 and six diodes FWD are provided for the three phases. A gate control circuit GCC is connected to the gate electrode of each switching element 30. The gate control circuit GCC controls the switching operation of the switching elements 30. In this configuration, the inverter INV controls the switching operation of the switching elements 30 with the gate control circuit GCC. As a result, the inverter INV can convert DC power into 3-phase AC power. The 3-phase AC power converted by the inverter INV is supplied to the 3-phase brushless motor MT.

[0050] As described above, the inverter INV converts DC power to AC power by controlling the switching operation of each of the six switching elements 30. For example, the switching frequency of the inverter INV is approximately 5kHz to 20kHz. Therefore, in order to reduce the power loss of the inverter INV, it is important to reduce the switching loss caused by the switching operation.

[0051] In particular, the output quality of the inverter (INV) improves as the switching frequency increases. Furthermore, as a noise reduction measure for the inverter (INV), operating it at around 20 kHz, which is above the human audible frequency range, is also being considered.

[0052] However, as the switching frequency increases, the number of switching losses that occur per unit time increases, resulting in greater switching losses. For this reason, reducing switching losses is also desired in inverters (INV).

[0053] The switching element 30 used in the inverter INV is a power transistor. Examples of power transistors include power MOSFETs and IGBTs.

[0054] In this specification, power MOSFETs are assumed to be power transistors used in DC / DC converters or inverters.

[0055] The following describes the configuration of power MOSFETs.

[0056] <Power MOSFET Configuration> Figure 4 is a cross-sectional view showing a semiconductor device 100 including a power MOSFET.

[0057] In Figure 4, the semiconductor device 100 includes a silicon carbide substrate 1, a buffer layer 2, a drift layer 3, a drain electrode 4, p-type wells 5A and 5B, a source region 6A and 6B, a body contact region 7A and 7B, a gate insulating film 8, a gate electrode 9, an interlayer insulating film 11, a source electrode 12, an epitaxial layer 13, a channel formation region CH1, and a channel formation region CH2.

[0058] The silicon carbide substrate 1 is 1 × 10 19 cm -3 It contains a certain amount of nitrogen. The thickness of the silicon carbide substrate 1 is approximately 50 μm to 500 μm. In a typical example, the thickness of the silicon carbide substrate 1 is approximately 150 μm.

[0059] The silicon carbide substrate 1 has an upper surface and a lower surface. A drain electrode 4 is formed on the lower surface of the silicon carbide substrate 1. On the other hand, a buffer layer 2 is formed on the upper surface of the silicon carbide substrate 1.

[0060] A drift layer 3 is formed on buffer layer 2. The buffer layer 2 and drift layer 3 constitute the epitaxial layer 13. The epitaxial layer 13 is 1 × 10 15 cm -3 The above 3 x 10 18 cm-3 It contains nitrogen to the following extent. The thickness of the epitaxial layer 13 is between 10 μm and 150 μm. In a typical example, the thickness of the epitaxial layer 13 is about 10 μm. The withstand voltage of the power MOSFET in the off state is determined by the epitaxial layer 13. In a typical example, the withstand voltage specification is 1.2 kV.

[0061] Within the epitaxial layer 13, p-type wells 5A and 5B are formed. For example, p-type impurities such as aluminum (Al) are introduced into p-type wells 5A and 5B. The depth of each p-type well 5A and p-type well 5B is approximately 1 μm. The impurity concentration in each p-type well 5A and p-type well 5B is, for example, 5 × 10⁻⁶ 17 cm -3 It is to that extent.

[0062] Within the p-type well 5A, a source region 6A and a body contact region 7A are formed. The source region 6A is an n-type semiconductor region. The depth of the source region 6A is approximately 0.1 μm. The impurity concentration in the source region 6A is 1 × 10⁻⁶. 20 cm -3 This is the extent of the issue. On the other hand, the body contact region 7A is a p-type semiconductor region. The body contact region 7A has a higher impurity concentration than the p-type well 5A. The source region 6A and the body contact region 7A are formed to be in contact with each other.

[0063] Source region 6B is an n-type semiconductor region. The depth of source region 6B is approximately 0.1 μm. The impurity concentration in source region 6B is 1 × 10⁻⁶. 20 cm -3 This is the extent of the issue. On the other hand, the body contact region 7B is a p-type semiconductor region. The body contact region 7B has a higher impurity concentration than the p-type well 5B. The source region 6B and the body contact region 7B are formed to be in contact with each other.

[0064] A gate insulating film 8 is formed on a portion of the source region 6B, on the channel formation region CH2, on a portion of the drift layer 3, on the channel formation region CH1, and on a portion of the source region 6A. The gate insulating film 8 is, for example, a film mainly composed of silicon oxide. The thickness of the gate insulating film 8 is, for example, about 50 nm. Nitrogen is introduced near the interface between the gate insulating film and the drift layer 3 to improve the interface properties.

[0065] A gate electrode 9 is formed on the gate insulating film 8. The gate electrode 9 is composed of, for example, a polysilicon film containing a high concentration of n-type impurities.

[0066] In the gate length direction of the gate electrode 9, a channel formation region CH1 is formed within the p-type well 5A between the end of the p-type well 5A and the source region 6A. The channel formation region CH1 is a p-type semiconductor region, but when a gate voltage above the threshold voltage is applied to the gate electrode 9, it inverts to an n-type semiconductor and becomes a channel.

[0067] In the gate length direction of the gate electrode 9, a channel formation region CH2 is formed within the p-type well 5B between the end of the p-type well 5B and the source region 6B. The channel formation region CH2 is a p-type semiconductor region, but when a gate voltage of a threshold voltage or higher is applied to the gate electrode 9, it becomes a channel consisting of an inversion layer which is an n-type semiconductor.

[0068] An interlayer insulating film 11 is formed to cover the gate electrode 9. Source electrodes 12 are formed on the body contact region 7B, a portion of the source region 6B, the interlayer insulating film 11, a portion of the source region 6A, and the body contact region 7A. As a result, the source region 6A and the body contact region 7A are electrically connected via the source electrodes 12. Therefore, the same potential is supplied to the source region 6A and the body contact region 7A. The source region 6B and the body contact region 7B are electrically connected via the source electrodes 12. Therefore, the same potential is supplied to the source region 6B and the body contact region 7B.

[0069] The semiconductor device 100 is configured as described above.

[0070] <Power MOSFET Operation> Next, we will briefly explain the operation of power MOSFETs.

[0071] In Figure 4, when a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 9, channels consisting of inversion layers are formed in the channel formation regions CH1 and CH2. As a result, electrons flow through the path source electrode 12 → source region 6A → channel formation region CH1 (inversion layer) → drift layer 3 → buffer layer 2 → silicon carbide substrate 1 → drain electrode 4. Similarly, electrons flow through the path source electrode 12 → source region 6B → channel formation region CH2 (inversion layer) → drift layer 3 → buffer layer 2 → silicon carbide substrate 1 → drain electrode 4. In this way, the power MOSFET is turned on.

[0072] In this state, if a gate voltage below the threshold voltage is applied to the gate electrode 9, the channel consisting of the inversion layer disappears, and the flow of electrons is interrupted. As a result, the power MOSFET turns off. The power MOSFET operates in this manner.

[0073] <Body Diode> Next, we will explain the body diode present in power MOSFETs.

[0074] As shown in Figure 4, a body diode BD parasitic exists between the p-type well 5B (p-type semiconductor layer) and the drift layer 3 (n-type semiconductor layer) in the power MOSFET. Similarly, although not shown in the figure, a body diode parasitic exists between the p-type well 5A (p-type semiconductor layer) and the drift layer 3 (n-type semiconductor layer).

[0075] The body diode BD is a pn junction diode. In other words, the body diode BD is a bipolar device. Therefore, recovery loss occurs due to the body diode BD. This point will be explained below.

[0076] For example, a semiconductor device 100 including a power MOSFET is used in an inverter. The inverter is used, for example, to drive and control a motor. In motor drive control, there is a mode in which a back electromotive force is generated due to the inductance contained in the motor. When a back electromotive force is generated, a positive potential is applied to the source electrode 12. On the other hand, a negative potential is applied to the drain electrode 4. Therefore, when a positive potential is applied to the source electrode 12 by the back electromotive force, a positive potential is applied to the anode (p-type well 5B) of the body diode BD via an electrically connected path from the source electrode 12 to the body contact region 7B to the p-type well 5B. Conversely, when a negative potential is applied to the drain electrode 4 by the back electromotive force, a negative potential is applied to the cathode (drift layer 3) of the body diode BD via an electrically connected path from the drain electrode 4 to the silicon carbide substrate 1 to the buffer layer 2 to the drift layer 3.

[0077] As a result, the body diode BD is forward-biased. Therefore, when a back electromotive force is generated, a freewheeling current flows through the forward-biased body diode BD. In other words, the body diode BD functions as a freewheeling diode.

[0078] Subsequently, when the back electromotive force disappears, 0V is supplied to the source electrode 12, while a positive potential is supplied to the drain electrode 4. In this state, 0V is applied to the anode (p-type well 5B) of the body diode BD, while a positive potential is applied to the cathode (drift layer 3) of the body diode BD. As a result, the body diode BD is reverse-biased.

[0079] Therefore, when the body diode BD is reverse-biased, electrons already injected into the p-type well 5B under forward bias are swept out toward the drain electrode 4. On the other hand, holes already injected into the drift layer 3 under forward bias are swept out toward the source electrode 12. This sweeping out of electrons and holes generates a recovery current. As a result, recovery losses occur due to this recovery current.

[0080] Based on the above, using a power MOSFET as a switching element eliminates the need for an external freewheeling diode connected in antiparallel to the switching element. This is because the body diode BD, which is parasitic on the power MOSFET, functions as a freewheeling diode.

[0081] However, when using a power MOSFET as the switching element, the switching loss increases due to the recovery loss generated in the body diode BD.

[0082] This point will be explained below.

[0083] <Discoveries made by the inventors> Figure 5 shows the voltage waveform, current waveform, and power loss waveform in relation to each other during the switching operation of a single power MOSFET used as a switching element.

[0084] In the voltage waveform shown in Figure 5, the horizontal axis represents time, and the vertical axis represents voltage. On the horizontal axis, "T1" represents the off period of the power MOSFET. "T2" represents the turn-on period of the power MOSFET. The turn-on period is the period during which the power MOSFET transitions from the off state to the on state. "T3" represents the on period of the power MOSFET. "T4" represents the turn-off period of the power MOSFET. The turn-off period is the period during which the power MOSFET transitions from the on state to the off state.

[0085] In the current waveform shown in Figure 5, the horizontal axis represents time, and the vertical axis represents current. "T1," "T2," "T3," and "T4" are the same as the voltage waveforms.

[0086] In the power loss waveform shown in Figure 5, the horizontal axis represents time, and the vertical axis represents power loss. "T1," "T2," "T3," and "T4" are the same as the voltage waveform.

[0087] During the power MOSFET's off period T1, 0V is applied to the source electrode, while the power supply voltage (e.g., 600V) is applied to the drain electrode. Therefore, the voltage between the source and drain electrodes is the power supply voltage.

[0088] During the off-period T1, the power MOSFET is in the off state. Therefore, almost no current flows through the power MOSFET. In other words, only a tiny leakage current flows through the power MOSFET.

[0089] As mentioned above, during the off period T1, the current flowing through the power MOSFET is minute. Therefore, the power loss, which is expressed as the product of voltage and current, becomes very small. Note that the power loss during the off period T1 is sometimes called "off-loss".

[0090] During the power MOSFET's ON period T3, the voltage applied to the source electrode and the voltage applied to the drain electrode are almost the same. Therefore, the voltage between the source and drain electrodes is a very small ON voltage.

[0091] During the ON period T3, the power MOSFET is in the ON state. Therefore, the rated current flows through the power MOSFET.

[0092] As mentioned above, during the ON period T3, the voltage between the source and drain electrodes of the power MOSFET is very small. Therefore, the power loss, which is expressed as the product of voltage and current, is very small. Note that the power loss during the ON period T3 is sometimes called "ON loss".

[0093] During the power MOSFET's turn-on period T2, the power MOSFET transitions from the off state to the on state. Therefore, the voltage between the source and drain electrodes gradually decreases from the power supply voltage, eventually reaching a very small on-voltage. Also, the current flowing through the power MOSFET increases from a very small leakage current to the rated current.

[0094] Here, consider a configuration in which a high-side MOSFET and a low-side MOSFET are connected in series, such as the DC / DC converter shown in Figure 1 or the inverter shown in Figure 3. For example, in Figure 3, "30H" represents the high-side MOSFET, and "30L" represents the low-side MOSFET. In this case, during the turn-on period T2 of the power MOSFET (high-side MOSFET 30H), the power MOSFET (low-side MOSFET 30L) is turned off. At this time, there is a mode in which a freewheeling current flows through the body diode of the low-side MOSFET 30L that is turned off. That is, a recovery current flows through the body diode of the low-side MOSFET 30L. In other words, during the turn-on period T2 of the power MOSFET (high-side MOSFET 30H), a recovery current flows through the body diode of the low-side MOSFET 30L that is turned off. Therefore, as shown in the current waveform, during the turn-on period T2, the recovery current flowing through the low-side MOSFET 30L is superimposed on the rated current flowing through the power MOSFET (high-side MOSFET 30H). The recovery current flows until the sweep of electrons and holes is complete. The time from the start to the end of electron and hole sweeping is called the reverse recovery time trr. Therefore, the turn-on period T2 is rate-limited by the reverse recovery time trr.

[0095] Thus, during the turn-on period T2, the voltage and current increase. Therefore, the power loss during the turn-on period T2 is large. The turn-on period T2 is the period during which the power MOSFET performs switching operations. Therefore, the power loss during the turn-on period T2 is the "switching loss". The switching loss during the turn-on period T2 is larger than the off-loss and on-loss. In particular, during the turn-on period T2, recovery losses due to the recovery current of the body diode are added. Also, the turn-on period T2 is lengthened by the reverse recovery time trr. Therefore, the switching loss during the turn-on period T2 is very large.

[0096] During the power MOSFET's turn-off period T4, the power MOSFET (high-side MOSFET 30H) transitions from the ON state to the OFF state. As a result, the voltage between the source and drain electrodes gradually increases from a very small ON voltage to the power supply voltage. Also, the current flowing through the power MOSFET (high-side MOSFET 30H) decreases from the rated current to a very small leakage current.

[0097] Here, during the turn-off period T4 of the power MOSFET (high-side MOSFET 30H), the low-side MOSFET 30L is turned on. At this time, there is a mode in which a freewheeling current flows through the body diode of the high-side MOSFET 30H that is being turned off. In other words, a recovery current flows through the body diode of the high-side MOSFET 30H. To put it another way, during the turn-off period T4 of the power MOSFET (high-side MOSFET 30H), a recovery current flows through the body diode of the high-side MOSFET 30H that is being turned off. Therefore, during the turn-off period T4 of the high-side MOSFET 30H, the recovery current flowing through the high-side MOSFET 30H is superimposed on the rated current flowing through the low-side MOSFET 30L.

[0098] However, Figure 5 shows the waveform of the power MOSFET (high-side MOSFET 30H). In other words, Figure 5 does not show the waveform of the low-side MOSFET 30L. Therefore, it is not shown that during the turn-off period T4 of the high-side MOSFET 30H, the recovery current flowing through the high-side MOSFET 30H is superimposed on the rated current flowing through the low-side MOSFET 30L. From the above, for example, in the DC / DC converter shown in Figure 1 or the inverter shown in Figure 3, the switching loss is large due to the recovery loss generated in the body diode, resulting in a large power loss.

[0099] In particular, as the switching frequency increases, the number of switching losses that occur per unit time increases, resulting in a significant increase in switching losses.

[0100] Therefore, it is desirable to reduce the recovery loss that occurs in the body diode.

[0101] Therefore, the technical concept of this disclosure will be explained below.

[0102] <Basic philosophy> The fundamental idea is to shorten the carrier lifetime within the epitaxial layer. This accelerates the extinction of carriers within the epitaxial layer. As a result, the number of carriers swept out of the epitaxial layer can be reduced. Therefore, the recovery current can be reduced. In addition, the reverse recovery time, which is the time required for carrier sweeping, can be shortened.

[0103] Thus, according to the basic concept, recovery losses can be reduced by reducing the recovery current and shortening the reverse recovery time. Therefore, recovery losses, which are part of the switching losses, can be reduced during the power MOSFET's turn-on time. As a result, according to the basic concept, switching losses during the turn-on period can be reduced.

[0104] To shorten the carrier lifetime within an epitaxial layer, for example, this can be achieved by forming numerous recombination centers within the epitaxial layer that induce electron-hole recombination. An epitaxial layer is a layer composed of silicon carbide. In this case, carbon vacancies act as recombination centers. Therefore, by forming numerous carbon vacancies within the epitaxial layer, electron-hole recombination within the epitaxial layer is promoted. As a result, according to the basic concept, the carrier lifetime within the epitaxial layer can be shortened.

[0105] To form a large number of carbon vacancies within an epitaxial layer, for example, this can be achieved by adjusting the growth conditions in the epitaxial growth method. Specifically, the balance between the carbon and silicon sources and the heating conditions are adjusted. Carbon vacancies are more easily formed by adopting a balance between the carbon and silicon sources such that the amount of carbon is less than the stoichiometric ratio. Furthermore, silicon carbide crystals containing carbon vacancies have higher entropy (disorder) than silicon carbide crystals without carbon vacancies. In this regard, higher temperatures make it easier to realize a structure with higher entropy. Therefore, increasing the heating temperature in the epitaxial growth method makes it easier to form an epitaxial layer containing a large number of carbon vacancies.

[0106] The following describes embodiments that embody the basic concept.

[0107] <Embodiment 1> <<Semiconductor Wafer Configuration>> Figure 6 is a plan view showing the semiconductor wafer WF in Embodiment 1.

[0108] The planar shape of the semiconductor wafer (WF) is approximately circular. The planar size of the semiconductor wafer (WF) is, for example, 4 inches (approximately 100 mm) or larger in diameter. From the viewpoint of mass production of semiconductor devices, the planar size of the semiconductor wafer (WF) is preferably 145 mm or larger in diameter, and more preferably 195 mm in diameter. In particular, the semiconductor wafer (WF) of Embodiment 1 has a planar size of 6 inches (approximately 150 mm) in diameter.

[0109] In Figure 6, the region EE located within a length L2 from the outer edge of the semiconductor wafer WF is called the edge exclusion region. Region EE is the region that includes the beveled portion. Region RA is the region enclosed by region EE. Region RA is the internal region enclosed by a circle with a diameter L1.

[0110] Figure 7 is a cross-sectional view showing a semiconductor wafer (WF) in Embodiment 1.

[0111] In Figure 7, the semiconductor wafer WF has a silicon carbide substrate 1 and an epitaxial layer 13. The silicon carbide substrate 1 has a 4H-SiC crystal structure. The silicon carbide substrate 1 contains, for example, an n-type impurity such as nitrogen (N). That is, in Embodiment 1, the silicon carbide substrate 1 is an n-type silicon carbide substrate. However, the technical concept of this disclosure is not limited to this, and can also be applied to semiconductor devices using a p-type silicon carbide substrate 1. That is, the technical concept of this disclosure can be broadly applied to semiconductor devices with opposite conductivity types. In this regard, this specification will describe the invention assuming that the silicon carbide substrate 1 is an n-type silicon carbide substrate.

[0112] The nitrogen concentration introduced into the silicon carbide substrate 1 is 1 × 10⁻⁶. 19 cm -3 The thickness of the silicon carbide substrate 1 is, for example, between 50 μm and 500 μm. A typical example of the thickness of the silicon carbide substrate 1 is approximately 350 μm.

[0113] The epitaxial layer 13 is formed on the silicon carbide substrate 1. The epitaxial layer 13 is a layer using silicon carbide as a semiconductor material. In Embodiment 1, the epitaxial layer 13 is an n-type semiconductor layer into which n-type impurities such as nitrogen have been introduced. In Embodiment 1, a large number of carbon vacancies are formed within the epitaxial layer 13. The carbon vacancies function as recombination centers for electrons and holes.

[0114] The epitaxial layer 13 has a lower impurity concentration than the silicon carbide substrate 1. The impurity concentration of the epitaxial layer 13 is, for example, 1 × 10⁻⁶ 15 cm -3 The above 5 x 10 18 cm -3 The following is a typical example of the impurity concentration in the epitaxial layer 13: 1 × 10⁻⁶ 16 cm -3The thickness of the epitaxial layer 13 is, for example, between 10 μm and 150 μm. A typical example of the thickness of the epitaxial layer 13 is about 10 μm. The withstand voltage of the semiconductor device in the off state is determined by the epitaxial layer 13. A typical specification for a semiconductor device is a withstand voltage of 1.2 kV.

[0115] The epitaxial layer 13 is composed of, for example, a buffer layer 2 and a drift layer 3. The buffer layer 2 is formed on the silicon carbide substrate 1. The drift layer 3 is formed on the buffer layer 2. The drift layer 3 has a lower impurity concentration than the buffer layer 2.

[0116] <<Manufacturing Method for Semiconductor Wafers>> Next, the method for manufacturing a semiconductor wafer (WF) in Embodiment 1 will be described.

[0117] A silicon carbide substrate 1 is prepared. The silicon carbide substrate 1 is, for example, an n-type substrate having a 4H-SiC crystal structure. n-type impurities are introduced into the silicon carbide substrate 1. The n-type impurities are, for example, nitrogen. The nitrogen impurity concentration is, for example, 5 × 10⁻⁶ 18 cm -3 The above 2 x 10 19 cm -3 The following applies: The silicon carbide substrate 1 has a silicon side (Si side) and a carbon side (C side), but the upper surface of the silicon carbide substrate 1 may be either the silicon side or the carbon side. In Embodiment 1, the upper surface of the silicon carbide substrate 1 is the silicon side.

[0118] Next, an epitaxial layer 13 is formed on the silicon carbide substrate 1. The epitaxial layer 13 is composed of, for example, a buffer layer 2 formed on the silicon carbide substrate 1 and a drift layer 3 formed on the buffer layer 2. The buffer layer 2 and the drift layer 3 can be formed, for example, by using an epitaxial growth method.

[0119] As described above, in Embodiment 1, the upper surface of the silicon carbide substrate 1 is a silicon surface, and therefore the epitaxial layer 13 is formed on the silicon surface.

[0120] The growth conditions in the epitaxial growth method are determined based on the following guidelines. Specifically, the guidelines include (1) and (2) below: (1) A balance between the carbon source and silicon source is adopted such that the amount of carbon is less than the stoichiometric ratio, so that carbon vacancies are easily formed in the silicon carbide crystal. (2) A high entropy state is achieved by increasing the heating temperature in the epitaxial growth method, so that carbon vacancies are easily formed in the silicon carbide crystal. This makes it possible to form an epitaxial layer 13 having a large number of carbon vacancies.

[0121] Each of the buffer layer 2 and drift layer 3 contains, for example, nitrogen, an n-type impurity. The nitrogen impurity concentration in drift layer 3 is lower than that in buffer layer 2. The impurity concentration in drift layer 3 depends on the device rating. For example, the impurity concentration in drift layer 3 is 1 × 10⁻⁶. 14 cm -3 The above 1 x 10 17 cm -3 The thickness of the drift layer 3 is, for example, approximately 10 μm to 150 μm. In this way, the semiconductor wafer WF in Embodiment 1 can be manufactured.

[0122] An example of specific manufacturing conditions for epitaxial layers based on the guidelines mentioned above will be explained. The epitaxial layer consists of a buffer layer and a drift layer. The buffer layer and the drift layer have different concentrations of dopant (nitrogen) impurities, and are basically formed continuously using the same epitaxial deposition apparatus.

[0123] The epitaxial layer is the layer used for device formation. In other words, the surface of the epitaxial layer is the surface used for device formation. Note that the layer used for device formation is the layer that has not undergone the "heat treatment at a temperature of 1700 degrees Celsius or higher" or the "irradiation treatment with electron beams, positron beams, or helium ions" described later. The surface used for device formation is the surface that has not undergone the "heat treatment at a temperature of 1700 degrees Celsius or higher" or the "irradiation treatment with electron beams, positron beams, or helium ions" described later.

[0124] The manufacturing conditions for the epitaxial growth method are as follows: (1) The ratio of carbon to silicon (C / Si ratio) is greater than 1.0 and less than or equal to 1.7. (2) The growth temperature is between 1550 degrees Celsius and 1650 degrees Celsius. (3) The pressure inside the chamber during growth is 1 × 10 4 Pa or higher, 4 x 10 4 It is below Pa. (4) The carrier gas is a mixture of hydrogen and hydrogen chloride (HCl). (5) The growth rate is 40 μm / hour. (6) The nitrogen concentration in the drift layer is 5 × 10 15 cm -3 That's all for 2 x 10 16 cm -3 The following applies: (7) The nitrogen concentration in the buffer layer is 5 × 10 17 cm -3 That's all for 8 x 10 18 cm -3 The following applies:

[0125] Under these manufacturing conditions, numerous carbon vacancies that serve as recombination centers can be formed. As a result, the carrier lifetime can be shortened.

[0126] The semiconductor wafers manufactured in Embodiment 1 are sold to device manufacturers. Device manufacturers then use methods such as ion implantation to introduce dopants into the semiconductor wafers in order to manufacture semiconductor devices. Because ion implantation damages the crystal, a "heat treatment at a temperature of 1700 degrees Celsius or higher" is performed to restore the crystal. On the other hand, by adopting Embodiment 1, semiconductor wafer manufacturers do not need to perform a "heat treatment at a temperature of 1700 degrees Celsius or higher".

[0127] Device manufacturers sometimes perform "electron beam, positron beam, or helium ion irradiation treatment" on semiconductor wafers to shorten the carrier lifetime. In this regard, the semiconductor wafer manufactured in Embodiment 1 has a sufficiently short carrier lifetime. If the device manufacturer performs "electron beam, positron beam, or helium ion irradiation treatment," the carrier lifetime can be shortened even further.

[0128] In Embodiment 1, semiconductor wafers with a short carrier lifetime can be manufactured without performing "heat treatment at a temperature of 1700 degrees Celsius or higher" or "irradiation treatment with electron beams, positron beams, or helium ions." In other words, according to Embodiment 1, semiconductor wafer manufacturers do not need to perform "heat treatment at a temperature of 1700 degrees Celsius or higher" or "irradiation treatment with electron beams, positron beams, or helium ions" in order to shorten the carrier lifetime. Therefore, semiconductor wafer manufacturers can simplify the process of manufacturing semiconductor wafers.

[0129] The advantage of Embodiment 1 is that the carrier lifetime can be sufficiently shortened without performing "heat treatment at temperatures of 1700 degrees Celsius or higher" or "irradiation treatment with electron beams, positron beams, or helium ions." As a result, device manufacturers can further shorten the carrier lifetime by performing "irradiation treatment with electron beams, positron beams, or helium ions." Alternatively, if the carrier lifetime achieved in Embodiment 1 is sufficient, device manufacturers can avoid performing "irradiation treatment with electron beams, positron beams, or helium ions." This simplifies the semiconductor device manufacturing process.

[0130] The epitaxial growth method under the manufacturing conditions described above not only shortens the carrier lifetime but also reduces the variation in carrier lifetime on semiconductor wafers.

[0131] This point is explained below. In the epitaxial growth method, a raw material gas and a carrier gas are used. The raw material gas includes a carbon source gas and a silicon source gas. The carbon source gas is, for example, propane. The silicon source gas is, for example, silane. In Embodiment 1, the carrier gas includes hydrogen and hydrogen chloride.

[0132] To reduce variations in carrier lifetime, it is desirable that the "C / Si ratio" of the supplied raw material gas be as uniform as possible across the entire silicon carbide substrate. In Embodiment 1, fluctuations in the "C / Si ratio" are suppressed.

[0133] In this regard, in Embodiment 1, the carrier gas contains hydrogen chloride in addition to hydrogen. Hydrogen chloride has the function of suppressing the accumulation of silicon in the piping used to supply the raw material gas. In other words, hydrogen chloride has the function of suppressing the decomposition of the silicon source gas. Therefore, by including hydrogen chloride in the carrier gas, the silicon source gas is supplied sufficiently to the semiconductor wafer without being decomposed, rather than just to the piping. In other words, because the carrier gas contains hydrogen chloride, the silicon source gas is less likely to be decomposed and consumed in the piping upstream of the semiconductor wafer. As a result, the C / Si ratio becomes smaller and less prone to fluctuation throughout the semiconductor wafer. As a result, according to Embodiment 1, carbon vacancies can be easily generated, making the carrier lifetime shorter and more uniform.

[0134] Figure 8 illustrates how including hydrogen chloride in the carrier gas can shorten the carrier lifetime and reduce variability.

[0135] Figure 8(a) is a graph showing the relationship between gas flow and reactant concentration. The reactants are carbon reactants (C reactants) and silicon reactants (Si reactants). The gas flow is from the gas piping → the center of the semiconductor wafer → the outer edge (right edge) and the outer edge (left edge) of the semiconductor wafer. Note that the outer edge (left edge) of the semiconductor wafer is omitted in Figure 8.

[0136] In Figure 8(a), graph (1) shows the relationship between the concentration of Si reactants and the gas flow when the carrier gas does not contain hydrogen chloride. Graph (2) shows the relationship between the concentration of Si reactants and the gas flow when the carrier gas contains hydrogen chloride. Graph (3) shows the relationship between the concentration of C reactants and the gas flow.

[0137] In all three graphs (1), (2), and (3), the concentration tends to decrease as the gas flows from upstream to downstream. This is because the gas decomposes as it flows from upstream to downstream. In particular, the decrease in the concentration of Si reactive species when the carrier gas does not contain hydrogen chloride (graph (1)) is greater than the decrease in the concentration of Si reactive species when the carrier gas contains hydrogen chloride (graph (2)). This is because the decomposition of the silicon source gas is suppressed when the carrier gas contains hydrogen chloride.

[0138] Figure 8(b) is a graph showing the relationship between gas flow and the "C / Si ratio". In Figure 8(b), graph (1) shows the relationship between the "C / Si ratio" and gas flow when the carrier gas does not contain hydrogen chloride. Graph (2) shows the relationship between the "C / Si ratio" and gas flow when the carrier gas contains hydrogen chloride. As can be seen from Figure 8(b), the change in the "C / Si ratio" when the carrier gas does not contain hydrogen chloride (graph (1)) is greater than the change in the "C / Si ratio" when the carrier gas contains hydrogen chloride (graph (2)).

[0139] Figure 8(c) is a graph showing the relationship between gas flow and the amount of carbon vacancies. In Figure 8(c), graph (1) shows the relationship between the amount of carbon vacancies and gas flow when the carrier gas does not contain hydrogen chloride. Graph (2) shows the relationship between the amount of carbon vacancies and gas flow when the carrier gas contains hydrogen chloride.

[0140] As can be seen from Figure 8(c), the amount of carbon vacancies when the carrier gas does not contain hydrogen chloride (Graph (1)) is smaller than the amount of carbon vacancies when the carrier gas contains hydrogen chloride (Graph (2)). Furthermore, the change in the amount of carbon vacancies when the carrier gas does not contain hydrogen chloride (Graph (1)) is larger than the change in the amount of carbon vacancies when the carrier gas contains hydrogen chloride (Graph (2)).

[0141] Figure 8(d) is a graph showing the relationship between gas flow and carrier lifetime. Graph (1) shows the relationship between carrier lifetime and gas flow when the carrier gas does not contain hydrogen chloride. Graph (2) shows the relationship between carrier lifetime and gas flow when the carrier gas contains hydrogen chloride.

[0142] As can be seen from Figure 8(d), the carrier lifetime when the carrier gas does not contain hydrogen chloride (Graph (1)) is greater than the carrier lifetime when the carrier gas contains hydrogen chloride (Graph (2)). Furthermore, the change in carrier lifetime when the carrier gas does not contain hydrogen chloride (Graph (1)) is greater than the change in carrier lifetime when the carrier gas contains hydrogen chloride (Graph (2)).

[0143] From the above, it can be seen that using a mixed gas of hydrogen and hydrogen chloride as the carrier gas can shorten the carrier lifetime and reduce variability.

[0144] Furthermore, the embodiment employs a film deposition apparatus suitable for reducing variations in carrier lifetime. The film deposition apparatus is a device that forms an epitaxial layer on the upper surface of a silicon carbide substrate. Specifically, in Embodiment 1, a "vertical single-wafer film deposition apparatus" is used.

[0145] Figure 9 shows a schematic configuration of the film deposition apparatus SA1 in Embodiment 1. The film deposition apparatus SA1 is a "vertical single-wafer film deposition apparatus". The film deposition apparatus SA1 is a film deposition apparatus that flows the raw material gas in the vertical direction. The film deposition apparatus SA1 is a film deposition apparatus that processes semiconductor wafers WF one at a time. The film deposition apparatus SA1 has a housing 50, a rotating susceptor 51, a heater 52, and a fixed susceptor 53.

[0146] The housing 50 is cylindrical. The rotating susceptor 51 is configured to hold the semiconductor wafer WF. The rotating susceptor 51 is configured to rotate. When the rotating susceptor 51 rotates, the semiconductor wafer WF also rotates on its central axis. The heater 52 is embedded inside the fixed susceptor 53. The heater 52 is made of a resistor. The heater 52 heats the semiconductor wafer WF using Joule heat generated by passing an electric current through the resistor. The heater 52 has an inner heater 52A and an outer heater 52B. The outer heater 52B has a concentric circular planar shape. The inner heater 52A is arranged within the concentric circle. The inner heater 52A and the outer heater 52B can each be controlled independently. Therefore, by appropriately controlling the inner heater 52A and the outer heater 52B, the in-plane temperature uniformity of the semiconductor wafer WF can be improved. As a result, the uniformity of the "C / Si ratio" on the upper surface of the semiconductor wafer (WF) can be improved.

[0147] The raw material gas flows in the direction of arrow GF1 → arrow GF2 → arrow GF3. Arrow GF1 indicates a flow perpendicular to the top surface of the semiconductor wafer WF. Arrow GF1 indicates a flow descending toward the semiconductor wafer WF. Arrow GF2 indicates a flow parallel to the top surface of the semiconductor wafer WF. Arrow GF2 indicates a flow from the center of the semiconductor wafer WF toward the outer edge. Arrow GF3 indicates a flow parallel to the side surface of the rotating susceptor 51. Arrow GF3 indicates a downward flow along the side surface of the rotating susceptor 51.

[0148] Figure 10 shows a schematic configuration of the film deposition apparatus SA2 in the example under consideration. Film deposition apparatus SA2 is a "horizontal batch-type film deposition apparatus". Film deposition apparatus SA2 is a film deposition apparatus that flows the raw material gas in a horizontal direction. Film deposition apparatus SA2 is a film deposition apparatus that processes multiple semiconductor wafers WF simultaneously. Multiple semiconductor wafers WF refer to, for example, six semiconductor wafers WF. Figure 10 shows semiconductor wafers WF1, WF2, WF3, WF4, WF5, and WF6.

[0149] The film deposition apparatus SA2 comprises a housing 60, a susceptor 61, and a coil 62. The susceptor 61 is located inside the housing 60. Six semiconductor wafers WF are placed on the susceptor 61. The susceptor 61 is configured to rotate. When the susceptor 61 rotates, the six semiconductor wafers WF revolve around it. However, in the film deposition apparatus SA2, even when the susceptor 61 rotates, each of the six semiconductor wafers WF does not rotate on its own axis. The coil 62 is located above the susceptor 61. High-frequency power is supplied to the coil 62. As a result, the coil 62 heats the six semiconductor wafers WF placed on the susceptor 61 by induction heating caused by the supplied high-frequency power.

[0150] The raw material gas flows along the direction of arrow GFA → arrow GFB. Arrows GFA and GFB each indicate a flow parallel to the top surface of the semiconductor wafer WF. The raw material gas is supplied along the direction of arrow GFA. On the other hand, the raw material gas is discharged along the direction of arrow GFB. Let's focus on semiconductor wafer WF1. In Figure 10, the susceptor 61 is rotated clockwise. For example, the "C / Si ratio" of the raw material gas supplied to semiconductor wafer WF1 varies greatly depending on whether semiconductor wafer WF1 is at the "9 o'clock position" or the "3 o'clock position". This is because a larger proportion of the raw material gas supplied at the "3 o'clock position" is consumed for the growth of the epitaxial layer than the raw material gas supplied at the "9 o'clock position". In other words, when the proportion consumed for the growth of the epitaxial layer changes, the "C / Si ratio" of the raw material gas changes. Therefore, in the SA2 film deposition apparatus, when focusing on a single semiconductor wafer WF, the "C / Si ratio" of the supplied raw material gas fluctuates significantly depending on its position during rotation (orbit). As a result, when focusing on a single semiconductor wafer WF in the SA2 film deposition apparatus, the variation in carrier lifetime becomes large.

[0151] In contrast, in the film deposition apparatus SA1, even when the rotating susceptor 51 is rotated, the semiconductor wafer WF rotates on its own axis but does not revolve. Therefore, in the film deposition apparatus SA1, even when the rotating susceptor 51 is rotated, the fluctuation in the "C / Si ratio" of the raw material gas is smaller than in the film deposition apparatus SA2.

[0152] Furthermore, the film deposition apparatus SA1 heats one semiconductor wafer WF by "resistive heating" using heater 52. On the other hand, the film deposition apparatus SA2 heats multiple semiconductor wafers WF by "induction heating" using coil 62. The configuration of heating one semiconductor wafer WF by "resistive heating" can achieve a more uniform temperature distribution within the semiconductor wafer WF than the configuration of heating multiple semiconductor wafers WF by "induction heating".

[0153] In particular, the film deposition apparatus SA1 has an independently controllable inner heater 52A and an outer heater 52B. Therefore, the film deposition apparatus SA1 allows for fine-grained control to improve in-plane temperature uniformity. Consequently, from this point of view as well, the film deposition apparatus SA1 can improve the in-plane temperature uniformity of semiconductor wafers WF compared to the film deposition apparatus SA2.

[0154] Based on the above, Embodiment 1, which employs the film deposition apparatus SA1, can reduce variations in carrier lifetime compared to the case where the film deposition apparatus SA2 is employed.

[0155] In the film deposition apparatus SA1 shown in Figure 9, as indicated by arrow GF2, the raw material gas flows along the top surface of the semiconductor wafer WF, from the center to the outer edge of the wafer WF. Therefore, a larger proportion of the raw material gas flowing along the outer edge of the semiconductor wafer WF is consumed for the growth of the epitaxial layer than the raw material gas supplied to the center of the wafer WF. Consequently, the "C / Si ratio" of the raw material gas supplied to the outer edge of the semiconductor wafer WF1 varies significantly from the "C / Si ratio" of the raw material gas supplied to the center. Therefore, it is desirable not to use the region near the outer edge of the semiconductor wafer WF (edge ​​exclusion region) as the product area. This can reduce variations in carrier lifetime.

[0156] <<First Feature Point in Embodiment 1>> The first feature point in Embodiment 1 embodies the basic idea of shortening the carrier lifetime in the epitaxial layer 13. Specifically, the first feature point is that the carrier lifetime distribution including the carrier lifetimes in the epitaxial layer 13 measured at a plurality of measurement points has the following characteristics.

[0157] (1) When the average value of the carrier lifetime is τ m τ m ≦0.4 μs. (2) When the standard deviation of the carrier lifetime distribution is σ τ σ τ ≦0.5τ m is satisfied.

[0158] Hereinafter, the verification result that the above-described first feature point is realized when manufacturing the semiconductor wafer WF in this Embodiment 1 will be described.

[0159] The manufacturing of the sample of the semiconductor wafer WF is carried out based on the above-described guidelines. The planar size of the sample is 6 inches in diameter (about 150 mm in diameter). In the sample, the concentration of nitrogen introduced into the epitaxial layer is about 6.2×10 15 cm -3 .

[0160] Measure the carrier lifetime τ in the epitaxial layer at a plurality of measurement points in the sample. For the measurement of τ, the μ-PCD method (Microwave PhotoConductivity Decay) is used. The μ-PCD method is the method shown below. That is, a pulsed laser beam is irradiated from the upper surface of the epitaxial layer. In this case, microwaves are reflected according to the concentrations of electrons and holes in the epitaxial layer. For example, when the concentrations of electrons and holes in the epitaxial layer are high, the reflectivity of the microwaves becomes high. On the other hand, when the concentrations of electrons and holes in the epitaxial layer are low, the reflectivity of the microwaves becomes low.

[0161] Therefore, when electron-hole recombination occurs within the epitaxial layer, the concentrations of electrons and holes decrease. As a result, the microwave reflectivity decreases. Thus, by measuring the microwave reflectivity over time using the μ-PCD method, it is possible to indirectly measure the time τ until the recombination annihilates the electrons and holes.

[0162] For example, the LTA-2000 instrument manufactured by Kobelco Scientific Instruments is used to measure τ. A YAG laser with a wavelength of 266 nm is used for the laser beam. The sample temperature during τ measurement is 25 degrees Celsius. The microwave frequency is 26 GHz.

[0163] Figure 11 shows the carrier lifetime distribution obtained from carrier lifetime τ measured at multiple measurement points within the epitaxial layer. This carrier lifetime distribution is based on the measurement points described below. Specifically, the length L2 of region EE shown in Figure 6 is set to 2 mm. The carrier lifetime distribution is then obtained using τ measured at measurement points within region RA (length L1 of 146 mm), excluding region EE.

[0164] Furthermore, the career lifetime distribution shown in Figure 11 exhibits a concentric distribution pattern. Such a concentric distribution pattern makes it easier to reduce variability in career lifetimes. In other words, from the perspective of reducing variability in career lifetimes, a concentric distribution pattern is desirable for the career lifetime distribution.

[0165] Figure 12 shows the Weibull distribution based on Figure 11. In Figure 12, the horizontal axis represents the career lifetime, and the vertical axis represents the cumulative probability.

[0166] Analysis of Figures 11 and 12 yields the following results. Minimum value of carrier lifetime τ: 0.05 μs Maximum carrier lifetime τ: 0.68 μs The average value τ of the carrier lifetime τ m : 0.16 μs The standard deviation σ of the carrier lifetime distribution τ : 0.052 μs (σ τ ≤ 0.5τ m ) The median value τ of the carrier lifetime τ c : 0.18 μs (τ c ≤ 1.5τ m ) From this result, the sample satisfies the first characteristic point. That is, it is verified that the first characteristic point can be realized.

[0167] Also, in the Weibull distribution, the carrier lifetime (0.1% percentile) at the point where the cumulative probability reaches 0.1% was 0.05 μs or more. The carrier lifetime (99.9% percentile) at the point where the cumulative probability reaches 99.9% in the Weibull distribution was 0.68 μs or less. As a result, the slope between the two points is (0.999 - 0.001) / (0.68 - 0.05) = 1.58 μs -1 or more. Since the variation in the carrier lifetime in the semiconductor wafer can be reduced, for the Weibull distribution, it is preferable that the slope between the 0.1% percentile and the 99.9% percentile is 1.5 μs -1 or more.

[0168] Next, the technical significance of the first characteristic point will be explained.

[0169] "When the average value is τ m and τ m ≤ 0.4 μs", by realizing this, the carrier lifetime in the epitaxial layer of the semiconductor wafer can be shortened. Thereby, the disappearance of carriers in the epitaxial layer can be promoted.

[0170] "When the standard deviation is σ τ and σ τ ≤ 0.5τ mBy achieving this, the variability of carrier lifetimes within the epitaxial layer can be reduced. In other words, the uniformity of carrier lifetimes within the epitaxial layer can be improved.

[0171] For example, as shown in Figure 1, a step-down DC / DC converter uses two power MOSFETs: a high-side MOSFET 10 and a low-side MOSFET 20. Similarly, as shown in Figure 3, a three-phase inverter uses six power MOSFETs. Generally, it is desirable to minimize characteristic variations among the multiple power MOSFETs that make up a DC / DC converter or inverter. Therefore, multiple semiconductor chips obtained from a single semiconductor wafer are often used.

[0172] However, even within a single semiconductor wafer, large variations in carrier lifetime within the epitaxial layer can lead to variations in switching loss. For example, if a power MOSFET with a long carrier lifetime is used in the high-side MOSFET 30H, the switching loss of the low-side MOSFET 30L will increase. Similarly, if a power MOSFET with a long carrier lifetime is used in the low-side MOSFET 30L, the switching loss of the high-side MOSFET 30H will increase.

[0173] Higher switching losses mean higher power losses. Higher power losses mean higher heat generation. Therefore, the temperature of power MOSFETs connected in series with power MOSFETs that have a long carrier lifetime may become abnormally high. As a result, the probability of failure of the power MOSFETs with abnormally high temperatures increases. For this reason, the cooling performance of the cooling mechanism needs to be improved. This, however, leads to the cooling mechanism becoming larger.

[0174] In this regard, according to the first feature, variations in carrier lifetime within the epitaxial layer can be reduced on a single semiconductor wafer. As a result, according to Embodiment 1, variations in switching losses can be reduced in multiple power MOSFETs that constitute each of the DC / DC converters or inverters. Consequently, in Embodiment 1, it is possible to suppress the abnormally high temperature of only a specific power MOSFET. Therefore, there is no need to increase the cooling performance of the cooling mechanism more than necessary. Thus, according to Embodiment 1, miniaturization of the cooling mechanism can be achieved.

[0175] <<Second characteristic feature in Embodiment 1>> The second characteristic feature of Embodiment 1 is that it embodies the fundamental idea of ​​shortening the carrier lifetime within the epitaxial layer 13. Specifically, the second characteristic feature is that the carrier lifetime distribution, which includes the carrier lifetimes within the epitaxial layer 13 measured at multiple measurement points, has the following characteristics.

[0176] (1) The average value of career lifetime is τ m In that case, τ m The interval is ≤0.2μs. (2) The standard deviation of the career lifetime distribution is σ τ In that case, σ τ ≤0.05τ m That is the case.

[0177] The following describes the verification results showing that the second feature point described above is realized when the semiconductor wafer WF in this embodiment 1 is manufactured. The sample used to verify the second feature point is the same as the sample used to verify the first feature point. However, as will be described later, the τ that constitutes the carrier lifetime distribution is different.

[0178] Figure 13 shows the carrier lifetime distribution obtained from carrier lifetimes τ within the epitaxial layer measured at multiple measurement points. This carrier lifetime distribution is based on the measurement points described below. Specifically, the L2 of region EE shown in Figure 6 is set to 25 mm. The carrier lifetime distribution is obtained using τ measured at measurement points within region RA (length L1 of 100 mm), excluding region EE. This is where it differs from the verification of the first feature point.

[0179] Furthermore, the career lifetime distribution shown in Figure 13 exhibits a radial distribution pattern when viewed from the center. This radial distribution pattern, when viewed from the center, helps to reduce the variability of career lifetimes. In other words, from the perspective of reducing the variability of career lifetimes, a radial distribution pattern when viewed from the center is desirable for the career lifetime distribution.

[0180] Figure 14 shows the Weibull distribution based on Figure 13. In Figure 14, the horizontal axis represents the career lifetime, and the vertical axis represents the cumulative probability. Figure 14 has a steeper slope compared to Figure 12. In the Weibull distribution, a steeper slope indicates smaller variability.

[0181] In the Weibull distribution, the carrier lifetime (0.1% percentile) at the point where the cumulative probability reaches 0.1% was 0.15 μs or greater. The carrier lifetime (99.9% percentile) at the point where the cumulative probability reaches 99.9% was 0.24 μs or less. As a result, the slope between these two points is (0.999 - 0.001) / (0.24 - 0.15) = 11.09 μs. -1 That concludes the explanation. Because the variation in carrier lifetime on semiconductor wafers can be significantly reduced, the slope between the 0.1% percentile and the 99.9% percentile of the Weibull distribution is 11.0 μs. -1 It is even more preferable that the above conditions are met. Therefore, Figure 14 shows less variation in τ than Figure 12.

[0182] Analysis of Figures 13 and 14 yields the following results. Minimum carrier lifetime τ: 0.15 μs Maximum carrier lifetime τ: 0.24 μs Average value of career lifetime τ m :0.196μs Standard deviation σ of the career lifetime distribution τ :0.012μs(σ τ ≤0.5τ m ) Median career lifetime τ c :0.20μs(τ c ≤1.5τ m ) This result confirms that the sample satisfies the second feature point, meaning that the second feature point is achievable.

[0183] Considering the career lifetime distribution in Figure 11 that satisfies the first feature point and the career lifetime distribution in Figure 13 that satisfies the second feature point, the following insights can be obtained.

[0184] The semiconductor wafer of Embodiment 1 exhibits superior uniformity closer to the center of the substrate. In particular, if a semiconductor wafer has a second characteristic point within a radius of 50 mm from the center of the substrate, it is possible to manufacture semiconductor devices using this semiconductor wafer, thereby providing semiconductor devices with reduced performance variations between products.

[0185] <<Third characteristic feature in Embodiment 1>> As mentioned above, it is desirable that the multiple power MOSFETs that make up a DC / DC converter or inverter have small variations in carrier lifetime. Therefore, it is desirable that the variation in carrier lifetime be small on a single semiconductor wafer from which the above-mentioned multiple power MOSFETs are obtained. In this regard, if the first or second feature point is realized, the variation in carrier lifetime can be reduced on a single semiconductor wafer. As a result, the variation in the characteristics of the multiple power MOSFETs can be suppressed. This can improve the performance of the DC / DC converter or inverter.

[0186] Furthermore, it is desirable that there be little variation among the multiple products constituting the DC / DC converter or inverter. This is because it is desirable that the multiple products have uniform performance. In this regard, for example, suppose that the first product among the multiple products uses multiple power MOSFETs obtained from the first semiconductor wafer. Also, suppose that the second product among the multiple products uses multiple power MOSFETs obtained from the second semiconductor wafer. In this case, in order to make the performance of the first product and the second product uniform, it is desirable to reduce the variation in carrier lifetime between the first product and the second product. In other words, it is desirable that there be little variation in carrier lifetime between the first semiconductor wafer and the second semiconductor wafer. By applying Embodiment 1, it is possible to suppress the variation in carrier lifetime among multiple semiconductor wafers.

[0187] Specifically, the third characteristic feature of Embodiment 1 is that in a semiconductor wafer group including multiple semiconductor wafers, the average value τ of the carrier lifetime of each semiconductor wafer included in the semiconductor wafer group m In a mean distribution that includes elements, the standard deviation is σ st In that case, σ st ≤0.2μs. More specifically, when the semiconductor wafer group consists of 25 semiconductor wafers, σ st The interval is ≤0.1μs.

[0188] This reduces variations in carrier lifetime across semiconductor wafers. Consequently, it reduces performance variations between multiple products.

[0189] <<Fourth characteristic feature in Embodiment 1>> The fourth feature of Embodiment 1 is that it reduces the mean value of carrier lifetime and the standard deviation of the carrier lifetime distribution in a semiconductor wafer with a diameter of 6 inches. In recent years, semiconductor wafers with a planar size of 6 inches or more in diameter have begun to be used. Improving the uniformity of carrier lifetime in semiconductor wafers with a planar size of 6 inches or more in diameter is more difficult than improving the uniformity of carrier lifetime in semiconductor wafers with a planar size of 4 inches in diameter. In this regard, Embodiment 1 achieves to reduce the mean value of carrier lifetime and the standard deviation of the carrier lifetime distribution in a semiconductor wafer with a planar size of 6 inches in diameter. Therefore, Embodiment 1 has great technical significance in that it overcomes a highly difficult challenge.

[0190] <Embodiment 2> <<Configuration of semiconductor device>> Embodiment 2 describes an example of a semiconductor device manufactured using the semiconductor wafer WF of Embodiment 1. The semiconductor device in Embodiment 2 is a semiconductor device that includes a power MOSFET. Specifically, the semiconductor device in Embodiment 2 has basically the same configuration as the semiconductor device 100 shown in Figure 4. The semiconductor device in Embodiment 2 is used in power conversion devices such as DC / DC converters or inverters.

[0191] The semiconductor device in Embodiment 2 is manufactured using the semiconductor wafer WF in Embodiment 1. Therefore, in Embodiment 2, the carrier lifetime distribution, which includes the carrier lifetimes within the epitaxial layer 13 measured at multiple measurement points, has the first or second feature point described above. In other words, in Embodiment 2, the carrier lifetime within the epitaxial layer 13 can be shortened.

[0192] This promotes the extinction of carriers within the epitaxial layer 13. Therefore, according to Embodiment 2, the number of carriers swept out from the epitaxial layer 13 can be reduced. As a result, the recovery current of the body diode, which is parasitic on the power MOSFET, can be reduced. In addition, the reverse recovery time of the body diode can be shortened.

[0193] Thus, according to Embodiment 2, recovery losses can be reduced by reducing the recovery current and shortening the reverse recovery time. As a result, recovery losses, which are part of the switching losses, can be reduced during the turn-on time of the power MOSFET. Consequently, according to Embodiment 2, switching losses during the turn-on period can be reduced.

[0194] <<Manufacturing Method for Semiconductor Devices>> Next, the method for manufacturing a semiconductor device in Embodiment 2 will be described.

[0195] First, prepare the semiconductor wafer WF manufactured in Embodiment 1.

[0196] Next, as shown in Figure 15, p-type wells 5A and 5B, source region 6A and 6B, body contact region 7A and 7B are formed within the drift layer 3, for example, by using photolithography and ion implantation. The thickness of the mask used in photolithography is, for example, about 0.5 μm to 5 μm. The mask material can be a silicon oxide film (hard mask) or a photoresist film.

[0197] Then, after removing the mask using ashing technology, a carbon film is formed on the upper surface of the epitaxial layer 13 and on the lower surface of the silicon carbide substrate 1, respectively. The carbon film can be formed, for example, by using plasma CVD (Chemical Vapor Deposition). The thickness of the carbon film is, for example, about 0.03 μm to 0.05 μm.

[0198] Next, the upper surface of the epitaxial layer 13 and the lower surface of the silicon carbide substrate 1 are covered with a carbon film, and then heat treatment is performed at a temperature of 1500 degrees Celsius or higher for 2 to 3 minutes. This activates the conductive impurities introduced into each layer (each region) within the epitaxial layer 13. After that, the carbon film is removed, for example, by plasma treatment.

[0199] Next, as shown in Figure 4, a gate insulating film 8 and an n-type polysilicon film are sequentially formed on the drift layer 3, and then a mask is formed on the n-type polysilicon film. The gate insulating film 8 can be formed, for example, using a thermal oxidation method. The n-type polysilicon film can be formed, for example, using a CVD method. Next, the n-type polysilicon film is processed by a dry etching method using the mask to form the gate electrode 9. The thickness of the gate insulating film 8 is, for example, about 0.05 μm to 0.15 μm. The thickness of the gate electrode 9 is, for example, about 0.2 μm to 0.5 μm.

[0200] Subsequently, an interlayer insulating film 11 is formed on the drift layer 3 so as to cover the gate electrode 9. The interlayer insulating film 11 can be formed, for example, by using a plasma CVD method.

[0201] Then, by using photolithography and dry etching techniques, a first through-hole TH1 and a second through-hole TH2 are formed in the interlayer insulating film 11. This exposes the source region 6A and the body contact region 7A from the bottom of the first through-hole TH1, and exposes the source region 6B and the body contact region 7B from the bottom of the second through-hole TH2.

[0202] Next, a silicide layer (not shown) is formed at the bottom of the first through-hole TH1 and the second through-hole TH2. Then, a metal film is formed to fill the interior of the first through-hole TH1 and the second through-hole TH2 using a sputtering method. The metal film is composed of a laminated film, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film stacked in sequence. Then, a source electrode 12 made of the metal film is formed using photolithography and etching techniques. The source electrode 12 is electrically connected to the source region 6A and the body contact region 7A. The source electrode 12 is electrically connected to the source region 6B and the body contact region 7B.

[0203] Next, for example, by using a sputtering method, a metal film is formed on the underside of the silicon carbide substrate 1. Then, a laser silicide treatment (heat treatment) is performed to react the metal film with the silicon carbide substrate 1 and form a silicide layer (not shown). After that, a drain electrode 4 is formed on the underside of the silicide layer. The drain electrode 4 can be formed, for example, by a sputtering method. The drain electrode 4 is composed of a laminated film in which a titanium film, a nickel film, and a gold film are stacked in that order from the silicide layer side. The thickness of the drain electrode 4 is, for example, about 0.5 μm to 1 μm.

[0204] As described above, the semiconductor device in Embodiment 2 can be manufactured.

[0205] <<Verification of effectiveness>> Next, we will explain how the power loss of the semiconductor device can be reduced according to Embodiment 2 by using simulation. Note that the power loss referred to here means the total loss, which includes on-loss, off-loss, and switching loss.

[0206] The simulation was conducted under the following conditions: Rated current: 40A On-resistance: R ON= 0.3Ω Off-current: I L = 0.1 μA Table 1 shows the simulation results.

[0207] [Table 1]

[0208] The reverse recovery time (trr) of the body diode in a power MOSFET shows the same trend as the carrier lifetime (τ). That is, as the carrier lifetime decreases, the reverse recovery time also decreases. For example, when τ = 1 μs, trr = 0.07 μs. In contrast, when τ = 0.2 μs, trr = 0.015 μs.

[0209] Assuming a typical DC / DC converter (operating frequency f=100kHz), the on-discharge of one power MOSFET is 60W. In contrast, the off-discharge of one power MOSFET is 30μW. This shows that the off-discharge is more than six orders of magnitude smaller than the on-discharge. On the other hand, the switching discharge of one power MOSFET is large at 84W when τ=1μs. In contrast, the switching discharge of one power MOSFET is large at 18W when τ=0.2μs. Therefore, according to the semiconductor device in Embodiment 2, the power loss of one power MOSFET can be reduced by more than 45% compared to the case where τ=1μs. Thus, the simulation results in Table 1 confirm that the power loss of the semiconductor device can be reduced according to Embodiment 2.

[0210] Furthermore, considering an inverter, the operating frequency of the inverter is approximately f = 5kHz to 20kHz. Therefore, although not as significant as with a DC / DC converter with an operating frequency of f = 100kHz, power loss can still be reduced in an inverter. Specifically, from the simulation results in Table 1, by using the semiconductor device in Embodiment 2 as an inverter, the power loss of one power MOSFET can be reduced by approximately 17% at an operating frequency of 20kHz. Also, at an operating frequency of 5kHz, the power loss of one power MOSFET can be reduced by approximately 5%.

[0211] Inverters are often used at operating frequencies of around 5 kHz. However, in the future, as a noise reduction measure, their use at operating frequencies of around 20 kHz, which are above the human audible frequency, is also being considered. Based on the simulation results in Table 1, the power loss reduction effect of a single power MOSFET is greater when the operating frequency is 20 kHz than when the operating frequency is 5 kHz. Therefore, the semiconductor device in Embodiment 2 has the potential for increased demand in the future. It is particularly excellent in that it has a significant power loss reduction effect in inverters operating at around 20 kHz.

[0212] As described above, reducing power loss allows for a miniaturization of the cooling mechanism (radiator) of the power converter. Furthermore, by aligning the carrier lifetimes of the multiple power MOSFETs constituting the power converter, the amount of heat generated from each power MOSFET is also made uniform. As a result, there is no need for excessive cooling in the cooling mechanism. In other words, according to Embodiment 2, the cooling mechanism can be miniaturized by (1) reducing power loss and (2) making the amount of heat generated uniform. Therefore, according to Embodiment 2, the power converter can be miniaturized.

[0213] <Embodiment 3> <<The necessity of an external diode>> For example, let's focus on the inverter INV shown in Figure 3.

[0214] Let's consider the case where a power MOSFET is used as the switching element 30 that constitutes the inverter INV. A parasitic body diode is formed on the power MOSFET. Therefore, the body diode functions as a freewheeling diode. For this reason, when a power MOSFET is used as the switching element 30, an external diode FWD that would normally be used as a freewheeling diode is unnecessary.

[0215] Now, let's consider the case where an IGBT is used as the switching element 30. An IGBT has a parasitic bipolar transistor. In other words, an IGBT does not have a body diode. Therefore, an IGBT cannot carry the reverse current caused by the motor's inductance. Consequently, when an IGBT is used as the switching element 30, an external diode FWD that functions as a freewheel diode is required. A Schottky barrier diode or a pn junction diode is used as the diode FWD. A Schottky barrier diode is a unipolar device. On the other hand, a pn junction diode is a bipolar device. Therefore, recovery losses occur in a pn junction diode. Thus, when a pn junction diode is used as the diode FWD, the technical concept of this disclosure, which can reduce recovery losses, is useful.

[0216] Embodiment 3 describes a semiconductor device including a pn junction diode as an example of a semiconductor device manufactured using the semiconductor wafer WF in Embodiment 1.

[0217] <<Configuration of semiconductor device>> Figure 16 is a cross-sectional view showing the semiconductor device 200 in Embodiment 3.

[0218] In FIG. 16, the semiconductor device 200 has a silicon carbide substrate 1, a buffer layer 2, a drift layer 3, an epitaxial layer 13, a cathode electrode 21, an anode region 22, an insulating film 23, and an anode electrode 24. The anode region 22 may be formed, for example, either by ion implantation or by an epitaxial layer.

[0219] The anode region 22 is a p-type semiconductor region. For example, aluminum, which is a p-type impurity, is introduced into the anode region 22. The depth of the anode region 22 is about 2 μm. The impurity concentration (concentration of acceptors) of the anode region 22 is, for example, 2×10 18 cm -3 or more and 1×10 20 cm -3 or less. The anode region 22 is in contact with the drift layer 3, which is an n-type semiconductor layer. Therefore, a pn junction is formed at the interface between the anode region 22 and the drift layer 3. As a result, the semiconductor device 200 includes a pn junction diode.

[0220] The anode region 22 is electrically connected to the anode electrode 24. Specifically, an insulating film 23 is formed on the epitaxial layer 13. An opening OP is formed in this insulating film 23. A part of the anode region 22 is exposed at the bottom of the opening OP. The anode electrode 24 is formed on the insulating film 23 including within the opening OP. Thereby, the anode region 22 and the anode electrode 24 are electrically connected.

[0221] On the other hand, the cathode electrode 21 is formed on the lower surface of the silicon carbide substrate 1. The cathode electrode 21 is electrically connected to the drift layer 3 through the silicon carbide substrate 1 and the buffer layer 2. That is, in the pn junction diode formed by the anode region 22 and the drift layer 3, the anode region 22 is electrically connected to the anode electrode 24, while the drift layer 3 is electrically connected to the cathode electrode 21.

[0222] The semiconductor device in Embodiment 3 is manufactured using the semiconductor wafer WF in Embodiment 1. Therefore, in Embodiment 3, the carrier lifetime distribution, which includes the carrier lifetimes within the epitaxial layer 13 measured at multiple measurement points, has the first or second feature point described above. In other words, in Embodiment 3, the carrier lifetime within the epitaxial layer 13 can be shortened.

[0223] This promotes the extinction of carriers within the epitaxial layer 13. Therefore, according to Embodiment 3, the number of carriers swept out from the epitaxial layer 13 can be reduced. As a result, the recovery current of the pn junction diode used as an external freewheeling diode can be reduced. In addition, the reverse recovery time of the pn junction diode can be shortened.

[0224] Thus, according to Embodiment 3, recovery losses can be reduced by reducing the recovery current and shortening the reverse recovery time. As a result, the recovery loss of the pn junction diode, which is part of the switching loss, can be reduced during the IGBT turn-on time. This reduces the switching loss during the turn-on period.

[0225] The present inventors have described the invention in detail based on its embodiments, but it goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0226] 1. Silicon carbide substrate 2 buffer layers 3 Drift Layer 4 Drain electrodes 5A p-type well 5B p-type well 6A Source Area 6B Source Area 7A Body contact area 7B Body Contact Area 8 Gate Insulating Film 9 Gate Electrode 10 High-Side MOSFET 11 Interlayer Insulating Film 12 Source Electrode 13 Epitaxial Layer 20 Low-Side MOSFET 21 Cathode Electrode 22 Anode Region 23 Insulating Film 24 Anode Electrode 30 Switching Element 30H High-Side MOSFET 30L Low-Side MOSFET 50 Housing 51 Rotating Susceptor 52 Heater 52A Inner Heater 52B Outer Heater 53 Fixed Susceptor 60 Housing 61 Susceptor 62 Coil 100 Semiconductor Device 200 Semiconductor Device BD Body Diode C Capacitor CC Control Circuit CH1 Channel Formation Region CH2 Channel Formation Region EE Region FWD Diode GCC Gate Control Circuit GFA Arrow GFB Arrow GF1 Arrow GF2 Arrow GF3 Arrow GND Ground INV Inverter L Inductor LG1 First Leg LG2 Second Leg LG3 Third Leg MT 3-Phase Brushless Motor NA Node NT negative potential terminal PT Positive potential terminal RA area RL load RT Rotor SA1 film deposition equipment SA2 film deposition equipment ST Stator TE1 Input Terminal TH1 1st through hole TH2 2nd through hole T OFF Off-season T ON On period Vin Input Voltage Vout output voltage WF Semiconductor wafer WF1 semiconductor wafer WF2 semiconductor wafer WF3 semiconductor wafer WF4 semiconductor wafer WF5 semiconductor wafer WF6 semiconductor wafer

Claims

1. A silicon carbide substrate having a 4H-SiC crystal structure, The epitaxial layer formed on the silicon carbide substrate, A semiconductor wafer comprising, In a carrier lifetime distribution that includes the carrier lifetimes within the epitaxial layer measured at multiple measurement points, The average value of the aforementioned career lifetime is τ ｍ In that case, τ ｍ The interval is ≤0.4 μs. The standard deviation of the aforementioned carrier lifetime distribution is σ τ In that case, σ τ ≤0.5τ ｍ This is a semiconductor wafer.

2. In the semiconductor wafer according to claim 1, The diameter of the semiconductor wafer is 145 mm or more.

3. In the semiconductor wafer according to claim 2, The diameter of the semiconductor wafer is 195 mm or more.

4. In the semiconductor wafer according to claim 2, The carrier lifetime distribution is comprised of the carrier lifetimes measured in a region excluding the first region, which is the area from the outer edge of the semiconductor wafer up to 2 mm.

5. In the semiconductor wafer according to claim 1, The median of the aforementioned carrier lifetime is τ ｃ In that case, τ ｃ ≤ 1.5τ ｍ That is the case.

6. In a group of semiconductor wafers having a plurality of semiconductor wafers as described in claim 1, For each τ of the semiconductor wafers included in the semiconductor wafer group ｍ in the average value distribution including the elements, let the standard deviation of the average value distribution be σ ｓｔ When it is set as σ ｓｔ σ ≤ 0.2 μs

7. In the semiconductor wafer group described in claim 6, The aforementioned semiconductor wafer group consists of 25 semiconductor wafers, σ ｓｔ The interval is ≤0.1 μs.

8. A silicon carbide substrate having a 4H-SiC crystal structure, The epitaxial layer formed on the silicon carbide substrate, A semiconductor wafer comprising, In a carrier lifetime distribution that includes the carrier lifetimes within the epitaxial layer measured at multiple measurement points, The average value of the aforementioned career lifetime is τ ｍ In that case, τ ｍ ≤0.2 μs, The standard deviation of the aforementioned carrier lifetime distribution is σ τ In that case, σ τ ≤0.05τ ｍ This is a semiconductor wafer.

9. In the semiconductor wafer according to claim 8, The diameter of the semiconductor wafer is 145 mm or more.

10. In the semiconductor wafer according to claim 9, The diameter of the semiconductor wafer is 195 mm or more.

11. In the semiconductor wafer according to claim 9, The carrier lifetime distribution is comprised of the carrier lifetimes measured in a region excluding the second region, which is the area from the outer edge of the semiconductor wafer up to 25 mm.

12. In the semiconductor wafer according to claim 8, The median of the aforementioned carrier lifetime is τ ｃ In that case, τ ｃ ≤ 1.5τ ｍ That is the case.

13. In a group of semiconductor wafers having a plurality of semiconductor wafers as described in claim 8, Each of the semiconductor wafers included in the group of semiconductor wafers τ ｍ In a mean distribution that includes elements, the standard deviation of the mean distribution is σ ｓｔ In that case, σ ｓｔ The interval is ≤0.2 μs.

14. In the semiconductor wafer group described in claim 13, The aforementioned semiconductor wafer group consists of 25 semiconductor wafers, σ ｓｔ The interval is ≤0.1 μs.

15. A silicon carbide substrate having a 4H-SiC crystal structure, The epitaxial layer formed on the silicon carbide substrate, A semiconductor device equipped with, In a carrier lifetime distribution that includes the carrier lifetimes within the epitaxial layer measured at multiple measurement points, The average value of the aforementioned career lifetime is τ ｍ In that case, τ ｍ The interval is ≤0.4 μs. The standard deviation of the aforementioned carrier lifetime distribution is σ τ In that case, σ τ ≤0.5τ ｍ A semiconductor device.

16. In the semiconductor device according to claim 15, The semiconductor device includes a power MOSFET.

17. In the semiconductor device according to claim 15, The semiconductor device has a pn junction diode.

18. In the semiconductor device according to claim 15, The semiconductor device is a component of a DC / DC converter or inverter.

19. A silicon carbide substrate having a 4H-SiC crystal structure, The epitaxial layer formed on the silicon carbide substrate, A semiconductor device equipped with, In a carrier lifetime distribution that includes the carrier lifetimes within the epitaxial layer measured at multiple measurement points, The average value of the aforementioned career lifetime is τ ｍ In that case, τ ｍ ≤0.2 μs, The standard deviation of the aforementioned carrier lifetime distribution is σ τ In that case, σ τ ≤0.05τ ｍ A semiconductor device.

20. In the semiconductor device described in claim 19, The semiconductor device includes a power MOSFET.

21. In the semiconductor device described in claim 19, The semiconductor device has a pn junction diode.

22. In the semiconductor device described in claim 19, The semiconductor device is a component of a DC / DC converter or inverter.

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