Plasma processing equipment

Abstract

To provide a plasma processing apparatus that improves the selectivity ratio. [Solution] The plasma processing apparatus 1 comprises a chamber 10, a substrate support 11 disposed within the chamber, a bias electrode in a conductive member and a ceramic member 1111a of a base 1110 disposed within the substrate support and functioning as a lower electrode, an upper electrode 13 disposed above the substrate support, a source RF power supply 31a electrically connected to the upper or lower electrode and generating a source RF signal for generating plasma in the chamber, a bias RF power supply 31b electrically connected to the lower electrode and generating a bias RF signal, and an upper DC pulse generator 32b electrically connected to the upper electrode and generating an upper DC pulse signal.

Description

Technical Field

[0001] The present disclosure relates to a plasma processing apparatus.

Background Art

[0002] Patent Document 1 discloses a method including: (a) a step of preparing a substrate on a substrate support in a chamber of a plasma processing apparatus, the substrate including a dielectric film containing silicon and oxygen and a metal hard mask provided on the dielectric film; (b) a step of forming a deposit on the substrate, the deposit being supplied from plasma generated from a processing gas containing a gas component containing fluorine and carbon in the chamber; (c) a step of modifying the deposit by supplying ions from the plasma generated from the processing gas to the deposit; and (d) a step of etching the dielectric film using the plasma generated in the chamber after (c). In (c), the power level of the source high-frequency power used to generate the plasma from the processing gas is less than or equal to the power level of the source high-frequency power used to generate the plasma from the processing gas in (b). The level of the electrical bias supplied to the substrate support in (c) is higher than the level of the electrical bias supplied to the substrate support in (b), or the electrical bias is not supplied to the substrate support in (b). The level of the electrical bias supplied to the substrate support in (d) is higher than the level of the electrical bias supplied to the substrate support in (c).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In one aspect, this disclosure provides a plasma processing apparatus that improves selectivity. [Means for solving the problem]

[0005] To solve the above problems, according to one embodiment, a chamber, a substrate support portion disposed within the chamber, a lower electrode disposed within the substrate support portion, an upper electrode disposed above the substrate support portion, and a source RF power supply electrically connected to the upper electrode or the lower electrode and configured to generate a source RF signal for generating plasma in the chamber, wherein the source RF signal has a first source power level in the first period of each cycle, a second source power level smaller than the first source power level in the first sub-period of the second sub-period which is alternately repeated in the second period following the first period of each cycle, a third source power level smaller than the second source power level in the second sub-period, and a third source power level smaller than the second source power level and smaller than the third source power level in the third period following the second period of each cycle. A plasma processing apparatus can be provided, comprising: a source RF power supply having a large fourth source power level; a bias RF power supply electrically connected to the lower electrode and configured to generate a bias RF signal, wherein the bias RF signal has a zero power level in the first period, a zero power level in the first sub-period, a first bias power level in the second sub-period, and a second bias power level greater than the first bias power level in the third period; and an upper DC pulse generator electrically connected to the upper electrode and configured to generate an upper DC pulse signal, wherein the upper DC pulse signal has a zero voltage level in the first period, a first voltage level with negative polarity in the first sub-period, a zero voltage level in the second sub-period, and a zero voltage level in the third period. [Effects of the Invention]

[0006] In one respect, it is possible to provide a plasma processing apparatus that improves the selectivity ratio. [Brief explanation of the drawing]

[0007] [Figure 1] An example of a diagram illustrating the configuration of a plasma processing system. [Figure 2] An example of a diagram illustrating the configuration of a capacitively coupled plasma processing apparatus. [Figure 3] An example flowchart illustrating the etching process. [Figure 4] An example of a diagram showing a pulse pattern. [Figure 5] An example of a diagram showing a pulse pattern. [Figure 6] An example of a diagram showing a pulse pattern. [Modes for carrying out the invention]

[0008] Various exemplary embodiments will be described in detail below with reference to the drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals.

[0009] [Plasma Processing System] Figure 1 is an example diagram illustrating an example configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber (chamber) 10, a substrate support section 11, and a plasma generation section 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space, and at least one gas outlet for discharging gas from the plasma processing space. The gas supply port is connected to a gas supply section 20, which will be described later, and the gas outlet is connected to an exhaust system 40, which will be described later. The substrate support section 11 is located in the plasma processing space and has a substrate support surface for supporting a substrate.

[0010] The plasma generation unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be a capacitively coupled plasma (CCP), an inductively coupled plasma (ICP), an electron cyclotron resonance (ECR) plasma, a helicon wave excited plasma (HWP), or a surface wave plasma (SWP), etc. Various types of plasma generation units, including an AC (alternating current) plasma generation unit and a DC (direct current) plasma generation unit, may also be used. In one embodiment, the AC signal (AC power) used in the AC plasma generation unit has a frequency in the range of 100 kHz to 10 GHz. Therefore, the AC signal includes an RF (radio frequency) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0011] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various processes described herein. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, some or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 is implemented, for example, by a computer 2a. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The functions implemented by the processing unit 2a1 described herein may be implemented in a circuit or processing circuitry, including a general-purpose processor, an application-specific processor, integrated circuits, ASICs (Application Specific Integrated Circuits), a CPU (Central Processing Unit), conventional circuitry, and / or a combination thereof, programmed to implement the functions described herein. A processor is considered a circuit or processing circuit, including transistors and other circuitry. A processor may be a programmed processor that executes a program stored in the storage unit 2a2. This program may be stored in the memory unit 2a2 in advance, or it may be retrieved via a medium when needed. The retrieved program is stored in the memory unit 2a2 and read from the memory unit 2a2 and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a, or it may be a communication line connected to the communication interface 2a3. The memory unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing device 1 via a communication line such as a LAN (Local Area Network).In this disclosure, circuits, units, and means are hardware programmed to perform or configured to perform the functions described. Such hardware may be any hardware described in this disclosure, or any hardware known to be programmed to perform or execute the functions described. If such hardware is a processor that is considered to be a type of circuit, such circuit, means, or unit is a combination of hardware and software used to constitute such hardware and / or processor.

[0012] [Plasma treatment device] The following describes an example configuration of a capacitively coupled plasma processing apparatus as an example of a plasma processing apparatus 1. Figure 2 is an example diagram illustrating an example configuration of a capacitively coupled plasma processing apparatus (substrate processing apparatus) 1.

[0013] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply system 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support unit 11 and a gas introduction unit. The gas introduction unit is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas introduction unit includes a shower head 13. The substrate support unit 11 is located inside the plasma processing chamber 10. The shower head 13 is located above the substrate support unit 11. In one embodiment, the shower head 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the shower head 13, the side walls 10a of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 is grounded. The shower head 13 and the substrate support unit 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0014] The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of the substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 in a plan view. The substrate W is placed on the central region 111a of the main body portion 111, and the ring assembly 112 is placed on the annular region 111b of the main body portion 111 so as to surround the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also called the substrate support surface for supporting the substrate W, and the annular region 111b is also called the ring support surface for supporting the ring assembly 112.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is placed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic chuck electrode 1111b placed within the ceramic member 1111a. The electrostatic chuck electrode 1111b is also called a clamping electrode. In one embodiment, the electrostatic chuck electrode 1111b is electrically connected or coupled to a chuck power supply. The chuck power supply may be a DC power supply or an AC power supply. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Furthermore, other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have an annular region 111b. In this case, the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or on both the electrostatic chuck 1111 and the annular insulating member. In addition, at least one bias electrode, electrically connected or coupled to the power supply 31 and / or power supply 32 described later, may be placed within the ceramic member 1111a. In this case, at least one bias electrode functions as a lower electrode. Also, the conductive member of the base 1110 and the bias electrode in the ceramic member 1111a may function as multiple lower electrodes. In one embodiment, the first voltage generation unit 32a, which functions as a voltage pulse generation unit described later, is electrically connected or coupled to the bias electrode in the ceramic member 1111a, and the first RF generation unit 31a, described later, is electrically connected or coupled to the conductive member of the base 1110. Furthermore, the electrostatic chuck electrode 1111b may function as a lower electrode. Therefore, the substrate support portion 11 includes at least one lower electrode. The lower electrode is also located within the substrate support portion 11.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive material or an insulating material, and the cover ring is formed of an insulating material.

[0017] Further, the substrate support 11 may include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate W to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid such as brine or gas flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. Further, the substrate support 11 may include a heat transfer gas supply unit configured to supply a heat transfer gas to the gap between the back surface of the substrate W and the central region 111a.

[0018] The shower head 13 is disposed above the substrate support 11 and is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. The shower head 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas introduction ports 13c. The process gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the plurality of gas introduction ports 13c. Further, the shower head 13 includes at least one upper electrode. The gas introduction part may include, in addition to the shower head 13, one or more side gas injection parts (SGI; Side Gas Injector) attached to one or more openings formed in the side wall 10a.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from the corresponding gas source 21 to the shower head 13 through the corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Further, the gas supply unit 20 may include at least one flow modulation device for modulating or pulsing the flow rate of at least one process gas.

[0020] The power supply system 30 includes a power supply 31 that is electrically connected or coupled to the plasma processing chamber 10. In one embodiment, the power supply 31 is electrically connected or coupled to the plasma processing chamber 10 through at least one impedance matcher. The impedance matcher may be a mechanically controlled matcher or an electronically controlled matcher. The power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. Thereby, plasma is generated from at least one process gas supplied to the plasma processing space 10s. Therefore, the power supply 31 may function as at least a part of the plasma generation unit 12. Also, by supplying a bias RF signal to at least one lower electrode, a bias potential is generated on the substrate W, and the ion component in the formed plasma can be drawn into the substrate W.

[0021] The power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is electrically connected or coupled to at least one lower electrode and / or at least one upper electrode and is configured to generate a source RF signal (source RF power) to generate plasma in the plasma processing space 10s. In one embodiment, the first RF generation unit 31a is electrically connected or coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matcher. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generation unit 31a may be configured to generate a plurality of source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0022] The second RF generation unit 31b is electrically connected to or coupled to at least one lower electrode and is configured to generate a bias RF signal (bias RF power). In one embodiment, the second RF generation unit 31b is electrically connected to or coupled to at least one lower electrode via at least one impedance matcher. If the first RF generation unit 31a is electrically connected to or coupled to a lower electrode, the second RF generation unit 31b may be electrically connected to or coupled to the same lower electrode, or it may be electrically connected to or coupled to a different lower electrode. The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a lower frequency than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generation unit 31b may be configured to generate a plurality of bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0023] The power supply system 30 may also include a power supply 32 that is electrically connected to or coupled to the plasma processing chamber 10. The power supply 32 includes a first voltage generation unit 32a and a second voltage generation unit 32b. In one embodiment, the first voltage generation unit 32a is electrically connected to or coupled to at least one lower electrode and configured to generate a first voltage signal. The generated first voltage signal is applied to at least one lower electrode. In one embodiment, the second voltage generation unit 32b is electrically connected to or coupled to at least one upper electrode and configured to generate a second voltage signal. The generated second voltage signal is applied to at least one upper electrode.

[0024] In various embodiments, the first and / or second voltage signals may be pulsed. In this case, the first voltage generation unit 32a and / or the second voltage generation unit 32b function as voltage pulse generation units configured to generate a sequence of voltage pulses. Thus, the sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. In one embodiment, the sequence of voltage pulses has multiple cycles, each cycle including a burst of voltage pulses in a first period and a constant reference voltage in a second period. That is, in the sequence of voltage pulses, bursts of voltage pulses are repeated. The absolute value of the voltage level of the voltage pulse is greater than the absolute value of the voltage level of the reference voltage. The voltage pulse may have an arbitrary waveform having a rectangular, trapezoidal, triangular, or a combination thereof, and the arbitrary waveform may change over time. The voltage pulse may have positive polarity or negative polarity. The sequence of voltage pulses may also include one or more positive voltage pulses and one or more negative voltage pulses within one cycle. The first and second voltage generation units 32a and 32b may be provided in addition to the power supply 31, and the first voltage generation unit 32a may be provided in place of the second RF generation unit 31b.

[0025] The exhaust system 40 may be connected to, for example, a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0026] [Etching process] Next, an example of the etching process will be explained using Figures 3 and 4. Figure 3 is an example of a flowchart showing the etching process. Figure 4 is an example of a diagram showing a pulse pattern.

[0027] Here, a source RF signal (e.g., 100 MHz) is supplied to the upper electrode from the first RF generation unit 31a (source RF power supply). Note that the source RF signal is not limited to being supplied to the upper electrode, but may also be supplied to the lower electrode. A bias RF signal (e.g., 13 MHz) is supplied to the lower electrode from the second RF generation unit 31b (bias RF power supply). An upper DC pulse signal (second voltage signal, e.g., a negative DC pulse signal of 400 kHz) is supplied to the upper electrode from the second voltage generation unit 32b (upper DC pulse generator). Figure 4 shows the power level of the source RF signal, the power level of the bias RF signal, and the voltage of the upper DC pulse signal, respectively. Note that in the following explanation, the power level may be used to include both the AC signal and the DC pulse signal.

[0028] Furthermore, as shown in Figure 4, the etching process consists of a first process P1, a second process P2, and a third process P3, with this cycle being repeated a predetermined number of times.

[0029] In step S101, the substrate W is prepared. Here, the substrate W is transported into the plasma processing chamber 10 by a transport device (not shown), and the substrate W is supported by the substrate support section 11.

[0030] In step S102, the supply of etching gas is started. Here, the pressure in the plasma processing space 10s is adjusted to a predetermined pressure (e.g., 10 mTorr) by the exhaust system 40. Etching gas is also supplied from the gas supply unit 20 to the shower head 13. As the etching gas, for example, a mixed gas of C4F6, O2, and Ar can be used.

[0031] Next, in the first period of each cycle, the first process P1 is executed. Specifically, the first process P1 includes step S103.

[0032] In step S103, the first RF generation unit 31a supplies a source RF signal (e.g., 100 MHz) with a first source power level L1 to the upper or lower electrode (first process P1). The bias RF signal is at a zero power level (OFF) and is not supplied to the lower electrode, and the upper DC pulse signal is at a zero voltage level (OFF) and is not supplied to the upper electrode. After the process time T1 has elapsed, the control unit 2 proceeds to step S104.

[0033] In the first process P1, a source RF signal with a first source power level L1, which is greater than the power levels described later (second to fourth source power levels L2 to L4), is supplied to the upper or lower electrode to generate etching gas radicals (e.g., CF radicals) in the plasma.

[0034] Next, in the second period following the first period of each cycle, the second process P2 is executed. The second process P2 alternately repeats the process P21 executed in the first sub-period and the process P22 executed in the second sub-period. Specifically, the second process P2 includes steps S104 to S106.

[0035] In step S104, a source RF signal (for example, 100 MHz) with a second source power level L2 is supplied from the first RF generation unit 31a to the upper electrode or the lower electrode, and an upper DC pulse signal with a first voltage level having a negative polarity is supplied (ON) from the second voltage generation unit 32b to the upper electrode (process P21). Note that the bias RF signal is in a zero power level state (OFF) where it is not supplied to the lower electrode. When the process time T21 elapses, the process of the control unit 2 proceeds to step S105.

[0036] Note that the second source power level L2 is smaller than the first source power level L1 (L2 < L1). Also, the process time T21 is shorter than the process time T1 and the process time T3 described later. For example, the processing time for one cycle (processes P1 to P3) is within a range of, for example, 500 μs or more and 2000 μs or less, and the process time T21 is preferably within a range of 5 μs or more and 50 μs or less.

[0037] In process P21, a source RF signal with a second source power level L2, which is larger than the third source power level L3 described later, is supplied to the upper electrode or the lower electrode, and an upper DC pulse signal with a first voltage level having a negative polarity is supplied to the upper electrode.

[0038] In step S105, a source RF signal (for example, 100 MHz) with a third source power level L3 is supplied from the first RF generation unit 31a to the upper electrode or the lower electrode, and a bias RF signal (for example, 13 MHz) with a first bias power level L5 is supplied (ON) from the second RF generation unit 31b to the lower electrode (process P22). Note that the upper DC pulse signal is in a zero voltage level state (OFF) where it is not supplied to the upper electrode. When the process time T22 elapses, the process of the control unit 2 proceeds to step S106.

[0039] Note that the third source power level L3 is smaller than the second source power level L2 (L3 < L2). Also, the process time T22 is shorter than the process time T1 and the process time T3 described later. For example, the processing time for one cycle (processes P1 to P3) is within a range of, for example, 500 μs or more and 2000 μs or less, and the process time T22 is preferably within a range of 5 μs or more and 50 μs or less.

[0040] In step S106, it is determined whether a predetermined number of repetitions has elapsed. If the predetermined number of repetitions has not elapsed (S106·NO), the processing of the control unit 2 returns to step S104, and steps S104 (process P21) to S105 (process P22) are repeated. If the predetermined number of repetitions has elapsed (S106·YES), the processing of the control unit 2 proceeds to step S107. Note that in FIG. 4, the case where the number of repetitions is 6 is shown.

[0041] Thus, in the second process P2, processes P21 and P22 are alternately repeated.

[0042] Next, in the third period following the second period of each cycle, the third process P3 is executed. Specifically, the third process P3 includes step S107.

[0043] In step S107, a source RF signal with a fourth source power level L4 (for example, 100 MHz) is supplied from the first RF generation unit 31a to the upper electrode or the lower electrode, and a bias RF signal with a second bias power level L6 (for example, 13 MHz) is supplied (ON) from the first voltage generation unit 32a to the lower electrode (third process P3). Note that the upper DC pulse signal is in a zero voltage level state (OFF) where it is not supplied to the upper electrode. When the process time T3 has elapsed, the processing of the control unit 2 proceeds to step S108.

[0044] The fourth source power level L4 preferably has enough power to maintain the plasma in the third process P3, and may be greater than, equal to, or less than the second source power level L2. Alternatively, it may be set to a zero power level (OFF) where the source RF signal is not supplied to the upper and lower electrodes. In other words, the fourth source power level L4 may be set to a zero power level (see the dashed line in Figure 4).

[0045] In step S108, it is determined whether a predetermined number of repetitions has elapsed. If the predetermined number of repetitions has not elapsed (S108 - NO), the control unit 2 returns to step S103, and steps S103 to S107 (processes P1 to P3) are repeated. If the predetermined number of repetitions has elapsed (S108 - YES), the etching process is terminated. That is, the supply of the source RF signal, bias RF signal, and upper DC pulse signal is stopped, and the supply of etching gas is stopped. After that, the substrate W is transported from the plasma processing chamber 10 by a transport device (not shown).

[0046] As described above, the first process P1 generates radicals. Then, in the second process P2h, the deposition of deposits (process P21) and the modification of deposits (process P22) are repeated multiple times. In the third process P3, the film to be etched is etched.

[0047] Figure 5 shows an example of a pulse pattern. In Figure 5, the power level of the source RF signal, the power level of the bias RF signal, and the voltage of the upper DC pulse signal are shown, respectively. In Figure 5, the processes are performed in the order of the first process P1, the second process P2 (processes P21 and P22), the fourth process P4, and the third process P3.

[0048] Here, the fourth process P4 is executed during the period between the second and third periods of each cycle. Specifically, the fourth process P4 turns off the plasma by setting the source RF signal to zero power level (OFF). Alternatively, the fourth process P4 may generate a low-density plasma by applying a small source RF signal. The bias RF signal is also set to zero power level (OFF), and the upper DC pulse signal is set to zero voltage level (OFF). This verticalizes the ion angle by lowering the electron temperature before the etching process (third process P3). This further improves the penetration.

[0049] Figure 6 is an example of a diagram showing a pulse pattern. In Figure 6, the power level of the source RF signal, the power level of the bias RF signal, and the voltage of the upper DC pulse signal are shown, respectively. In Figure 6, the process is carried out in the order of the first process P1, the second process P2 (processes P21 and P22), the third process P3, and the fifth process P5.

[0050] Here, in the fourth period following the third period of each cycle, the fifth process P5 is executed. Specifically, the fifth process P5 turns off the plasma by setting the source RF signal to zero power level (OFF). It also sets the bias RF signal to zero power level (OFF) and the upper DC pulse signal to zero voltage level (OFF). This allows the byproducts to be exhausted and reset after each cycle.

[0051] While embodiments of the plasma processing system have been described above, this disclosure is not limited to the embodiments described above, and various modifications and improvements are possible within the scope of the gist of this disclosure as described in the claims.

[0052] The embodiments disclosed above include, for example, the following aspects: (Note 1) Chamber and, A substrate support portion is arranged within the chamber, The lower electrode is disposed within the substrate support portion, An upper electrode positioned above the substrate support portion, A source RF power supply electrically connected to the upper electrode or the lower electrode and configured to generate a source RF signal for generating plasma in the chamber, wherein the source RF signal has a first source power level in a first period of each cycle, a second source power level smaller than the first source power level in the first sub-period of a second sub-period which alternately repeats in a second period following the first period of each cycle, a third source power level smaller than the second source power level in the second sub-period, and a fourth source power level smaller than the second source power level and larger than the third source power level in a third period following the second period of each cycle. A bias RF power supply electrically connected to the lower electrode and configured to generate a bias RF signal, wherein the bias RF signal has a zero power level in the first period, a zero power level in the first sub-period, a first bias power level in the second sub-period, and a second bias power level greater than the first bias power level in the third period. An upper DC pulse generator is electrically connected to the upper electrode and configured to generate an upper DC pulse signal, wherein the upper DC pulse signal has a zero voltage level in the first period, a first voltage level with negative polarity in the first sub-period, a zero voltage level in the second sub-period, and a zero voltage level in the third period. Equipped with, Plasma processing equipment. (Note 2) The source RF signal has a zero power level during the fourth period following the third period of each cycle. The bias RF signal has a zero power level during the fourth period. The upper DC pulse signal has a zero voltage level during the fourth period. The plasma processing apparatus described in Appendix 1. (Note 3) Chamber and, A substrate support portion is arranged within the chamber, The lower electrode is disposed within the substrate support portion, An upper electrode positioned above the substrate support portion, A source RF power supply electrically connected to the upper electrode or the lower electrode and configured to generate a source RF signal for generating plasma in the chamber, wherein the source RF signal has a first source power level in a first period of each cycle, a second source power level smaller than the first source power level in the first sub-period of a second sub-period which alternately repeats in a second period following the first period of each cycle, a third source power level smaller than the second source power level in the second sub-period, a zero power level in a third period following the second period of each cycle, and a fourth source power level smaller than the second source power level and larger than the third source power level in a fourth period following the third period of each cycle, A bias RF power supply electrically connected to the lower electrode and configured to generate a bias RF signal, wherein the bias RF signal has a zero power level in the first period, a zero power level in the first sub-period, a first bias power level in the second sub-period, a zero power level in the third period, and a second bias power level greater than the first bias power level in the fourth period. An upper DC pulse generator is electrically connected to the upper electrode and configured to generate an upper DC pulse signal, wherein the upper DC pulse signal has a zero voltage level in the first period, a first voltage level with negative polarity in the first sub-period, a zero voltage level in the second sub-period, a zero voltage level in the third period, and a zero voltage level in the fourth period. Equipped with, Plasma processing equipment. [Explanation of Symbols]

[0053] W board 1. Plasma processing equipment 2 Control Unit 10 Plasma processing chamber (chamber) 10s Plasma Processing Space 11 Substrate support part (lower electrode) 13. Shower head (upper electrode) 20 Gas Supply Department 31a First RF generation unit (source RF power supply) 31b Second RF generation unit (bias RF power supply) 32b Second voltage generation unit (upper DC pulse generator) 40 Exhaust System

Claims

1. Chamber and, A substrate support portion is arranged within the chamber, The lower electrode is disposed within the substrate support portion, An upper electrode positioned above the substrate support portion, A source RF power supply electrically connected to the upper electrode or the lower electrode and configured to generate a source RF signal for generating plasma in the chamber, wherein the source RF signal has a first source power level in a first period of each cycle, a second source power level smaller than the first source power level in the first sub-period of a second sub-period which alternately repeats in a second period following the first period of each cycle, a third source power level smaller than the second source power level in the second sub-period, and a fourth source power level smaller than the second source power level and larger than the third source power level in a third period following the second period of each cycle. A bias RF power supply electrically connected to the lower electrode and configured to generate a bias RF signal, wherein the bias RF signal has a zero power level in the first period, a zero power level in the first sub-period, a first bias power level in the second sub-period, and a second bias power level greater than the first bias power level in the third period. An upper DC pulse generator is electrically connected to the upper electrode and configured to generate an upper DC pulse signal, wherein the upper DC pulse signal has a zero voltage level in the first period, a first voltage level with negative polarity in the first sub-period, a zero voltage level in the second sub-period, and a zero voltage level in the third period. Equipped with, Plasma processing equipment.

2. The source RF signal has a zero power level during the fourth period following the third period of each cycle. The bias RF signal has a zero power level during the fourth period. The upper DC pulse signal has a zero voltage level during the fourth period. The plasma processing apparatus according to claim 1.

3. Chamber and, A substrate support portion is arranged within the chamber, The lower electrode is disposed within the substrate support portion, An upper electrode positioned above the substrate support portion, A source RF power supply electrically connected to the upper electrode or the lower electrode and configured to generate a source RF signal for generating plasma in the chamber, wherein the source RF signal has a first source power level in a first period of each cycle, a second source power level smaller than the first source power level in the first sub-period of a second sub-period which alternately repeats in a first sub-period and a second sub-period following the first period of each cycle, a third source power level smaller than the second source power level in the second sub-period, a zero power level in a third period following the second period of each cycle, and a fourth source power level smaller than the second source power level and greater than the third source power level in a fourth period following the third period of each cycle, A bias RF power supply electrically connected to the lower electrode and configured to generate a bias RF signal, wherein the bias RF signal has a zero power level in the first period, a zero power level in the first sub-period, a first bias power level in the second sub-period, a zero power level in the third period, and a second bias power level greater than the first bias power level in the fourth period. An upper DC pulse generator is electrically connected to the upper electrode and configured to generate an upper DC pulse signal, wherein the upper DC pulse signal has a zero voltage level in the first period, a first voltage level with negative polarity in the first sub-period, a zero voltage level in the second sub-period, a zero voltage level in the third period, and a zero voltage level in the fourth period. Equipped with, Plasma processing equipment.

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