Logic circuits using photorelays and methods for configuring logic circuits using photorelays

Abstract

To provide a logic circuit using a photorelay with high reliability. [Solution] A logic circuit using a photorelay comprises a photorelay and a resistor network including n resistors, each corresponding to n input variables (n is an integer of 2 or more) of a logic function. The resistance value of each resistor in the resistor network is set to correspond to the weight wi in the threshold decision function f(x), and the circuit is configured such that the conduction or non-conduction state of the output side of the photorelay is determined according to the type of photorelay.

Description

[Technical Field]

[0001] The present invention relates to a logic circuit using a photorelay and a method for configuring a logic circuit using a photorelay. [Background technology]

[0002] Logic circuits are typically composed of semiconductor elements. Numerous publicly available documents exist on this technology, including, for example, Patent Document 2. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-98081 [Patent Document 2] Japanese Patent Publication No. 2022-044813 [Non-patent literature]

[0004] [Non-Patent Document 1] https: / / www.signal.co.jp / products / railway / faq / faq09 / [Non-Patent Document 2] Y. Koga, Y. Suzuki and K. Mizukami, "Logic Elements for Fail-Safe Circuit Design", IEEE, FTCS-10, pp351-353, (1980). [Non-Patent Document 3] Mizukami, Koga: A Method for Realizing Fail-Safe Logic Circuits Using Semiconductors, Transactions of the Institute of Electrical, Information and Communication Engineers, J65-D, No.12, pp. "Circled 1", 1550-1557, (1982). [Non-Patent Document 4] S. Muroga, "Threshold Logics AND Its Applications", John Wiley & Sons, (1972) [Overview of the project] [Problems that the invention aims to solve]

[0005] The inventors are considering constructing a logic circuit using a photorelay. A configuration in which the output of a logic circuit composed of semiconductor elements causes the photorelay to conduct or not conduct is conceivable, but this presents reliability issues in harsh environments.

[0006] To solve these problems, the present invention aims to provide a method for configuring a logic circuit using a photorelay with high reliability, and a logic circuit using a photorelay.

[0007] Furthermore, the present invention aims to provide a logic circuit simulator and program that enables easier and more intuitive simulation of this type of logic circuit through visual means. [Means for solving the problem]

[0008] The method for configuring a logic circuit using a photorelay according to the present invention comprises a first group of resistors and a second group of resistors corresponding to the input of a logic function, wherein the resistors of the first group of resistors supply a power supply voltage to one terminal on the input side of the photorelay via the resistors when the logic value of the logic function is input to 1, and the resistors of the second group of resistors are grounded via the resistors when the logic value of the logic function is input to 0, and the resistor network is configured to be connected in parallel between both terminals on the input side of the photorelay, and the resistor network is configured based on the following threshold logic function f(x) such that the logic value corresponding to the input of the logic function becomes the conduction function on the output side of the photorelay.

[0009] TIFF2026127717000002.tif50106

[0010] Here t: Electrical energy threshold of the photorelay wi: Resistance value of each resistor as a weight xi: A variable that determines whether each resistor is part of a first group of resistors that takes the power supply voltage corresponding to the logical value 1 of the logic function as input, or part of a second group of resistors that takes ground corresponding to the logical value 0 as input. In the method for configuring a logic circuit using a photorelay according to the present invention, the logic circuit may be structured in a hierarchical manner using a network based on the conduction function of the output side of the photorelay.

[0011] The logic circuit using a photorelay according to the present invention comprises a photorelay and a resistor network configured to supply a power supply voltage to one terminal on the input side of the photorelay via the resistors of the first resistor group in response to an input where the logic value of the logic function is 1, and to ground the resistors of the second resistor group in response to an input where the logic value of the logic function is 0, and to connect in parallel between both terminals on the input side of the photorelay according to the input of the logic circuit, wherein the logic value corresponding to the input of the logic function is the conduction function on the output side of the photorelay.

[0012] In the logic circuit using a photorelay according to the present invention, the resistor network is configured based on the threshold logic function f(x) described above.

[0013] In the logic circuit using a photorelay according to the present invention, a hierarchical structure may be created using a network based on the conduction function of the output side of the photorelay.

[0014] The logic circuit simulator according to the present invention is a logic circuit simulator that includes at least relay elements and connecting lines as circuit elements, comprising: a circuit configuration unit that connects each of the circuit elements by predetermined operations on a display unit to constitute the logic circuit; and a calculation unit that inputs a voltage corresponding to the variables of the logic function to the input side of the relay elements, obtains the voltage application state of each circuit element as current flowing from the terminal with a higher potential to the terminal with a lower potential at both terminals of each circuit element and displays it on the display unit, and obtains a conduction variable as a logic value of the logic function from the output side of the relay elements.

[0015] The logic circuit simulator according to the present invention includes a fault generation unit that generates a fault such as a disconnection or short circuit in a desired circuit element by a predetermined operation on the display unit, and the calculation unit may input a voltage corresponding to the variables of the logic function to the input side of the relay element, obtain the voltage application state of each circuit element after the fault has occurred and display it on the display unit, and obtain the conduction variable as the logic value of the logic function from the output side of the relay element.

[0016] The present invention is a program for a simulator of a logic circuit which includes at least relay elements and connecting lines as circuit elements, and causes a computer to perform the following steps: input a voltage corresponding to the variables of the logic function to the input side of the relay element, obtain the voltage application state of each circuit element as current flowing from the terminal with a higher potential to the terminal with a lower potential at both terminals of each circuit element and display it on the display unit, and obtain a conduction variable as the logic value of the logic function from the output side of the relay element.

[0017] The program according to the present invention includes a step of causing a fault such as a disconnection or short circuit in a desired circuit element by performing a predetermined operation on the display unit, and the step of obtaining the continuity variable may involve inputting a voltage corresponding to the variable of the logic function to the input side of the relay element, obtaining the voltage application state of each circuit element after the fault occurs and displaying it on the display unit, and obtaining the continuity variable as the logic value of the logic function from the output side of the relay element.

[0018] The logic circuit according to the present invention comprises a photorelay with one end of its input side grounded and whose logical value of a logic function is used as a conduction variable on its output side, and a resistor network having resistors connected to the other end of the input side of the photorelay via a switch that switches the connection to a power supply / predetermined potential in accordance with the variables of the logic function, with resistors corresponding to each variable of the logic function.

[0019] In the logic circuit according to the present invention, when the logic function is an OR logic function, the photo relay is of the normally open type, the input supply voltage from the power supply is E, and the voltage at which the photo relay turns on exceeding the threshold value is V on When the number of resistors in the resistor network is n, E / n > V on It may be configured to satisfy this condition.

[0020] In the logic circuit according to the present invention, when the logic function is an AND logic function, the photo relay is of the normally open type, a parallel resistor is connected in parallel between the terminals on the input side of the photo relay, the input supply voltage from the power supply is E, and the voltage at which the photo relay turns on exceeding the threshold value is V on When the voltage at which the photo relay turns off without exceeding the threshold value is V off When the number of resistors in the resistor network is n, and R s / R p = m (R s is the combined resistance value of the resistors that will be connected in series to the input side, R p is the combined resistance value of the resistors that will be connected in parallel to the input side), then E / (1 + m / n) > V on E·(n−1) / (n + m) < V off It may be configured to satisfy this condition.

[0021] In the logic circuit according to the present invention, when the logic function is a majority logic function with any n and the smallest integer k > n / 2, the photo relay is of the normally open type, a parallel resistor is connected in parallel between the terminals on the input side of the photo relay, the input supply voltage from the power supply is E, and the voltage at which the photo relay turns on exceeding the threshold value is V on When the voltage at which the photo relay turns off without exceeding the threshold value is V off When the number of resistors in the resistor network is n, and R s / R p = m (R s is the combined resistance value of the resistors that will be connected in series to the input side, R pWhen (the equivalent resistance value of the resistors connected in parallel to the input side) E·k / (n+m)>V on E·(k-1) / (n+m) <V off You should configure it so that it looks like this.

[0022] The logic circuit described in the present invention, when the logic function is a NOR logic function, has a photorelay of the normally closed type, the input supply voltage from the power supply is E, and the voltage that exceeds the threshold value of the photorelay to turn it ON is V. on Let n be the number of resistors in the resistor network. E / n>V on You should configure it so that it looks like this.

[0023] In the logic circuit according to the present invention, when the logic function is a NAND logic function, the photorelay is of the normally closed type, a parallel resistor is connected in parallel between the input terminals of the photorelay, the input supply voltage from the power supply is E, and the voltage that exceeds the threshold voltage and turns on the photorelay is V. on The voltage at which the photorelay turns off does not exceed the threshold voltage is set to V off Let n be the number of resistors in the resistor network, and R s / R p =m(R s R is the combined resistance value of the resistors connected in series to the input side. p When (the equivalent resistance value of the resistors connected in parallel to the input side) E / (1+m / n)>V on E·(n-1) / (n+m) <V off You should configure it so that it looks like this.

[0024] The logic circuit according to the present invention comprises first and second normally open type photorelays whose output sides are connected in parallel, a resistor network which connects the first and second switch units to the other ends of the input sides of the first and second photorelays via resistors, a first switch unit which switches the connection to the power supply / predetermined potential in accordance with the first variable of the EXOR logic function and is connected to one end of the input side of the first photorelay, a second switch unit which switches the connection to the power supply / predetermined potential in accordance with the second variable of the EXOR logic function and is connected to one end of the input side of the second photorelay, and the first and second switch units to the other ends of the input sides of the first and second photorelays.

[0025] The logic circuit according to the present invention has first to fourth logic circuits, each consisting of any of the above logic circuits and having the same configuration in which the same variables of the logic function are input, the output side of the first logic circuit and the output side of the second logic circuit are connected in series, the output side of the third logic circuit and the output side of the fourth logic circuit are connected in series, and the output sides of the first and second logic circuits connected in series and the output sides of the third and fourth logic circuits connected in parallel are connected to a group of relays, and a detection unit is interposed between a first connection part between the output side of the first logic circuit and the output side of the second logic circuit and a second connection part between the output side of the third logic circuit and the output side of the fourth logic circuit to detect whether or not current flows between them.

[0026] The logic circuit according to the present invention has first to fourth relays to which the first variable (X) of a majority logic function is input, fifth to eighth relays to which the second variable (Y) of a majority logic function is input, and ninth to twelfth relays to which the third variable (Z) of a majority logic function is input, wherein the conduction variable f on the output side of the logic circuit ij In that case, the logical formula is f ij =XYXY+XZXZ+YXYX+YZYZ+ZYZY+ZXZX The output sides of the first to twelfth relays are connected to satisfy the condition described above.

[0027] The present invention provides a method for configuring a logic circuit using a photorelay, comprising a photorelay with one input end grounded and whose output conduction variable is the logic value of a logic function, and a resistor network having resistors connected to the other input end of the photorelay via a switch that switches the connection to a power supply / predetermined potential in accordance with the variables of the logic function, wherein the method for configuring a logic circuit using a logic circuit comprises a photorelay with one input end grounded and whose output conduction variable is the logic value of a logic function, and a resistor network having resistors corresponding to each variable of the logic function, wherein the method for configuring a logic circuit using a logic circuit comprising a photorelay with one input end grounded and whose output conduction variable is the logic value of a logic function, and the method for configuring a logic circuit using a logic circuit comprising a photorelay with one input end grounded and whose output conduction variable is the logic value of a logic function, and a resistor network having resistors corresponding to each variable of the logic function, connected to the other input end of the photorelay via a switch that switches the connection to a power supply / predetermined potential in accordance with the variables of the logic function, wherein the method for configuring a logic circuit using a logic circuit comprises a photorelay with one input end grounded and whose output conduction variable is the logic value of a logic function, and the method for configuring a logic circuit using a logic circuit having a resistor connected to the other input end of the photorelay via a switch that switches the connection to a power supply / predetermined potential in accordance with the variables of the logic function, wherein the method for configuring a logic circuit using a logic circuit comprises a photorelay with one input end grounded and whose output conduction variable is the logic value of a logic function, and the method for configuring a logic circuit using a logic circuit having one off Set it.

[0028] Incidentally, electromagnetic relays are used in railway signal control. While electromagnetic relays are expected to operate stably and safely even in environments with high levels of noise and frequent external surges (see Non-Patent Document 1), the use of more compact and power-efficient photorelays in railway signal control is being considered (see Patent Document 1). Furthermore, fail-safe logic circuits to enhance safety in this type of circuit have also been proposed (see Non-Patent Documents 2 and 3). When using photorelays for this type of control, it is required to ensure the same level of safety as that of electromagnetic relays.

[0029] The present invention aims to provide a sensor that is more compact and power-efficient by using a photorelay, and that can also detect faults such as wire breaks.

[0030] The sensor according to the present invention is a sensor in which a sensor switch and a first photorelay connected in series with the sensor switch via a cable, the input side of which is connected or disconnected in accordance with the connected / disconnected state of the sensor switch are interposed between a power supply and ground, the sensor comprising a first resistor connected in parallel with the sensor switch, and a fault detection LED or second photorelay connected in series or in parallel with the input side of the first photorelay.

[0031] The sensor according to the present invention may include a second resistor connected in parallel with the input side of the first photorelay for setting the threshold value of the first photorelay. [Effects of the Invention]

[0032] According to the present invention, it is possible to provide a logic circuit using a photorelay with high reliability.

[0033] According to the present invention, this type of logic circuit can be simulated more easily and intuitively through visual means. [Brief explanation of the drawing]

[0034] [Figure 1] This graph shows the electrical characteristics of the input side of a photorelay. [Figure 2] This is a circuit diagram showing the logic circuit for one embodiment of the present invention. [Figure 3] This is a circuit diagram showing the configuration of the resistor network. [Figure 4] This is a circuit diagram of a logic circuit in which parallel resistors are not connected in parallel between the input terminals of a photorelay according to one embodiment of the present invention. [Figure 5] This diagram illustrates how to handle parallel resistors when the input voltage of a photorelay does not exceed a threshold. [Figure 6] This diagram illustrates how to handle parallel resistors when the voltage on the input side of a photorelay exceeds a threshold. [Figure 7] This is a circuit diagram showing a logic circuit according to another embodiment of the present invention. [Figure 8] This is a circuit diagram of a logic circuit when parallel resistors are connected in parallel between the input terminals of a photorelay according to one embodiment of the present invention. [Figure 9] This figure shows the configuration of a logic circuit that implements an EXOR logic function according to one embodiment of the present invention. [Figure 10]This figure shows the configuration of a logic circuit having FTC function and fault detection function according to one embodiment of the present invention. [Figure 11] This is an example of the configuration of an FTC-enabled logic circuit related to one embodiment of the present invention. [Figure 12] This is a circuit diagram showing the configuration of a sensor capable of detecting faults such as wire breaks according to an embodiment of the present invention. [Figure 13] This is a display screen diagram showing the state in which a program for simulating a logic circuit is launched in a computer system according to one embodiment of the present invention, and the FTC-enabled logic circuit shown in Figure 11 is configured on the screen. [Figure 14] Figure 13 shows a display screen illustrating the simulation status and results when the variables X=0, Y=0, and Z=0 in the majority voting logic circuit. [Figure 15] Figure 13 shows a display screen illustrating the simulation status and results when the variables X=0, Y=0, and Z=1 in the majority voting logic circuit. [Figure 16] Figure 13 shows a display screen illustrating the simulation status and results when the variables X=0, Y=1, and Z=0 in the majority voting logic circuit. [Figure 17] This is a display screen showing the simulation status and results when the variables X=1, Y=1, and Z=0 in the majority voting logic circuit shown in Figure 13. [Figure 18] This is a display screen showing the simulation status and results when the variables X=0, Y=1, and Z=1 in the majority voting logic circuit shown in Figure 13. [Figure 19] Figure 13 shows a display screen illustrating the simulation status and results when the variables X=1, Y=0, and Z=1 in the majority voting logic circuit. [Figure 20] Figure 13 shows a display screen illustrating the simulation status and results when the variables X=1, Y=1, and Z=1 in the majority voting logic circuit. [Figure 21]This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the connection line of the majority voting logic circuit shown in Figure 13, and the variables X=0, Y=0, and Z=0. [Figure 22] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the connection line of the majority voting logic circuit shown in Figure 13, and the variables are X=0, Y=0, and Z=1. [Figure 23] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the connection line of the majority voting logic circuit shown in Figure 13, and the variables X=0, Y=1, and Z=0. [Figure 24] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the connection line of the majority voting logic circuit shown in Figure 13, and the variables X=1, Y=1, and Z=0. [Figure 25] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the connection line of the majority voting logic circuit shown in Figure 13, and the variables X=0, Y=1, and Z=1. [Figure 26] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the connection line of the majority voting logic circuit shown in Figure 13, and the variables X=1, Y=0, and Z=1. [Figure 27] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the connection line of the majority voting logic circuit shown in Figure 13, and the variables X=1, Y=1, and Z=1. [Figure 28] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the photodevice in the majority logic circuit of Figure 13, and the variables are X=0, Y=0, and Z=0. [Figure 29]This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the photodevice in the majority logic circuit of Figure 13, and the variables are X=0, Y=0, and Z=1. [Figure 30] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the photodevice in the majority logic circuit of Figure 13, and the variables are X=0, Y=1, and Z=0. [Figure 31] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the photodevice in the majority logic circuit of Figure 13, and the variables are X=1, Y=1, and Z=0. [Figure 32] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the photodevice in the majority logic circuit of Figure 13, and the variables are X=0, Y=1, and Z=1. [Figure 33] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the photodevice in the majority logic circuit of Figure 13, and the variables are X=1, Y=0, and Z=1. [Figure 34] This is a display screen showing the simulation status and results when a disconnection fault occurs at one point in the photodevice in the majority logic circuit of Figure 13, and the variables X=1, Y=1, and Z=1. [Modes for carrying out the invention]

[0035] Embodiments of the present invention will be described below with reference to the drawings.

[0036] The present invention provides a method for configuring logic circuits using photorelays, which are newly developed and becoming widespread as photodevices. This method involves adding a resistor network to the input side of the photorelay to realize multivariable logic functions. Threshold multivariable logic was developed in the early days of computers in relation to domestically produced parametron computers.

[0037] The threshold logic, which originated with the parametron element, is summarized in Non-Patent Document 4 by Professor Saburo Muroga, who was employed at the University of Illinois.

[0038] The threshold logic function f(x) is defined as shown in (Equation 1).

[0039] TIFF2026127717000003.tif50106 (Formula 1)

[0040] wi is the weight, t is the threshold, and xi can take values ​​of 0 or 1. The definition means that when the values ​​of each of the n variables are multiplied by the weight, the sum of the variable terms is defined as 1 if it is equal to or greater than the threshold t, and 0 if the function value is less than or equal to the threshold. Here, wi can be a positive or negative value.

[0041] In this invention, for example, the threshold value inherent to the photorelay is kept constant, and the resistance value of each resistor in the resistor network, which acts as a gate logic circuit connected to the input side, is set to wi to provide a threshold function.

[0042] For example, the output side of a photorelay can conduct current in both directions, and the logical value of the resistance network on the input side of the photorelay can be applied to the conduction function on the output side. Also, for example, the output side of a photorelay can have a hierarchical logical configuration using a network based on the conduction function.

[0043] In a photorelay, a light-emitting diode (LED) that emits light when current flows through it acts as a switch at the input side. On the output side, there is a photodiode (PD) that generates voltage due to the LED's light emission, and a semiconductor device that conducts in both directions based on that voltage. The excitation coil of the electromagnetic relay can be considered the input LED, and the switching mechanism that operates due to the magnetic force when the excitation coil is excited can be considered the output semiconductor device.

[0044] Electromagnetic relays require electrical circuits to compensate for the chattering phenomenon caused by mechanical contacts. Photorelays do not exhibit chattering, so they do not require auxiliary circuits. Furthermore, photorelays have the advantage of achieving faster logical operation than electromagnetic relays, which rely on mechanical movement. The circuit configuration using a resistor network is treated as an analog electrical circuit, and therefore Ohm's law can be applied.

[0045] The electrical energy threshold at which the output side of a photorelay conducts or becomes non-conductive, i.e., the photorelay threshold, is related to a fixed voltage level and the resulting trigger current. An example of the electrical characteristics of the input side of a photorelay is shown in Figure 1.

[0046] The horizontal axis represents the input supply voltage, and the left side of the vertical axis shows the input terminal voltage of the LED terminal, while the right side shows the input current value. Here, an 800Ω series protection resistor is connected. As shown in Figure 1, a photorelay can realize a logic function by utilizing the fact that the input power changes depending on the resistance value. The resistance value on the input side of the photorelay is large before the input terminal voltage exceeds the threshold (measured results show over 50kΩ), and almost no current flows. However, once the input terminal voltage exceeds the threshold, the internal resistance becomes a few ohms or less (measured results show), and current flows. In other words, the resistance value on the input side of the photorelay changes greatly depending on the input terminal voltage. In previous threshold logic circuits, the coefficient of wi only focused on voltage, but with photorelays, it is necessary to handle the logic configuration including the current change due to the threshold. For example, a photorelay that can supply a maximum current of 5A using AC / DC voltage requires a current of 3mA or more and a power of 5.4mW to turn on the output side at an input voltage of 1.8V, and it has been confirmed that even if the voltage is increased to 1.8V or higher, the output side will not turn on if no current flows. The resistance values ​​can differ by tens of thousands of times or more across a threshold, and this difference is used to configure the logical operation. Generally, electromagnetic relays do not have such a clear threshold. Also, as shown in Figure 1, the input side of a photorelay has a threshold of about 1V due to the LED.

[0047] In this specification, a logic circuit that utilizes the threshold value on the input side of a photorelay is also called a threshold logic function. The symbols used in this specification are defined below.

[0048] Definition of voltage variables (unit: volts) Input supply voltage (input supply voltage of the resistor network) E Voltage V that exceeds the threshold and turns on on Voltage V that does not exceed the threshold and turns off off Voltage V at the photorelay input LED terminal k Definition of current variables (unit: milliamperes) Maximum allowable input current for photorelay I max The trigger current I that causes the photorelay to turn Von min Current I that maintains the input voltage in the Von state on Based on the characteristic that the internal resistance value on the input side of a photorelay changes by tens of thousands of times or more around a threshold, this explains the fundamental aspects of resistor network configurations that can be applied to threshold logic.

[0049] Figure 2 shows the resistor network connected to the input side of the photorelay.

[0050] The resistor network 20 has a first resistor group 21 and a second resistor group 22, each consisting of resistors corresponding to the input of a logic function. The resistor network 20 is configured to supply a power supply voltage E to one terminal of the input side 12 of the photorelay 10 through the resistors of the first resistor group 21, according to the input of a logic function. The resistor network 20 is configured to connect the resistors of the second resistor group 22 in parallel between the two terminals of the input side 12 of the photorelay 10, according to the input of a logic function. Such a resistor network 20 is constructed based on a threshold logic function f(x) such that the logic value corresponding to the input of the logic function becomes the conduction function of the output side 11 of the photorelay 10.

[0051] Here, we define the representation of resistance values ​​as follows.

[0052] Internal resistance value R of the input side 12 of the photorelay 10 i Resistance value R of the first group of resistors 21 s Resistance value R of the second group of resistors 22 p As mentioned earlier, when the input to the photorelay 10 exceeds a threshold, the internal resistance R i Since the resistance value is low, around a few ohms, even with a supply voltage of 3 volts, a current of several amperes will flow, causing damage. Therefore, a protective resistor R is used to prevent exceeding the absolute maximum value. s They need to be connected in series.

[0053] When the input internal resistance of the photorelay 10 changes, the current flowing through the surrounding resistance network 20 also changes. In this specification, the logical values ​​of the output side 12 are defined as conduction variables, and the input side 11 is defined as having a logical value of 1 for power supply connection and a logical value of 0 for ground connection. However, this is only one example.

[0054] The reason for setting the ground connection to a logical value of 0 is that the threshold logic configuration at the input side 11 of the photorelay 10 depends on voltage and the logic function can be changed by current, so this is necessary to ensure logically accurate operation. It has been confirmed that the function changes if the connection is simply disconnected instead of grounded. Failures at the input side 11 and output side 12 of the photorelay 10 are the subject of a separate theory.

[0055] A more detailed explanation will be given regarding the resistor network 20, which has n switches corresponding to n variables connected to the input side 11 of the photorelay 10.

[0056] The switch section 23, which consists of changeover switch contacts corresponding to the values ​​of each variable in Figure 3, is a switch designed to clearly explain that the logical value is 1 when connected to the input supply voltage E and the logical value is 0 when connected to ground. The function corresponding to these switch contacts can also be replaced by a photorelay.

[0057] In the resistor network 20 of Figure 3, if all the switch sections 23 are connected to the ground side, terminal R in the figure... t According to Ohm's law, the resistance value R s When the voltage is connected to ground at / n, and the entire switch section 23 is connected to the input supply voltage E, terminal R t Similarly, the resistance value R s / n is connected to the input supply voltage E.

[0058] Here, we define k as a number that represents the state in which any k switch units 23 are connected to the power supply E side and the remaining n-k units are connected to the ground side. Using this value of k, the resistance value on the power supply E side shown in Figure 3 is R as shown in Figure 4. s / k is the resistance value on the grounded side, and R is the resistance value on the grounded side. s It is / (n-k).

[0059] If the voltage at the input side 11 of the photorelay 10 does not exceed the threshold value, the internal resistance value R of the input side 11 of the photorelay 10 will be used. i >>R s Since / (n-k), R i The value of is considered to be approximately infinite, and the resistance value of R is low. s It is acceptable to use only / (n-k). Therefore, as shown in Figure 5, the photorelay 10 can be treated as if it were disconnected from the resistor network 20.

[0060] If the input terminal voltage exceeds the threshold, reverse and R s / (n―k)>>R i Next, the internal resistance R i The resistance is approximately a few ohms. s The value of / (n-k) is R i If it is several orders of magnitude larger, R i Assuming it is approximately 0, the input supply voltage E is R as shown in Figure 6. s Grounding can be done using / k.

[0061] Based on the above assumptions, the voltage V on the input side 11 of the photorelay 10 is determined when k switch units 23 are connected to the input supply voltage E and the remaining nk switch units 23 are connected to ground. k The following equation holds true depending on the supply voltage E.

[0062] TIFF2026127717000004.tif51131 (Formula 2)

[0063] Input LED voltage V k <V off In this case, the state shown in Figure 5 is obtained, and the current I flowing through the resistor network 20 is given by the following equation.

[0064] TIFF2026127717000005.tif3883 (Formula 3)

[0065] Input terminal voltage V k >V on In this case, the state will be as shown in Figure 6, and the R of the resistor network 20 s The potential difference across the k terminals is EV onTherefore, the resistance value of the input side 11 of the photorelay 10 can be considered to be Ri ≈ 0, and the current flowing is given by the following equation.

[0066] TIFF2026127717000006.tif4173 (Formula 4)

[0067] In the logic circuit 1 shown in Figure 2, one end of the parallel-connected photorelay 10 and second resistor group 22 is grounded. However, the present invention is not limited to this, and a predetermined voltage other than 0 may be applied to one end of the parallel-connected photorelay 10 and second resistor group 22. Furthermore, as shown in Figure 7, a variable voltage power supply 26 capable of applying a desired positive voltage and / or negative voltage may be connected to one end of the parallel-connected photorelay 10 and second resistor group 22 to configure logic circuit 1'. By varying the voltage of the variable voltage power supply 26, one of the desired logic functions, such as an OR logic function, an AND logic function, or a majority logic function, can be selected.

[0068] Here, as shown in Figure 8, the logic function differs depending on whether a resistor 25, separate from the conventional resistor network 20, is connected in parallel to the input side 11 of the photorelay 10, or whether such a resistor 25 is not connected in parallel (see Figure 4). These cases will be explained below.

[0069] <Without resistor 25> As shown in Figure 4, an embodiment is described in which there is no resistor 25 for parallel connection to the input side 11 of the photorelay 10. In this case, the photorelay 10 is of the normally open type, and this photorelay 10 is used to construct a logic circuit of an OR logic function.

[0070] In Figure 4, when k=0, i.e., all inputs are grounded, V k Since = 0, there is no continuity on the output side 12 of the photorelay 10.

[0071] The OR logic function can be constructed by setting thresholds such that when the logical value of any one variable is 1, the output side 12 of the photorelay 10 is 1 and the remaining n-1 variables are 0. The threshold here refers to the electrical energy threshold for switching between conduction and non-conductivity on the output side of the photorelay. Electrical energy is voltage and current, as shown in Figure 1.

[0072] Therefore, if we set k=1 in (Equation 2), the OR logic function for n variables is given by the following equation, which is independent of the resistance value, so the number of input variables can be determined only by the input supply voltage. The maximum value of n can be determined only by the input supply voltage E.

[0073] V1=E / n=V on (Formula 5) The current exceeding the threshold is given by the following equation (Equation 3).

[0074] I on =(EV on ) / R s >I min (Formula 6) Here, when configuring the threshold logic function using the photorelay 10, it is important to note that the maximum allowable current I of the photorelay 10 is set on the input side 11 (LED) of the photorelay 10. max There is.

[0075] The resistance value when all n variables are 1 is R. s Since / n, the following equation represents all current limiting conditions for the threshold logic function of photorelay 10.

[0076] (EV on ) / (R s / n) max (Formula 7) <When there is a resistance of 25> Figure 8 shows the resistance value R between the input terminals 11 of the photorelay 10 according to this embodiment. p This is a circuit diagram of the logic circuit when the parallel resistors 25 are connected in parallel. The photorelay 10 is of the normally open type.

[0077] ​ While the OR logic function can be configured without connecting a resistor in parallel to the input side of the photorelay, the AND logic function and the majority logic function require a resistor 25 to be connected in parallel between the input terminals 11 of the photorelay 10, as shown in Figure 8, in order to accurately set the threshold.

[0078] In Figure 8, if k of the n inputs are connected to the input supply voltage side with a logical value of 1, and the remaining n-k variables are connected to ground with a logical value of 0, the resulting parallel connection resistance R will be... t The equation is as follows:

[0079] TIFF2026127717000007.tif38169 (Formula 8)

[0080] Since k switch units 23 are connected between the power supply E and the input terminal 11 of the photorelay 10, the resistance value is R s An equivalent resistance of / k is connected in series. Therefore, k of the n switch units 23 are connected to the power supply side, and the resistance R between the input voltage E and ground (right side in the figure) is R in Figure 8. k The equation is as follows:

[0081] TIFF2026127717000008.tif30170 (Formula 9)

[0082] Voltage V across the input terminal 11 (LED) of the photorelay 10 k R is the resistance value between the input supply voltage E and ground. k Let R be the denominator and the resistance value between the terminals t It is given by the following equation with as the numerator.

[0083] TIFF2026127717000009.tif39118 (Formula 10)

[0084] Add R to equation (10) s / R p When we simplify by setting =m, we get V k The following simplified equation is obtained to determine the value of .

[0085] Vk = E·k / (n+m) (Equation 11) The meaning of this (Equation 11) is that when the number of input variables is n and k of the n switch units 23 corresponding to the variables are connected to the power supply side, the resistance value R s and the resistance value R p the voltage V applied between the terminals of the input side 11 of the photo relay 10 is given by the ratio m of k is given by (Equation 11). The threshold logic function can be set based on (Equation 11) by setting which integer of k for the threshold of the photo relay 10 with n input variables.

[0086] By setting the value of k, an AND logic function and a majority logic function can be configured as follows.

[0087] 〈AND Logic Function〉 The AND logic function is configured by the circuit shown in FIG. 8, and the photo relay 10 is of the normally open type.

[0088] Since the AND logic function becomes 1 only when the logical values of all variables of the n variables become 1, in (Equation 10), when k = n, the value V n when all variable logical values are 1 is set to a voltage higher than the threshold value V on Therefore, the following equation is the condition.

[0089] V n = E / (1 + m / n)> V on (Equation 12) Also, when setting the threshold value of the AND logic function to 0 up to n - 1 variables, it is necessary to make it a voltage lower than V off To satisfy this condition, when k in (Equation 11) is set to n - 1 and V n―1 the following equation is also a condition.

[0090] V n―1 = E·(n - 1) / (n + m)< V off (Equation 13) When all variables of the AND logic function become 1, since the resistance value becomes R s / n, I on becomes the following equation.

[0091] I on =( E―V on ) / (R s / n)>I min (Formula 14) <Majority Rule Logic Function> The majority voting logic function is similarly constructed using the circuit shown in Figure 8, and the photorelay 10 is of the normally open type.

[0092] A majority logic function is a majority logic function that satisfies any n and the smallest integer k > n / 2, and any majority logic function can be constructed from equation (11) under the following condition.

[0093] V k =E·k / (n+m)>V on (Formula 15) The majority logic function is subject to the same constraints as the AND logic function, as shown in the following equation.

[0094] V k―1 = E·(k-1) / (n+m) <V off (Formula 16) I exceed the threshold of the majority logic function on The equation is as follows: I on =( E―V on ) / (R s / k)>I min (Formula 17) <NAND logic function, NOR logic function> By using a normally closed type photorelay 10 and configuring the resistor network 20 in the same way as in the case of the OR logic function described above, a logic circuit 1 that realizes the NOR logic function can be constructed.

[0095] By using a normally closed type photorelay 10 and configuring the resistor network 20 in the same way as in the case of the AND logic function described above, a logic circuit 1 that realizes a NAND logic function can be constructed.

[0096] <EXOR (exclusive OR) logic function> Figure 9 shows the configuration of a logic circuit that implements an EXOR logic function according to one embodiment of the present invention.

[0097] As shown in Figure 9, the logic circuit 30 that implements the EXOR logic function includes first and second photorelays 40 and 50, and a resistor network 60.

[0098] The first and second photorelays 40 and 50 are both normally open type, and the output side 41 of the first photorelay 40 and the output side 51 of the second photorelay 50 are connected in parallel. Let X be the output value, that is, the value of the conduction function.

[0099] The resistor network 60 connects a first switch unit 61, which switches the connection between the power supply and ground in accordance with the first variable A of the EXOR logic function, to one end of the input side 42 of the first photorelay 40, and a second switch unit 62, which switches the connection between the power supply and ground in accordance with the second variable B of the EXOR logic function, to one end of the input side 52 of the second photorelay 50. The first and second switch units 61 and 62 are connected to the other ends of the input sides 42 and 52 of the first and second photorelays 40 and 50 via resistors 63 and 64.

[0100] Here, the EXOR logical function is a logical function in which X is 0 if the first variable A and the second variable B are equal in value, and X is 1 if they are different in value.

[0101] When the first variable A and the second variable B are connected to ground or the supply voltage, the potential becomes below the threshold, so no current flows through the input sides 42 and 52 of the first and second photorelays 40 and 50.

[0102] Therefore, since no current flows through either the input sides 42 and 52 of the first and second photorelays 40 and 50, the value of the conduction function is X=0. If either the first variable A or the second variable B remains grounded and the supply voltage is applied to the other, resistors 63 and 64 are connected in series, so a voltage equivalent to half the input voltage is generated on one side, causing conduction on the output sides 41 and 51. Since the output sides 41 and 51 are connected in parallel, if either one conducts, the value of the conduction function becomes X=1.

[0103] Furthermore, the resistance values ​​of the two resistors 63 and 64 satisfy the necessary resistance value requirement by keeping within the input current limiting current set by the photorelays 40 and 50, as described above, depending on the input supply voltage E. Also, when the output sides 41 and 51 conduct, a reverse voltage is applied to the photorelay 40 or 50 that is not involved in the conduction, so the allowable reverse voltage V rev The input supply voltage E must be as follows:

[0104] <Logic circuits with FTC (Fault Tolerant Circuit) functionality and fault detection functionality> Figure 10 shows the configuration of a logic circuit having FTC function and fault detection function according to one embodiment of the present invention.

[0105] The logic circuit 70 shown in Figure 10 has a relay group 71 consisting of first to fourth logic circuits E1, E2, E3, and E4, each with the same configuration and receiving the same logic function variables as inputs. Each of the first to fourth logic circuits E1, E2, E3, and E4 is, for example, a logic circuit 1 that implements the majority voting logic function described in the above embodiment.

[0106] In the relay group 71, the output side of the first logic circuit E1 (the output side 12 of the photorelay 10 of logic circuit 1 shown in Figure 1, and so on) and the output side of the second logic circuit E2 are connected in series, the output side of the third logic circuit E3 and the output side of the fourth logic circuit E4 are connected in series, and the output sides of the first logic circuit E1 and the second logic circuit E2, which are connected in series, and the output sides of the third logic circuit E3 and the fourth logic circuit E4, which are connected in series, are connected in parallel. ij is the output side (conductivity function value) of this relay group 71, that is, the logic circuit 70.

[0107] The bidirectional LED 72, acting as a detection unit, is interposed between a first connection point between the output side of the first logic circuit E1 and the output side of the second logic circuit E2, and a second connection point between the output side of the third logic circuit E3 and the output side of the fourth logic circuit E4. It lights up when current flows in either direction between these connections. The bidirectional LED 72 detects the presence or absence of current flow between the first and second connection points. The detection unit only needs to have this function and is not limited to a bidirectional LED. For example, a pair of light-emitting diodes with different conductive directions may be used.

[0108] Figure 10 shows the case where the first logic circuit E1 has a fault and the output value remains 0. The second and third logic circuits E2, E3, and E4 are functioning normally and without faults, and even if the output values ​​of the second and third logic circuits E2, E3, and E4 become 1, the output value of the first logic circuit E1 remains 0. Therefore, current flows not only to the output side of the fourth logic circuit E4 but also to the second logic circuit E2 via the third logic circuit E3, causing the bidirectional LED 72 to light up. As a result, even if one of the four logic circuits E2, E3, and E4 fails, the normal function of the majority logic function can be maintained, and it is possible to detect that there is a fault in one of the four logic circuits E2, E3, and E4. In the logic circuit 70 according to this embodiment, each logic circuit E2, E3, and E4 implements the majority logic function with one photorelay, so such a function can be realized with four photorelays, that is, a very small number of photorelays.

[0109] Furthermore, the present invention can also be applied to logic circuits that implement logic functions other than the majority-voting logic function described above, as well as other logic functions according to the embodiments already described.

[0110] <Logic circuits that have been converted to FTC> Figure 11 shows an example of a logic circuit configuration using FTC.

[0111] In Figure 11, X, Y, and Z represent the variables of the majority logic function, and the input sides of the six photodevices correspond to these variables: X, Y, and Z. For example, if variable X is 0, the output sides of the six photodevices are 0, and if variable X is 1, the output sides of the six photodevices are 1.

[0112] In other words, this logic circuit 80 has first to fourth photodevices to which the first variable (X) of the majority logic function is input, fifth to eighth photodevices to which the second variable (Y) of the majority logic function is input, and ninth to twelfth photodevices to which the third variable (Z) of the majority logic function is input.

[0113] The logic circuit 80 has a conduction variable f on the output side of the logic circuit 80. ij In that case, the logical formula is f ij =XYXY+XZXZ+YXYX+YZYZ+ZYZY+ZXZX The output sides of the first to twelfth photodevices are connected to satisfy the condition. The logic circuit 80 shown in Figure 11 illustrates this connection configuration.

[0114] Here, when a voltage is applied between i and j in the logic circuit 80, and current flows from i to j, the current i is input to three output sides of a photodevice: the first variable (X) of the majority logic function is input to the input side of the photodevice; the second variable (Y) of the majority logic function is input to the input side of the photodevice; and the third variable (Z) of the majority logic function is input to the input side of the photodevice. Let the outputs of these three output sides be X, Y, and Z, respectively.

[0115] X is input to two output sides of a photodevice: one where the second variable (Y) of the majority logic function is input, and the other where the third variable (Z) of the majority logic function is input. Let the outputs of these two output sides be XY and XZ, respectively.

[0116] Y is input to two output sides of a photodevice: the first variable (X) of the majority logic function is input to the input side, and the third variable (Z) of the majority logic function is input to the input side. Let the outputs of these two output sides be YX and YZ, respectively.

[0117] Z is input to two output sides of a photodevice: one where the second variable (Y) of the majority logic function is input, and the other where the first variable (X) of the majority logic function is input. Let the outputs of these two output sides be ZY and ZX, respectively.

[0118] XY is input to one output side of a photodevice, where the first variable (X) of a majority logic function is input to the input side. Let the output of this single output side be XYX.

[0119] XZ is input to one output side of a photodevice, where the first variable (X) of a majority logic function is input to the input side. Let the output of this single output side be XZX.

[0120] YX is input to one output side of a photodevice, where the second variable (Y) of a majority logic function is input to the input side. Let the output of this single output side be YXY.

[0121] YZ is input to one output side of a photodevice, where the second variable (Y) of a majority logic function is input to the input side. Let the output of this single output side be YZY.

[0122] ZY is input to one output side of a photodevice, where the third variable (Z) of a majority logic function is input to the input side. Let the output of this single output side be ZYZ.

[0123] ZX is input to one output side of a photodevice, where the third variable (Z) of a majority logic function is input to the input side. Let the output of this single output side be ZXZ.

[0124] YXY and ZXZ are input to one output side of a photodevice, where the first variable (X) of the mathematical logic function is input. Let the output of this single output side be YXYX + ZXZX.

[0125] XYX and ZYZ are input to one output side of a photodevice to which the second variable (Y) is input. Let the output of this single output side be XYXY + ZYZY.

[0126] YZY and XZX are input to one output side of a photodevice, where the third variable (Z) of the majority logic function is input. Let the output of this single output side be YZYZ + XZXZ.

[0127] Therefore, the output on the j side will be YXYX+ZXZX+XYXY+ZYZY+YZYZ+XZXZ.

[0128] In other words, in the logic circuit 80 configured in this way, f ij =XYXY+XZXZ+YXYX+YZYZ+ZYZY+ZXZX This is true.

[0129] In the logic circuit 80 shown in Figure 11, even if there is a fault such as a break in the wire or a short circuit in the photodevice corresponding to X circled in the diagram, the normal function as a majority-voting logic function can be maintained. This will be explained later in the section on "Simulation Method of Logic Circuits Using Logic Circuits".

[0130] It is known that a logic circuit that implements a majority voting logic function using relays can withstand a single failure by implementing a quadruple redundancy FTC. In contrast, the logic circuit 80 according to this embodiment can be triple-redundant, as shown in Figure 11, and can be constructed with 18 photodevices. Therefore, the number of photodevices can be reduced.

[0131] Furthermore, this invention is also applicable to electromagnetic relays and the like.

[0132] <Sensors capable of detecting faults such as broken wires> Figure 12 is a circuit diagram showing the configuration of a sensor capable of detecting faults such as wire breaks according to an embodiment of the present invention.

[0133] As shown in Figure 12, the sensor 140 includes a sensor switch 101 and a normally open photorelay 103 connected in series with the sensor switch 101 via a cable 105. One end of the sensor switch 101 is connected to cable 105, and the other end is grounded. One end of the input side of the photorelay 103 is connected to cable 105, and the other end is connected to power supply E, to which a 3V DC voltage is applied. A resistor 102 is connected in parallel with the sensor switch 101, and a resistor 108 is connected in series with the input side of the photorelay 103. A resistor 110 for setting a threshold is connected in parallel with the input side of the photorelay 103. An LED 109 that lights up at approximately 0.5mA for fault detection is interposed in parallel with the input side of the photorelay 103. One end of the LED 109 is connected to cable 105 via resistor 107, and the other end of the LED 109 is connected to power supply E.

[0134] When the sensor switch 101 is closed, a voltage below the threshold is applied to the photorelay 103, causing it to close in the same way as the sensor switch 101. When the sensor switch 101 is closed, a voltage above the threshold is applied to the photorelay 103, causing it to close in the same way as the sensor switch 101. As a result, the sensor 140 detects the closed / closed state of, for example, the distant sensor switch 101 at the output side of the photorelay 103.

[0135] In this embodiment, with the power supply E voltage set to 3V, the resistance of resistor 102 was set to 1KΩ, the resistance of resistor 108 to 1KΩ, the resistance of resistor 107 to 2KΩ, and the resistance of resistor 110 to 2KΩ. When the power supply E voltage was set to 5V, the resistance of resistor 110 was set to 470Ω. In other words, in this embodiment, a high-resistance resistor 102 is connected in parallel to the normally open sensor switch 101, and the conduction state is constantly monitored with a low voltage and current. When the sensor switch 101 is closed, a voltage and current exceeding the threshold of the photorelay 103 are applied.

[0136] In the sensor 140 according to this embodiment, the fact that the LED 109 lights up with approximately 0.5mA is utilized to check the continuity state by flowing a weak current through the LED 109. That is, when the sensor 140 is functioning normally, the power supply E is connected to the ground side of the sensor switch 101 via the resistor 107, a weak current flows and the LED 109 lights up. However, if there is a break in the cable 105 or a poor contact in a connector (not shown), the power supply E is no longer grounded via the resistor 107, no current flows and the LED 109 turns off. As a result, the sensor 140 according to this embodiment can constantly monitor for breaks in the cable 105 or poor contact in a connector (not shown) using the LED 109.

[0137] In the above embodiment, the sensor switch 101 is normally open, but if it is normally closed, a failure of the sensor switch 101 can also be detected and distinguished from a failure of the photorelay 103 system.

[0138] In this invention, a photorelay may be used instead of the LED 109. Alternatively, the photorelay 103 and the LED 109 (or photorelay) may be connected in series.

[0139] <Methods for simulating logic circuits> In the conduction function simulator according to this embodiment, typically, a computer system has a program implemented in which a logic circuit using relay elements is constructed on its screen, which serves as a display unit, and a simulation of that logic circuit is performed.

[0140] In the conduction function simulator according to this embodiment, circuit elements such as relay elements and connecting lines each exist as a single object. By placing the circuit elements on the screen and connecting them with connecting lines, a logic circuit using relay elements can be constructed, and its simulation can be executed. Specifically, it is as follows:

[0141] The circuit elements handled by the conduction function simulator according to this embodiment include relay elements and connecting wires, as well as a power supply and resistors. The relay elements include magnetic relays and photorelays.

[0142] Magnetic relays come in three types: open in the de-energized state (a-contact), closed in the de-energized state (b-contact), and contact switching between de-energized and energized states (c-contact). They also have an energization terminal (sw). Therefore, the terminals are {r, a, b, sw}.

[0143] Photo relays come in two types: normally open (type a) and normally closed (type b).

[0144] The connecting wire treats the connection between contacts as a connection between two points. The power supply has two values ​​for the magnetic relay: logic (potential) [Zero, True] and excitation [ON, OFF]. The excitation value indicates that the relay will react when the two terminals of switch (sw) have opposing logic values. In actual simulations, if no connection wire is made to terminal switch, the excitation value can be directly input to switch. The photorelay will be handled with three values: logic (potential) [Uncertain, Zero, True], and the evaluation of these values ​​will be as shown in the truth table for the element below.

[0145] [Table 1]

[0146] In circuit design, when connecting the switch terminals individually, the excitation value can be obtained by passing a logical value through them.

[0147] In the conduction function simulator according to this embodiment, the following is used as test data.

[0148] For contact excitation Number of test patterns: Rn Contact name list: ["R1","R2",···,"Rx"] Input data: [[Data column corresponding to contact name] × Rn] For power supply Number of test patterns: Pn Power supply name list: ["PowerR1", "PowerR2", ..., "PowerRx"] Input data: [[Data column corresponding to power supply name] × Pn] The overview of logical calculations is as follows:

[0149] (1) Relay logic circuits are undirected graphs in which current flows in both directions, and therefore cannot be treated like general logic simulators. For this reason, we decided to investigate the phenomenon that current flows from the higher potential to the lower potential.

[0150] (2) Verification algorithm a. Initialize (set to zero) all contacts and terminals of the connecting wires.

[0151] i. Provide excitation data to the contacts and apply power (set to True).

[0152] U. According to the distinction between contacts a, b, and c, the True value is passed in the direction of the Zero value, and the result is set to True.

[0153] E. For the connecting lines as well, the True value is passed in the direction of the Zero value, making it True.

[0154] O. Repeat steps U through E for a number of stages equal to or greater than the number of connections in the relay logic circuit.

[0155] (3) Test data pattern a. The data sequence for the logic circuit is transmitted via an excitation pattern.

[0156] I. Therefore, the power supply application pattern is the single pattern determined during the circuit design, and the simulation of the relay logic circuit is completed.

[0157] (c) The bidirectional nature of the circuit and the identification of fault locations can be verified by applying power supply patterns to arbitrary locations.

[0158] E. Therefore, the simulation will involve simulating the number of times the excitation test pattern Rn × the power supply test pattern Pn is performed.

[0159] Here, to evaluate the effectiveness of the undirected graph as a circuit, we simulated current flowing from higher potential to lower potential. Therefore, after simulating one state, the voltage at each terminal must be cleared to zero. This is a necessary procedure for simulating electrical circuits as undirected graphs. In the real world, a value of zero indicates a grounded state, and therefore must always be zero.

[0160] In other words, the conduction function simulator according to this embodiment constructs a logic circuit by connecting various circuit elements such as relay elements and connecting wires, inputs a voltage corresponding to the variables of the logic function to the input side of the relay element, and shows the voltage application state of each circuit element as current flowing from the terminal with the higher potential to the terminal with the lower potential at both terminals of each circuit element, and obtains the conduction variable as the logic value of the logic function from the output side of the relay element.

[0161] Conventional logic simulators use AND and OR logic gates, and the direction of current is unidirectional. Therefore, in the case of relay elements including magnetic relays and photorelays, where current flows in both directions, it is necessary to set a conduction function for each direction of current flow and perform multiple simulations. In contrast, the conduction function simulator according to this embodiment only requires performing one simulation. Furthermore, the conduction function simulator according to this embodiment can handle not only DC but also AC.

[0162] Next, we will describe an example of simulating the FTC-enabled logic circuit shown in Figure 11 using the conduction function simulator according to this embodiment.

[0163] Figure 13 shows the state after launching a program that simulates a logic circuit using a photorelay on a computer system, and configuring the FTC-enabled logic circuit shown in Figure 11 on the screen.

[0164] In Figure 13, the configured logic circuit is shown in most of the upper area of ​​the screen. In this circuit, the areas enclosed by rectangular boxes are circuit elements, excluding the connecting lines. Dotted lines indicate connecting lines. Connecting lines are shown as dotted lines when no voltage is applied (grounded), and become solid lines when voltage is applied.

[0165] The rectangular boxes in the lower part of the screen contain buttons for executing various commands. For example, clicking the "Simulation" button will run a simulation of the logic circuit displayed on the screen. Alternatively, clicking a specific part of the logic circuit on the screen and then clicking "Set Fault" will set that part as a fault. Faults can be set to include, for example, open or short-circuited connection lines or relay elements.

[0166] The simulation results are displayed in the area between the circuit display area at the top of the screen and the command button display area at the bottom of the screen.

[0167] Figure 13 shows the state after all contacts and terminals of the connecting wires have been initialized (set to Zero) (as described in "(2) Verification Algorithm A." above). Note that in this state, no results are shown in the simulation results display area of ​​Figure 13.

[0168] The simulation is performed from the state shown in Figure 13.

[0169] In other words, as described in "(2) Verification Algorithm" above, i. Provide excitation data to the contacts and apply power (set to True).

[0170] U. According to the distinction between contacts a, b, and c, the True value is passed in the direction of the Zero value, and the result is set to True.

[0171] E. For the connecting lines as well, the True value is passed in the direction of the Zero value, making it True.

[0172] O. Repeat steps U through E for a number of stages equal to or greater than the number of connections in the relay logic circuit.

[0173] Figure 14 shows the application of excitation data to the contacts "X0_E-net" to "X5_E-net", "Y0_E-net" to "Y5_E-net", and "Z0_E-net" to "Z5_E-net", with the power supply "Y0_E-net.r" being applied (set to True) (Verification Algorithm I). At that time, "Verification Algorithm U" and "Verification Algorithm D" are executed. The simulation result in Figure 14 shows that the grounded side (Z5_E-net.a) is Zero.

[0174] The simulation results displayed in the display area of ​​Figure 14 X0_E-net.sw0,Y0_E-net.sw0,Z0_E-net.sw0,Y0_E-net.r,Z5_E-net.a Zero, Zero, Zero, True, Zero This illustrates the situation described above.

[0175] In other words, the situation in Figure 14 shows that in the majority logic circuit shown in Figure 11, when X=0, Y=0, and Z=0, the logical value of this majority logic circuit is 0.

[0176] Figure 15 shows the results when X=0, Y=0, and Z=1. (The bottom row of the simulation results display area, and so on.) Figure 16 shows the results when X=0, Y=1, and Z=0.

[0177] Figure 17 shows the results when X=1, Y=1, and Z=0.

[0178] Figure 18 shows the results when X=0, Y=1, and Z=1.

[0179] Figure 19 shows the results when X=1, Y=0, and Z=1.

[0180] Figure 20 shows the results when X=1, Y=1, and Z=1.

[0181] This completes the "Verification Algorithm O," meaning that steps U through E have been repeated more times than the number of stages in the relay logic circuit.

[0182] From the above simulation results, it can be confirmed that the majority-voting logic circuit shown in Figure 11 is functioning correctly.

[0183] As previously described, for example, by clicking on a specific part of the logic circuit on the screen shown in Figure 13 and then clicking "Set Fault," that specific part can be set as a fault. Examples of faults that can be set include open or short circuits in connecting wires or relay elements.

[0184] Figure 21 shows a screen with a simulation setting to check whether this FTC-enabled relay element will function correctly as a majority-rule logic circuit when one of the connecting wires is broken. In the figure, a "0" with an "x" superimposed on it is called a 0 fault and means a broken wire. A "1" with an "x" superimposed on it is called a 1 fault and means a short circuit.

[0185] The simulations corresponding to Figures 14 to 20 are shown in Figures 22 to 27.

[0186] Figure 28 shows a screen where a simulation has been set up to check whether the FTC-modified relay element will function normally as a majority-ruling logic circuit when one of the photo-devices acting as a relay element is disconnected.

[0187] The simulations corresponding to Figures 14 to 20 are shown in Figures 28 to 34.

[0188] It can be seen that the values ​​in the simulation result display area in Figure 27 and the simulation result display area in Figure 34 match the values ​​in the simulation result display area in Figure 20. Therefore, the simulation according to the present invention can be verified to show that even if there is a fault such as an open circuit or short circuit in one circuit element of the FTC-modified relay element 80 shown in Figure 11, it can maintain normal function as a majority-voting logic function.

[0189] Furthermore, the simulator according to the present invention allows users to set up a circuit to be simulated by placing objects corresponding to circuit elements on the screen, and to grasp the flow of current and other factors in the simulation on the screen. Therefore, for example, if there is a problem with the circuit design, the cause can be intuitively grasped visually.

[0190] The present invention is not limited to the embodiments described above, and can be implemented in various modified forms, with the scope of such implementation also falling within the technical scope of the present invention. [Explanation of Symbols]

[0191] 1. Logic Circuits 10 Photo Relay 11. Input side of photorelay 12. Output side of photorelay 20 resistance net 21. First group of resistors 22 Second group of resistors E Input supply voltage 1' Logic Circuit 23 Switch Section 24 Resistor 25 Parallel Resistor 26 Variable Voltage Power Supply 30 Logic Circuit 40 First Photo Relay 41 Output Side of the First Photo Relay 42 Input Side of the First Photo Relay 50 Second Photo Relay 51 Output Side of the Second Photo Relay 52 Input Side of the Second Photo Relay 60 Resistance Network 61 First Switch Section 62 Second Switch Section 63 Resistor 64 Resistor 70 Logic Circuit 71 Relay Group 72 Bidirectional LED E1 First Logic Circuit E2 Second Logic Circuit E3 Third Logic Circuit E4 Fourth Logic Circuit 80 FTC-Converted Logic Circuit 140 Sensor 101 Sensor Switch 102 Resistor 103 Normally Open Photo Relay 105 Cable 107 Resistor 108 Resistor 109 LED

Claims

1. A logic circuit using a photorelay to implement a logic function, Photo relay and A resistor network including n resistors, each corresponding to n input variables (where n is an integer of 2 or more) of the aforementioned logic function, It is equipped with, Each i-th resistor in the resistor network (where i is an integer between 1 and n) has a resistance value corresponding to the weight wi in the threshold decision function. The i-th resistor is configured to switch between a first connection state, in which the power supply voltage is supplied to one terminal on the input side of the photorelay via the resistor when the logical value of the i-th input variable is 1, and a second connection state, in which the one terminal on the input side of the photorelay is grounded via the resistor when the logical value of the i-th input variable is 0, depending on the logical value of the input variable. Depending on the combination of logical values ​​of the n input variables, the electrical energy based on the voltage applied to the input side of the photorelay and the current flowing through it changes. The resistance values ​​of each resistor in the resistor network are set in accordance with the weight wi such that the following threshold determination function f(x) corresponds to the relationship between the electrical energy applied to the input side of the photorelay and the threshold value t of the photorelay. Here, xi is the value of the i-th input variable (0 or 1), The aforementioned photorelay is of the normally open type or the normally closed type. If the photorelay is of the normally open type, when f(x) = 1, the output side of the photorelay is in a conductive state, and when f(x) = 0, the output side of the photorelay is in a non-conductive state. If the photorelay is of the normally closed type, the output side of the photorelay will be in a non-conductive state when f(x) = 1, and the output side of the photorelay will be in a conductive state when f(x) = 0. A logic circuit using a photorelay.

2. A logic circuit using a photorelay as described in claim 1, The photorelay further comprises a parallel resistor connected in parallel between both input terminals of the aforementioned photorelay. A logic circuit using a photorelay.

3. A logic circuit using a photorelay as described in claim 2, The aforementioned logic function is an AND logic function, The aforementioned photorelay is of the normally open type. The resistance values ​​of each resistor in the aforementioned resistor network are all set to the same value Rs. Let E be the input supply voltage from the power supply, Von be the threshold voltage at which the photorelay turns on, Voff be the threshold voltage at which the photorelay turns off, and let Rs / Rp = m (where Rp is the resistance value of the parallel resistor), E / (1+m / n)>Von E・(n-1) / (n+m)<Voff Configured to satisfy, The output side of the photorelay becomes conductive when the logical values ​​of all n input variables are 1, and the output side of the photorelay becomes non-conductive when the logical value of at least one of the n input variables is 0. A logic circuit using a photorelay.

4. A logic circuit using a photorelay as described in claim 2, The aforementioned logic function is a NAND logic function, The aforementioned photorelay is of the normally closed type, The resistance values ​​of each resistor in the aforementioned resistor network are all set to the same value Rs. Let E be the input supply voltage from the power supply, Von be the threshold voltage at which the photorelay turns on, Voff be the threshold voltage at which the photorelay turns off, and let Rs / Rp = m (where Rp is the resistance value of the parallel resistor), E / (1+m / n)>Von E・(n-1) / (n+m)<Voff Configured to satisfy, The output side of the photorelay becomes non-conductive when the logical values ​​of all n input variables are 1, and the output side of the photorelay becomes conductive when the logical value of at least one of the n input variables is 0. A logic circuit using a photorelay.

5. A logic circuit using a photorelay as described in claim 2, The aforementioned logic function is a majority-vote logic function, The aforementioned photorelay is of the normally open type. The resistance values ​​of each resistor in the aforementioned resistor network are all set to the same value Rs. Let E be the input supply voltage from the power supply, Von be the threshold voltage at which the photorelay turns on, Voff be the threshold voltage at which the photorelay turns off, Rs / Rp = m (where Rp is the resistance value of the parallel resistor), and k be the smallest integer greater than n / 2. E・k / (n+m)>Von E・(k-1) / (n+m)<Voff Configured to satisfy, The output side of the photorelay becomes conductive when the number of input variables with a logical value of 1 among the n input variables is k or more, and the output side of the photorelay becomes non-conductive when the number of input variables with a logical value of 1 is less than k. A logic circuit using a photorelay.

6. A logic circuit using a photorelay to implement the EXOR logic function, A first and second photorelay of the normally open type, with their output sides connected in parallel to each other, A first switch unit that switches the connection to the power supply or ground according to the logical value of the first input variable of the EXOR logic function, A second switch unit that switches the connection to the power supply or ground according to the logical value of the second input variable of the EXOR logic function, A first resistor, one end of which is connected to the first switch section and the other end of which is commonly connected to one end of the input side of the first photorelay and one end of the input side of the second photorelay, A second resistor, one end of which is connected to the second switch section and the other end of which is commonly connected to the other input end of the first photorelay and the other input end of the second photorelay, It is equipped with, When the logical value of the first input variable and the logical value of the second input variable are equal, a voltage below the threshold is applied to both the input side of the first photorelay and the input side of the second photorelay, causing both the output side of the first photorelay and the output side of the second photorelay to become non-conductive, and as a result, the combined output side of the first and second photorelays connected in parallel becomes non-conductive. When the logical value of the first input variable and the logical value of the second input variable are different, a voltage exceeding the threshold is applied to either the input side of the first photorelay or the input side of the second photorelay via the first and second resistors, causing the output side of that photorelay to become conductive, and as a result, the combined output side of the parallel-connected first and second photorelays becomes conductive. A logic circuit using a photorelay.

7. A method for configuring a logic circuit using a photorelay to implement an EXOR logic function, The process involves preparing a first photorelay and a second photorelay of the normally open type, and connecting the output side of the first photorelay and the output side of the second photorelay in parallel with each other. The process of providing a first switch unit that switches the connection to the power supply or ground according to the logical value of the first input variable of the EXOR logic function, and a second switch unit that switches the connection to the power supply or ground according to the logical value of the second input variable of the EXOR logic function, The process involves connecting one end of the first resistor to the first switch section, and connecting the other end of the first resistor to one end of the input side of the first photorelay and one end of the input side of the second photorelay, The process involves connecting one end of the second resistor to the second switch section, and connecting the other end of the second resistor to the other input end of the first photorelay and the other input end of the second photorelay, Equipped with A method for constructing logic circuits using photorelays.

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