Wide bandgap semiconductor device

Abstract

We provide wide-bandgap semiconductor devices that can improve reliability. [Solution] The wide-bandgap semiconductor device 1A includes a wide-bandgap semiconductor, a chip 2 having a main surface 3, a main surface electrode 11 disposed on the main surface 3, a thermosetting resin 19 including a matrix resin 27 and a plurality of fillers 28 that covers the main surface 3 so as to expose a part of the main surface electrode 11, and a pad electrode 30 formed on the portion of the main surface electrode 11 exposed from the thermosetting resin 19, having an electrode surface 30a exposed from the thermosetting resin 19 and a protruding portion 30b that slopes diagonally downward from the thermosetting resin 19 side toward the main surface electrode 11 side between the thermosetting resin 19 and the main surface electrode 11, wherein the thickness of the pad electrode 30 exceeds the thickness of the main surface electrode 11.

Description

Technical Field

[0006] , , , ,

[0001] This application corresponds to Japanese Patent Application No. 2021-045115 filed with the Japan Patent Office on March 18, 2021, and the entire disclosure of this application is incorporated herein by reference. The present invention relates to a wide bandgap semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, an electrode, and an organic protective layer. The semiconductor substrate is formed of SiC. The electrode is formed on the semiconductor substrate. The organic protective film partially covers the electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment provides a wide bandgap semiconductor device capable of improving reliability.

Means for Solving the Problems

[0005] [ One embodiment provides a wide bandgap semiconductor device including a wide bandgap semiconductor, a chip having a main surface, a main surface electrode disposed on the main surface, and a thermosetting resin including a matrix resin and a plurality of fillers, the thermosetting resin covering the main surface so as to expose a part of the main surface electrode.

[0006] The above-described or further other objects, features, and effects of the present invention will be clarified by the embodiments described with reference to the accompanying drawings.

Brief Description of the Drawings

[0007] [Figure 1] Figure 1 is a perspective view showing a wide-bandgap semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a plan view of the wide-bandgap semiconductor device shown in Figure 1. [Figure 3] Figure 3 is a cross-sectional view taken along the line III-III shown in Figure 2. [Figure 4] Figure 4 is an enlarged view of region IV shown in Figure 3. [Figure 5] Figure 5 corresponds to Figure 3 and is a cross-sectional view showing a wide-bandgap semiconductor device according to the second embodiment. [Figure 6] Figure 6 corresponds to Figure 3 and is a cross-sectional view showing a wide-bandgap semiconductor device according to the third embodiment. [Figure 7] Figure 7 corresponds to Figure 3 and is a cross-sectional view showing a wide-bandgap semiconductor device according to the fourth embodiment. [Figure 8] Figure 8 corresponds to Figure 3 and is a cross-sectional view showing a wide-bandgap semiconductor device according to the fifth embodiment. [Figure 9] Figure 9 corresponds to Figure 3 and is a cross-sectional view showing a wide-bandgap semiconductor device according to the sixth embodiment. [Figure 10] Figure 10 is a perspective view showing a wide-bandgap semiconductor device according to the seventh embodiment. [Figure 11] Figure 11 is a plan view of the wide-bandgap semiconductor device shown in Figure 10. [Figure 12] Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 11. [Figure 13] Figure 13 is a plan view showing region XIII, as shown in Figure 11, along with its internal structure. [Figure 14] Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 13. [Figure 15] Figure 15 is an enlarged view of region XV shown in Figure 12. [Figure 16]FIG. 16 corresponds to FIG. 12 and is a cross-sectional view showing a wide-bandgap semiconductor device according to the eighth embodiment. [Figure 17] FIG. 17 corresponds to FIG. 12 and is a cross-sectional view showing a wide-bandgap semiconductor device according to the ninth embodiment. [Figure 18] FIG. 18 corresponds to FIG. 12 and is a cross-sectional view showing a wide-bandgap semiconductor device according to the tenth embodiment. [Figure 19] FIG. 19 corresponds to FIG. 12 and is a cross-sectional view showing a wide-bandgap semiconductor device according to the eleventh embodiment. [Figure 20] FIG. 20 corresponds to FIG. 12 and is a cross-sectional view showing a wide-bandgap semiconductor device according to the twelfth embodiment. [Figure 21] FIG. 21 corresponds to FIG. 3 and is a cross-sectional view showing a modified example of a pad electrode. [Figure 22] FIG. 22 is a plan view showing a semiconductor package on which the wide-bandgap semiconductor devices according to the first to sixth embodiments are mounted. [Figure 23] FIG. 23 is a plan view showing a semiconductor package on which the wide-bandgap semiconductor devices according to the seventh to twelfth embodiments are mounted. [Figure 24] FIG. 24 is a perspective view showing a semiconductor package on which the wide-bandgap semiconductor devices according to the first to sixth embodiments and the wide-bandgap semiconductor devices according to the seventh to twelfth embodiments are mounted. [Figure 25] FIG. 25 is an exploded perspective view of semiconductor package shown in FIG. 24. [Figure 26] FIG. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 24.

Embodiments for Carrying Out the Invention

[0008] The attached drawings are schematic diagrams, not necessarily strictly illustrated, and the scales etc. do not necessarily match. Also, the same reference numerals are assigned to corresponding structures among the attached drawings, and duplicate explanations are omitted or simplified. Further, in the following embodiments, for structures where the explanation is omitted or simplified, the explanation made before the omission or simplification is applied.

[0009] FIG. 1 is a perspective view showing a wide bandgap semiconductor device 1A according to the first embodiment. FIG. 2 is a plan view of the wide bandgap semiconductor device 1A shown in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. 2. FIG. 4 is an enlarged view of region IV shown in FIG. 3.

[0010] Referring to FIGS. 1 to 4, the wide bandgap semiconductor device 1A is a semiconductor device including an SBD (Schottky Barrier Diode) as an example of a functional device. The wide bandgap semiconductor device 1A is made of a wide bandgap semiconductor and includes a chip 2 formed in a hexahedron shape (specifically, a rectangular parallelepiped shape). The chip 2 may be referred to as a "semiconductor chip" or a "wide bandgap semiconductor chip". The wide bandgap semiconductor is a semiconductor having a bandgap exceeding that of Si (silicon).

[0011] In this embodiment, the chip 2 is a SiC chip made of a hexagonal SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor. That is, the wide bandgap semiconductor device 1A is a SiC semiconductor device. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example where the chip 2 is made of a 4H-SiC single crystal is shown, but other polytypes are not excluded.

[0012] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and a side surface 5 connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view (hereinafter simply referred to as "plan view") as seen from their normal direction Z. Preferably, the second main surface 4 is a ground surface having grinding marks.

[0013] Side surface 5 includes the first to fourth side surfaces 5A to 5D. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically orthogonal to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in a second direction Y and face the first direction X. Side surface 5 (first to fourth side surfaces 5A to 5D) preferably consists of a ground surface having grinding marks. The chip 2 may have a thickness of 10 μm or more and 250 μm or less with respect to the normal direction Z. The thickness of the chip 2 is preferably 80 μm or less. The thickness of the chip 2 is particularly preferably 40 μm or less.

[0014] The wide-bandgap semiconductor device 1A includes an n-type (first conductivity type) first semiconductor region 6 formed in the region on the second main surface 4 side within the chip 2. The first semiconductor region 6 is formed in a layered manner extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 may have a thickness of 5 μm or more and 200 μm or less with respect to the normal direction Z. The thickness of the first semiconductor region 6 is preferably 50 μm or less. The thickness of the first semiconductor region 6 is particularly preferably 20 μm or less.

[0015] The wide-bandgap semiconductor device 1A includes an n-type second semiconductor region 7 formed in the region on the first main surface 3 side within the chip 2. The second semiconductor region 7 has a lower n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6. The second semiconductor region 7 is formed in layers extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0016] The second semiconductor region 7 may have a thickness of 5 μm or more and 50 μm or less with respect to the normal direction Z. Preferably, the thickness of the second semiconductor region 7 is 30 μm or less. Particularly preferable is a thickness of 20 μm or less. Preferably, the thickness of the second semiconductor region 7 exceeds the thickness of the first semiconductor region 6.

[0017] In this configuration, the first semiconductor region 6 consists of a wide-bandgap semiconductor substrate (specifically, a SiC semiconductor substrate). In this configuration, the second semiconductor region 7 consists of a wide-bandgap semiconductor epitaxial layer (specifically, a SiC epitaxial layer). In other words, the chip 2 has a stacked structure including a wide-bandgap semiconductor substrate and a wide-bandgap semiconductor epitaxial layer. The wide-bandgap semiconductor substrate forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. The wide-bandgap semiconductor epitaxial layer forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0018] The wide-bandgap semiconductor device 1A includes a p-type (second conductivity type) guard region 8 formed on the surface layer of the first main surface 3. The p-type impurities in the guard region 8 may or may not be activated. The guard region 8 is formed on the surface layer of the second semiconductor region 7, spaced inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. In this configuration, the guard region 8 is formed in an annular shape (a square annular shape in this configuration) surrounding the inner part of the first main surface 3 in a plan view. Thus, the guard region 8 is formed as a guard ring region. The guard region 8 has an inner edge on the inner side of the first main surface 3 and an outer edge on the periphery side of the first main surface 3.

[0019] The wide-bandgap semiconductor device 1A includes a first inorganic insulating film 9 that covers the first main surface 3. The first inorganic insulating film 9 covers the region between the periphery of the first main surface 3 and the guard region 8. Specifically, the first inorganic insulating film 9 covers the outer edges of the first main surface 3 and the guard region 8, while exposing the inner portion of the first main surface 3 and the inner edge of the guard region 8. In this embodiment, the first inorganic insulating film 9 is formed in an annular shape (a quadrangular annular shape in this embodiment) that surrounds the inner portion of the first main surface 3 in a plan view.

[0020] The first inorganic insulating film 9 has an inner wall on the inner side of the first main surface 3 and an outer wall on the peripheral side of the first main surface 3. The inner wall of the first inorganic insulating film 9 defines a contact opening 10 in the inner part of the first main surface 3 that exposes the inner edges of the second semiconductor region 7 and the guard region 8. The contact opening 10 is formed in a rectangular shape along the guard region 8 in a plan view. The outer wall of the first inorganic insulating film 9 is formed at a distance inward from the periphery of the first main surface 3, exposing the second semiconductor region 7 at the periphery of the first main surface 3.

[0021] Of course, the first inorganic insulating film 9 may cover the entire area between the periphery of the first main surface 3 and the guard region 8. In this case, the first inorganic insulating film 9 has an outer wall that is continuous with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2. Preferably, the outer wall of the first inorganic insulating film 9 is made of a ground surface having grinding marks. Preferably, the outer wall of the first inorganic insulating film 9 forms a single ground surface with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2.

[0022] The first inorganic insulating film 9 comprises at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the first inorganic insulating film 9 has a single-layer structure made of a silicon oxide film. Particularly preferable is that the first inorganic insulating film 9 includes a silicon oxide film made of the oxide of the chip 2. The first inorganic insulating film 9 may have a thickness of 10 nm to 500 nm.

[0023] The wide-bandgap semiconductor device 1A includes a first main surface electrode 11 that covers the first main surface 3. The first main surface electrode 11 is formed on the first main surface 3, spaced inward from the periphery of the first main surface 3. In this embodiment, the first main surface electrode 11 is formed in a quadrilateral shape with four sides parallel to the periphery of the first main surface 3 in a plan view. The first main surface electrode 11 is electrically connected to the inner edges of the second semiconductor region 7 and the guard region 8 in the inner part of the first main surface 3.

[0024] The first main surface electrode 11 specifically has a main body portion 11a located within the contact opening 10, and a lead-out portion 11b drawn out from the main body portion 11a onto the first inorganic insulating film 9. The main body portion 11a forms a Schottky junction with the second semiconductor region 7 (first main surface 3). The lead-out portion 11b is formed with a gap inward from the outer wall of the first inorganic insulating film 9 and faces the outer edge of the guard region 8 and the second semiconductor region 7 across the first inorganic insulating film 9. The first main surface electrode 11 may have a thickness of 0.5 μm or more and 11 μm or less.

[0025] Referring to Figure 4, the first main surface electrode 11 has a laminated structure including a first main surface electrode film 12 and a second main surface electrode film 13 stacked in this order from the tip 2 side. In this embodiment, the first main surface electrode film 12 includes a Ti-based metal film. The first main surface electrode film 12 may have a single-layer structure consisting of a Ti film or a TiN film. The first main surface electrode film 12 may have a laminated structure including a Ti film and a TiN film in any order. The first main surface electrode film 12 may have a thickness of 10 nm or more and 1 μm or less.

[0026] The second main surface electrode film 13 consists of a Cu-based metal film or an Al-based metal film. The second main surface electrode film 13 may include at least one of the following: a pure Cu film (a Cu film with a purity of 99% or higher), a pure Al film (an Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the second main surface electrode film 13 consists of an Al-based metal film. The second main surface electrode film 13 has a thickness exceeding the thickness of the first main surface electrode film 12. The thickness of the second main surface electrode film 13 may be 0.5 μm or more and 10 μm or less.

[0027] The wide-bandgap semiconductor device 1A includes a second inorganic insulating film 14 that covers the first main surface electrode 11. Specifically, the second inorganic insulating film 14 covers the first inorganic insulating film 9 and the peripheral edge of the first main surface electrode 11, while exposing the inner portion of the first main surface electrode 11. More specifically, the second inorganic insulating film 14 covers the pull-out portion 11b of the first main surface electrode 11, while exposing the main body portion 11a. The second inorganic insulating film 14 may also cover a portion of the main body portion 11a. The second inorganic insulating film 14 is pulled out from above the first inorganic insulating film 9 onto the peripheral edge of the first main surface 3, directly covering the second semiconductor region 7.

[0028] In this embodiment, the second inorganic insulating film 14 is formed in an annular shape (a rectangular annular shape in this embodiment) surrounding the inner portion of the first main surface 3 in a plan view. The second inorganic insulating film 14 has an inner wall on the inner side of the first main surface electrode 11 and an outer wall on the peripheral side of the first main surface 3. The inner wall of the second inorganic insulating film 14 defines a first opening 15 that exposes the inner portion (main body portion 11a) of the first main surface electrode 11. The first opening 15 is formed in a rectangular shape along the periphery of the first main surface electrode 11 in a plan view.

[0029] The outer wall of the second inorganic insulating film 14 is formed with a gap inward from the periphery of the first main surface 3, and defines the dicing street 16 that exposes the periphery of the first main surface 3. Of course, the outer wall of the second inorganic insulating film 14 may be continuous with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2. In this case, it is preferable that the outer wall of the second inorganic insulating film 14 consists of a ground surface having grinding marks. It is preferable that the outer wall of the second inorganic insulating film 14 forms a single ground surface with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2.

[0030] The second inorganic insulating film 14 is made of an inorganic insulator having a relatively high density and has barrier properties (shielding properties) against moisture (humidity). The second inorganic insulating film 14 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the second inorganic insulating film 14 includes an insulating material different from that of the first inorganic insulating film 9. Preferably, the second inorganic insulating film 14 includes a silicon nitride film. Preferably, the second inorganic insulating film 14 has a thickness less than the thickness of the first main surface electrode 11. The thickness of the second inorganic insulating film 14 may be 0.1 μm or more and 5 μm or less.

[0031] The wide-bandgap semiconductor device 1A includes a photosensitive resin 17 that covers the periphery of the first main surface electrode 11. The photosensitive resin 17 may also be referred to as the "first organic film" or the "first organic insulating film." In this embodiment, the photosensitive resin 17 is formed on the second inorganic insulating film 14, covering the first main surface electrode 11 with the second inorganic insulating film 14 in between. The photosensitive resin 17 has a hardness lower than that of the second inorganic insulating film 14. In other words, the photosensitive resin 17 has an elastic modulus smaller than that of the second inorganic insulating film 14, and functions as a buffer (protective film) against external forces. The photosensitive resin 17 protects the chip 2, the first main surface electrode 11, the second inorganic insulating film 14, etc.

[0032] The photosensitive resin 17 extends in a band shape along the periphery of the first main surface electrode 11 in a plan view. In this embodiment, the photosensitive resin 17 is formed in an annular shape (specifically, a square annular shape) surrounding the inner part of the first main surface electrode 11 in a plan view, and covers the periphery of the first main surface electrode 11 all around. Specifically, the photosensitive resin 17 covers the lead-out portion 11b of the first main surface electrode 11, leaving the main body portion 11a exposed. The photosensitive resin 17 may also cover a part of the main body portion 11a.

[0033] The photosensitive resin 17 has an inner wall on the inner side of the first main surface electrode 11 and an outer wall on the peripheral side of the first main surface 3. The inner wall of the photosensitive resin 17 defines a second opening 18 in the inner part of the first main surface electrode 11 that exposes the inner part of the first main surface electrode 11. The second opening 18 is formed in a rectangular shape along the periphery of the first main surface electrode 11 in a plan view. The outer wall of the photosensitive resin 17 is formed at a distance inward from the periphery of the first main surface 3 and defines a dicing street 16 that exposes the peripheral part of the first main surface 3.

[0034] In this embodiment, the photosensitive resin 17 is formed on the second inorganic insulating film 14 such that both the inner peripheral edge (inner wall) and the outer peripheral edge (outer wall) of the second inorganic insulating film 14 are exposed. Therefore, the inner wall of the photosensitive resin 17 demarcates the second opening 18 which communicates with the first opening 15 of the second inorganic insulating film 14. The outer wall of the photosensitive resin 17, together with the second inorganic insulating film 14, demarcates the dicing street 16. When the outer wall of the second inorganic insulating film 14 is connected to the side surface 5 (first to fourth side surfaces 5A to 5D) of the chip 2, the outer wall of the photosensitive resin 17 demarcates the dicing street 16 which exposes the second inorganic insulating film 14.

[0035] The inner wall of the photosensitive resin 17 may be formed in a curved shape that bulges toward the inward side of the first main surface electrode 11. The outer wall of the photosensitive resin 17 may be formed in a curved shape that bulges toward the peripheral edge side of the chip 2. The photosensitive resin 17 may cover either or both of the inner and outer walls of the second inorganic insulating film 14. In other words, the photosensitive resin 17 may have either or both a portion that directly covers a part of the first main surface electrode 11 and a portion that directly covers the peripheral edge (second semiconductor region 7) of the chip 2.

[0036] The photosensitive resin 17 preferably has a thickness exceeding the thickness of the first inorganic insulating film 9. The thickness of the photosensitive resin 17 preferably exceeds the thickness of the second inorganic insulating film 14. The thickness of the photosensitive resin 17 preferably exceeds the thickness of the first main surface electrode 11. The thickness of the photosensitive resin 17 may be 3 μm or more and 30 μm or less. The thickness of the photosensitive resin 17 preferably is 20 μm or less.

[0037] The photosensitive resin 17 may be of the negative type or the positive type. The photosensitive resin 17 may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. In this embodiment, the photosensitive resin 17 contains a polybenzoxazole film.

[0038] The wide-bandgap semiconductor device 1A includes a thermosetting resin 19 that covers the first main surface 3. The thermosetting resin 19 may also be referred to as a "sealing resin," a "second organic film," or a "second organic insulating film." In this embodiment, the thermosetting resin 19 covers the photosensitive resin 17 so as to expose at least a portion of the first main surface electrode 11, and covers the first main surface electrode 11 and the second inorganic insulating film 14 with the photosensitive resin 17 in between.

[0039] In a plan view, the thermosetting resin 19 extends in a band shape along the periphery of the first main surface 3. In this embodiment, the thermosetting resin 19 is formed in an annular shape (specifically, a square annular shape) surrounding the inner part of the first main surface electrode 11 in a plan view, and covers the periphery of the first main surface electrode 11 with the photosensitive resin 17 sandwiched in between. In this embodiment, the thermosetting resin 19 covers the lead-out portion 11b of the first main surface electrode 11 with the photosensitive resin 17 sandwiched in between, exposing the main body portion 11a. If the photosensitive resin 17 covers the main body portion 11a, the thermosetting resin 19 may cover a part of the main body portion 11a with the photosensitive resin 17 sandwiched in between.

[0040] In this embodiment, the thermosetting resin 19 exposes the inner wall (second opening 18) of the photosensitive resin 17 and covers the outer wall of the photosensitive resin 17. The thermosetting resin 19 covers the dicing street 16 demarcated by the photosensitive resin 17 (second inorganic insulating film 14) at the periphery of the chip 2. The thermosetting resin 19 directly covers the second semiconductor region 7 exposed from the first main surface 3 in the dicing street 16.

[0041] The thermosetting resin 19 has a resin main surface 20, a resin inner wall 21 on the inner side of the first main surface electrode 11, and a resin side surface 22 on the peripheral side of the first main surface 3. The resin main surface 20, the resin inner wall 21, and the resin side surface 22 may be referred to as the "organic main surface," "organic inner wall," and "organic side surface," respectively. The resin main surface 20 extends along the first main surface 3. Specifically, the resin main surface 20 extends substantially parallel to the first main surface 3. Preferably, the resin main surface 20 is a ground surface having grinding marks.

[0042] The resin inner wall 21 defines a pad opening 23 in the inner part of the resin main surface 20 that exposes the inner part of the first main surface electrode 11. In this configuration, the pad opening 23 communicates with the first opening 15 of the second inorganic insulating film 14 and the second opening 18 of the photosensitive resin 17. In a plan view, the pad opening 23 is formed in a rectangular shape along the periphery of the tip 2 (first main surface electrode 11). Preferably, the resin inner wall 21 has a smooth surface without grinding marks.

[0043] The resin inner wall 21 has an upper end (open end) on the resin main surface 20 side and a lower end on the tip 2 (photosensitive resin 17) side. The lower end of the resin inner wall 21 is recessed along the outer surface of the photosensitive resin 17, forming a gap 24 with the photosensitive resin 17. Specifically, the resin inner wall 21 has a first wall portion 25 on the open end side and a second wall portion 26 on the lower end side. The first wall portion 25 extends in the thickness direction between the open end and the lower end. Preferably, the first wall portion 25 occupies 80% or more of the resin inner wall 21 in cross-sectional view.

[0044] The second wall portion 26 extends in a direction intersecting the first wall portion 25 toward the outer wall of the photosensitive resin 17, between the outer surface of the photosensitive resin 17 and the first wall portion 25, and defines a gap 24 between the outer surface of the photosensitive resin 17 and the second wall portion 26. Specifically, the second wall portion 26 is inclined diagonally toward the outer surface of the photosensitive resin 17 from the first wall portion 25, and defines a tapered gap 24 in which the width along the normal direction Z gradually decreases as it moves away from the first wall portion 25 (first main surface electrode 11). Preferably, the second wall portion 26 (gap 24) occupies an area of ​​less than 20% of the inner wall 21 of the resin in cross-sectional view.

[0045] The resin side surface 22 includes the first to fourth resin side surfaces 22A to 22D. The first resin side surface 22A is located on the side of the first side surface 5A, the second resin side surface 22B is located on the side of the second side surface 5B, the third resin side surface 22C is located on the side of the third side surface 5C, and the fourth resin side surface 22D is located on the side of the fourth side surface 5D. The first resin side surface 22A and the second resin side surface 22B extend in the first direction X along the first main surface 3 and are opposite to the second direction Y. The third resin side surface 22C and the fourth resin side surface 22D extend in the second direction Y and are opposite to the first direction X.

[0046] The resin side surfaces 22 (first to fourth resin side surfaces 22A to 22D) extend toward the chip 2 and form the outer resin wall. The resin side surfaces 22 are formed at approximately right angles to the resin main surface 20. The angle between the resin side surfaces 22 and the resin main surface 20 may be 88° or more and 92° or less. The resin side surfaces 22 are connected to the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2. Preferably, the resin side surfaces 22 consist of a ground surface having grinding marks. Preferably, the resin side surfaces 22 and the side surfaces 5 of the chip 2 form a single ground surface.

[0047] The thermosetting resin 19 preferably has a thickness exceeding the thickness of the first inorganic insulating film 9. The thickness of the thermosetting resin 19 preferably exceeds the thickness of the second inorganic insulating film 14. The thickness of the thermosetting resin 19 preferably exceeds the thickness of the first main surface electrode 11. The thickness of the thermosetting resin 19 is particularly preferably exceeding the thickness of the photosensitive resin 17. In this embodiment, the thickness of the thermosetting resin 19 exceeds the thickness of the chip 2. The thickness of the thermosetting resin 19 may be 10 μm or more and 300 μm or less. The thickness of the thermosetting resin 19 is preferably 30 μm or more. The thickness of the thermosetting resin 19 may be 200 μm or less.

[0048] The thermosetting resin 19 has a higher hardness than the photosensitive resin 17. In other words, the thermosetting resin 19 has a higher modulus of elasticity than the photosensitive resin 17. The thermosetting resin 19 reinforces the chip 2 from above the first main surface 3. Referring to Figure 4, the thermosetting resin 19 is composed of a matrix resin 27 and a plurality of fillers 28. The matrix resin 27 may contain at least one of epoxy resin, phenolic resin, and thermosetting polyimide resin. In this embodiment, the matrix resin 27 contains epoxy resin. The matrix resin 27 may be colored with a colorant such as carbon black.

[0049] Each of the multiple fillers 28 consists of a spherical object composed of ceramic, oxide, insulator, etc. In other words, the multiple fillers 28 are not formed in a fibrous manner. In this form, each of the multiple fillers 28 consists of silicon oxide particles (silica particles). The thermosetting resin 19 contains multiple fillers 28 with different particle sizes.

[0050] The multiple fillers 28 specifically include multiple small-diameter fillers 28a (first fillers), multiple medium-diameter fillers 28b (second fillers), and multiple large-diameter fillers 28c (third fillers). The small-diameter fillers 28a have a thickness less than the thickness of the first main surface electrode 11. The medium-diameter fillers 28b have a thickness greater than the thickness of the first main surface electrode 11 but less than or equal to the thickness of the photosensitive resin 17. The large-diameter fillers 28c have a thickness greater than the thickness of the photosensitive resin 17.

[0051] Multiple small-diameter fillers 28a, multiple medium-diameter fillers 28b, and multiple large-diameter fillers 28c are filled together with the matrix resin 27 in the region on the resin main surface 20 side of the photosensitive resin 17. Filler attack on the structure on the chip 2 side caused by the medium-diameter fillers 28b and large-diameter fillers 28c is mitigated by the photosensitive resin 17.

[0052] Multiple small-diameter fillers 28a and multiple medium-diameter fillers 28b are filled together with the matrix resin 27 in the region below the photosensitive resin 17. In particular, the small-diameter fillers 28a are filled together with the matrix resin 27 in the gaps caused by the photosensitive resin 17 (in this embodiment, the gap between the second inorganic insulating film 14 and the photosensitive resin 17). The adhesion force of the matrix resin 27 to the structure on the chip 2 side is also enhanced by the multiple fillers 28 with different particle sizes.

[0053] The plurality of fillers 28 include a plurality of filler fragments 29 having particle shapes formed in the surface layer of the thermosetting resin 19. The plurality of filler fragments 29 include a plurality of first filler fragments 29a (main surface side filler fragments) formed in the surface layer of the main resin surface 20, and a plurality of second filler fragments 29b (side side filler fragments) formed in the surface layer of the side resin surface 22.

[0054] The first filler fragment 29a and the second filler fragment 29b are each formed from either a portion of the small-diameter filler 28a, a portion of the medium-diameter filler 28b, or a portion of the large-diameter filler 28c. Each of the multiple filler fragments 29 forms a portion of the grinding marks on the outer surface of the thermosetting resin 19.

[0055] The thermosetting resin 19 has almost no filler fragments 29 in the surface layer of the resin inner wall 21 (first wall portion 25 and second wall portion 26). In other words, the resin inner wall 21 (pad opening 23) is formed by the matrix resin 27 and a plurality of normal fillers 28. In this case, the proportion of filler fragments 29 among the plurality of fillers 28 forming the resin inner wall 21 is less than the proportion of normal fillers 28 forming the resin inner wall 21.

[0056] The wide-bandgap semiconductor device 1A includes a pad electrode 30 positioned on the exposed portion of the first main surface electrode 11. The pad electrode 30 is an external terminal electrically connected to a conductive connecting member (e.g., a wire or a conductive plate). The pad electrode 30 is positioned on the first main surface electrode 11, spaced inward from its periphery. In this embodiment, the pad electrode 30 is positioned within the pad opening 23 and covers the inner portion of the first main surface electrode 11. That is, the pad electrode 30 is in contact with the matrix resin 27 and a plurality of fillers 28 within the pad opening 23.

[0057] The pad electrode 30 is not located outside the pad opening 23. The pad electrode 30 has a planar shape (a rectangular shape in this embodiment) that is aligned with the pad opening 23 in a planar view. The pad electrode 30 has a planar area less than the planar area of ​​the first main surface electrode 11. In this embodiment, the pad electrode 30 enters the second opening 18 and the first opening 15 from the pad opening 23 and is in contact with the first main surface electrode 11, the second inorganic insulating film 14, the photosensitive resin 17 and the thermosetting resin 19.

[0058] It is preferable that the pad electrode 30 has a thickness exceeding the thickness of the first inorganic insulating film 9. It is preferable that the thickness of the pad electrode 30 exceeds the thickness of the second inorganic insulating film 14. It is preferable that the thickness of the pad electrode 30 exceeds the thickness of the first main surface electrode 11. It is particularly preferable that the thickness of the pad electrode 30 exceeds the thickness of the photosensitive resin 17. In this embodiment, the thickness of the pad electrode 30 exceeds the thickness of the chip 2.

[0059] The thickness of the pad electrode 30 may be between 10 μm and 300 μm. Preferably, the thickness of the pad electrode 30 is 30 μm or more. The thickness of the pad electrode 30 may be 200 μm or less. A relatively thick pad electrode 30 (for example, thicker than the first main surface electrode 11) also serves as a heat sink electrode to dissipate heat generated on the chip 2 side to the outside.

[0060] The pad electrode 30 has an electrode surface 30a exposed from the thermosetting resin 19 (pad opening 23). The electrode surface 30a extends along the first main surface 3. Specifically, the electrode surface 30a extends substantially parallel to the first main surface 3. The electrode surface 30a is connected to the resin main surface 20 of the thermosetting resin 19. The electrode surface 30a consists of a ground surface with grinding marks. The electrode surface 30a forms a single ground surface with the resin main surface 20.

[0061] The pad electrode 30 has a protruding portion 30b that rests on the outer surface of the photosensitive resin 17 within the gap 24 of the thermosetting resin 19. The protruding portion 30b is in contact with the photosensitive resin 17 and the thermosetting resin 19 within the gap 24 and has a cross-sectional shape that conforms to the gap 24. In other words, the protruding portion 30b is formed in a tapered shape that slopes diagonally downward from the first wall portion 25 toward the outer surface of the photosensitive resin 17 and gradually decreases in thickness as it moves away from the first wall portion 25.

[0062] The length of the protruding portion 30b along the first main surface 3 may exceed the thickness of the photosensitive resin 17. Of course, the length of the protruding portion 30b may be less than or equal to the thickness of the photosensitive resin 17. The protruding portion 30b prevents the pad electrode 30 from falling out of the thermosetting resin 19. The protruding portion 30b may also be called a "retaining portion".

[0063] Referring to Figure 4, the pad electrode 30 includes a first pad electrode film 31 and a second pad electrode film 32, which are stacked in this order from the first main surface electrode 11 side. The first pad electrode film 31 covers the first main surface electrode 11. In this embodiment, the first pad electrode film 31 is drawn out in a film-like manner from above the first main surface electrode 11 onto the second inorganic insulating film 14 and onto the photosensitive resin 17.

[0064] The first pad electrode film 31 has a thickness less than the thickness of the first main surface electrode 11 and has portions located within the first opening 15 and the second opening 18. The first pad electrode film 31 has a thickness less than the width of the gap 24 with respect to the thickness direction (normal direction Z) and has portions that cover the photosensitive resin 17 within the gap 24. In this embodiment, the first pad electrode film 31 partially covers the second wall portion 26 of the pad opening 23 within the gap 24, while exposing the first wall portion 25 of the pad opening 23.

[0065] The second pad electrode film 32 covers the first pad electrode film 31 and forms the main body of the pad electrode 30. The second pad electrode film 32 has a thickness exceeding the thickness of the photosensitive resin 17 (the thickness of the chip 2 in this embodiment) and has portions located within the first opening 15, the second opening 18, and the pad opening 23.

[0066] The second pad electrode film 32 has a thickness exceeding the width of the gap 24 in the thickness direction (normal direction Z), and has a portion that contacts the first pad electrode film 31 and the thermosetting resin 19 within the gap 24. In other words, the protruding portion 30b of the pad electrode film 30 includes the first pad electrode film 31 and the second pad electrode film 32. The electrode surface 30a of the pad electrode 30 is formed by the second pad electrode film 32.

[0067] In this embodiment, the first pad electrode film 31 consists of a seed film formed by sputtering. The first pad electrode film 31 may also contain a Ti-based metal film. The first pad electrode film 31 may have a single-layer structure consisting of a Ti film or a TiN film. The first pad electrode film 31 may have a laminated structure containing Ti films and TiN films stacked in any order. In this embodiment, the second pad electrode film 32 consists of a plating film formed by electroplating or electroless plating. The second pad electrode film 32 may also contain a Cu-based metal plating film. In this embodiment, the second pad electrode film 32 has a single-layer structure consisting of a pure Cu plating film (a Cu film with a purity of 99% or higher).

[0068] The pad electrode 30 may have at least one minute void 33 at the connection point with the first main surface electrode 11. Figure 4 shows an example in which the void 33 is formed between the first pad electrode film 31 and the first main surface electrode 11. Of course, the void 33 may also be formed between the first pad electrode film 31 and the second pad electrode film 32. The void 33 has a size smaller than the thickness of the first main surface electrode 11. With respect to the thickness direction of the pad electrode 30, the size of the void 33 may be 1 μm or less. Preferably, the size of the void 33 is 0.5 μm or less.

[0069] The wide-bandgap semiconductor device 1A includes a second main surface electrode 34 that covers the second main surface 4. The second main surface electrode 34 is electrically connected to the second main surface 4. Specifically, the second main surface electrode 34 forms ohmic contact with the first semiconductor region 6 exposed from the second main surface 4. The second main surface electrode 34 covers the entire area of ​​the second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Preferably, the outer wall of the second main surface electrode 34 is made of a ground surface having grinding marks. Preferably, the outer wall of the second main surface electrode 34 forms a single ground surface with the side surface 5 of the chip 2.

[0070] The wide-bandgap semiconductor device 1A includes a chip 2, a first main surface electrode 11, and a thermosetting resin 19. The chip 2 includes a wide-bandgap semiconductor and has a first main surface 3. The first main surface electrode 11 covers the first main surface 3. The thermosetting resin 19 is composed of a matrix resin 27 and a plurality of fillers 28, and covers the first main surface 3 such that at least a portion of the first main surface electrode 11 is exposed.

[0071] This structure allows for the reinforcement and protection of the chip 2 with the thermosetting resin 19 while ensuring contact with the first main surface electrode 11. Therefore, a wide-bandgap semiconductor device 1A with improved reliability can be provided.

[0072] Preferably, the thermosetting resin 19 covers the peripheral edge of the first main surface electrode 11. Due to the characteristics of wide-bandgap semiconductors, the wide-bandgap semiconductor device 1A is mounted in vehicles that use motors as a power source, such as hybrid vehicles, electric vehicles, and fuel cell vehicles. Therefore, the wide-bandgap semiconductor device 1A is required to have durability that can withstand harsh operating environmental conditions. The durability of the wide-bandgap semiconductor device 1A is evaluated, for example, by a high-temperature, high-humidity bias test. In the high-temperature, high-humidity bias test, the electrical operation of the wide-bandgap semiconductor device 1A is evaluated when exposed to a high-temperature, high-humidity environment.

[0073] In high-temperature environments, the first main surface electrode 11 may delaminate due to stress caused by thermal expansion of the first main surface electrode 11. In high-humidity environments, the electrical properties of the first main surface electrode 11 may change due to moisture (humidity) entering the delaminated portion of the first main surface electrode 11. Therefore, by using a thermosetting resin 19 to cover the peripheral portion of the first main surface electrode 11, the starting point of delamination of the first main surface electrode 11 can be reduced, and at the same time, the intrusion of moisture from the outside can be suppressed. Thus, a wide-bandgap semiconductor device 1A with improved reliability can be provided.

[0074] The wide-bandgap semiconductor device 1A preferably further includes a photosensitive resin 17 that covers the peripheral edge of the first main surface electrode 11. In this case, the thermosetting resin 19 preferably covers the photosensitive resin 17. With this structure, the peeling point of the first main surface electrode 11 can be reduced by both the photosensitive resin 17 and the thermosetting resin 19.

[0075] In this structure, the multiple fillers 28 may include multiple large-diameter fillers 28c that are thicker than the photosensitive resin 17. With this structure, the fluidity of the matrix resin 27 can be improved by utilizing the multiple large-diameter fillers 28c, and at the same time, the impact caused by the large-diameter fillers 28c can be mitigated by the photosensitive resin 17. Thus, a thermosetting resin 19 that appropriately protects the photosensitive resin 17 and the like can be formed.

[0076] The wide-bandgap semiconductor device 1A preferably includes a pad electrode 30 electrically connected to the first main surface electrode 11 within a pad opening 23 of the thermosetting resin 19. With this structure, in a structure in which a step is formed between the first main surface electrode 11 and the thermosetting resin 19, electrical signals between the first main surface electrode 11 and a conductive connecting member (e.g., a conductor or a conductive plate) can be appropriately transmitted by the pad electrode 30.

[0077] Figure 5 is a cross-sectional view corresponding to Figure 3, showing a wide-bandgap semiconductor device 1B according to the second embodiment. In the first embodiment, an example was described in which the photosensitive resin 17 exposes the inner peripheral edge (inner wall) of the second inorganic insulating film 14. In contrast, the wide-bandgap semiconductor device 1B includes a photosensitive resin 17 that covers the inner peripheral edge (inner wall) of the second inorganic insulating film 14.

[0078] In other words, the photosensitive resin 17 includes a portion that directly covers the first main surface electrode 11. The inner wall 21 of the thermosetting resin 19 (pad opening 23) exposes the photosensitive resin 17 and the inner portion of the first main surface electrode 11, but does not expose the second inorganic insulating film 14. The pad electrode 30 is in contact with the first main surface electrode 11, the photosensitive resin 17, and the thermosetting resin 19 within the pad opening 23, but is not in contact with the second inorganic insulating film 14.

[0079] In summary, the wide-bandgap semiconductor device 1B produces the same effects as those described for the wide-bandgap semiconductor device 1A.

[0080] Figure 6 is a cross-sectional view corresponding to Figure 3, showing a wide-bandgap semiconductor device 1C according to the third embodiment. In the first embodiment, an example was described in which the thermosetting resin 19 exposes the inner peripheral edge (inner wall) of the second inorganic insulating film 14 and the inner peripheral edge (inner wall) of the photosensitive resin 17. In contrast, the wide-bandgap semiconductor device 1C includes a thermosetting resin 19 that covers the inner peripheral edge (inner wall) of the second inorganic insulating film 14 and the inner peripheral edge (inner wall) of the photosensitive resin 17.

[0081] In other words, the thermosetting resin 19 includes a portion that directly covers the first main surface electrode 11. The inner wall 21 (pad opening 23) of the thermosetting resin 19 exposes only the first main surface electrode 11, and does not expose the second inorganic insulating film 14 and the photosensitive resin 17. In this configuration, the lower end of the inner wall 21 of the resin forms a gap 24 with the first main surface electrode 11. The pad electrode 30 is in contact with the first main surface electrode 11 and the thermosetting resin 19 within the pad opening 23, but not with the second inorganic insulating film 14 and the photosensitive resin 17.

[0082] As described above, the wide-bandgap semiconductor device 1C also provides the same effects as those described for the wide-bandgap semiconductor device 1A. Of course, the form of the thermosetting resin 19 according to the third embodiment may also be applied to the second embodiment.

[0083] Figure 7 is a cross-sectional view corresponding to Figure 3, showing a wide-bandgap semiconductor device 1D according to the fourth embodiment. In the first embodiment, an example was described in which the chip 2 has a stacked structure including a first semiconductor region 6 (wide-bandgap semiconductor substrate) and a second semiconductor region 7 (wide-bandgap semiconductor epitaxial layer) formed in this order from the second main surface 4 side.

[0084] In contrast, the wide-bandgap semiconductor device 1D does not have a first semiconductor region 6 (wide-bandgap semiconductor substrate) and includes a chip 2 having a single-layer structure consisting of a second semiconductor region 7 (wide-bandgap semiconductor epitaxial layer).

[0085] As described above, the wide-bandgap semiconductor device 1D also provides the same effects as those described for the wide-bandgap semiconductor device 1A. Furthermore, with the wide-bandgap semiconductor device 1D, the resistance value of the first semiconductor region 6 can be reduced, thus reducing the overall resistance value of the chip 2. In addition, since the chip 2 is supported by the thermosetting resin 19, the strength of the thinned chip 2 can be compensated for by the thermosetting resin 19. Therefore, a wide-bandgap semiconductor device 1D can be provided that improves electrical characteristics while increasing reliability. Of course, the form of the chip 2 according to the fourth embodiment may also be applied to the second and third embodiments.

[0086] Figure 8 is a cross-sectional view corresponding to Figure 3, showing a wide-bandgap semiconductor device 1E according to the fifth embodiment. In the first embodiment, an example was described in which the second inorganic insulating film 14 covers the peripheral portion of the first main surface electrode 11. In contrast, the wide-bandgap semiconductor device 1E has a removal portion 14a that exposes the electrode sidewall of the first main surface electrode 11 and includes a second inorganic insulating film 14 that partially covers the first main surface electrode 11. The structure of the wide-bandgap semiconductor device 1E will be described in detail below.

[0087] In this embodiment, the first inorganic insulating film 9 covers the entire area between the periphery of the first main surface 3 and the guard region 8. The first inorganic insulating film 9 has an outer wall that extends along the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2. The outer wall of the first inorganic insulating film 9 consists of a ground surface with grinding marks. The outer wall of the first inorganic insulating film 9 forms a single ground surface with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2. Of course, the first inorganic insulating film 9 may be formed in the same manner as in the first embodiment.

[0088] The second inorganic insulating film 14, as in the first embodiment, covers the first main surface electrode 11 and the first inorganic insulating film 9, and has an inner wall on the inner side of the first main surface electrode 11 and an outer wall on the peripheral side of the first main surface 3. The inner wall of the second inorganic insulating film 14 defines a first opening 15 that exposes the inner part (main body portion 11a) of the first main surface electrode 11. In this embodiment, the outer wall of the second inorganic insulating film 14 is formed at a distance inward from the periphery of the first main surface 3 and defines a dicing street 16 that exposes the first inorganic insulating film 9.

[0089] In this embodiment, the second inorganic insulating film 14 has at least one removal portion 14a that exposes the electrode sidewall of the first main surface electrode 11 between the first main surface electrode 11 and the first inorganic insulating film 9. Specifically, the removal portion 14a is formed at a distance from the inner and outer walls, exposing the peripheral edge of the first main surface electrode 11 and a portion of the first inorganic insulating film 9.

[0090] The second inorganic insulating film 14 may cover a part of the main body 11a and a part of the lead-out portion 11b, or it may cover a part of the main body 11a with a gap between it and the lead-out portion 11b. In other words, the removal portion 14a may expose a part or all of the lead-out portion 11b, or it may expose all of the lead-out portion 11b and a part of the main body 11a.

[0091] If the second inorganic insulating film 14 has one removal portion 14a, the removal portion 14a may be formed in the shape of a strip extending along the periphery of the first main surface electrode 11 in a plan view, partially exposing the periphery of the first main surface electrode 11. Alternatively, the removal portion 14a may be formed in the shape of an annular shape extending along the periphery of the first main surface electrode 11, exposing the periphery of the first main surface electrode 11 over its entire circumference.

[0092] If the second inorganic insulating film 14 has a plurality of removal portions 14a, the plurality of removal portions 14a may be arranged at intervals along the periphery of the first main surface electrode 11. In this case, the plurality of removal portions 14a may be arranged in a dot shape in a plan view, or each may be formed in a strip shape extending along the periphery of the first main surface electrode 11.

[0093] Furthermore, the multiple removal portions 14a may be arranged at intervals from the peripheral edge inward of the first main surface electrode 11. In this case, the multiple removal portions 14a may be arranged in a dot pattern in a plan view, or they may each be formed in a strip or ring shape extending along the peripheral edge of the first main surface electrode 11. In this case, it is sufficient that at least one removal portion 14a exposes the electrode side wall (periphery) of the first main surface electrode 11.

[0094] In this embodiment, the photosensitive resin 17 penetrates the removal portion 14a from above the second inorganic insulating film 14. Within the removal portion 14a, the photosensitive resin 17 covers the electrode sidewall of the first main surface electrode 11. Specifically, within the removal portion 14a, the photosensitive resin 17 directly covers the peripheral portion of the first main surface electrode 11 and a part of the first inorganic insulating film 9. In other words, the photosensitive resin 17 has a resin anchor portion located within the removal portion 14a.

[0095] In this embodiment, the thermosetting resin 19 includes a portion that covers the removal portion 14a of the second inorganic insulating film 14 with the photosensitive resin 17 in between. That is, the thermosetting resin 19 includes a portion that covers the peripheral portion of the first inorganic insulating film 9 and the first main surface electrode 11 with only the photosensitive resin 17 in between, without the second inorganic insulating film 14 in between. It is preferable that the thermosetting resin 19 covers the entire area of ​​the removal portion 14a in both plan view and cross-sectional view. In this embodiment, the thermosetting resin 19 includes a portion that directly covers the first inorganic insulating film 9 exposed from the first main surface 3 in the dicing street 16.

[0096] As described above, the wide-bandgap semiconductor device 1E exhibits the same effects as those described for the wide-bandgap semiconductor device 1A. Furthermore, the wide-bandgap semiconductor device 1E includes a second inorganic insulating film 14 having a removal portion 14a that exposes the electrode sidewall of the first main surface electrode 11. This structure reduces the starting point for delamination of the second inorganic insulating film 14 caused by thermal expansion of the first main surface electrode 11. Therefore, a wide-bandgap semiconductor device 1E with improved reliability can be provided.

[0097] In this structure, the wide-bandgap semiconductor device 1E includes a photosensitive resin 17 that covers the electrode sidewall of the first main surface electrode 11 within the removal portion 14a. This structure reduces the peeling point of the first main surface electrode 11 in a structure in which the second inorganic insulating film 14 has a removal portion 14a. Therefore, a wide-bandgap semiconductor device 1E with improved reliability can be provided.

[0098] The wide-bandgap semiconductor device 1E further includes a thermosetting resin 19 that covers the removal portion 14a of the second inorganic insulating film 14 with a photosensitive resin 17 in between. With this structure, in a structure where the second inorganic insulating film 14 has a removal portion 14a, the peeling starting point of the first main surface electrode 11 can be reduced by the photosensitive resin 17 and the thermosetting resin 19. Of course, the forms of the first inorganic insulating film 9, first main surface electrode 11, second inorganic insulating film 14, photosensitive resin 17 and thermosetting resin 19 according to the fifth embodiment may also be applied to the second to fourth embodiments.

[0099] Figure 9 corresponds to Figure 3 and is a cross-sectional view showing a wide-bandgap semiconductor device 1F according to the sixth embodiment. In the first embodiment, an example was described in which the photosensitive resin 17 has a curved inner wall that bulges toward the inward side of the first main surface electrode 11 and a curved outer wall that bulges toward the peripheral edge side of the chip 2. In contrast, the wide-bandgap semiconductor device 1F includes a photosensitive resin 17 having an inner wall that slopes diagonally downward toward the inward side of the first main surface electrode 11 and an outer wall that slopes diagonally downward toward the peripheral edge side of the chip 2. In other words, the photosensitive resin 17 is formed in a trapezoidal (tapered) shape in cross-sectional view.

[0100] As described above, the wide-bandgap semiconductor device 1F also provides the same effects as those described for the wide-bandgap semiconductor device 1A. Furthermore, the wide-bandgap semiconductor device 1F can improve the fluidity of the thermosetting resin 19 (matrix resin 27 and multiple fillers 28) relative to the photosensitive resin 17. This suppresses the formation of gaps between the thermosetting resin 19 and the photosensitive resin 17. Of course, the form of the photosensitive resin 17 according to the sixth embodiment may also be applied to the second to fifth embodiments.

[0101] Figure 10 is a perspective view showing a wide-bandgap semiconductor device 1G according to the seventh embodiment. Figure 11 is a plan view of the wide-bandgap semiconductor device 1G shown in Figure 10. Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 11. Figure 13 is a plan view showing region XIII shown in Figure 11 along with its internal structure. Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 13. Figure 15 is an enlarged view of region XV shown in Figure 12.

[0102] Referring to Figures 10 to 15, the wide-bandgap semiconductor device 1G is a semiconductor device that includes a MISFET (Metal Insulator Semiconductor Field Effect Transistor) as an example of a functional device. The wide-bandgap semiconductor device 1G includes the aforementioned chip 2, the aforementioned first semiconductor region 6, and the aforementioned second semiconductor region 7. In this embodiment, the wide-bandgap semiconductor device 1G includes an active surface 41, an outer surface 42, and first to fourth connecting surfaces 43A to 43D formed on the first main surface 3 of the chip 2.

[0103] The active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D demarcate the active mesa 44 on the first main surface 3. The active surface 41 may be referred to as the "first surface," the outer surface 42 as the "second surface," and the active mesa 44 as the "mesa." The active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D (i.e., the active mesa 44) may be considered components of the first main surface 3.

[0104] The active surface 41 is formed with a gap inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 41 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 41 is formed in a quadrilateral shape with four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0105] The outer surface 42 is located outside the active surface 41 and is recessed from the active surface 41 in the thickness direction of the chip 2 (towards the second main surface 4). Specifically, the outer surface 42 is recessed to a depth less than the thickness of the second semiconductor region 7 so as to expose the second semiconductor region 7. In a plan view, the outer surface 42 is formed in a band shape extending along the active surface 41. In this embodiment, the outer surface 42 is formed in an annular shape (specifically a square annular shape) surrounding the active surface 41 in a plan view. The outer surface 42 has a flat surface extending in the first direction X and the second direction Y and is formed substantially parallel to the active surface 41. The outer surface 42 is continuous with the first to fourth sides 5A to 5D.

[0106] The first to fourth connecting surfaces 43A to 43D extend in the normal direction Z and connect the active surface 41 and the outer surface 42. The first connecting surface 43A is located on the side of the first surface 5A, the second connecting surface 43B is located on the side of the second surface 5B, the third connecting surface 43C is located on the side of the third surface 5C, and the fourth connecting surface 43D is located on the side of the fourth surface 5D. The first connecting surface 43A and the second connecting surface 43B extend in the first direction X and face the second direction Y. The third connecting surface 43C and the fourth connecting surface 43D extend in the second direction Y and face the first direction X.

[0107] The first to fourth connecting surfaces 43A to 43D may extend almost vertically between the active surface 41 and the outer surface 42 so as to define the rectangular prism-shaped active platform 44. The first to fourth connecting surfaces 43A to 43D may also be inclined diagonally downward from the active surface 41 toward the outer surface 42 so as to define the pyramidal-shaped active platform 44. In this way, the wide bandgap semiconductor device 1G includes an active platform 44 formed in the second semiconductor region 7 on the first main surface 3. The active platform 44 is formed only in the second semiconductor region 7 and not in the first semiconductor region 6.

[0108] Referring to Figures 13 and 14, the wide-bandgap semiconductor device 1G includes a MISFET formed on the active surface 41. In this embodiment, the MISFET is of the trench gate type. The structure of the MISFET will be described in detail below. The wide-bandgap semiconductor device 1G includes a p-type body region 48 formed on the surface of the active surface 41. The body region 48 may be formed over the entire surface of the active surface 41.

[0109] The wide-bandgap semiconductor device 1G includes an n-type source region 49 formed on the surface of the body region 48. The source region 49 may be formed over the entire surface of the body region 48. The source region 49 has an n-type impurity concentration that exceeds the n-type impurity concentration of the second semiconductor region 7. The source region 49 forms a channel CH of the MISFET with the second semiconductor region 7 within the body region 48.

[0110] The wide-bandgap semiconductor device 1G includes a plurality of trench gate structures 50 formed on the active surface 41. The plurality of trench gate structures 50 control the inversion and non-inversion of the channel CH. The plurality of trench gate structures 50 penetrate the body region 48 and the source region 49 to the second semiconductor region 7. The plurality of trench gate structures 50 are formed with spacing from the bottom of the second semiconductor region 7 toward the active surface 41. In a plan view, the plurality of trench gate structures 50 are formed with spacing in the first direction X and are each formed in a strip shape extending in the second direction Y.

[0111] Each trench gate structure 50 includes a gate trench 51, a gate insulating film 52, and a gate electrode 53. The gate trench 51 is formed on the active surface 41. The gate insulating film 52 covers the inner wall of the gate trench 51. The gate electrode 53 is embedded in the gate trench 51, with the gate insulating film 52 in between. The gate electrode 53 faces the second semiconductor region 7, the body region 48, and the source region 49, with the gate insulating film 52 in between. A gate potential is applied to the gate electrode 53.

[0112] The wide-bandgap semiconductor device 1G includes a plurality of trench source structures 54 formed on the active surface 41. Each of the plurality of trench source structures 54 is formed in the region between two adjacent trench gate structures 50 on the active surface 41. Each of the plurality of trench source structures 54 is formed in a strip shape extending in the second direction Y in a plan view. The plurality of trench source structures 54 penetrate the body region 48 and the source region 49 to the second semiconductor region 7.

[0113] Multiple trench source structures 54 are formed at intervals from the bottom of the second semiconductor region 7 toward the active surface 41. The multiple trench source structures 54 have a depth exceeding the depth of the trench gate structure 50. In this embodiment, the bottom walls of the multiple trench source structures 54 are located substantially coplanar with the outer surface 42. Of course, each trench source structure 54 may have a depth substantially equal to the depth of the trench gate structure 50.

[0114] Each trench source structure 54 includes a source trench 55, a source insulating film 56, and a source electrode 57. The source trench 55 is formed on the active surface 41. The source insulating film 56 covers the inner wall of the source trench 55. The source electrode 57 is embedded in the source trench 55, sandwiching the source insulating film 56. A source potential is applied to the source electrode 57.

[0115] The wide-bandgap semiconductor device 1G includes a plurality of p-type contact regions 58 formed in regions along a plurality of trench source structures 54 in the second semiconductor region 7. The p-type impurity concentration in the plurality of contact regions 58 exceeds the p-type impurity concentration in the body region 48. The plurality of contact regions 58 each cover the corresponding trench source structures 54 in a one-to-many correspondence, spaced apart in the second direction Y. Each contact region 58 covers the side and bottom walls of each trench source structure 54 and is electrically connected to the body region 48.

[0116] The wide-bandgap semiconductor device 1G includes a plurality of p-type well regions 59 formed in the surface layer of the active surface 41, along the regions of the plurality of trench source structures 54. Preferably, the p-type impurity concentration in the plurality of well regions 59 is greater than the p-type impurity concentration in the body region 48 and less than the p-type impurity concentration in the contact region 58.

[0117] Multiple well regions 59 each cover a corresponding trench source structure 54, flanking multiple contact regions 58. Each well region 59 may be formed in a strip shape extending along the corresponding trench source structure 54. Each well region 59 covers the side and bottom walls of each trench source structure 54 and is electrically connected to the body region 48.

[0118] Referring to Figure 15, the wide-bandgap semiconductor device 1G includes a p-type outer contact region 60 formed on the surface layer of the second semiconductor region 7 on the outer surface 42. Preferably, the outer contact region 60 has a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 48. In a plan view, the outer contact region 60 is formed with a gap between it and the periphery of the active surface 41 and the periphery of the outer surface 42.

[0119] The outer contact region 60 is formed in a band shape extending along the active surface 41 in a plan view. In this configuration, the outer contact region 60 is formed in an annular shape (specifically, a square annular shape) surrounding the active surface 41 in a plan view. The outer contact region 60 is formed with a gap from the bottom of the second semiconductor region 7 to the outer surface 42. The outer contact region 60 is located on the bottom side of the second semiconductor region 7 with respect to the bottom walls of the multiple trench gate structures 50.

[0120] The wide-bandgap semiconductor device 1G includes a p-type outer well region 61 formed on the surface layer of the outer surface 42. The outer well region 61 has a p-type impurity concentration lower than that of the outer contact region 60. Preferably, the p-type impurity concentration of the outer well region 61 is approximately equal to that of the well region 59. In a plan view, the outer well region 61 is formed in the region between the periphery of the active surface 41 and the outer contact region 60.

[0121] The outer well region 61 is formed in a band shape extending along the active surface 41 in a plan view. In this configuration, the outer well region 61 is formed in an annular shape (specifically, a square annular shape) surrounding the active surface 41 in a plan view. The outer well region 61 is electrically connected to the outer contact region 60. In this configuration, the outer well region 61 extends from the outer surface 42 toward the first to fourth connection surfaces 43A to 43D and covers the first to fourth connection surfaces 43A to 43D within the chip 2.

[0122] The outer well region 61 is formed deeper than the outer contact region 60. The outer well region 61 is formed with a gap between the bottom of the second semiconductor region 7 and the outer surface 42. The outer well region 61 is located on the bottom side of the second semiconductor region 7 relative to the bottom walls of the multiple trench gate structures 50. The outer well region 61 is electrically connected to the body region 48 at the surface of the active surface 41.

[0123] The wide-bandgap semiconductor device 1G includes at least one (preferably two to twenty) p-type field regions 62 formed in the region between the outer contact region 60 and the periphery of the outer surface 42 on the surface layer of the outer surface 42. In this embodiment, the wide-bandgap semiconductor device 1G includes five field regions 62. The multiple field regions 62 relax the electric field within the chip 2 on the outer surface 42. The number, width, depth, and p-type impurity concentration of the field regions 62 are arbitrary and can take various values ​​depending on the electric field to be relaxed.

[0124] Multiple field regions 62 are formed at intervals from the outer contact region 60 towards the peripheral edge of the outer surface 42. In a plan view, the multiple field regions 62 are formed in a band shape extending along the active surface 41. In this configuration, in a plan view, the multiple field regions 62 are formed in an annular shape (specifically, a square annular shape) surrounding the active surface 41. Thus, each of the multiple field regions 62 is formed as an FLR (Field Limiting Ring) region.

[0125] Multiple field regions 62 are formed at intervals from the bottom of the second semiconductor region 7 to the outer surface 42. The multiple field regions 62 are located on the bottom side of the second semiconductor region 7 relative to the bottom walls of the multiple trench gate structures 50. The multiple field regions 62 are formed deeper than the outer contact region 60. The innermost field region 62 may be connected to the outer contact region 60. Field regions 62 other than the innermost field region 62 may be formed in an electrically floating state.

[0126] The wide-bandgap semiconductor device 1G includes the aforementioned first inorganic insulating film 9 covering the first main surface 3. In this embodiment, the first inorganic insulating film 9 covers the active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D. The first inorganic insulating film 9 is continuous with the gate insulating film 52 and the source insulating film 56, exposing the gate electrode 53 and the source electrode 57. The outer wall of the first inorganic insulating film 9 is formed with a gap inward from the periphery of the outer surface 42, exposing the second semiconductor region 7 from the periphery of the outer surface 42.

[0127] Of course, the first inorganic insulating film 9 may cover the outer surface 42 so as to be continuous with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2. In this case, the first inorganic insulating film 9 has an outer wall that is continuous with the side surfaces 5 of the chip 2. Preferably, the outer wall of the first inorganic insulating film 9 is made of a ground surface having grinding marks. Preferably, the outer wall of the first inorganic insulating film 9 forms a single ground surface with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2.

[0128] The wide-bandgap semiconductor device 1G includes a sidewall structure 63 formed on the outer surface 42 side of the first inorganic insulating film 9 so as to cover at least one of the first to fourth connection surfaces 43A to 43D. In this embodiment, the sidewall structure 63 is formed in an annular (quadrilateral annular) shape surrounding the active surface 41 in a plan view. The sidewall structure 63 may contain an inorganic insulator or polysilicon.

[0129] The wide-bandgap semiconductor device 1G includes an interlayer insulating film 64 formed on a first inorganic insulating film 9. The interlayer insulating film 64 covers the active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D with the first inorganic insulating film 9 in between. The interlayer insulating film 64 covers the first inorganic insulating film 9 with a sidewall structure 63 in between. The interlayer insulating film 64 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The outer wall of the interlayer insulating film 64 is formed with a gap inward from the periphery of the outer surface 42, similar to the outer wall of the first inorganic insulating film 9, and the second semiconductor region 7 is exposed from the periphery of the outer surface 42.

[0130] Of course, the outer wall of the interlayer insulating film 64 may be continuous with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2. In this case, it is preferable that the outer wall of the interlayer insulating film 64 consists of a ground surface having grinding marks. It is preferable that the outer wall of the interlayer insulating film 64 forms a single ground surface with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2.

[0131] The wide-bandgap semiconductor device 1G includes a plurality of first main surface electrodes 11 formed on the first main surface 3 (on the interlayer insulating film 64). The plurality of first main surface electrodes 11 each have a stacked structure including a first main surface electrode film 12 and a second main surface electrode film 13 stacked in this order from the chip 2 side, as in the first embodiment. The plurality of first main surface electrodes 11 include a gate main surface electrode 65 and a source main surface electrode 67.

[0132] The gate main electrode 65 receives a gate potential from an external source. The gate main electrode 65 is positioned on the active surface 41 and not on the outer surface 42. In this configuration, the gate main electrode 65 is positioned in a region on the periphery of the active surface 41, close to the center of the first connection surface 43A. In this configuration, the gate main electrode 65 is formed in a rectangular shape in plan view.

[0133] The source main electrode 67 is positioned on the active surface 41 at a distance from the gate main electrode 65. An external source potential is input to the source main electrode 67. In this embodiment, the source main electrode 67 is formed in a polygonal shape with a recess that aligns with the gate main electrode 65 in a plan view. Of course, the source main electrode 67 may be formed in a square shape in a plan view. The source main electrode 67 penetrates the interlayer insulating film 64 and the first inorganic insulating film 9 and is electrically connected to a plurality of trench source structures 54, source regions 49 and a plurality of well regions 59.

[0134] The wide-bandgap semiconductor device 1G includes gate wiring electrodes 66 and source wiring electrodes 68 formed on the first main surface 3 (on the interlayer insulating film 64). The gate wiring electrodes 66 and source wiring electrodes 68 each have a laminated structure including a first main surface electrode film 12 and a second main surface electrode film 13, which are stacked in this order from the chip 2 side, similar to the multiple first main surface electrodes 11.

[0135] The gate wiring electrode 66 is drawn out from the gate main surface electrode 65 onto the interlayer insulating film 64. The gate wiring electrode 66 is formed in a strip shape that extends along the periphery of the active surface 41 so as to intersect (specifically orthogonally) with the ends of the multiple trench gate structures 50 in a plan view. The gate wiring electrode 66 penetrates the interlayer insulating film 64 and is electrically connected to the multiple trench gate structures 50 (gate electrodes 53). The gate wiring electrode 66 transmits the gate potential applied to the gate main surface electrode 65 to the multiple trench gate structures 50.

[0136] The source wiring electrode 68 is drawn out from the source main surface electrode 67 onto the interlayer insulating film 64. The source wiring electrode 68 is formed in a strip shape extending along the periphery of the active surface 41 (first to fourth connection surfaces 43A to 43D) in the region on the outer surface 42 side of the gate wiring electrode 66. In this configuration, the source wiring electrode 68 is formed in an annular shape (specifically a rectangular annular shape) surrounding the gate main surface electrode 65, the source main surface electrode 67, and the gate wiring electrode 66 in a plan view.

[0137] The source wiring electrode 68 covers the sidewall structure 63 with the interlayer insulating film 64 in between, and is drawn out from the active surface 41 side to the outer surface 42 side. On the outer surface 42 side, the source wiring electrode 68 penetrates the interlayer insulating film 64 and the first inorganic insulating film 9 and is electrically connected to the outer contact region 60. Preferably, the source wiring electrode 68 covers the entire area of ​​the sidewall structure 63 and the entire area of ​​the outer contact region 60 around its entire circumference. The source wiring electrode 68 transmits the source potential applied to the source main surface electrode 67 to the multiple outer contact regions 60.

[0138] The wide-bandgap semiconductor device 1G includes the interlayer insulating film 64 and the aforementioned second inorganic insulating film 14 that covers the plurality of first main surface electrodes 11. In this embodiment, the second inorganic insulating film 14 covers the active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D with the interlayer insulating film 64 in between. The thickness of the second inorganic insulating film 14 is preferably less than the thickness of the interlayer insulating film 64. The second inorganic insulating film 14 covers the periphery of the interlayer insulating film 64 and the plurality of first main surface electrodes 11, while exposing the inner portions of the plurality of first main surface electrodes 11.

[0139] Specifically, the second inorganic insulating film 14 exposes the inner portion of the gate main surface electrode 65 in a plan view and covers the peripheral edge of the gate main surface electrode 65 around its entire circumference. Furthermore, the second inorganic insulating film 14 exposes the inner portion of the source main surface electrode 67 in a plan view and covers the peripheral edge of the source main surface electrode 67 around its entire circumference. The second inorganic insulating film 14 also covers the entire area of ​​the gate wiring electrode 66 and the entire area of ​​the source wiring electrode 68.

[0140] The second inorganic insulating film 14 has a first gate inner wall on the gate main electrode 65 side, a first source inner wall on the source main electrode 67 side, and an outer wall on the outer surface 42 side. The first gate inner wall of the second inorganic insulating film 14 defines a first gate opening 69 that exposes the inner portion of the gate main electrode 65. In a plan view, the first gate opening 69 is formed in a rectangular shape along the periphery of the gate main electrode 65.

[0141] The inner wall of the first source of the second inorganic insulating film 14 defines a first source opening 70 that exposes the inner portion of the source main surface electrode 67. The first source opening 70 is formed in a polygonal shape with a recess that follows the recess of the source main surface electrode 67 in a plan view. Of course, the first source opening 70 may be formed in a rectangular shape in a plan view. The outer wall of the second inorganic insulating film 14 is formed with a gap inward from the periphery of the outer surface 42 and defines a dicing street 16 that exposes the second semiconductor region 7 from the periphery of the outer surface 42.

[0142] Of course, the outer wall of the second inorganic insulating film 14 may be continuous with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2. In this case, it is preferable that the outer wall of the second inorganic insulating film 14 consists of a ground surface having grinding marks. It is preferable that the outer wall of the second inorganic insulating film 14 forms a single ground surface with the side surfaces 5 (first to fourth side surfaces 5A to 5D) of the chip 2.

[0143] The wide-bandgap semiconductor device 1G includes the aforementioned photosensitive resin 17 that covers a plurality of first main surface electrodes 11. Preferably, the thickness of the photosensitive resin 17 exceeds the thickness of the interlayer insulating film 64. In this embodiment, the photosensitive resin 17 is formed on the second inorganic insulating film 14 and covers the active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D with the second inorganic insulating film 14 in between.

[0144] The photosensitive resin 17 covers the peripheral edges of the gate main electrode 65 and the source main electrode 67 with the second inorganic insulating film 14 in between, while exposing the inner parts of the gate main electrode 65 and the source main electrode 67. Specifically, in a plan view, the photosensitive resin 17 covers the entire peripheral edge of the gate main electrode 65 and the entire peripheral edge of the source main electrode 67. The photosensitive resin 17 covers the entire area of ​​the gate wiring electrode 66 and the entire area of ​​the source wiring electrode 68 with the second inorganic insulating film 14 in between.

[0145] The photosensitive resin 17 has a second gate inner wall on the gate main electrode 65 side, a second source inner wall on the source main electrode 67 side, and an outer wall on the peripheral edge side of the first main surface 3. The second gate inner wall of the photosensitive resin 17 defines a second gate opening 71 that exposes the inner portion of the gate main electrode 65. The second gate opening 71 is formed in a rectangular shape along the periphery of the gate main electrode 65 in a plan view. The second source inner wall of the photosensitive resin 17 defines a second source opening 72 that exposes the inner portion of the source main electrode 67. The second source opening 72 is formed in a polygonal shape along the periphery of the source main electrode 67 in a plan view.

[0146] In this embodiment, the photosensitive resin 17 is formed on the second inorganic insulating film 14 such that it exposes all of the first gate inner wall, first source inner wall, and outer wall of the second inorganic insulating film 14. Therefore, the second gate opening 71 communicates with the first gate opening 69 of the second inorganic insulating film 14. Also, the second source opening 72 communicates with the first source opening 70 of the second inorganic insulating film 14. Furthermore, the outer wall of the photosensitive resin 17, together with the second inorganic insulating film 14, demarcates the dicing street 16.

[0147] When the outer wall of the second inorganic insulating film 14 is connected to the side surface 5 (first to fourth side surfaces 5A to 5D) of the chip 2, the outer wall of the photosensitive resin 17 demarcates the dicing street 16 that exposes the second inorganic insulating film 14. The inner wall of the second gate of the photosensitive resin 17 may be formed in a curved shape that bulges inward toward the gate main surface electrode 65. The inner wall of the second source of the photosensitive resin 17 may be formed in a curved shape that bulges inward toward the source main surface electrode 67. The outer wall of the photosensitive resin 17 may be formed in a curved shape that bulges toward the peripheral edge of the outer surface 42.

[0148] The photosensitive resin 17 may cover at least one of the first gate inner wall, the first source inner wall, and the outer wall of the second inorganic insulating film 14. In other words, the photosensitive resin 17 may have at least one of the following: a portion that directly covers a part of the gate main surface electrode 65, a portion that directly covers a part of the source main surface electrode 67, and a portion that directly covers the peripheral edge (second semiconductor region 7) of the outer surface 42.

[0149] The wide-bandgap semiconductor device 1G includes the aforementioned thermosetting resin 19 that covers the first main surface 3. The thermosetting resin 19 is formed on top of the photosensitive resin 17 and covers the active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D with the photosensitive resin 17 in between. In this embodiment, the thermosetting resin 19 covers the photosensitive resin 17 such that at least a portion of each of the multiple first main surface electrodes 11 is exposed, and covers the peripheral edges of the multiple first main surface electrodes 11 and the second inorganic insulating film 14 with the photosensitive resin 17 in between.

[0150] Specifically, the thermosetting resin 19 covers the peripheral edge of the gate main surface electrode 65 around its entire circumference in a plan view, sandwiching the photosensitive resin 17. The thermosetting resin 19 also covers the peripheral edge of the source main surface electrode 67 around its entire circumference in a plan view, sandwiching the photosensitive resin 17. Furthermore, the thermosetting resin 19 covers the entire area of ​​the gate wiring electrode 66 and the entire area of ​​the source wiring electrode 68, sandwiching the photosensitive resin 17.

[0151] In this embodiment, the thermosetting resin 19 exposes the inner walls of the second gate and second source of the photosensitive resin 17 and covers the outer wall of the photosensitive resin 17. The thermosetting resin 19 covers the dicing street 16, which is partitioned by the photosensitive resin 17 (second inorganic insulating film 14) at the periphery of the outer surface 42. The thermosetting resin 19 directly covers the second semiconductor region 7 exposed from the outer surface 42 in the dicing street 16.

[0152] The thermosetting resin 19 has a resin main surface 20, a plurality of resin inner walls 21, and resin side surfaces 22. The resin main surface 20 and resin side surfaces 22 are formed in the same manner as in the first embodiment. In this embodiment, the plurality of resin inner walls 21 partition a plurality of pad openings 23 that expose a plurality of first main surface electrodes 11. Specifically, the plurality of resin inner walls 21 include a gate resin inner wall 73 and a source resin inner wall 74.

[0153] The inner wall 73 of the gate resin defines a gate pad opening 75 (pad opening 23) in the inner part of the resin main surface 20, exposing the inner part of the gate main surface electrode 65. The gate pad opening 75 is defined on the photosensitive resin 17 and communicates with the first gate opening 69 of the second inorganic insulating film 14 and the second gate opening 71 of the photosensitive resin 17. In a plan view, the gate pad opening 75 is formed in a rectangular shape along the periphery of the gate main surface electrode 65. Preferably, the inner wall 73 of the gate resin has a smooth surface without grinding marks.

[0154] The inner wall 74 of the source resin defines a source pad opening 76 (pad opening 23) in the inner part of the resin main surface 20, exposing the inner part of the source main surface electrode 67. The source pad opening 76 is defined on the photosensitive resin 17 and communicates with the first source opening 70 of the second inorganic insulating film 14 and the second source opening 72 of the photosensitive resin 17. In a plan view, the source pad opening 76 is formed in a rectangular shape along the periphery of the source main surface electrode 67. Preferably, the inner wall 74 of the source resin has a smooth surface without grinding marks.

[0155] The multiple resin inner walls 21 (gate resin inner wall 73 and source resin inner wall 74) each have an upper end (open end) on the resin main surface 20 side and a lower end on the tip 2 (photosensitive resin 17) side, similar to the first embodiment. The lower ends of the multiple resin inner walls 21 are recessed along the outer surface of the photosensitive resin 17, forming gaps 24 between them and the photosensitive resin 17. Specifically, the multiple resin inner walls 21 each have a first wall portion 25 on the open end side and a second wall portion 26 on the lower end side. The first wall portion 25 extends in the thickness direction between the open end and the lower end. Preferably, the first wall portion 25 occupies 80% or more of the resin inner wall 21 in cross-sectional view.

[0156] The second wall portion 26 extends in a direction intersecting the first wall portion 25 toward the outer wall of the photosensitive resin 17 between the outer surface of the photosensitive resin 17 and the first wall portion 25, and defines a gap 24 between the outer surface of the photosensitive resin 17 and the second wall portion 26. Specifically, the second wall portion 26 is inclined diagonally toward the outer surface of the photosensitive resin 17 from the first wall portion 25, and defines a tapered gap 24 whose width along the normal direction Z narrows as it moves away from the first wall portion 25 (first main surface electrode 11). Preferably, the second wall portion 26 occupies an area of ​​less than 20% of the inner wall 21 of the resin in cross-sectional view.

[0157] The thermosetting resin 19 is composed of a matrix resin 27 and a plurality of fillers 28, as in the first embodiment. The plurality of fillers 28 include a plurality of small-diameter fillers 28a (first fillers), a plurality of medium-diameter fillers 28b (second fillers), and a plurality of large-diameter fillers 28c (third fillers), as in the first embodiment. The small-diameter fillers 28a have a thickness less than the thickness of the first main surface electrode 11. The medium-diameter fillers 28b have a thickness greater than the thickness of the first main surface electrode 11 and less than or equal to the thickness of the photosensitive resin 17. The large-diameter fillers 28c have a thickness greater than the thickness of the photosensitive resin 17.

[0158] The plurality of fillers 28, as in the first embodiment, include a plurality of filler fragments 29 having a fractured granular shape in the surface layer of the thermosetting resin 19. The plurality of filler fragments 29 include a plurality of first filler fragments 29a formed in the surface layer of the main resin surface 20, and a plurality of second filler fragments 29b formed in the surface layer of the side surface 22 of the resin. The plurality of filler fragments 29 each form a portion of the grinding marks on the outer surface of the thermosetting resin 19.

[0159] The thermosetting resin 19 has almost no filler fragments 29 in the surface layer of the multiple resin inner walls 21 (first wall portion 25 and second wall portion 26). In other words, the multiple resin inner walls 21 (pad opening 23) are formed by the matrix resin 27 and multiple normal fillers 28. In this case, the proportion of filler fragments 29 among the multiple fillers 28 forming the resin inner wall 21 is less than the proportion of normal fillers 28 forming the resin inner wall 21.

[0160] The wide-bandgap semiconductor device 1G includes a plurality of pad electrodes 30 arranged within a plurality of pad openings 23. The plurality of pad electrodes 30 include a gate pad electrode 80 arranged within a gate pad opening 75 and a source pad electrode 81 arranged within a source pad opening 76. The gate pad electrode 80 extends from the gate pad opening 75 into a second gate opening 71 and a first gate opening 69, and is in contact with the gate main surface electrode 65, a second inorganic insulating film 14, a photosensitive resin 17, and a thermosetting resin 19.

[0161] In other words, the gate pad electrode 80 is in contact with the matrix resin 27 and the multiple fillers 28 within the gate pad opening 75. The gate pad electrode 80 is not located outside the gate pad opening 75. In a planar view, the gate pad electrode 80 has a planar shape (a rectangular shape in this configuration) that is aligned with the gate pad opening 75. The gate pad electrode 80 has a planar area less than the planar area of ​​the gate main surface electrode 65.

[0162] The gate pad electrode 80 has a gate electrode surface 80a exposed from the gate pad opening 75. The gate electrode surface 80a is connected to the main resin surface 20 of the thermosetting resin 19. The gate electrode surface 80a consists of a ground surface having grinding marks. The gate electrode surface 80a forms a single ground surface with the main resin surface 20.

[0163] The source pad electrode 81 enters the second source opening 72 and the first source opening 70 from the source pad opening 76 and is in contact with the source main surface electrode 67, the second inorganic insulating film 14, the photosensitive resin 17, and the thermosetting resin 19. In other words, the source pad electrode 81 is in contact with the matrix resin 27 and the multiple fillers 28 within the source pad opening 76. The source pad electrode 81 is not located outside the source pad opening 76. In a planar view, the source pad electrode 81 has a planar shape (a polygonal shape in this embodiment) that is aligned with the source pad opening 76. The source pad electrode 81 has a planar area less than the planar area of ​​the source main surface electrode 67.

[0164] The source pad electrode 81 has a source electrode surface 81a exposed from the source pad opening 76. The source electrode surface 81a is connected to the main resin surface 20 of the thermosetting resin 19. The source electrode surface 81a consists of a ground surface with grinding marks. The source electrode surface 81a forms a single ground surface with the main resin surface 20.

[0165] Each of the multiple pad electrodes 30 (gate pad electrode 80 and source pad electrode 81) has a protruding portion 30b that rides up on the outer surface of the photosensitive resin 17 within the gap 24, similar to the first embodiment. The protruding portion 30b is in contact with the photosensitive resin 17 and the thermosetting resin 19 within the gap 24 and has a cross-sectional shape that conforms to the gap 24.

[0166] In other words, the protruding portion 30b is formed in a tapered shape, sloping diagonally downward from the first wall portion 25 toward the outer surface of the photosensitive resin 17, with its thickness gradually decreasing as it moves away from the first wall portion 25. The length of the protruding portion 30b along the first main surface 3 may exceed the thickness of the photosensitive resin 17. Of course, the length of the protruding portion 30b may be less than or equal to the thickness of the photosensitive resin 17.

[0167] The multiple pad electrodes 30 each have a laminated structure including a first pad electrode film 31 and a second pad electrode film 32, which are stacked in this order from the first main surface electrode 11 side, as in the first embodiment. The multiple pad electrodes 30 may also have at least one minute gap 33 at the connection portion with the first main surface electrode 11, as in the first embodiment.

[0168] The wide-bandgap semiconductor device 1G includes a second main surface electrode 34 covering the second main surface 4, similar to the first embodiment. The second main surface electrode 34 is electrically connected to the second main surface 4. Specifically, the second main surface electrode 34 forms ohmic contact with the first semiconductor region 6 exposed from the second main surface 4. The second main surface electrode 34 covers the entire area of ​​the second main surface 4 so as to extend along the periphery (first to fourth side surfaces 5A to 5D) of the chip 2.

[0169] In summary, the wide-bandgap semiconductor device 1G produces the same effects as those described for the wide-bandgap semiconductor device 1A.

[0170] Figure 16 is a cross-sectional view corresponding to Figure 12, showing a wide-bandgap semiconductor device 1H according to the eighth embodiment. In the seventh embodiment, an example was described in which the wide-bandgap semiconductor device 1G includes a photosensitive resin 17 that exposes the inner peripheral edge (inner wall) of the second inorganic insulating film 14. In contrast, the wide-bandgap semiconductor device 1H includes a photosensitive resin 17 that covers the first gate inner wall and the first source inner wall of the second inorganic insulating film 14. That is, the photosensitive resin 17 includes a portion that directly covers the plurality of first main surface electrodes 11.

[0171] Multiple resin inner walls 21 (gate resin inner wall 73 and source resin inner wall 74) of the thermosetting resin 19 expose the inner portions of the photosensitive resin 17 and multiple first main surface electrodes 11 (gate main surface electrode 65 and source main surface electrode 67), but do not expose the second inorganic insulating film 14. Multiple pad electrodes 30 (gate pad electrode 80 and source pad electrode 81) are in contact with the corresponding first main surface electrodes 11, photosensitive resin 17, and thermosetting resin 19 within the corresponding pad openings 23 (gate pad opening 75 and source pad opening 76), but are not in contact with the second inorganic insulating film 14.

[0172] In summary, the wide-bandgap semiconductor device 1H produces the same effects as those described for the wide-bandgap semiconductor device 1A.

[0173] Figure 17 corresponds to Figure 12 and is a cross-sectional view showing a wide-bandgap semiconductor device 1I according to the ninth embodiment. In the seventh embodiment, an example was described in which the thermosetting resin 19 exposes the first gate inner wall and the first source inner wall of the second inorganic insulating film 14, and the second gate inner wall and the second source inner wall of the photosensitive resin 17.

[0174] In contrast, the wide-bandgap semiconductor device 1I includes a thermosetting resin 19 that covers the first gate inner wall and the first source inner wall of the second inorganic insulating film 14, as well as the second gate inner wall and the second source inner wall of the photosensitive resin 17. In other words, the thermosetting resin 19 includes a portion that directly covers the plurality of first main surface electrodes 11.

[0175] Multiple resin inner walls 21 (pad openings 23) each expose only the corresponding first main surface electrode 11, while not exposing the second inorganic insulating film 14 and the photosensitive resin 17. In this configuration, the lower ends of the multiple resin inner walls 21 each form a gap 24 with the corresponding first main surface electrode 11. Multiple pad electrodes 30 are in contact with the corresponding first main surface electrode 11 and thermosetting resin 19 within the corresponding pad openings 23, but are not in contact with the second inorganic insulating film 14 and the photosensitive resin 17.

[0176] As described above, the wide-bandgap semiconductor device 1I also provides the same effects as those described for the wide-bandgap semiconductor device 1A. Of course, the form of the thermosetting resin 19 according to the ninth embodiment may also be applied to the eighth embodiment.

[0177] Figure 18 corresponds to Figure 12 and is a cross-sectional view showing a wide-bandgap semiconductor device 1J according to the 10th embodiment. In the 7th embodiment, an example was described in which the chip 2 has a stacked structure including a first semiconductor region 6 (wide-bandgap semiconductor substrate) and a second semiconductor region 7 (wide-bandgap semiconductor epitaxial layer) formed in this order from the second main surface 4 side. In contrast, the wide-bandgap semiconductor device 1J does not have a first semiconductor region 6 (wide-bandgap semiconductor substrate) and includes a chip 2 having a single-layer structure consisting of a second semiconductor region 7 (wide-bandgap semiconductor epitaxial layer).

[0178] As described above, the wide-bandgap semiconductor device 1J also exhibits the same effects as those described for the wide-bandgap semiconductor device 1A. Furthermore, with the wide-bandgap semiconductor device 1J, the resistance value of the first semiconductor region 6 can be reduced, thereby reducing the overall resistance value of the chip 2. In addition, since the chip 2 is supported by the thermosetting resin 19, the strength of the thinned chip 2 can be compensated for by the thermosetting resin 19. Thus, a wide-bandgap semiconductor device 1J can be provided that improves electrical characteristics while increasing reliability. Of course, the form of the chip 2 according to the 10th embodiment may also be applied to the 8th and 9th embodiments.

[0179] Figure 19 corresponds to Figure 12 and is a cross-sectional view showing a wide-bandgap semiconductor device 1K according to the 11th embodiment. In the 7th embodiment, an example was described in which the second inorganic insulating film 14 covers the electrode sidewall of the gate main electrode 65 and the electrode sidewall of the source main electrode 67. In contrast, the wide-bandgap semiconductor device 1K has a gate removal portion 14G that exposes the electrode sidewall of the gate main electrode 65 and a source removal portion 14S that exposes the electrode sidewall of the source main electrode 67, and includes a second inorganic insulating film 14 that partially covers the gate main electrode 65 and the source main electrode 67. The structure of the wide-bandgap semiconductor device 1K will be described in detail below.

[0180] The second inorganic insulating film 14, as in the seventh embodiment, covers the gate main electrode 65, the source main electrode 67, and the interlayer insulating film 64, and has a first gate inner wall on the gate main electrode 65 side, a first source inner wall on the source main electrode 67 side, and an outer wall on the outer surface 42 side. The first gate inner wall defines a first gate opening 69 that exposes the inner portion of the gate main electrode 65. The first source inner wall defines a first source opening 70 that exposes the inner portion of the source main electrode 67. The outer wall is formed at a distance inward from the periphery of the outer surface 42 and defines a dicing street 16 that exposes the second semiconductor region 7.

[0181] In this embodiment, the second inorganic insulating film 14 includes at least one gate removal portion 14G that exposes the electrode sidewall of the gate main surface electrode 65 between the gate main surface electrode 65 and the interlayer insulating film 64. Specifically, the gate removal portion 14G is formed at a distance from the inner and outer walls of the first gate and exposes the peripheral edge of the gate main surface electrode 65 and a portion of the interlayer insulating film 64.

[0182] If the second inorganic insulating film 14 has one gate removal portion 14G, the gate removal portion 14G may be formed in a strip shape extending along the periphery of the gate main surface electrode 65 in a plan view, partially exposing the periphery of the gate main surface electrode 65. Alternatively, the gate removal portion 14G may be formed in an annular shape extending along the periphery of the gate main surface electrode 65, exposing the periphery of the gate main surface electrode 65 over its entire circumference.

[0183] If the second inorganic insulating film 14 has a plurality of gate removal portions 14G, the plurality of gate removal portions 14G may be arranged at intervals along the periphery of the gate main surface electrode 65. In this case, the plurality of gate removal portions 14G may be arranged in a dot shape in a plan view, or each may be formed in a strip shape extending along the periphery of the gate main surface electrode 65.

[0184] Furthermore, the multiple gate removal sections 14G may be arranged at intervals from the peripheral edge inward of the gate main surface electrode 65. In this case, the multiple gate removal sections 14G may be arranged in a dot pattern in a plan view, or they may each be formed in a strip or ring shape extending along the peripheral edge of the gate main surface electrode 65. In this case, it is sufficient that at least one gate removal section 14G exposes the electrode side wall (periphery) of the gate main surface electrode 65.

[0185] In this configuration, the gate removal section 14G also exposes the electrode sidewall of the gate wiring electrode 66. Preferably, the gate removal section 14G exposes the entire area of ​​the gate wiring electrode 66. In other words, it is preferable that the second inorganic insulating film 14 does not cover the gate wiring electrode 66.

[0186] In this embodiment, the second inorganic insulating film 14 includes at least one source removal portion 14S that exposes the electrode sidewall of the source main surface electrode 67 between the source main surface electrode 67 and the interlayer insulating film 64. Specifically, the source removal portion 14S is formed at a distance from the inner and outer walls of the first source and exposes the peripheral edge of the source main surface electrode 67 and a portion of the interlayer insulating film 64.

[0187] If the second inorganic insulating film 14 has one source removal portion 14S, the one source removal portion 14S may be formed in a strip shape extending along the periphery of the source main surface electrode 67 in a plan view, partially exposing the periphery of the source main surface electrode 67. Alternatively, the one source removal portion 14S may be formed in an annular shape extending along the periphery of the source main surface electrode 67, exposing the periphery of the source main surface electrode 67 over its entire circumference.

[0188] If the second inorganic insulating film 14 has a plurality of source removal portions 14S, the plurality of source removal portions 14S may be arranged at intervals along the periphery of the source main surface electrode 67. In this case, the plurality of source removal portions 14S may be arranged in a dot pattern in a plan view, or each may be formed in a strip shape extending along the periphery of the source main surface electrode 67.

[0189] Furthermore, the multiple source removal sections 14S may be arranged at intervals from the peripheral edge inward of the source main surface electrode 67. In this case, the multiple source removal sections 14S may be arranged in a dot pattern in a plan view, or they may each be formed in a strip or ring shape extending along the peripheral edge of the source main surface electrode 67. In this case, it is sufficient that at least one source removal section 14S exposes the electrode side wall (periphery) of the source main surface electrode 67.

[0190] In this configuration, the source removal section 14S also exposes the electrode sidewall of the source wiring electrode 68. Preferably, the source removal section 14S exposes the entire surface of the source wiring electrode 68. In other words, it is preferable that the second inorganic insulating film 14 does not cover the source wiring electrode 68. Furthermore, it is preferable that the source removal section 14S exposes the stepped portion (first to fourth connection surfaces 43A to 43D) formed between the active surface 41 and the outer surface 42.

[0191] In this embodiment, the photosensitive resin 17 penetrates the gate removal portion 14G from above the second inorganic insulating film 14. Within the gate removal portion 14G, the photosensitive resin 17 covers the electrode sidewalls of the gate main surface electrode 65 and the electrode sidewalls of the gate wiring electrode 66. In this embodiment, within the gate removal portion 14G, the photosensitive resin 17 directly covers the peripheral portion of the gate main surface electrode 65, the entire area of ​​the gate wiring electrode 66, and a portion of the interlayer insulating film 64. In other words, the photosensitive resin 17 has a resin gate anchor portion located within the gate removal portion 14G.

[0192] In this embodiment, the photosensitive resin 17 penetrates the source removal section 14S from above the second inorganic insulating film 14. Within the source removal section 14S, the photosensitive resin 17 covers the electrode sidewalls of the source main surface electrode 67 and the electrode sidewalls of the source wiring electrode 68. In this embodiment, the photosensitive resin 17 directly covers the peripheral portion of the source main surface electrode 67, the entire area of ​​the source wiring electrode 68, and a portion of the interlayer insulating film 64 within the source removal section 14S. In other words, the photosensitive resin 17 has a resin source anchor portion located within the source removal section 14S.

[0193] In this embodiment, the thermosetting resin 19 includes a portion that covers the gate removal portion 14G and the source removal portion 14S of the second inorganic insulating film 14, sandwiching the photosensitive resin 17. That is, the thermosetting resin 19 includes a portion that covers the peripheral edge of the gate main surface electrode 65 and the gate wiring electrode 66, sandwiching only the photosensitive resin 17 without the second inorganic insulating film 14. Furthermore, the thermosetting resin 19 includes a portion that covers the peripheral edge of the source main surface electrode 67 and the source wiring electrode 68, sandwiching only the photosensitive resin 17 without the second inorganic insulating film 14. Preferably, the thermosetting resin 19 covers the entire area of ​​the gate removal portion 14G and the entire area of ​​the source removal portion 14S in both plan view and cross-sectional view.

[0194] As described above, the wide-bandgap semiconductor device 1K exhibits the same effects as those described for the wide-bandgap semiconductor device 1A. Furthermore, the wide-bandgap semiconductor device 1K includes a second inorganic insulating film 14 having a gate removal portion 14G that exposes the electrode sidewall of the gate main surface electrode 65. This structure reduces the starting point for delamination of the second inorganic insulating film 14 caused by thermal expansion of the gate main surface electrode 65. Therefore, a wide-bandgap semiconductor device 1K with improved reliability can be provided.

[0195] The wide-bandgap semiconductor device 1K preferably includes a photosensitive resin 17 that covers the electrode sidewall of the gate main surface electrode 65 within the gate removal portion 14G. This structure reduces the peeling point of the gate main surface electrode 65 in a structure in which the second inorganic insulating film 14 has a gate removal portion 14G. Therefore, a wide-bandgap semiconductor device 1K with improved reliability can be provided.

[0196] The wide-bandgap semiconductor device 1K preferably has a thermosetting resin 19 that includes a portion that covers the gate removal portion 14G with a photosensitive resin 17 in between. With this structure, in a structure in which the second inorganic insulating film 14 has a gate removal portion 14G, the peeling starting point of the gate main surface electrode 65 can be reduced by the photosensitive resin 17 and the thermosetting resin 19.

[0197] Furthermore, the wide-bandgap semiconductor device 1K includes a second inorganic insulating film 14 having a source removal portion 14S that exposes the electrode sidewall of the source main surface electrode 67. This structure reduces the starting point for delamination of the second inorganic insulating film 14 caused by thermal expansion of the source main surface electrode 67. Therefore, a wide-bandgap semiconductor device 1K with improved reliability can be provided.

[0198] The wide-bandgap semiconductor device 1K preferably includes a photosensitive resin 17 that covers the electrode sidewall of the source main surface electrode 67 within the source removal section 14S. With this structure, in a structure in which the second inorganic insulating film 14 has a source removal section 14S, the peeling initiation point of the source main surface electrode 67 can be reduced by the photosensitive resin 17 and the thermosetting resin 19.

[0199] The wide-bandgap semiconductor device 1K preferably has a thermosetting resin 19 that includes a portion that covers the source removal portion 14S with a photosensitive resin 17 in between. With this structure, in a structure in which the second inorganic insulating film 14 has a source removal portion 14S, the peeling starting point of the source main surface electrode 67 can be reduced by the photosensitive resin 17 and the thermosetting resin 19.

[0200] The second inorganic insulating film 14 preferably has a gate removal portion 14G that exposes the electrode sidewall of the gate wiring electrode 66. This structure reduces the starting point of delamination of the second inorganic insulating film 14 caused by thermal expansion of the gate wiring electrode 66. The second inorganic insulating film 14 preferably has a source removal portion 14S that exposes the electrode sidewall of the source wiring electrode 68. This structure reduces the starting point of delamination of the second inorganic insulating film 14 caused by thermal expansion of the source wiring electrode 68.

[0201] Of course, the forms of the gate main surface electrode 65, gate wiring electrode 66, source main surface electrode 67, source wiring electrode 68, second inorganic insulating film 14, photosensitive resin 17, and thermosetting resin 19 according to the 11th embodiment may also be applied to the 8th to 10th embodiments.

[0202] Figure 20 corresponds to Figure 12 and is a cross-sectional view showing a wide bandgap semiconductor device 1L according to the 12th embodiment. In the 7th embodiment, an example was described in which the photosensitive resin 17 has a curved second gate inner wall that bulges toward the inward side of the gate main surface electrode 65, a curved second source inner wall that bulges toward the inward side of the source main surface electrode 67, and a curved outer wall that bulges toward the peripheral side of the outer surface 42.

[0203] In contrast, the wide-bandgap semiconductor device 1L includes a photosensitive resin 17 having a second gate inner wall that slopes diagonally downward toward the inward side of the gate main surface electrode 65, a second source inner wall that slopes diagonally downward toward the inward side of the source main surface electrode 67, and an outer wall that slopes diagonally downward toward the peripheral side of the chip 2 (outer surface 42). In other words, the photosensitive resin 17 is formed in a trapezoidal (tapered) shape in cross-section.

[0204] As described above, the wide-bandgap semiconductor device 1L also provides the same effects as those described for the wide-bandgap semiconductor device 1A. Furthermore, the wide-bandgap semiconductor device 1L can improve the fluidity of the thermosetting resin 19 (matrix resin 27 and multiple fillers 28) relative to the photosensitive resin 17. This suppresses the formation of gaps between the thermosetting resin 19 and the photosensitive resin 17. Of course, the form of the photosensitive resin 17 according to the 12th embodiment may also be applied to the 8th to 11th embodiments.

[0205] The following shows modified versions of the pad electrode 30. Figure 21 corresponds to Figure 3 and is a cross-sectional view showing a modified version of the pad electrode 30. In the first embodiment described above, an example was described in which the wide bandgap semiconductor device 1A includes a pad electrode 30 having a laminated structure that includes a first pad electrode film 31 and a second pad electrode film 32 stacked in this order from the first main surface electrode 11 side.

[0206] However, as shown in Figure 21, the pad electrode 30 may have a laminated structure including a nickel film 90, a palladium film 91, and a gold film 92, which are stacked in this order from the first main surface electrode 11 side. The nickel film 90, palladium film 91, and gold film 92 may be formed by electroplating and / or electroless plating.

[0207] The nickel film 90 may be formed to a thickness that fills the first opening 15 and the second opening 18 and is in contact with the resin inner wall 21. The nickel film 90 may have an electrode surface 90a exposed from the thermosetting resin 19 (pad opening 23). The electrode surface 90a may extend along the first main surface 3. The electrode surface 90a may extend substantially parallel to the first main surface 3. The electrode surface 90a may be connected to the resin main surface 20. The electrode surface 90a may consist of a ground surface having grinding marks. The electrode surface 90a may form a single ground surface with the resin main surface 20. The nickel film 90 may have an overhang 30b that rides up onto the outer surface of the photosensitive resin 17 within the gap 24.

[0208] The palladium film 91 may be coated with a nickel film 90 so as to protrude from the main resin surface 20. The palladium film 91 may have a coating portion that covers a part of the thermosetting resin 19 (main resin surface 20) at a distance from the resin side surface 22. The coating portion of the palladium film 91 may cover at least one filler fragment 29 (first filler fragment 29a).

[0209] The gold film 92 may be coated with a palladium film 91 so as to protrude from the resin main surface 20. The gold film 92 may have a covering portion that covers a part of the thermosetting resin 19 (resin main surface 20) at a distance from the resin side surface 22. The covering portion of the gold film 92 may cover at least one filler fragment 29 (first filler fragment 29a). The gold film 92 may have an electrode surface 92a that is exposed from the thermosetting resin 19 (resin main surface 20). In this case, the electrode surface 92a may be a smooth surface without grinding marks.

[0210] As described above, even when the pad electrode 30 according to the modified example is present, the same effects as those described for the wide-bandgap semiconductor device 1A are achieved. In this embodiment, an example is shown in which the palladium film 91 and the gold film 92 are located outside the pad opening 23. However, the nickel film 90, palladium film 91, and gold film 92 may all be placed inside the pad opening 23. In this case, the electrode surface 92a of the gold film 92 may be a smooth surface without grinding marks.

[0211] Furthermore, the pad electrode 30 does not necessarily have to include the palladium film 91, and may also include nickel films 90 and gold films 92 stacked in that order from the first main surface electrode 11 side. Of course, the modified pad electrode 30 may be applied to the pad electrode 30 (including the gate pad electrode 80 and the source pad electrode 81) according to the second to twelfth embodiments.

[0212] The following shows examples of package configurations on which wide-bandgap semiconductor devices 1A to 1L according to the first to twelfth embodiments are mounted. Figure 22 is a plan view of semiconductor package 101A on which wide-bandgap semiconductor devices 1A to 1F according to the first to sixth embodiments are mounted.

[0213] The semiconductor package 101A includes a rectangular parallelepiped package body 102. The package body 102 is made of a mold resin containing a matrix resin (e.g., epoxy resin) and a plurality of fillers. The package body 102 has a first surface 103 on one side, a second surface 104 on the other side, and first to fourth side walls 105A to 105D connecting the first surface 103 and the second surface 104.

[0214] The first surface 103 and the second surface 104 are formed in a quadrilateral shape in a plan view taken from their normal direction Z. The first side wall 105A and the second side wall 105B extend in the first direction X and face the second direction Y which is perpendicular to the first direction X. The third side wall 105C and the fourth side wall 105D extend in the second direction Y and face the first direction X.

[0215] The semiconductor package 101A includes a metal plate 106 (conductor plate) disposed within the package body 102. The metal plate 106 is formed in a rectangular shape (specifically, a square shape) in plan view. The metal plate 106 includes a lead plate portion 107 that extends from the fourth side wall 105D to the outside of the package body 102. The lead plate portion 107 may be referred to as a "heat spreader portion". The lead plate portion 107 has a circular through hole 108. The metal plate 106 may be exposed from the second surface 104.

[0216] The semiconductor package 101A includes a plurality (two in this configuration) of terminal electrodes 109 that are drawn out from inside the package body 102 to the outside. The plurality of terminal electrodes 109 are arranged on the third side wall 105C side. Each of the plurality of terminal electrodes 109 is formed in a strip shape extending in a direction perpendicular to the third side wall 105C (i.e., the second direction Y). One terminal electrode 109 is arranged at a distance from the metal plate 106, while the other terminal electrode 109 is formed integrally with the metal plate 106.

[0217] The semiconductor package 101A includes an SBD chip 110 disposed on a metal plate 106 within the package body 102. The SBD chip 110 consists of one of the wide bandgap semiconductor devices 1A to 1F according to the first to sixth embodiments. The second main surface electrode 34 of the SBD chip 110 is electrically connected to the metal plate 106. The semiconductor package 101A includes a conductive bonding material 111. The conductive bonding material 111 may include solder or metal paste (preferably solder). The conductive bonding material 111 is interposed between the second main surface electrode 34 and the metal plate 106, connecting the SBD chip 110 to the metal plate 106.

[0218] The semiconductor package 101A includes at least one conductor 112 (conductive connecting member) that connects the terminal electrode 109 and the pad electrode 30 of the SBD chip 110 within the package body 102. The conductor 112 may be referred to as a "bonding wire". The conductor 112 may include at least one of gold wire, copper wire, and aluminum wire.

[0219] Figure 23 is a plan view showing a semiconductor package 101B on which wide bandgap semiconductor devices 1G to 1L according to the 7th to 12th embodiments are mounted. Referring to Figure 23, the semiconductor package 101B includes a package body 102, a metal plate 106, a plurality (3 in this embodiment) of terminal electrodes 109, a MISFET chip 113, a conductive bonding material 111, and a plurality of conductors 112. The differences from semiconductor package 101A will be explained below.

[0220] Of the multiple terminal electrodes 109, the terminal electrodes 109 on both sides are arranged with a gap between them and the metal plate 106, while the central terminal electrode 109 is integrally formed with the metal plate 106. The arrangement of the terminal electrodes 109 connected to the metal plate 106 is arbitrary. The MISFET chip 113 consists of one of the wide bandgap semiconductor devices 1G to 1L according to the 7th to 12th embodiments.

[0221] The second main surface electrode 34 of the MISFET chip 113 is electrically connected to the metal plate 106. A conductive bonding material 111 is interposed between the second main surface electrode 34 and the metal plate 106, connecting the MISFET chip 113 to the metal plate 106. Multiple conductors 112 are connected to multiple terminal electrodes 109, gate pad electrode 80, and source pad electrode 81, respectively.

[0222] Figure 24 is a perspective view showing a semiconductor package 101C on which wide bandgap semiconductor devices 1A to 1F according to the first to sixth embodiments and wide bandgap semiconductor devices 1G to 1L according to the seventh to twelfth embodiments are mounted. Figure 25 is an exploded perspective view of the semiconductor package 101C shown in Figure 24. Figure 26 is a cross-sectional view along the line XXVI-XXVI shown in Figure 24.

[0223] Referring to Figures 24 to 26, the semiconductor package 101C includes a rectangular parallelepiped package body 122. The package body 122 is made of a molding resin containing a matrix resin (e.g., epoxy resin) and a plurality of fillers. The package body 122 has a first surface 123 on one side, a second surface 124 on the other side, and first to fourth side walls 125A to 125D connecting the first surface 123 and the second surface 124.

[0224] The first surface 123 and the second surface 124 are formed in a quadrilateral shape (rectangular in this form) when viewed from their normal direction Z in a plan view. The first side wall 125A and the second side wall 125B extend in a first direction X along the first surface 123 and face the second direction Y. The first side wall 125A and the second side wall 125B form the short side of the package body 122. The third side wall 125C and the fourth side wall 125D extend in a second direction Y and face the first direction X. The third side wall 125C and the fourth side wall 125D form the long side of the package body 122.

[0225] The semiconductor package 101C includes a first metal plate 126 (first conductor plate, terminal electrodes) arranged inside and outside the package body 122. The first metal plate 126 is positioned on the first surface 123 side of the package body 122 and includes a first pad portion 127 and a first terminal portion 128. The first pad portion 127 is formed in a rectangular shape extending in the second direction Y within the package body 122 and is exposed from the first surface 123.

[0226] The first terminal portion 128 is drawn out in a strip shape from the first pad portion 127 in a first direction X so as to penetrate the third side wall 125C. In a plan view, the first terminal portion 128 is located on the second side wall 125B side. The first terminal portion 128 is connected to the first pad portion 127 via a first bend portion 129 that bends from the first surface 123 side to the second surface 124 side within the package body 122. The first terminal portion 128 is exposed from the third side wall 125C with a gap between the first surface 123 and the second surface 124 side.

[0227] The semiconductor package 101C includes a second metal plate 130 (conductor plate, terminal electrodes) arranged inside and outside the package body 122. The second metal plate 130 is positioned on the second surface 124 side of the package body 122, spaced apart from the first metal plate 126 in the normal direction Z, and includes a second pad portion 131 and a second terminal portion 132. The second pad portion 131 is formed in a rectangular shape extending in the second direction Y within the package body 122 and is exposed from the second surface 124.

[0228] The second terminal portion 132 is drawn out in a strip shape from the second pad portion 131 in the first direction X so as to penetrate the third side wall 125C. In a plan view, the second terminal portion 132 is located on the side of the first side wall 125A. The second terminal portion 132 is connected to the second pad portion 131 via a second bent portion 133 that bends from the second surface 124 side to the first surface 123 side within the package body 122. The second terminal portion 132 is exposed from the third side wall 125C with a gap between the second surface 124 and the first surface 123 side.

[0229] The second terminal portion 132 is drawn from a different thickness position than the first terminal portion 128 with respect to the normal direction Z. In this embodiment, the second terminal portion 132 is formed with a gap from the first terminal portion 128 toward the second surface 124 side and does not face the first terminal portion 128 in the second direction Y. The second terminal portion 132 has a different length from the first terminal portion 128 with respect to the first direction X. The first terminal portion 128 and the second terminal portion 132 are distinguished by their shapes (lengths).

[0230] The semiconductor package 101C includes a plurality (five in this embodiment) of terminal electrodes 134 that are drawn out from the inside to the outside of the package body 122. In this embodiment, the plurality of terminal electrodes 134 are positioned at a thickness between the first pad portion 127 and the second pad portion 131. The plurality of terminal electrodes 134 are exposed from a fourth side wall 125D opposite to the third side wall 125C from which the first terminal portion 128 and the second terminal portion 132 are exposed.

[0231] The arrangement of the multiple terminal electrodes 134 is arbitrary. In this embodiment, the multiple terminal electrodes 134 are arranged on the fourth side wall 125D side such that they are collinear with the second terminal portion 132 in a plan view. Each of the multiple terminal electrodes 134 is formed in a strip shape extending in the first direction X. The multiple terminal electrodes 134 may have curved portions that are recessed toward the first surface 123 and / or the second surface 124 in the portion located outside the package body 122.

[0232] The semiconductor package 101C includes an SBD chip 135 disposed within the package body 122. The SBD chip 135 is one of the wide bandgap semiconductor devices 1A to 1F according to the first to sixth embodiments. The SBD chip 135 is positioned between the first pad portion 127 and the second pad portion 131. In a plan view, the SBD chip 135 is positioned on the second side wall 125B side. The second main surface electrode 34 of the SBD chip 135 is electrically connected to the second pad portion 131.

[0233] The semiconductor package 101C includes a MISFET chip 136 disposed within the package body 122 at a distance from the SBD chip 135. The MISFET chip 136 consists of one of the wide bandgap semiconductor devices 1G to 1L according to the 7th to 12th embodiments. The MISFET chip 136 is positioned between the first pad portion 127 and the second pad portion 131. In a plan view, the MISFET chip 136 is positioned on the first side wall 125A side. The second main surface electrode 34 of the MISFET chip 136 is electrically connected to the second pad portion 131.

[0234] The semiconductor package 101C includes a first conductor spacer 137 (first conductive connecting member) and a second conductor spacer 138 (second conductive connecting member), which are respectively disposed within the package body 122. The first conductor spacer 137 is interposed between the SBD chip 135 and the first pad portion 127 and is electrically connected to the SBD chip 135 and the first pad portion 127.

[0235] The second conductor spacer 138 is interposed between the MISFET chip 136 and the first pad portion 127 and is electrically connected to the MISFET chip 136 and the first pad portion 127. The first conductor spacer 137 and the second conductor spacer 138 may each include a metal plate (for example, a Cu-based metal plate). In this embodiment, the second conductor spacer 138 is a separate entity from the first conductor spacer 137, but it may be formed integrally with the first conductor spacer 137.

[0236] The semiconductor package 101C includes first to sixth conductive bonding materials 139A to 139F. The first to sixth conductive bonding materials 139A to 139F may each contain solder or metal paste (preferably solder). The first conductive bonding material 139A is interposed between the second main surface electrode 34 and the second pad portion 131 of the SBD chip 135, connecting the SBD chip 135 to the second pad portion 131.

[0237] The second conductive bonding material 139B is interposed between the second main surface electrode 34 and the second pad portion 131 of the MISFET chip 136, connecting the MISFET chip 136 to the second pad portion 131. The third conductive bonding material 139C is interposed between the pad electrode 30 and the first conductor spacer 137 of the SBD chip 135, connecting the first conductor spacer 137 to the SBD chip 135.

[0238] The fourth conductive bonding material 139D is interposed between the source pad electrode 81 of the MISFET chip 136 and the second conductor spacer 138, connecting the second conductor spacer 138 to the MISFET chip 136. The fifth conductive bonding material 139E is interposed between the first pad portion 127 and the first conductor spacer 137, connecting the first pad portion 127 to the first conductor spacer 137. The sixth conductive bonding material 139F is interposed between the first pad portion 127 and the second conductor spacer 138, connecting the first pad portion 127 to the second conductor spacer 138.

[0239] The semiconductor package 101C includes a plurality of conductors 140 (third conductive connecting members). The plurality of conductors 140 are connected to the inner ends of a plurality of terminal electrodes 134 and to the gate pad electrodes 80 of the MISFET chip 136, respectively. The plurality of conductors 140 may also include conductors 140 connected to the inner ends of any terminal electrodes 134 and to the second pad portion 131. The plurality of conductors 140 may be referred to as "bonding wires". The plurality of conductors 140 may include at least one of gold wire, copper wire, and aluminum wire.

[0240] Each of the embodiments described above can be implemented in other forms. For example, in each of the embodiments described above, the first main surface 3 and the second main surface 4 may be formed by the c-plane ((0001) plane) of the SiC single crystal, respectively. In this case, it is preferable that the first main surface 3 is formed by the silicon plane of the SiC single crystal and the second main surface 4 is formed by the carbon plane of the SiC single crystal.

[0241] The first principal surface 3 and the second principal surface 4 may have an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and less than or equal to 10°. The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and less than or equal to 4.5°.

[0242] In each of the embodiments described above, it is preferable that the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, in each of the embodiments described above, the first direction X may be the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y may be the m-axis direction ([1-100] direction) of the SiC single crystal.

[0243] In the embodiments described above, examples were given in which a chip 2 made of a SiC single crystal was used. However, a wide-bandgap semiconductor chip made of a wide-bandgap semiconductor other than SiC may also be used. Diamond or GaN (gallium nitride) may be used as the wide-bandgap semiconductor other than SiC.

[0244] Of course, the chip 2 in each of the above embodiments may be made of a Si (silicon) single crystal. However, in this case, considering the electrical properties of Si (especially the breakdown voltage), it is necessary to form a thicker second semiconductor region 7 (Si epitaxial layer), so it should be noted that when a thermosetting resin 19 is provided, the size will be larger than in the case of a wide-bandgap semiconductor device.

[0245] In the embodiments described above, examples in which a second inorganic insulating film 14 is formed were described. However, the second inorganic insulating film 14 is not necessarily required and may be removed if necessary. In the embodiments described above, examples were described in which the thermosetting resin 19 partitions the gap 24 with the photosensitive resin 17, and the pad electrode 30 has a protruding portion 30b located within the gap 24. However, a thermosetting resin 19 that does not partition the gap 24 with the photosensitive resin 17 may be formed, and a pad electrode 30 without a protruding portion 30b may be formed.

[0246] In the embodiments described above, examples were given in which SBDs and MISFETs, as examples of functional devices, are formed on different chips 2, respectively. However, SBDs and MISFETs may be formed on different regions of the first main surface 3 on the same chip 2.

[0247] In the embodiments described above, a configuration in which the first conductivity type is n-type and the second conductivity type is p-type was described. However, in the embodiments described above, a configuration in which the first conductivity type is p-type and the second conductivity type is n-type may also be adopted. In this case, the specific configuration can be obtained by replacing the n-type region with a p-type region and the p-type region with an n-type region, as shown in the above description and attached drawings.

[0248] The following are examples of features extracted from this specification and the accompanying drawings. Items [A1] to [A20] and [B1] to [B21] below provide a semiconductor device that can improve reliability. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each item to the embodiments. In the following items, "wide bandgap semiconductor" may be replaced with "semiconductor".

[0249] [A1] A wide-bandgap semiconductor device (1A~1L) comprising: a chip (2) having a main surface (3) and including a wide-bandgap semiconductor; first main surface electrodes (11, 65, 67) disposed on the main surface (3); and a thermosetting resin (19) comprising a matrix resin (27) and a plurality of fillers (28) that covers the main surface (3) such that a portion of the first main surface electrodes (11, 65, 67) is exposed.

[0250] [A2] The thermosetting resin (19) is thicker than the first main surface electrodes (11, 65, 67), in the wide bandgap semiconductor device (1A~1L) according to A1 or A2.

[0251] [A3] The wide bandgap semiconductor device (1A~1L) according to A2, wherein the plurality of fillers (28) include a plurality of first fillers (28a) that are thinner than the first main surface electrodes (11, 65, 67), and a plurality of second fillers (28b, 28c) that are thicker than the first main surface electrodes (11, 65, 67).

[0252] [A4] A wide bandgap semiconductor device (1A to 1L) according to any one of A1 to A3, further comprising a photosensitive resin (17) that covers the peripheral edges of the first main surface electrodes (11, 65, 67), wherein the thermosetting resin (19) covers the photosensitive resin (17).

[0253] [A5] The wide bandgap semiconductor device (1A~1L) described in A4, wherein the photosensitive resin (17) is thicker than the first main surface electrodes (11, 65, 67), and the thermosetting resin (19) is thicker than the photosensitive resin (17).

[0254] [A6] The wide bandgap semiconductor device (1A~1L) according to A5, wherein the plurality of fillers (28) include a plurality of large-diameter fillers (28c) that are thicker than the photosensitive resin (17).

[0255] [A7] The thermosetting resin (19) is thicker than the chip (2), and is a wide bandgap semiconductor device (1A to 1L) as described in any one of A1 to A6.

[0256] [A8] A wide bandgap semiconductor device (1A to 1L) according to any one of A1 to A7, further comprising pad electrodes (30, 80, 81) formed on the portion of the first main surface electrodes (11, 65, 67) exposed from the thermosetting resin (19), and having electrode surfaces (30a, 80a, 81a, 90a, 92a) exposed from the thermosetting resin (19).

[0257] [A9] The wide bandgap semiconductor device (1A~1L) according to A8, wherein the electrode surfaces (30a, 80a, 81a, 90a) form a single flat surface with the outer surface of the thermosetting resin (19).

[0258] [A10] The wide bandgap semiconductor device (1A~1L) according to A8 or A9, wherein the pad electrodes (30, 80, 81) have a laminated structure including a first electrode film (31) covering the first main surface electrodes (11, 65, 67) and a second electrode film (32) covering the first electrode film (31).

[0259] [A11] A wide bandgap semiconductor device (1A to 1L) according to any one of A1 to A10, wherein the plurality of fillers (28) include a plurality of filler fragments (29, 29a, 29b) having a granular shape formed by fracture in the surface layer of the thermosetting resin (19).

[0260] [A12] The wide bandgap semiconductor device (1A to 1L) according to any one of A1 to A11, wherein the chip (2) has side surfaces (5, 5A to 5D), and the thermosetting resin (19) has resin side surfaces (22, 22A to 22D) connected to the side surfaces (5, 5A to 5D).

[0261] [A13] The wide bandgap semiconductor device (1A-1L) according to A12, wherein the resin side surfaces (22, 22A-22D) form a single grinding surface with the side surfaces (5, 5A-5D) of the chip (2).

[0262] [A14] The thermosetting resin (19) includes a portion that directly covers the main surface (3) at the peripheral edge of the chip (2), as described in any one of A1 to A13, wide bandgap semiconductor device (1A to 1L).

[0263] [A15] A wide bandgap semiconductor device (1A to 1L) according to any one of A1 to A14, wherein a plurality of first main surface electrodes (11, 65, 67) are arranged on the main surface, and the thermosetting resin (19) covers the main surface (3) such that a portion of each of the plurality of first main surface electrodes (11, 65, 67) is exposed.

[0264] [A16] The chip (2) has a stacked structure including a semiconductor substrate (6) and an epitaxial layer (7), each composed of a wide bandgap semiconductor, and includes the main surface (3) formed by the epitaxial layer (7), as described in any one of A1 to A15 (1A to 1L).

[0265] [A17] The chip (2) has a single-layer structure consisting of an epitaxial layer (7) made of a wide-bandgap semiconductor, as described in any one of A1 to A15 (1A to 1L).

[0266] [A18] A wide bandgap semiconductor device (1A to 1L) according to any one of A1 to A17, further comprising a functional device formed on the chip (2), wherein the first main surface electrodes (11, 65, 67) are electrically connected to the functional device.

[0267] [A19] The wide bandgap semiconductor device (1A to 1L) according to A18, wherein the functional device includes at least one of a diode (SBD) and a transistor (MISFET).

[0268] [A20] A package body (102, 122) made of molded resin, conductive plates (106, 126) disposed inside the package body (102, 122), terminal electrodes (109, 130, 134) disposed inside the package body (102, 122) at a distance from the conductive plates (106, 126) so as to be partially exposed from the package body (102, 122), and inside the package body (102, 122) A semiconductor package (101A to 101C) comprising a wide bandgap semiconductor device (1A to 1L) described in any one of A1 to A19, disposed on the conductive plates (106, 126), and conductive connecting members (112, 137, 138, 140) electrically connected to the terminal electrodes (109, 130, 134) and the wide bandgap semiconductor device (1A to 1L) within the package body (102, 122).

[0269] [B1] A semiconductor device (1A~1L) comprising: a chip (2) having a main surface (3); first main surface electrodes (11, 65, 67) disposed on the main surface (3); a first organic film (17) covering the peripheral edges of the first main surface electrodes (11, 65, 67); and a second organic film (19) comprising a matrix resin (27) and a plurality of fillers (28) that covers the main surface (3) and the first organic film (17) such that a portion of the first main surface electrodes (11, 65, 67) is exposed.

[0270] [B2] The semiconductor device (1A to 1L) according to B1, wherein the second organic film (19) contains a plurality of the fillers (28) having different particle sizes.

[0271] [B3] The semiconductor device (1A to 1L) according to B1 or B2, wherein the plurality of the fillers (28) contain a plurality of filler fragments (29, 29a, 29b) having a broken grain shape in the surface layer portion of the second organic film (19).

[0272] [B4] The semiconductor device (1A to 1L) according to any one of B1 to B3, wherein the second organic film (19) is thicker than the first organic film (17).

[0273] [B5] The semiconductor device (1A to 1L) according to B4, wherein the plurality of the fillers (28) contain a plurality of small-diameter fillers (28a) thinner than the first main surface electrodes (11, 65, 67), and a plurality of large-diameter fillers (28c) thicker than the second organic film (19).

[0274] [B6] The semiconductor device (1A to 1L) according to any one of B1 to B5, wherein the first organic film (17) is thicker than the first main surface electrodes (11, 65, 67).

[0275] [B7] The semiconductor device (1A to 1L) according to any one of B1 to B6, further including pad electrodes (30, 80, 81) disposed on a portion of the first main surface electrodes (11, 65, 67) exposed from the second organic film (19).

[0276] [B8] The semiconductor device (1A to 1L) according to B7, wherein the second organic film (19) has openings (23, 75, 76) partitioned by a wall surface located on the first organic film (17), and the pad electrodes (30, 8, 81) are in contact with the first organic film (17) and the second organic film (19) within the openings (23, 75, 76).

[0277] [B9]The wall surface of the opening (23, 75, 76) has a lower end portion that forms a gap (24) with the outer surface of the first organic film (17), and the pad electrodes (30, 80, 81) are located within the gap (24) and have an overhanging portion (30b) that rides on the outer surface of the first organic film (17). The semiconductor device (1A to 1L) according to B8.

[0278] [B10]The wall surface of the opening (23, 75, 76) has a first wall portion (25) that extends in the thickness direction from the opening end to the lower end portion, and a second wall portion (26) that extends in a direction intersecting the first wall portion (25) so as to form the gap (24) with the outer surface of the first organic film (17) at the lower end portion. The semiconductor device (1A to 1L) according to B9.

[0279] [B11]The length of the overhanging portion (30b) exceeds the thickness of the first organic film (17). The semiconductor device (1A to 1L) according to B9 or B10.

[0280] [B12]The pad electrodes (30, 80, 81) have a laminated structure including a first electrode film (31) that covers the first main surface electrode (11, 65, 67), and a second electrode film (32) that covers the first electrode film (31), and the overhanging portion (30b) includes the first electrode film (31) and the second electrode film (32). The semiconductor device (1A to 1L) according to any one of B9 to B11.

[0281] ​​​​​​​​​[B15] The semiconductor device (1A to 1L) according to any one of B7 to B14, wherein the pad electrodes (30, 80, 81) have electrode surfaces (30a, 80a, 81a) that form a single flat surface with the outer surface of the second organic film (19).

[0284] [B16] The semiconductor device (1A to 1L) according to any one of B1 to B15, wherein the chip (2) has sides (5, 5A to 5D), and the second organic film (19) has organic sides (23, 23A to 23D) that form a single flat surface with the sides (5, 5A to 5D) of the chip (2).

[0285] [B17] The chip (2) has a second main surface (4) that faces away from the main surface (3) and is made of a ground surface, according to any one of B1 to B16 (1A to 1L).

[0286] [B18] A semiconductor device (1A to 1F) according to any one of B1 to B17, comprising a single first main surface electrode (11).

[0287] [B19] The semiconductor device (1A~1F) described in B18, wherein the first main surface electrode (11) forms a Schottky junction with the main surface (3).

[0288] [B20] A semiconductor device (1G to 1L) according to any one of B1 to B17, comprising a plurality of first main surface electrodes (11, 65, 66), wherein the first organic film (17) covers the peripheral edges of each of the plurality of first main surface electrodes (11, 65, 66), and the second organic film (19) covers the main surface (3) such that parts of each of the plurality of first main surface electrodes (11, 65, 66) are exposed.

[0289] [B21] The semiconductor device (1G~1L) according to B20, further comprising a channel (CH) formed on the surface layer of the main surface (3), and a gate structure (50) formed on the main surface (3) to control the channel (CH), wherein a plurality of the first main surface electrodes (11, 65, 66) include gate main surface electrodes (11, 65) electrically connected to the gate structure (50), and channel main surface electrodes (11, 66) electrically connected to the channel (CH).

[0290] Although embodiments have been described in detail, these are merely specific examples used to clarify the technical content, and the present invention should not be interpreted as being limited to these specific examples. The scope of the present invention is limited by the appended claims. [Explanation of Symbols]

[0291] 1A: Wide bandgap semiconductor device, 1B: Wide bandgap semiconductor device, 1C: Wide bandgap semiconductor device, 1D: Wide bandgap semiconductor device, 1E: Wide bandgap semiconductor device, 1F: Wide bandgap semiconductor device, 1G: Wide bandgap semiconductor device, 1H: Wide bandgap semiconductor device, 1I: Wide bandgap semiconductor device, 1J: Wide bandgap semiconductor device, 1K: Wide bandgap semiconductor device, 1L: Wide bandgap semiconductor device, 2: Chip, 3: First main surface, 4: Second main surface, 5: Side surface, 6: First semiconductor region (semiconductor substrate), 7: Second semiconductor region (epitaxial layer), 11: First main surface electrode, 17: Photosensitive resin, 19: Thermosetting resin, 20: Pad opening, 21: Resin main surface, 23: Resin side surface, 27: Matrix resin, 28: Filler, 28a: Small diameter filler, 28b: Medium diameter filler, 28c: Large diameter filler, 29: Filler fragment ,29a:First filler fragment,29b:Second filler fragment,30:Pad electrode,30a:Electrode surface,31:First pad electrode film,32:Second pad electrode film,65:Gate main surface electrode (First main surface electrode),67:Source main surface electrode (First main surface electrode),73:Gate pad opening (Pad opening),74:Source pad opening (Pad opening),80:Gate pad electrode (Pad electrode),80a:Electrode surface,81:Source pad electrode (Pad electrode),81a:Electrode surface,101A: Semiconductor package, 101B: Semiconductor package, 101C: Semiconductor package, 102: Package body, 106: Metal plate (conductor plate), 109: Terminal electrode, 112: Conductor (conductive connecting member), 122: Package body, 126: First metal plate (conductor plate, terminal electrode), 130: Second metal plate (conductor plate, terminal electrode), 134: Terminal electrode, 137: First conductor spacer (conductive connecting member), 138: Second conductor spacer (conductive connecting member), 139: Conductor (conductive connecting member)

Claims

1. A chip containing a wide-bandgap semiconductor and having a main surface, A main surface electrode disposed on the main surface, A thermosetting resin comprising a matrix resin and a plurality of fillers, covering the main surface such that a portion of the main surface electrode is exposed, The present invention further includes a pad electrode formed on the portion of the main surface electrode exposed from the thermosetting resin, having an electrode surface exposed from the thermosetting resin, and a protruding portion that slopes diagonally downward from the thermosetting resin side toward the main surface electrode side between the thermosetting resin and the main surface electrode, A wide-bandgap semiconductor device in which the thickness of the pad electrode exceeds the thickness of the main surface electrode.

2. A chip containing a wide-bandgap semiconductor and having a main surface, A main surface electrode disposed on the main surface, A thermosetting resin comprising a matrix resin and a plurality of fillers, which covers the main surface such that a portion of the main surface electrode is exposed, The thermosetting resin is thicker than the main surface electrode. A wide-bandgap semiconductor device comprising a plurality of fillers, each of which includes a plurality of first fillers thinner than the main surface electrode and a plurality of second fillers thicker than the main surface electrode.

3. A chip containing a wide-bandgap semiconductor and having a main surface, A main surface electrode disposed on the main surface, A thermosetting resin comprising a matrix resin and a plurality of fillers, which covers the main surface such that a portion of the main surface electrode is exposed, The material further includes a photosensitive resin that covers the peripheral edge of the main surface electrode, The thermosetting resin coats the photosensitive resin in a wide-bandgap semiconductor device.

4. A chip containing a wide-bandgap semiconductor and having a main surface, A main surface electrode disposed on the main surface, A thermosetting resin comprising a matrix resin and a plurality of fillers, which covers the main surface such that a portion of the main surface electrode is exposed, A wide-bandgap semiconductor device comprising a plurality of filler fragments having a granular shape formed by fracture in the surface layer of the thermosetting resin.

5. The wide-bandgap semiconductor device according to claim 1, 3, or 4, wherein the thermosetting resin is thicker than the main surface electrode.

6. The wide bandgap semiconductor device according to claim 1, 3, 4, or 5, wherein the plurality of fillers include a plurality of first fillers that are thinner than the main surface electrode and a plurality of second fillers that are thicker than the main surface electrode.

7. The material further includes a photosensitive resin that covers the peripheral edge of the main surface electrode, The wide-bandgap semiconductor device according to claim 1, 2, or 4, wherein the thermosetting resin coats the photosensitive resin.

8. The photosensitive resin is thicker than the main surface electrode. The wide-bandgap semiconductor device according to claim 3 or 7, wherein the thermosetting resin is thicker than the photosensitive resin.

9. The wide bandgap semiconductor device according to claim 8, wherein the plurality of fillers include a plurality of large-diameter fillers that are thicker than the photosensitive resin.

10. The thermosetting resin is thicker than the chip, as described in any one of claims 1 to 9, for a wide bandgap semiconductor device.

11. The wide-bandgap semiconductor device according to any one of claims 2 to 4, further comprising a pad electrode formed on a portion of the main surface electrode exposed from the thermosetting resin, and having an electrode surface exposed from the thermosetting resin.

12. The wide-bandgap semiconductor device according to claim 1 or 11, wherein the electrode surface forms a single flat surface with the outer surface of the thermosetting resin.

13. The wide bandgap semiconductor device according to claim 11 or 12, wherein the pad electrode has a laminated structure including a first electrode film covering the main surface electrode and a second electrode film covering the first electrode film.

14. The wide bandgap semiconductor device according to any one of claims 1 to 3, wherein the plurality of fillers include a plurality of filler fragments having a granular shape that is fractured in the surface layer of the thermosetting resin.

15. The aforementioned chip has sides, The wide-bandgap semiconductor device according to any one of claims 1 to 14, wherein the thermosetting resin has a resin side surface that is continuous with the side surface.

16. The wide-bandgap semiconductor device according to claim 15, wherein the resin side surface forms a single grinding surface with the side surface of the chip.

17. The wide-bandgap semiconductor device according to any one of claims 1 to 16, wherein the thermosetting resin includes a portion that directly covers the main surface at the peripheral edge of the chip.

18. Multiple main surface electrodes are arranged on the main surface, The wide-bandgap semiconductor device according to any one of claims 1 to 17, wherein the thermosetting resin covers the main surface such that a portion of each of the multiple main surface electrodes is exposed.

19. The chip has a stacked structure including a semiconductor substrate and an epitaxial layer, each composed of a wide-bandgap semiconductor, and includes the main surface formed by the epitaxial layer, according to any one of claims 1 to 18.

20. The wide-bandgap semiconductor device according to any one of claims 1 to 18, wherein the chip has a single-layer structure consisting of an epitaxial layer.

21. The chip further includes a functional device formed on the chip, The wide-bandgap semiconductor device according to any one of claims 1 to 20, wherein the main surface electrode is electrically connected to the functional device.

22. The wide-bandgap semiconductor device according to claim 21, wherein the functional device includes at least one of a diode and a transistor.

23. The package body is made of molded resin, A conductive plate arranged inside the package body, Terminal electrodes are arranged within the package body at a distance from the conductive plate so as to be partially exposed from the package body, A wide-bandgap semiconductor device according to any one of claims 1 to 22, disposed on the conductive plate within the package body, A semiconductor package comprising a terminal electrode and a connecting member electrically connected to the wide-bandgap semiconductor device within the package body.

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