Semiconductor equipment

Abstract

To provide a semiconductor device that enables diodes to operate at a higher speed. [Solution] The semiconductor device according to the embodiment comprises first and second electrodes and first and second regions. The second electrode is separated from the first electrode. The first region includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a gate electrode, a fourth semiconductor region of a second conductivity type, a fifth semiconductor region of a first conductivity type, and a sixth semiconductor region of a first conductivity type. The fifth semiconductor region is provided between a part of the third semiconductor region and the fourth semiconductor region. The gate electrode faces the third to fifth semiconductor regions in a second direction. Multiple sets of a part of the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are provided in a third direction. The fifth semiconductor region has a higher impurity concentration of the first conductivity type than the third semiconductor region. The sixth semiconductor region is provided between the third semiconductor region and a part of the second electrode.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] One type of semiconductor device used for power conversion and other applications is the Reverse Conducting Insulated Gate Bipolar Transistor (RC-IGBT), which incorporates a diode into an Insulated Gate Bipolar Transistor (IGBT). There is a need for technology that enables faster diode operation in this type of semiconductor device. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6384425 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device that can operate diodes at a higher speed. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment comprises a first electrode, a second electrode, a first region, and a second region. The second electrode is separated from the first electrode. The first region is located between the first electrode and the second electrode and is provided on a portion of the first electrode. The first region includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a gate electrode, a fourth semiconductor region of a second conductivity type, a fifth semiconductor region of a first conductivity type, and a sixth semiconductor region of a first conductivity type. A portion of the second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the portion of the second semiconductor region. The gate electrode faces the third semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the second electrode and is electrically insulated from the second electrode. The fourth semiconductor region is provided on the third semiconductor region and is aligned with a portion of the second electrode in the second direction. The fifth semiconductor region is provided between a part of the third semiconductor region and the fourth semiconductor region in a third direction perpendicular to the first and second directions, and is aligned with a part of the second electrode in the second direction, and has a higher impurity concentration of the first conductivity type than the third semiconductor region. The sixth semiconductor region is provided between the third semiconductor region and a part of the second electrode, and has a higher impurity concentration of the first conductivity type than the third semiconductor region. The gate electrode faces the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region in the second direction. Multiple sets of a part of the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are provided in the third direction. The second region is provided between the first electrode and the second electrode, on another part of the first electrode. The second region includes a seventh semiconductor region of the second conductivity type, another part of the second semiconductor region, and an eighth semiconductor region of the first conductivity type. The seventh semiconductor region has a higher impurity concentration of the second conductivity type than the second semiconductor region. Another portion of the second semiconductor region is provided on the seventh semiconductor region. The eighth semiconductor region is provided on the other portion of the second semiconductor region. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a plan view of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is an enlarged plan view of part A of Figure 1. [Figure 3] Figure 3 is a cross-sectional view of the line B1-B2 in Figure 2. [Figure 4] Figure 4 is a cross-sectional view of the line C1-C2 in Figure 2. [Figure 5] Figure 5 is a cross-sectional view taken along the line D1-D2 in Figure 2. [Figure 6] Figure 6 is a plan view showing a part of a semiconductor device according to a reference example. [Figure 7] Figure 7 is a schematic diagram illustrating the characteristics of a semiconductor device. [Figure 8] Figure 8 is a plan view showing a part of a semiconductor device according to a first modified example of the first embodiment. [Figure 9] Figure 9 is an enlarged plan view of part A of Figure 8. [Figure 10] Figure 10 is a cross-sectional view of the line B1-B2 in Figure 9. [Figure 11] Figure 11 is a cross-sectional view of the line C1-C2 in Figure 9. [Figure 12] Figure 12 is a plan view showing a part of a semiconductor device according to a second modified example of the first embodiment. [Figure 13] Figure 13 is a plan view showing a part of the semiconductor device according to the second embodiment. [Figure 14] Figure 14 is a cross-sectional view of the line A1-A2 in Figure 13. [Figure 15] Figure 15 is a cross-sectional view of the line B1-B2 in Figure 13. [Figure 16] Figure 16 is a cross-sectional view showing a part of a semiconductor device according to a first modified example of the second embodiment. [Figure 17] Figure 17 is a cross-sectional view showing a part of a semiconductor device according to a second modified example of the second embodiment. [Figure 18] Figure 18 is a cross-sectional view of the line A1-A2 in Figure 17. [Figure 19] Figure 19 is a cross-sectional view of the line B1-B2 in Figure 17.

Embodiment for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual ones. Even when representing the same part, there are cases where the dimensions and ratios are represented differently in the drawings. In the specification of the present application and each figure, the same reference numerals are given to the same elements as those already described, and the detailed description will be omitted as appropriate. In the following description, n + , n, n - and p + , the notations of p represent the relative levels of the impurity concentrations in each conductivity type. That is, n + indicates that the impurity concentration of the n-type is relatively higher than that of n, and n - indicates that the impurity concentration of the n-type is relatively lower than that of n. Also, p + indicates that the impurity concentration of the p-type is relatively higher than that of p, and p - indicates that the impurity concentration of the p-type is relatively lower than that of p. For each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] (First Embodiment) FIG. 1 is a plan view of a semiconductor device according to the first embodiment. FIG. 2 is an enlarged plan view of part A in FIG. 1. FIG. 3 is a cross-sectional view taken along B1 - B2 in FIG. 2. FIG. 4 is a cross-sectional view taken along C1 - C2 in FIG. 2. FIG. 5 is a cross-sectional view taken along D1 - D2 in FIG. 2. In FIG. 2, the insulating layer 25 and the emitter electrode 32 are shown transparently. The semiconductor device according to the first embodiment is an RC-IGBT. As shown in FIGS. 1 to 5, the semiconductor device 100 according to the first embodiment includes a p-type (first conductivity type) collector region 1 (first semiconductor region), an n - -type (second conductivity type) base region 2 (second semiconductor region), a p-type base region 3 (third semiconductor region), an n +Shape emitter region 4 (fourth semiconductor region), p + Shaped contact region 5 (5th semiconductor region), p + Shaped contact region 6 (sixth semiconductor region), n + p-type cathode region 7 (seventh semiconductor region), p-type anode region 8 (eighth semiconductor region), p + The device comprises an n-type anode region 9, an n-type buffer region 10, an n-type barrier region 11, an n-type barrier region 12, a gate electrode 20, a conductive portion 21, an insulating layer 25, a collector electrode 31 (first electrode), an emitter electrode 32 (second electrode), and a gate pad 33.

[0009] In describing the embodiments, the XYZ Cartesian coordinate system is used. The direction from the collector electrode 31 to the emitter electrode 32 is defined as the Z direction (first direction). The two directions perpendicular to the Z direction and mutually orthogonal are defined as the X direction (second direction) and the Y direction (third direction). For the sake of explanation, the direction from the collector electrode 31 to the emitter electrode 32 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the collector electrode 31 and the emitter electrode 32 and are independent of the direction of gravity.

[0010] As shown in Figure 1, emitter electrodes 32 and gate pads 33 are provided on the upper surface of the semiconductor device 100. The emitter electrodes 32 and gate pads 33 are spaced apart from each other. For example, multiple emitter electrodes 32 are provided in the Y direction. Gate wiring 33a is provided around each emitter electrode 32. A portion of the gate wiring 33a extends in the Y direction between the emitter electrodes 32. The gate wiring 33a is electrically connected to the gate pads 33.

[0011] As shown in Figures 1 and 2, the semiconductor device 100 has an IGBT region R1 (first region) and a diode region R2 (second region). In the example shown in Figure 1, multiple IGBT regions R1 and diode regions R2 are provided in the X and Y directions, respectively. In the X direction, IGBT regions R1 and diode regions R2 are provided alternately.

[0012] As shown in Figures 3 to 5, a collector electrode 31 is provided on the lower surface of the semiconductor device 100. The collector electrode 31 and the emitter electrode 32 are separated from each other, and multiple IGBT regions R1 and multiple diode regions R2 are located between the collector electrode 31 and the emitter electrode 32.

[0013] As shown in Figures 2 to 5, each IGBT region R1 has a p-type collector region 1, n - Part of the base region 2, p-shaped base region 3, n + Shape emitter region 4, p + Shape Contact area 5, p + A type contact region 6, a part of the n-type buffer region 10, an n-type barrier region 11, and a gate electrode 20 are provided.

[0014] The p-type collector region 1 is provided on a portion of the collector electrode 31 and is electrically connected to the collector electrode 31. - A portion of the base region 2 is located on the p-type collector region 1. The p-type base region 3 is n - It is provided on a portion of the p-type base region 2 and is located on the p-type collector region 1. The gate electrode 20 faces the p-type base region 3 in the X direction via the gate insulating layer 20a.

[0015] As shown in Figure 3, n + The type emitter region 4 is provided on the p-type base region 3. The emitter electrode 32 has a contact portion 32a that protrudes toward the collector electrode 31. + The emitter region 4 is aligned with the contact portion 32a in the X direction.

[0016] As shown in Figure 4, p + The p-shaped contact region 5 is provided on the p-shaped base region 3 and is aligned with the contact portion 32a in the X direction. As shown in Figure 2, + The contact region 5 is a part of the p-shaped base region 3 and n in the Y direction. + It is located between the shape emitter region 4 and p. +The p-type impurity concentration in the contact region 5 is higher than the p-type impurity concentration in the p-type base region 3.

[0017] As shown in Figures 3 to 5, p + The shaped contact region 6 is provided between the p-shaped base region 3 and the contact portion 32a in the Z direction. + The shape of the contact area 6 is n + Shape emitter region 4 and p + It is located below the contact area 5. + The p-type impurity concentration in the contact region 6 is higher than the p-type impurity concentration in the p-type base region 3. + Shape emitter region 4, p + Shaped contact area 5, and p + The contact area 6 is electrically connected to the emitter electrode 32.

[0018] The Y-direction end of the gate electrode 20 is electrically connected to the gate wiring 33a. An insulating layer 25 is provided between the gate electrode 20 and the emitter electrode 32, so that the gate electrode 20 and the emitter electrode 32 are electrically isolated from each other.

[0019] As shown in Figures 3 to 5, p-shaped base region 3, n + Shape emitter region 4, p + Shape Contact area 5, p + Multiple p-shaped contact regions 6, gate electrodes 20, and contact portions 32a are provided in the X direction. Multiple p-shaped base regions 3, multiple p + Each of the shaped contact region 6, the multiple gate electrodes 20, and the multiple contact portions 32a is arranged in a stripe pattern and extends in the Y direction. + Shape emitter region 4 and p + Each of the contact regions 5 is further provided with multiple regions in the Y direction.

[0020] As a specific example, as shown in Figure 2, on one p-shaped base region 3, one n + The shape emitter region 4 is a pair of p+ It is located between the shaped contact regions 5. Part of the p-shaped base region 3 and one n + Shape emitter region 4 and pair of p + Group G, which includes a contact region 5, is arranged alternately in the Y direction.

[0021] Each diode region R2 has n + Shape of cathode region 7, n - Another part of the base region 2, p-shaped anode region 8, p + An n-type anode region 9, another part of the n-type buffer region 10, an n-type barrier region 12, and a conductive portion 21 are provided. + The cathode region 7 is located on another part of the collector electrode 31 and is electrically connected to the collector electrode 31. - Another part of the shape base region 2 is n + It is located on top of the p-shaped cathode region 7. The p-shaped anode region 8 is n - Provided on the other part of the shaped base region 2, n + It is located above the cathode region 7.

[0022] The conductive portion 21 faces the p-type anode region 8 in the X direction via the insulating layer 21a. + The p-shaped anode region 9 is located on top of the p-shaped anode region 8. + The p-type impurity concentration in p-type anode region 9 is higher than that in p-type anode region 8. + The anode region 9 and the conductive portion 21 are electrically connected to the emitter electrode 32.

[0023] As shown in Figures 3 to 5, the emitter electrode 32 may include a contact portion 32b that protrudes toward the collector electrode 31. A portion of the p-type anode region 8 is aligned with the contact portion 32b in the X direction. + The p-type anode region 9 is located in the Z direction between the p-type anode region 8 and the emitter electrode 32.

[0024] p-type anode region 8, p +Multiple p-shaped anode regions 9, conductive portion 21, and contact portion 32b are provided in the X direction. Multiple p-shaped anode regions 8, multiple p + Each of the shaped anode region 9, the plurality of conductive parts 21, and the plurality of contact parts 32b is arranged in a stripe pattern and extends in the Y direction.

[0025] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the collector electrode 31 relative to the emitter electrode 32, a voltage above a threshold is applied to the gate electrode 20. This forms a channel (inversion layer) in the p-type base region 3. Electrons pass through the channel, + Shape emitter region 4 to n - The flow enters the p-shaped base region 2, and the holes are generated from the p-shaped collector region 1 to n - It flows into the base region 2. - The carrier density accumulated in the base region 2 increases, causing conductivity modulation. As a result, n - The electrical resistance of the p-type base region 2 decreases significantly, and the IGBT region R1 turns on. Subsequently, when the voltage applied to the gate electrode 20 falls below a threshold, the channel in the p-type base region 3 disappears, and the IGBT region R1 switches to the off state.

[0026] After the IGBT region R1 switches to the off state, n - Electrons accumulated in the p-type base region 2 are discharged to the collector electrode 31 through the p-type collector region 1. Holes are discharged to the emitter electrode 32 through the p-type base region 3.

[0027] For example, a bridge circuit is formed by multiple semiconductor devices 100. When one semiconductor device 100 switches from the ON state to the OFF state, the inductance component of the bridge circuit induces an electromotive force at the emitter electrode 32 of another semiconductor device 100. As a result, the diode region R2 in that other semiconductor device 100 operates. From the p-type anode region 8 to n - Holes flow into the base region 2, n + Shape cathode region 7 to n -Electrons flow into the base region 2. The diode region R2 functions as a freewheeling diode (FWD).

[0028] As shown in Figures 3 to 5, the p-type collector region 1 and n - Between the shape base region 2 and n + Shape cathode region 7 and n - An n-type buffer region 10 may be provided between the n-type base region 2. The n-type impurity concentration in the n-type buffer region 10 is n + The n-type impurity concentration is lower than that of the cathode region 7, n - It is higher than the n-type impurity concentration in the base region 2. By providing the n-type buffer region 10, - The expansion of the depletion layer in the base region 2 can be more reliably suppressed by the n-type buffer region 10.

[0029] n - An n-type barrier region 11 may be provided between the p-type base region 2 and the p-type base region 3. By providing the n-type barrier region 11, when the IGBT region R1 is in the ON state, n - This can suppress the discharge of holes accumulated in the base region 2, - The carrier density in the n-type base region 2 can be increased. This makes it possible to reduce the electrical resistance when the IGBT region R1 is ON. In addition to the n-type barrier region 11, n - An n-type barrier region 12 may be provided between the p-type base region 2 and the p-type anode region 8. The n-type impurity concentrations in the n-type barrier region 11 and the n-type barrier region 12 are n - It is higher than the n-type impurity concentration in the shape-based region 2.

[0030] In the IGBT region R1, some of the multiple gate electrodes 20 may be replaced with conductive parts 21. By replacing some of the gate electrodes 20 with conductive parts 21, when the IGBT region R1 is ON, n - By increasing the carrier density in the base region 2, the electrical resistance of the semiconductor device 100 can be further reduced.

[0031] An example of the materials used for each component of the semiconductor device 100 will be described. p-type collector region 1, n - Shape base region 2, p-shaped base region 3, n + Shape emitter region 4, p + Shape Contact area 5, p + Shaped contact area 6, n + p-type cathode region 7, p-type anode region 8, p + The n-type anode region 9, n-type buffer region 10, n-type barrier region 11, and n-type barrier region 12 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as p-type impurities.

[0032] The gate electrode 20 and the conductive portion 21 contain a conductive material such as polysilicon. The gate insulating layer 20a, insulating layer 21a, and insulating layer 25 contain an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The collector electrode 31, emitter electrode 32, gate pad 33, and gate wiring 33a contain a metal such as aluminum. The contact portions 32a and 32b may include a barrier metal layer in the portion that contacts each semiconductor region and the insulating layer 25. The barrier metal layer may include titanium, titanium nitride, or the like.

[0033] Figure 6 is a plan view showing a part of a semiconductor device according to a reference example. In the semiconductor device 100r shown in Figure 6, in the IGBT region R1, n + Shape emitter region 4 and p + The contact regions 5a are arranged alternately along the Y direction. In other words, in the Y direction, n + In all regions between two shape emitter regions 4, p + A contact area 5a is provided.

[0034] The advantages of the first embodiment will be explained. The semiconductor device 100r has a p-type collector region 1, n -The parasitic thyristor includes a p-shaped base region 3, an n-shaped base region 2, and an n-shaped emitter region 4. + When the IGBT region R1 switches to the off state, holes flow through the p-shaped base region 3. When the potential of the p-shaped base region 3 rises due to the flow of holes, the parasitic thyristor may operate. When the parasitic thyristor operates, a large current flows through the semiconductor device 100r, and the semiconductor device 100r is destroyed.

[0035] In the semiconductor device 100r, in order to suppress the operation of the parasitic thyristor, a p-shaped contact region 5a is provided between the n-shaped emitter regions 4. + The p-shaped impurity concentration of the p-shaped contact region 5a is higher than the p-shaped impurity concentration of the p-shaped base region 3. When holes flow through the p-shaped base region 3, the holes are more likely to be discharged to the emitter electrode 32 through the p-shaped contact region 5a. Thereby, the operation of the parasitic thyristor can be suppressed. In other words, the latch-up tolerance of the semiconductor device 100r can be improved. + The p-shaped contact region 5a is provided. + When holes flow through the p-shaped base region 3, the holes are more likely to be discharged to the emitter electrode 32 through the p-shaped contact region 5a. + Thereby, the operation of the parasitic thyristor can be suppressed. In other words, the latch-up tolerance of the semiconductor device 100r can be improved.

[0036] On the other hand, the IGBT region R1 also includes a parasitic diode composed of an n-shaped base region 2 and a p-shaped base region 3 and a parasitic diode composed of a p-shaped base region 3 and an n-shaped cathode region 7. When the diode region R2 is in the on state, due to the operation of the parasitic diode of the IGBT region R1, holes can flow from the emitter electrode 32 to the n-shaped base region 2. In particular, when the p-shaped contact region 5a is provided in the IGBT region R1, since the electrical resistance between the p-shaped contact region 5a and the emitter electrode 32 is low, more holes flow to the n-shaped base region 2. Thereby, the carriers accumulated in the n-shaped base region 2 increase. When the diode region R2 switches to the off state, - The parasitic diode consists of an n-shaped base region 2 and a p-shaped base region 3, and the parasitic diode consists of a p-shaped base region 3 and an n-shaped cathode region 7. + When the diode region R2 is in the on state, due to the operation of the parasitic diode of the IGBT region R1, holes can flow from the emitter electrode 32 to the n-shaped base region 2. - In particular, when the p-shaped contact region 5a is provided in the IGBT region R1, + Since the electrical resistance between the p-shaped contact region 5a and the emitter electrode 32 is low, more holes flow to the n-shaped base region 2. + Thereby, the carriers accumulated in the n-shaped base region 2 increase. - When the diode region R2 switches to the off state, - 形ベース領域2に蓄積されるキャリアが増加する。ダイオード領域R2がオフ状態に切り替わったとき、n -It takes a longer time to discharge the carriers accumulated in the base region 2. As a result, the switching of the diode region R2 from the on state to the off state becomes slower. For example, the high-speed operation of the diode region R2 is impaired.

[0037] Regarding this issue, in the semiconductor device 100 according to this embodiment, p + The contact region 5 is part of the p-shaped base region 3 and n + It is provided between the emitter region 4. That is, when comparing semiconductor device 100 and semiconductor device 100r, p + The length of the contact region 5 in the Y direction is p + The length of the contact region 5a in the Y direction is shorter than the length of the contact region 5a. p per unit area + The area of ​​the contact region 5 is p per unit area. + It is smaller than the area of ​​the contact region 5a. In semiconductor device 100, p + A portion of the shaped contact area 5a is omitted, and instead, a portion of the p-shaped base area 3 is provided.

[0038] p + Replace contact area 5a with p + By providing the contact region 5, when the diode region R2 is ON, p + Through the contact area 5, the hole enters n - This suppresses the flow to the base region 2. It also allows for faster operation of the diode region R2 and reduces switching losses due to the operation of the diode region R2. Furthermore, p + The contact region 5 is a part of the p-shaped base region 3 and n + A space is provided between the shape emitter region 4 and n + It is adjacent to the emitter region 4. Therefore, when the IGBT region R1 switches to the off state, n + The holes flowing in the vicinity of the emitter region 4 are p + It flows easily into contact area 5. + This suppresses the rise in potential in the region near the emitter region 4, thereby suppressing latch-up of the semiconductor device 100.

[0039] Furthermore, in semiconductor device 100, p + A contact area 6 is further provided. + The shape of the contact area 6 is n + It is located below the p-type emitter region 4. Therefore, the holes that flow into the p-type base region 3 are n + Before passing through the vicinity of the emitter region 4, p + It is discharged to the contact portion 32a through the contact area 6. + The amount of holes passing near the emitter region 4 can be reduced, + This makes it possible to suppress the potential rise in the region near the emitter region 4. As a result, latch-up of the semiconductor device 100 can be further suppressed.

[0040] Figure 7 is a schematic diagram illustrating the characteristics of a semiconductor device. In Figure 7, the horizontal axis represents time, and the vertical axis represents the magnitude of voltage or current. The voltage applied to the collector electrode 31 relative to the emitter electrode 32 is represented by a "+" sign. The current flowing from the emitter electrode 32 to the collector electrode 31 is also represented by a "+" sign.

[0041] When the diode region R2 is ON, a current If flows from the emitter electrode 32 to the collector electrode 31. When the diode region R2 switches from the ON state to the OFF state and the voltage Vr at the collector electrode 31 rises, n - Carriers accumulated in the base region 2 are discharged. As a result, a negative current If flows through the diode region R2. In this case, the smaller the current If is (closer to zero), the faster the diode region R2 can operate.

[0042] In Figure 7, the dashed line shows the characteristics of the semiconductor device 100r according to the reference example. The solid line shows the characteristics of the semiconductor device 100 according to the embodiment. As shown in Figure 7, in the semiconductor device 100 according to the embodiment, the current If when the diode region R2 switches to the off state is smaller compared to the semiconductor device 100r according to the reference example. In other words, the diode region R2 of the semiconductor device 100 can operate at a faster speed than the diode region R2 of the semiconductor device 100r.

[0043] According to this embodiment, the diode region R2 can be operated at a faster speed while suppressing a decrease in the latch-up withstand capability of the semiconductor device 100.

[0044] (First variation) Figure 8 is a plan view showing a part of a semiconductor device according to a first modified example of the first embodiment. In the semiconductor device 110 according to the first modified example shown in Figure 8, the IGBT region R1 includes a first portion R1a and a second portion R1b. The second portion R1b is located between the first portion R1a and the diode region R2. As shown in Figure 8, when the IGBT region R1 and the diode region R2 are arranged alternately in the X direction, one IGBT region R1 is located between a pair of diode regions R2. In such one IGBT region R1, one first portion R1a is located between a pair of second portions R1b.

[0045] p-shaped base region 3, n + Shape emitter region 4, p + Shape Contact area 5, p + Each of the contact region 6 and the gate electrode 20 is provided in the first portion R1a and the second portion R1b, respectively. In the first portion R1a, some of the multiple gate electrode 20 may be replaced by conductive portions 21. In the second portion R1b, some or all of the multiple gate electrode 20 may be replaced by conductive portions 21.

[0046] Figure 9 is an enlarged plan view of section A of Figure 8. Figure 10 is a cross-sectional view of B1-B2 in Figure 9. Figure 11 is a cross-sectional view of C1-C2 in Figure 9. As shown in Figure 9, in the first part R1a and the second part R1b, p + The length of the contact region 5 in the Y direction is different. p provided in the first part R1a + The length L1 in the Y direction of the contact region 5 is provided in the second portion R1b. + It is longer than the length L2 in the Y direction of the contact region 5. Therefore, in the XY plane, the p per unit area in the first part R1a+ The area of ​​the contact region 5 is the area per unit area in the second part R1b. + It is larger than the area of ​​contact region 5a.

[0047] In the illustrated example, in the first section R1a, adjacent n in the Y direction + In all regions between two shape emitter regions 4, p + A contact region 5 is provided. In the second part R1b, adjacent n in the Y direction + In the region between two shape emitter regions 4, a pair of p + A shaped contact area 5 and a part of the p-shaped base area 3 are provided.

[0048] As shown in Figure 10, p provided in the first part R1a + A portion of the contact area 5 is provided in the second portion R1b in the X direction. + It is aligned with the shape contact region 5. As shown in Figure 11, p is provided in the first part R1a + Another part of the shaped contact region 5 is aligned in the X direction with the p-shaped base region 3 provided in the second part R1b. + Except for the size of the contact area 5, the structure of the IGBT area R1 and diode area R2 in the semiconductor device 110 is the same as the structure of the IGBT area R1 and diode area R2 in the semiconductor device 100.

[0049] The advantages of the first variation will be explained. As described above, when the diode region R2 is turned ON, n is emitted from the parasitic diode of the IGBT region R1. - Holes flow into the base region 2. At this time, more holes flow into the part of the IGBT region R1 that is closer to the diode region R2. - The current flows into the base region 2. That is, the amount of holes flowing through the parasitic diode of the second part R1b is greater than the amount of holes flowing through the parasitic diode of the first part R1a. Therefore, in the second part R1b, p + By shortening the contact area 5, the parasitic diode can reduce n -The amount of holes flowing into the base region 2 can be effectively reduced. Also, the first part R1a and n + The distance along the XY plane between the shaped cathode region 7 and the second part R1b and n + It is longer than the distance along the XY plane between the n-type cathode region 7 and the p-type collector region 1. In the first part R1a, the potential between the n-type buffer region 10 and the p-type collector region 1 is more easily biased in the forward direction compared to the second part R1b. For this reason, the amount of holes injected from the p-type collector region 1 tends to be greater in the first part R1a than in the second part R1b. + By lengthening the contact region 5, the potential of the p-shaped base region 3 provided in the first portion R1a becomes less likely to rise. This improves the latch-up tolerance.

[0050] According to the first modified example semiconductor device 110, compared to the semiconductor device 100, the latch-up tolerance can be improved while suppressing the decrease in the operating speed of the diode region R2.

[0051] In the semiconductor device 110, it is preferable that the length L3 in the X direction of the second portion R1b (shown in Figure 8) is longer than the distance D1 in the Z direction between the collector electrode 31 and the emitter electrode 32 (shown in Figure 10). In other words, length L3 is the distance in the X direction between the first portion R1a and the diode region R2. By making length L3 longer than the distance D1, the p of the first portion R1a + n of the contact region 5 and diode region R2 + The distance between the cathode region 7 and the first portion R1a can be increased. The amount of holes flowing through the parasitic diode of the first portion R1a can be further reduced. On the other hand, if the length L3 is excessively long, the size of the first portion R1a becomes smaller, and the effect of improving the latch-up withstand capability decreases. In order to effectively reduce the inflow of holes through the parasitic diode while maximizing the effect of improving the latch-up withstand capability, it is preferable that the length L3 is longer than the distance D1 and shorter than twice the distance D1.

[0052] When measuring length L3, the boundary between the first part R1a and the second part R1b is p +This can be distinguished by the difference in the length of the contact region 5. Also, at the position in the X direction of the boundary between the second part R1b and the diode region R2, there are p-type collector region 1 and n + The position in the X direction of the boundary with the cathode region 7 can be used.

[0053] (Second variation) Figure 12 is a plan view showing a part of a semiconductor device according to a second modified example of the first embodiment. In the semiconductor device 120 according to the second modified example shown in Figure 12, each p provided in the second portion R1b + The length of the contact region 5 in the Y direction becomes shorter as it approaches the diode region R2. According to the second modification, the region in which the parasitic diode is more easily operated is p + The contact area 5 is shorter. Therefore, the parasitic diode causes n - The amount of holes flowing into the base region 2 can be effectively reduced. Also, the more difficult the parasitic diode is to operate in a region, the more p + The p-type contact region 5 is longer. The potential of the p-type base region 3 is less likely to rise, and latch-up of the semiconductor device 120 can be suppressed.

[0054] According to the second modified semiconductor device 120, the operating speed of the diode region R2 can be increased and the latch-up tolerance can be further improved compared to the semiconductor device 110.

[0055] (Second Embodiment) Figure 13 is a plan view showing a part of the semiconductor device according to the second embodiment. Figure 14 is a cross-sectional view taken along line A1-A2 in Figure 13. Figure 15 is a cross-sectional view taken along line B1-B2 in Figure 13. The semiconductor device according to the second embodiment is an RC-IGBT. As shown in Figure 13, the semiconductor device 200 according to the second embodiment includes a first part R1a and a second part R1b, similar to the semiconductor device 110 or 120 according to the first embodiment. The semiconductor device 200 has p in the second part R1b. + This semiconductor device differs from the semiconductor device according to the first embodiment in that it does not have a contact region 5.

[0056] As shown in Figures 13 to 15, in the first part R1a, adjacent n in the Y direction + In all regions between two shape emitter regions 4, p + A contact region 5 is provided. In the Y direction, n + Shape emitter region 4 and p + The contact regions 5 are arranged alternately. In the second part R1b, adjacent n in the Y direction + A p-type base region 3 is provided in all the regions between the p-type emitter regions 4. In the Y direction, a part of the p-type base region 3 and n + The shape emitter regions 4 are arranged alternately.

[0057] In the semiconductor device 200 according to the second embodiment, p + A contact region 5 is not provided. Therefore, the operating speed of the diode region R2 can be further increased compared to the semiconductor device 100 according to the first embodiment.

[0058] As shown in Figure 13, n provided in the second part R1b + The length of the shape emitter region 4 in the Y direction is n provided in the first portion R1a. + The shape may be longer than the length of the emitter region 4 in the Y direction. The second part R1b is p + A contact region 5 is not provided. Therefore, in the second part R1b, compared to the first part R1a, when heat treatment is performed to activate impurities, n + n-type impurities in emitter region 4 diffuse more easily in the Y direction. As a result, in the Y direction, n-type impurities in the second part R1b + The shape of the emitter region 4 is n of the first part R1a. + The shape becomes longer than the emitter region 4. By doing this, n + The withdrawal of electron current through the p-type emitter region 4 is promoted, and from the p-type base region 3 to n - This can suppress the injection of holes into the shape base region 2.

[0059] Furthermore, in the semiconductor device 200, it is preferable that the length of the second portion R1b in the X direction is longer than the distance in the Z direction between the collector electrode 31 and the emitter electrode 32, and shorter than twice that distance. This significantly improves the latch-up withstand capability while effectively reducing the inflow of holes due to the parasitic diode.

[0060] (First variation) Figure 16 is a cross-sectional view showing a part of a semiconductor device according to a first modified example of the second embodiment. Figure 16 shows n of the first part R1a. + Shape emitter region 4, n of the second part R1b + This corresponds to the XZ cross-sectional view passing through the emitter region 4 and the diode region R2. In the semiconductor device 210 according to the first modified example shown in Figure 16, the n-type barrier region 12 is not provided in the diode region R2.

[0061] For example, the length of the p-type anode region 8 in the Z direction is longer than the length of the p-type base region 3 in the Z direction. The p-type impurity concentration in the p-type anode region 8 and the p-type impurity concentration in the p-type base region 3 may be different from each other. Preferably, the p-type impurity concentration in the p-type anode region 8 is lower than the p-type impurity concentration in the p-type base region 3. This allows n to be produced from the p-type anode region 8. - This reduces the amount of holes flowing into the base region 2.

[0062] By optimizing the surface structure of the IGBT region R1 and the diode region R2, respectively, including the presence or absence of n-type barrier regions and the length of the p-type semiconductor region in the Z direction, the characteristics of the semiconductor device 210 can be further enhanced.

[0063] (Second variation) Figure 17 is a cross-sectional view showing a part of a semiconductor device according to a second modified example of the second embodiment. Figure 18 is a cross-sectional view taken along line A1-A2 in Figure 17. Figure 19 is a cross-sectional view taken along line B1-B2 in Figure 17. The semiconductor device 220 according to the second modified example shown in Figures 17 to 19 differs from the semiconductor device 200 in the structure of the second part R1b. In the semiconductor device 220, in the second part R1b, p + Multiple contact regions 6 and contact portions 32a are provided in the Y direction. + The contact regions 6 are spaced apart from each other in the Y direction. The multiple contact portions 32a are spaced apart from each other in the Y direction. + A portion of the p-shaped base region 3 is provided between the contact regions 6 and between the contact portions 32a.

[0064] p + The contact area 6 and contact portion 32a are n + It is provided only in the region adjacent to the emitter region 4. For example, as shown in Figure 18, the contact portion 32a is provided in the region adjacent to a pair of n in the X direction. + It is located between two shape emitter regions 4. + The shaped contact region 6 is located in the Z direction between the p-shaped base region 3 and the contact portion 32a.

[0065] When the parasitic diode R1 in the IGBT region is activated, p + In addition to the contact area 5, p + Holes can also flow from the contact region 6. In the semiconductor device 220, in the XY plane, the p per unit area in the second part R1b + The area of ​​the contact region 6 is equal to the p per unit area in the first part R1a. + It is smaller than the area of ​​the contact region 6. Therefore, when the diode region R2 is ON, p + Through the contact area 6, n - The amount of holes flowing into the base region 2 can be reduced. This allows for faster operation of the diode region R2 and reduces switching losses due to the operation of the diode region R2. + The contact area 6 and contact portion 32a are n + It is located in a region adjacent to the emitter region 4. Therefore, n+ This effectively suppresses the potential increase in the region near the emitter region 4.

[0066] The semiconductor device 220 according to the second modified example can further speed up the operation of the diode region R2 while suppressing a decrease in latch-up withstand capability compared to the semiconductor device 200.

[0067] Embodiments of the present invention include the following configurations. (Composition 1) First electrode and, A second electrode separated from the preceding first electrode, A first region provided between the first electrode and the second electrode, on a part of the first electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type, a portion of which is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on a portion of the second semiconductor region, In a second direction perpendicular to the first direction toward the second electrode from the first electrode, a gate electrode facing the third semiconductor region via a gate insulating layer, A fourth semiconductor region of a second conductivity type is provided on the third semiconductor region and is aligned with a part of the second electrode in the second direction, A fifth semiconductor region of a first conductivity type is provided between a part of the third semiconductor region and the fourth semiconductor region in a third direction perpendicular to the first and second directions, and is aligned with the part of the second electrode in the second direction, and has a higher impurity concentration of the first conductivity type than the third semiconductor region. A sixth semiconductor region of a first conductivity type is provided between the third semiconductor region and the part of the second electrode, and has a higher impurity concentration of the first conductivity type than the third semiconductor region. The first region including, A second region provided between the first electrode and the second electrode, on another part of the first electrode, A seventh semiconductor region of the second conductivity having a higher impurity concentration of the second conductivity than the aforementioned second semiconductor region, Another part of the second semiconductor region provided on the seventh semiconductor region, An eighth semiconductor region of a first conductivity type is provided on another part of the second semiconductor region, The second region including, A semiconductor device equipped with the following features. (Configuration 2) The semiconductor device according to configuration 1, wherein the fourth semiconductor region is provided between a pair of fifth semiconductor regions in the third direction. (Composition 3) The semiconductor device according to configuration 2, wherein a portion of the third semiconductor region and a group including the fourth semiconductor region and the pair of fifth semiconductor regions are alternately arranged in the third direction. (Composition 4) The first region includes a first part and a second part located between the first part and the second region. The third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region are each provided in the first and second portions, respectively. A semiconductor device according to any one of configurations 1 to 3, wherein the length of the fifth semiconductor region in the third direction provided in the first portion is longer than the length of the fifth semiconductor region in the third direction provided in the second portion. (Composition 5) In the second part, the fifth semiconductor region is provided in multiple locations in the second direction. The semiconductor device according to configuration 4, wherein the length of each of the multiple fifth semiconductor regions in the third direction is shorter towards the second region. (Composition 6) The semiconductor device according to configuration 4 or 5, wherein the length of the second portion in the second direction is longer than the distance between the first electrode and the second electrode in the first direction. (Composition 7) First electrode and, A second electrode separated from the preceding first electrode, A first region is provided between the first electrode and the second electrode, on a part of the first electrode, and includes a first portion and a second portion. A first semiconductor region of a first conductivity type provided in the first and second portions, A second semiconductor region of a second conductivity type, a portion of which is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided in each of the first and second portions and is located on the portion of the second semiconductor region, A gate electrode is provided in the first portion and faces the third semiconductor region via a gate insulating layer in a second direction perpendicular to the first direction toward the second electrode from the first electrode, A fourth semiconductor region of second conductivity type is provided in each of the first and second portions, located on the third semiconductor region and aligned with a portion of the second electrode in the second direction, A fifth semiconductor region of a first conductivity type is provided in the first portion, and in the second direction, it is aligned with the portion of the second electrode and has a higher impurity concentration of the first conductivity type than the third semiconductor region. A sixth semiconductor region of a first conductivity type having a higher impurity concentration of the first conductivity type than the third semiconductor region is provided in each of the first and second portions, and is provided between the third semiconductor region and the part of the second electrode, The first portion includes the first region in which the fourth semiconductor region and the fifth semiconductor region are alternately provided in a third direction perpendicular to the first and second directions, and the second portion includes the first region in which a part of the third semiconductor region and the fourth semiconductor region are alternately provided in the third direction, A second region provided between the first electrode and the second electrode, on another part of the first electrode, A seventh semiconductor region of the second conductivity having a higher impurity concentration of the second conductivity than the aforementioned second semiconductor region, Another part of the second semiconductor region provided on the seventh semiconductor region, An eighth semiconductor region of a first conductivity type is provided on another part of the second semiconductor region, The second region includes the second portion which is located between the first portion and the second region, A semiconductor device equipped with the following features. (Composition 8) The semiconductor device according to configuration 7, wherein the length of the second portion in the second direction is longer than the distance between the first electrode and the second electrode. (Composition 9) In the second part, the sixth semiconductor region is provided in multiple locations in the third direction. The semiconductor device according to configuration 7 or 8, wherein the plurality of the sixth semiconductor regions are separated from each other. (Composition 10) The semiconductor device according to any one of configurations 1 to 9, wherein the impurity concentration of the second conductivity type in the eighth semiconductor region is lower than the impurity concentration of the second conductivity type in the third semiconductor region.

[0068] The relative levels of impurity concentrations between semiconductor regions in each embodiment described above can be confirmed, for example, using an SCM (Scanning Capacitive Microscope). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using an SCM. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry).

[0069] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0070] 1: p-type collector region, 2: n - Shape base region, 3: p-shaped base region, 4: n +Shape emitter region, 5:p + Shaped contact area, 5a:p + Shaped contact area, 6:p + Shape of contact area, 7:n + 8:p-type cathode region, 8:p-type anode region, 9:p + R1: anode region, 10: n-type buffer region, 11, 12: n-type barrier region, 20: gate electrode, 20a: gate insulating layer, 21: conductive part, 21a: insulating layer, 25: insulating layer, 31: collector electrode, 32: emitter electrode, 32a, 32b: contact parts, 33: gate pad, 33a: gate wiring, 100~120, 100r, 200~220: semiconductor device, R1: IGBT region, R1a: first part, R1b: second part, R2: diode region

Claims

1. First electrode and A second electrode separated from the first electrode, A first region provided between the first electrode and the second electrode, on a part of the first electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type, a portion of which is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on a portion of the second semiconductor region, In a second direction perpendicular to the first direction toward the second electrode from the first electrode, a gate electrode faces the third semiconductor region via a gate insulating layer and is electrically insulated from the second electrode, A fourth semiconductor region of a second conductivity type is provided on the third semiconductor region and is aligned with a part of the second electrode in the second direction, A fifth semiconductor region of a first conductivity type is provided between a part of the third semiconductor region and the fourth semiconductor region in a third direction perpendicular to the first and second directions, and is aligned with the part of the second electrode in the second direction, and has a higher impurity concentration of the first conductivity type than the third semiconductor region. A sixth semiconductor region of a first conductivity type is provided between the third semiconductor region and the part of the second electrode, and has a higher impurity concentration of the first conductivity type than the third semiconductor region. The gate electrode faces the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region in the second direction, and a plurality of sets of the part of the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are provided in the third direction, the first region, A second region provided between the first electrode and the second electrode, on another part of the first electrode, A seventh semiconductor region of the second conductivity having a higher impurity concentration of the second conductivity than the second semiconductor region, Another part of the second semiconductor region provided on the seventh semiconductor region, An eighth semiconductor region of a first conductivity type is provided on another part of the second semiconductor region, The second region including, A semiconductor device equipped with the following features.

2. The first region includes a conductive portion electrically connected to the second electrode, The first region includes a first portion and a second portion located between the first portion and the second region. The semiconductor device according to claim 1, wherein in the second portion, the gate electrode is provided in the region adjacent to the first portion, and the conductive portion is provided in the other region.

3. The part of the third semiconductor region, the fourth semiconductor region, and the multiple sets of the fifth semiconductor region and the sixth semiconductor region are provided in the second portion. The first portion is provided with another fifth semiconductor region of the first conductivity type, The semiconductor device according to claim 2, wherein the length in the third direction of the other fifth semiconductor region provided in the first portion is longer than the length in the third direction of the fifth semiconductor region provided in the second portion.

4. The first region includes a first portion and a second portion located between the first portion and the second region. The sixth semiconductor region is provided in each of the first and second portions, The semiconductor device according to claim 1, wherein the area of ​​the sixth semiconductor region per unit area in the second portion is smaller than the area of ​​the sixth semiconductor region per unit area in the first portion.

5. The plurality of sets of the portion of the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are further provided in the second direction. The semiconductor device according to claim 2 or 3, wherein the gate electrode faces a pair of third semiconductor regions, a pair of fourth semiconductor regions, and a pair of fifth semiconductor regions on both sides along the second direction, via the gate insulating layer.

6. The semiconductor device according to claim 5, wherein the conductive portion faces, on both sides along the second direction, another pair of the third semiconductor regions, another pair of the fourth semiconductor regions, and another pair of the fifth semiconductor regions, via an insulating layer.

7. The semiconductor device according to any one of claims 1 to 3, wherein the gate electrode faces the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region via the gate insulating layer on one side along the second direction, and faces the eighth semiconductor region of the second region via the gate insulating layer on the other side along the second direction.

8. The semiconductor device according to any one of claims 1 to 3, wherein in the set, the fourth semiconductor region is provided between a pair of fifth semiconductor regions in the third direction.

9. In the second portion, the fifth semiconductor region is provided in multiple locations in the second direction. The semiconductor device according to claim 3, wherein the length of each of the plurality of fifth semiconductor regions in the third direction is shorter towards the second region.

10. The semiconductor device according to claim 2 or 3, wherein the length of the second portion in the second direction is longer than the distance between the first electrode and the second electrode in the first direction.

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