Power semiconductor device and method for manufacturing the same

Abstract

The present invention provides a silicon carbide power semiconductor device and a method for manufacturing the same that can increase channel density while mitigating electric field concentration. [Solution] A power semiconductor device according to one aspect of the present invention comprises a SiC semiconductor layer, at least one trench formed from its surface into the interior, a gate insulating layer provided on the inner wall of the trench, and a gate electrode layer filling the gate electrode. The semiconductor layer has a drift region of a first conductivity type, a well region of a second conductivity type, and a source region of a first conductivity type. The drift region has a vertical portion on one side of the gate electrode layer, and a channel region is provided between the vertical portion and the source region where an accumulation channel is formed. The well region has a protrusion that projects from the source region toward the vertical portion of the drift region, and the channel region is formed on the protrusion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission and a method for manufacturing the same.

Background Art

[0002] A power semiconductor device is a semiconductor device that operates in a high-voltage and high-current environment. Such power semiconductor devices are used in fields that require high-power switching, such as power conversion, power converters, inverters, and the like. For example, power semiconductor devices include insulated gate bipolar transistors (IGBTs), power MOSFETs (metal oxide semiconductor field effect transistors), and the like. Such power semiconductor devices basically require breakdown voltage characteristics with respect to high voltages, and recently, additionally require fast switching operations.

[0003] Therefore, power semiconductor devices using silicon carbide (SiC) instead of existing silicon (Si) have been studied. Silicon carbide (SiC) is a wide-gap semiconductor material having a higher bandgap than silicon, and can maintain stability even at high temperatures compared to silicon. Furthermore, since silicon carbide has a very high breakdown electric field compared to silicon, it can operate stably even at high voltages. Therefore, silicon carbide exhibits characteristics of having a high breakdown voltage while being excellent in heat dissipation and being operable at high temperatures compared to silicon.

[0004] To increase the channel density of power semiconductor devices using silicon carbide, trench-type gate structures with vertical channel structures are being studied. However, such trench-type gate structures have the problem of electric field concentration at the corners of the trenches, limiting the reduction in channel density by applying structures to protect the lower part of the trenches. Furthermore, since source contact structures are placed between gate electrodes, and it is difficult to reduce the spacing between gate electrodes, there are limits to reducing the channel density. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Public Gazette of the Republic of Korea No. 2011-0049249 (Published May 12, 2011) [Overview of the project] [Problems that the invention aims to solve]

[0006] The present invention aims to solve the aforementioned problems and to provide a silicon carbide power semiconductor device and a method for manufacturing the same that can increase channel density while mitigating electric field concentration. However, these problems are illustrative and do not limit the scope of the present invention. [Means for solving the problem]

[0007] A power semiconductor device according to one aspect of the present invention for solving the above problems includes: a silicon carbide (SiC) semiconductor layer; at least one trench formed in a predetermined depth recessed from the surface of the semiconductor layer into the interior of the semiconductor layer and extending in one direction; a gate insulating layer formed on at least the inner wall of the at least one trench; at least one gate electrode layer formed on the gate insulating layer so as to fill the at least one trench; a drift region formed in the semiconductor layer on at least one side of the at least one gate electrode layer and having a first conductivity type; a well region formed in the semiconductor layer deeper than the at least one gate electrode layer and having a second conductivity type, in contact with at least a part of the drift region and surrounding the bottom surface of the at least one gate electrode layer at at least one end of the at least one gate electrode layer; a source region formed within the well region and having a first conductivity type; and at least one channel region formed in the semiconductor layer on one side of the at least one gate electrode layer between the drift region and the source region, with an inversion channel formed along the one direction and having a second conductivity type.

[0008] According to the power semiconductor device, the source region may include a source contact region connected to the source electrode layer outside one end of the at least one gate electrode layer.

[0009] According to the power semiconductor device, the source contact region includes a well contact region that extends from the well region through the source region, is connected to the source electrode layer, and has a second conductivity type, and the well contact region can be doped to a higher concentration than the well region.

[0010] According to the power semiconductor device, the drift region includes a vertical portion extending perpendicularly to one semiconductor layer of the at least one gate electrode layer, and the at least one channel region can be formed in the semiconductor layer between the vertical portion of the drift region and the source region.

[0011] According to the power semiconductor device, the well region, the source region, and the channel region can be formed in the semiconductor layers on both sides of the vertical portion of the drift region, respectively.

[0012] According to the power semiconductor device, the drift region includes vertical portions extending perpendicularly to the semiconductor layers on both sides of the at least one gate electrode layer, and the at least one channel region may include a channel region formed in the semiconductor layer between the vertical portion of the drift region and the source region. In the power semiconductor device described above, the at least one channel region may be part of the well region.

[0013] The power semiconductor device described above includes, the at least one trench comprises a plurality of trenches formed in the semiconductor layer in a unidirectional direction, the at least one gate electrode layer comprises a plurality of gate electrode layers formed by filling the plurality of trenches, the well region and the source region extend across the plurality of gate electrode layers, and the at least one channel region comprises a plurality of channel regions formed in the semiconductor layer on one side of the plurality of gate electrode layers.

[0014] According to the power semiconductor device, the source region may include a source contact region connected to the source electrode layer outside one end of the plurality of gate electrode layers.

[0015] According to the power semiconductor device, the drift region includes a vertical portion extending perpendicularly to the semiconductor layer between the plurality of gate electrode layers, and the channel region can be formed in the semiconductor layer between the vertical portion of the drift region and the source region.

[0016] According to the power semiconductor device, the at least one trench includes a plurality of trenches spaced apart in a row in one direction, the at least one gate electrode layer includes a plurality of gate electrode layers formed by filling the plurality of trenches, and the well region and the source region can be formed in the semiconductor layer between at least the plurality of trenches, respectively.

[0017] The power semiconductor device further includes a drain region having a first conductivity type in the semiconductor layer below the drift region, and the drain region can be doped to a higher concentration than the drift region.

[0018] A power semiconductor device according to another aspect of the present invention for solving the aforementioned problems includes: a silicon carbide (SiC) semiconductor layer; a plurality of trenches formed in recesses from the surface of the semiconductor layer to a predetermined depth into the interior of the semiconductor layer and extending in a unidirectional direction; a gate insulating layer formed on at least the inner walls of the plurality of trenches; a plurality of gate electrode layers formed on the gate insulating layer so as to fill the plurality of trenches; a drift region having a first conductivity type and including a plurality of vertical portions formed in the semiconductor layer between the plurality of gate electrode layers; a well region having a second conductivity type and being in contact with the plurality of vertical portions of the drift region and formed in the semiconductor layer deeper than the plurality of gate electrode layers so as to surround the bottom surfaces of the plurality of gate electrode layers at both ends of the plurality of gate electrode layers; a source region having a first conductivity type and formed within the well region; and a plurality of channel regions having a second conductivity type and being formed in the semiconductor layers on both sides of the plurality of gate electrode layers between the vertical portions of the drift region and the source region, and forming inversion channels along the unidirectional direction.

[0019] A method for manufacturing a power semiconductor device according to another aspect of the present invention for solving the aforementioned problems is a method comprising the steps of: forming a drift region having a first conductivity type in a silicon carbide (SiC) semiconductor layer; forming a well region having a second conductivity type in the semiconductor layer, in contact with at least a portion of the drift region; forming a source region having a first conductivity type within the well region; forming at least one channel region having a second conductivity type in the semiconductor layer between the drift region and the source region, such that an inversion channel is formed along one direction; and forming a recessed portion from the surface of the semiconductor layer to the interior of the semiconductor layer by a predetermined depth, in the direction of the drift region The process includes the steps of forming at least one trench extending across the region and being shallower than the well region, forming a gate insulating layer on at least the inner wall of the at least one trench, and forming at least one gate electrode layer on the gate insulating layer so as to fill the at least one trench, wherein the well region is formed in the semiconductor layer deeper than the at least one gate electrode layer so as to surround the bottom surface of the at least one gate electrode layer at one end of the at least one gate electrode layer, and the channel region is formed in the semiconductor layer on one side of the at least one gate electrode layer between the drift region and the source region.

[0020] According to the method for manufacturing the power semiconductor device, the step of forming the source region may further include the step of forming a source contact region connected to the source electrode layer on the outside of one end of the at least one gate electrode layer.

[0021] The method for manufacturing the power semiconductor device further includes the step of forming a well contact region within the source contact region, which extends from the well region through the source region, is connected to the source electrode layer, and has a second conductivity type, wherein the well contact region can be doped with a higher concentration than the well region.

[0022] According to the manufacturing method of the power semiconductor device, the step of forming the well region is performed by implanting impurities of the second conductivity type into the semiconductor layer, and the step of forming the source region can be performed by implanting impurities of the first resistivity type into the well region.

[0023] According to the manufacturing method of the power semiconductor device, the drift region is formed on a drain region having the first conductivity type, and the drain region can be doped at a higher concentration than the drift region.

[0024] According to the manufacturing method of the power semiconductor device, the drain region is provided as a substrate of the first conductivity type, and the drift region can be formed as an epitaxial layer on the substrate.

Advantages of the Invention

[0025] According to the power semiconductor device and its manufacturing method according to an embodiment of the present invention made as described above, it is possible to increase the integration degree by increasing the channel density while relaxing the electric field concentration. Of course, such an effect is exemplary, and the scope of the present invention is not limited by such an effect.

Brief Description of the Drawings

[0026] [Figure 1] It is a schematic perspective view showing a power semiconductor device according to an embodiment of the present invention. [Figure 2] It is a plan view showing a power semiconductor device cut along the line II-II of FIG. 1. [Figure 3] It is a cross-sectional view showing a power semiconductor device cut along the line III-III of FIG. 2. [Figure 4] It is a schematic perspective view showing a power semiconductor device according to another embodiment of the present invention. [Figure 5] It is a cross-sectional view showing a power semiconductor device cut along the line V-V of FIG. 4. [Figure 6] It is a cross-sectional view showing a power semiconductor device cut along the line VI-VI of FIG. 4. [Figure 7] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 8] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 9] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 10] This is a schematic perspective view showing a power semiconductor device relating to one embodiment of the present invention. [Figure 11] This is a plan view showing a power semiconductor device cut along the line II-II in Figure 10. [Figure 12] This is a cross-sectional view showing a power semiconductor device cut along the line III-III in Figure 11. [Figure 13] This is a perspective view showing a power semiconductor device according to another embodiment of the present invention. [Figure 14] This is a schematic perspective view showing a power semiconductor device according to another embodiment of the present invention. [Figure 15] This is a plan view showing a power semiconductor device cut along the line VI-VI in Figure 14. [Figure 16] This is a cross-sectional view showing a power semiconductor device cut along the line VII-VII in Figure 15. [Figure 17] This is a cross-sectional view showing a power semiconductor device cut along the line VIII-VIII in Figure 15. [Figure 18] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 19] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 20] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 21] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 22]This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 23] This graph shows the change in the electric field of a power semiconductor device according to one embodiment of the present invention, with respect to the depth. [Figure 24] This is a schematic perspective view showing a power semiconductor device relating to one embodiment of the present invention. [Figure 25] This is a plan view showing a power semiconductor device cut along the line II-II in Figure 24. [Figure 26] This is a cross-sectional view of a power semiconductor device taken along the line III-III in Figure 25. [Figure 27] This is a cross-sectional view showing a power semiconductor device cut along the line VI-VI in Figure 25. [Figure 28] This is a cross-sectional view showing a power semiconductor device according to another embodiment of the present invention. [Figure 29] This is a cross-sectional view showing a power semiconductor device according to another embodiment of the present invention. [Figure 30] This is a schematic perspective view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 31] This is a schematic perspective view showing a power semiconductor device according to another embodiment of the present invention. [Figure 32] This is a plan view showing a power semiconductor device cut along the line XI-XI in Figure 31. [Figure 33] This is a cross-sectional view showing a power semiconductor device cut along line XX in Figure 32. [Figure 34] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 35] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 36] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 37] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 38]This is a schematic perspective view showing a power semiconductor device relating to one embodiment of the present invention. [Figure 39] This is a plan view showing a power semiconductor device cut along the line II-II in Figure 38. [Figure 40] This is a cross-sectional view of a power semiconductor device taken along the line III-III in Figure 39. [Figure 41] Figure 39 is a cross-sectional view showing a power semiconductor device cut along the IV-IV line. [Figure 42] This is a cross-sectional view showing a power semiconductor device according to another embodiment of the present invention. [Figure 43] This is a cross-sectional view showing a power semiconductor device according to another embodiment of the present invention. [Figure 44] This is a schematic cross-sectional view showing a power semiconductor device according to another embodiment of the present invention. [Figure 45] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 46] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 47] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 48] This graph shows the characteristics of a diode in a power semiconductor device according to an embodiment of the present invention. [Figure 49] This is a schematic perspective view showing a power semiconductor device relating to one embodiment of the present invention. [Figure 50] This is a plan view showing a power semiconductor device cut along the line II-II in Figure 49. [Figure 51] This is a cross-sectional view of a power semiconductor device taken along the line III-III in Figure 50. [Figure 52] This is a cross-sectional view showing a power semiconductor device according to another embodiment of the present invention. [Figure 53] This is a schematic perspective view showing a power semiconductor device according to another embodiment of the present invention. [Figure 54]This is a plan view showing a power semiconductor element cut along the line VI-VI in Figure 53. [Figure 55] This is a cross-sectional view showing a power semiconductor device cut along the line VII-VII in Figure 54. [Figure 56] This is a cross-sectional view showing a power semiconductor device cut along the line VIII-VIII in Figure 54. [Figure 57] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 58] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 59] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 60] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 61] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 62] This is a schematic perspective view showing a power semiconductor device relating to one embodiment of the present invention. [Figure 63] This is a plan view showing a power semiconductor device cut along the line II-II in Figure 62. [Figure 64] This is a cross-sectional view showing a power semiconductor device cut along the line III-III in Figure 63. [Figure 65] This is a cross-sectional view showing a power semiconductor device according to another embodiment of the present invention. [Figure 66] This is a schematic perspective view showing a power semiconductor device according to another embodiment of the present invention. [Figure 67] This is a plan view showing power semiconductor elements cut along the line VI-VI in Figure 66. [Figure 68] This is a cross-sectional view showing a power semiconductor device cut along the line VII-VII in Figure 67. [Figure 69] This is a cross-sectional view showing a power semiconductor device cut along the line VIII-VIII in Figure 67. [Figure 70] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 71] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 72] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 73] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 74] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 75] This is a schematic perspective view showing a power semiconductor device relating to one embodiment of the present invention. [Figure 76] This is a plan view showing a power semiconductor device cut along the line II-II in Figure 75. [Figure 77] This is a cross-sectional view showing a power semiconductor device cut along the line III-III in Figure 76. [Figure 78] Figure 76 is a cross-sectional view showing a power semiconductor device cut along the IV-IV line. [Figure 79] This is a schematic perspective view showing a power semiconductor device according to another embodiment of the present invention. [Figure 80] This is a plan view showing a power semiconductor device cut along the line VI-VI in Figure 79. [Figure 81] This is a cross-sectional view showing a power semiconductor device cut along the line VII-VII in Figure 80. [Figure 82] This is a cross-sectional view showing a power semiconductor device cut along the line VIII-VIII in Figure 80. [Figure 83] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 84] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 85] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 86] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 87] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 88] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 89] This is a schematic perspective view showing a manufacturing method for a power semiconductor device according to one embodiment of the present invention. [Figure 90] This is a schematic perspective view showing a power semiconductor device relating to one embodiment of the present invention. [Figure 91] This is a plan view showing a power semiconductor device cut along the line II-II in Figure 90. [Figure 92] This is a cross-sectional view showing a power semiconductor device cut along the line III-III in Figure 91. [Figure 93] This is a perspective view showing a power semiconductor device according to another embodiment of the present invention. [Figure 94] This is a schematic perspective view showing a power semiconductor device according to another embodiment of the present invention. [Figure 95] This is a plan view showing a power semiconductor device cut along the line VI-VI in Figure 94. [Figure 96] This is a cross-sectional view of a power semiconductor device taken along the line VII-VII in Figure 95. [Figure 97] This is a cross-sectional view of a power semiconductor device taken along the line VIII-VIII in Figure 95. [Figure 98] This is a cross-sectional view showing a power semiconductor device according to yet another embodiment of the present invention. [Figure 99] This is a perspective view showing a power semiconductor device according to yet another embodiment of the present invention. [Modes for carrying out the invention]

[0027] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be realized in a variety of different forms, and the following embodiments are provided to ensure that the disclosure of the present invention is complete and to fully inform a person of ordinary skill of the scope of the invention. Also, for the sake of convenience of explanation, at least some of the components in the drawings may be exaggerated or reduced in size. In the drawings, the same reference numerals refer to the same element.

[0028] Unless otherwise defined, all terms used herein have the same meaning as that commonly understood by those with ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for illustrative purposes and are provided to illustrate the general structure of the present invention.

[0029] The same reference numeral indicates the same component. When one component, such as a layer, region, or substrate, is said to be on another component, it will be understood that it is either directly above the other component or that other intervening components may exist between them. Conversely, when one component is said to be "directly on" another component, it will be understood that there are no intermediate components.

[0030] Figure 1 is a schematic perspective view showing a power semiconductor device according to one embodiment of the present invention, Figure 2 is a plan view showing the power semiconductor device cut along the line II-II in Figure 1, and Figure 3 is a cross-sectional view showing the power semiconductor device cut along the line III-III in Figure 2.

[0031] Referring to Figures 1 to 3, the power semiconductor device 100-1 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-1 may have a power MOSFET structure.

[0032] The semiconductor layer 105 can refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 can refer to one or multiple epitaxial layers on a semiconductor substrate.

[0033] For example, the semiconductor layer 105 can be composed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one silicon carbide epitaxial layer.

[0034] Because silicon carbide (SiC) has a wider bandgap than silicon, it can maintain stability even at higher temperatures. Furthermore, because silicon carbide has a much higher dielectric breakdown field than silicon, it can operate stably even at high voltages. Therefore, the power semiconductor device 100-1 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage while also exhibiting superior heat dissipation characteristics and stable operating characteristics even at high temperatures, compared to the case using silicon.

[0035] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and can be formed by implanting an impurity of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 can be formed by doping an epitaxial layer of silicon carbide with an impurity of the first conductivity type.

[0036] The well region 110 is formed in the semiconductor layer 105 so as to be in contact with at least a portion of the drift region 107 and may have a second conductivity type. For example, the well region 110 can be formed by doping the drift region 107 with an impurity of a second conductivity type opposite to the first conductivity type.

[0037] For example, the well region 110 can be formed to surround at least a portion of the drift region 107. Thus, the drift region 107 can include a vertical portion 107a that is at least partially surrounded by the well region 110. During operation of the power semiconductor device 100-1, the vertical portion 107a can provide a vertical charge transfer path.

[0038] Figure 1 shows that the well region 110 is formed so as to be separated into two regions, with the vertical portion 107a confined between them, but it can be modified in various other ways. For example, the vertical portion 107a may have a shape in which its sides are surrounded by the well region 110.

[0039] The source region 112 is formed within the well region 110 and may have a first conductivity type. For example, the source region 112 can be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 can be formed by doping the drift region 107 with an even higher concentration of the impurity of the first conductivity type.

[0040] At least one channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a may have a second conductivity type such that an inversion channel is formed along one direction.

[0041] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction with the source region 112 and the drift region 107. Thus, the channel region 110a does not allow charge movement under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inverting channel is formed inside it, allowing charge movement.

[0042] In some embodiments, the channel region 110a may be part of the well region 110. In this case, the channel region 110a may be formed to be continuously connected to the well region 110. The doping concentration of the second conductivity type impurity in the channel region 110a may be the same as that of the rest of the well region 110, or it may differ to adjust the threshold voltage.

[0043] In some embodiments, the well region 110, the channel region 110a, and the source region 112 can be formed symmetrically around the vertical portion 107a of the drift region 107. For example, the well region 110, the channel region 110a, and the source region 112 may each include a left portion and a right portion, respectively, that are formed symmetrically around the vertical portion 107a. The left portion and the right portion of such a well region 110, the channel region 110a, and the source region 112 may be separated from each other or connected to each other.

[0044] Additionally, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, the drain region 102 can be doped to a higher concentration than the drift region 107.

[0045] In some embodiments, the drain region 102 may also be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0046] At least one trench 116 can be formed by recessing from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. The trench 116 can extend in one direction within the semiconductor layer 105. This one direction refers to the length direction of the trench 116, rather than the depth direction, and can refer to the II-II line or III-III line direction in Figure 1.

[0047] The gate insulating layer 118 can be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 may include or include a laminated structure of an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide. The thickness of the gate insulating layer 118 may be uniform, or the portion formed on the bottom surface of the trench 116 may be thicker than the portion formed on the side wall.

[0048] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 so as to fill the trench 116. For example, the gate electrode layer 120 may include a suitable conductor, such as polysilicon, metal, metal nitride, metal silicide, or a laminated structure thereof.

[0049] The drift region 107 can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 can extend perpendicularly to the semiconductor layer 105 on one side of the gate electrode layer 120.

[0050] In some embodiments, the drift region 107 can be formed in the semiconductor layer 105 on both sides of the gate electrode layer 120. For example, the drift region 107 may include vertical portions 107a extending perpendicularly to the semiconductor layer 105 on both sides of the gate electrode layer 120.

[0051] The well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Furthermore, the well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120. As a result, both ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0052] Such a structure can mitigate the problem of electric field concentration at the bottom of the trench 116, i.e., at the lower end of the gate electrode layer 120. Therefore, according to the power semiconductor element 100-1 of this embodiment, there is no need to form an additional deep well, and by forming the well region 110 deeper than the gate electrode layer 120, the problem of electric field concentration at the bottom of the trench 116 can be mitigated. In conventional vertical channel structures, there was a problem in that the junction resistance and threshold voltage increased when the distance between the deep well and the trench narrowed, but this can be solved in the power semiconductor element 100-1 of this embodiment.

[0053] The channel region 110a can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Thus, the semiconductor layer 105 on one side of the gate electrode layer 120 can include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected along one direction.

[0054] Such a channel region 110a can be referred to as a lateral channel structure, as it is formed along the side wall of the gate electrode layer 120.

[0055] Furthermore, the channel region 110a can also be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112.

[0056] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed not only inside the trench 116 but also to extend further outside the trench 116.

[0057] In some embodiments, one or more trenches 116 may be provided within the semiconductor layer 105. The number of trenches 116 may be appropriately selected and thus do not limit the scope of this embodiment.

[0058] For example, multiple trenches 116 can be formed in the semiconductor layer 105 along one direction. The trenches 116 can extend in one direction and be spaced apart in a direction perpendicular to that direction.

[0059] In this case, multiple gate electrode layers 120 can be formed on the gate insulating layer 118 so as to fill the inside of the trench 116. Thus, the gate electrode layers 120 can be formed in a trench type within the semiconductor layer 105 and arranged to extend in a unidirectional manner, similar to the trench 116.

[0060] Furthermore, the well region 110 and the source region 112 can extend across the gate electrode layer 120, respectively. The vertical portion 107a of the drift region 107 can be located in the semiconductor layer 105 between the gate electrode layers 120. Multiple channel regions 110a can be formed on one or both sides of the gate electrode layer 120 in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107.

[0061] In some embodiments, the well region 110 can be formed in the semiconductor layer 105 deeper than the gate electrode layer 120, so as to be in contact with the vertical portion 107a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120. The interlayer insulating layer 130 can be formed on the gate electrode layer 120.

[0062] The source electrode layer 140 is formed on the interlayer insulating layer 130 and can be connected to the source region 112. For example, the source electrode layer 140 can be formed from an appropriate conductive material, metal, etc. For clarity in the illustration, unlike Figures 2 and 3, the interlayer insulating layer 130 and the source electrode layer 140 are omitted from Figure 1.

[0063] In the power semiconductor device 100-1 described above, the first conductivity type and the second conductivity type are opposite to each other, but each may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0064] More specifically, if the power semiconductor element 100-1 is an N-type MOSFET, the drift region 107 may be an N- region, the source region 112, the source contact region 112a, and the drain region 102 may be N+ regions, the well region 110 and the channel region 110a may be P- regions, and the well contact region 114 may be a P+ region.

[0065] During operation of the power semiconductor element 100-1, current can flow generally vertically from the drain region 102 along the vertical portion 107a of the drift region 107, and then through the channel region 110a along the side surface of the gate electrode layer 120 to the source region 112.

[0066] In the aforementioned power semiconductor device 100-1, the gate electrode layer 120 can be densely arranged in parallel in a stripe type, and the channel region 110a can be placed on the side surface of the gate electrode layer 120, thereby increasing the channel density.

[0067] Furthermore, in the power semiconductor element 100-1, since the bottom surface of the gate electrode layer 120 is surrounded by the well region 110, the phenomenon of breakdown occurring due to electric field concentration at the corners of the trench 116 can be mitigated. Therefore, the breakdown voltage characteristics of the power semiconductor element 100-1 can be improved, and the operational reliability can be enhanced.

[0068] Figure 4 is a schematic perspective view showing a power semiconductor element 100a-1 according to another embodiment of the present invention; Figure 5 is a cross-sectional view showing the power semiconductor element 100a-1 cut along the VV line in Figure 4; and Figure 6 is a cross-sectional view showing the power semiconductor element 100a-1 cut along the VI-VI line in Figure 4.

[0069] The power semiconductor element 100a-1 according to this embodiment is either the same as or a modified version of the power semiconductor element 100-1 shown in Figures 1 to 3; therefore, redundant explanations are omitted.

[0070] Referring to Figures 4 to 6, the source region 112 may include a source contact region 112a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120. For example, the source contact region 112a may refer to the portion to which the source electrode layer 140 is connected as part of the source region 112.

[0071] The well contact region 114 can be formed within the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 through the source region 112 and have a second conductivity type. One or more well contact regions 114 can be formed within the source contact region 112a.

[0072] For example, the well contact region 114 can be connected to the source electrode layer 140, and when connected to the source electrode layer 140, the well contact region 114 can be doped with a higher concentration of second-conductivity impurities than the well contact region 110 in order to reduce the contact resistance.

[0073] Figures 4 to 6 show that the source contact region 112a and the well contact region 114 are formed on one side of the source region 112 with respect to the vertical portion 107a of the drift region 107. However, if the source region 112 and the well region 110 are separated into multiple parts, the source contact region 112a and the well contact region 114 may be formed on each of them.

[0074] In some embodiments, the trenches 116 can be spaced apart in a single row along one direction. This allows the gate electrode layer 120 to also be spaced apart in a single row along the trenches 116 in one direction. In this case, the well region 110 and the source region 112 can be formed in the semiconductor layer 105 between the spaced trenches 116, respectively, which are spaced apart in a single row along one direction.

[0075] For example, multiple power semiconductor element structures 100-1 shown in Figures 1 to 3 can be arranged along one direction, with well regions 110 and source regions 112 formed between them. For clarity in the illustration, unlike Figures 5 and 6, Figure 4 omits the depiction of the interlayer insulating layer 130 and the source electrode layer 140.

[0076] According to the power semiconductor element 100a-1 of this embodiment, by placing the source contact region 112a and the well contact region 114 outside the gate electrode layer 120 instead of between them, the gate electrode layer 120 can be arranged very densely. As a result, the channel density of the power semiconductor element 100a-1 can be significantly increased. Furthermore, according to the power semiconductor element 110a-1, the phenomenon of breakdown occurring due to electric field concentration at the corners of the trench 116 can be mitigated, improving the breakdown voltage characteristics of the power semiconductor element 100a-1 and enhancing operational reliability.

[0077] Figures 7 to 9 are schematic perspective views showing a manufacturing method for a power semiconductor device 100-1 according to one embodiment of the present invention. Referring to Figure 7, a drift region 107 having a first conductivity type can be formed on a silicon carbide (SiC) semiconductor layer 105. For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 is provided as a substrate of the first conductivity type, and the drift region 107 can be formed on such a substrate as one or more epitaxial layers.

[0078] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with at least a portion of the drift region 107. For example, the step of forming the well region 110 can be performed by implanting an impurity of the second conductivity type into the semiconductor layer 105.

[0079] For example, the well region 110 can be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a in which at least a portion is surrounded by the well region 11. More specifically, the well region 110 can be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107.

[0080] Next, a source region 112 having a first conductivity type can be formed within the well region 110. For example, the step of forming the source region 112 can be performed by injecting an impurity of the first conductivity type into the well region 110.

[0081] Along with the formation of the source region 112, an inversion channel can be formed in the semiconductor layer 105 between the source region 112 and the drift region 107 along one direction, thereby forming at least one channel region 110a having a second conductivity type. For example, the channel region 110a can be formed between the source region 112 and the vertical portion 107a of the drift region 107.

[0082] In the manufacturing method described above, impurity implantation or impurity doping can be performed by ion implanting impurities into the semiconductor layer 105, or by introducing impurities during the formation of the epitaxial layer. However, for impurity implantation in selective regions, an ion implantation method using a mask pattern can be used. Selectively, after ion implantation, a heat treatment step can be followed to activate or diffuse impurities.

[0083] Referring to Figure 8, at least one trench 116 can be formed such that it is recessed from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. For example, the trench 116 can extend in one direction across the drift region 107 and be formed shallower than the well region 110.

[0084] Furthermore, multiple trenches 116 can be formed in the semiconductor layer 105 in a unidirectional arrangement. For example, the trenches 116 can be formed by creating a photomask using photolithography, and then etching the semiconductor layer 105 using such a photomask as an etching protective film.

[0085] Referring to Figure 9, a gate insulating layer 118 can be formed on the inner wall of the trench 116. For example, the gate insulating layer 118 can be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or nitride onto the semiconductor layer 105.

[0086] Next, a gate electrode layer 120 can be formed on the gate insulating layer 118 to fill the trench 116. For example, the gate electrode layer 120 can be formed by patterning a conductive layer after it has been formed on the gate insulating layer 118. The gate electrode layer 120 can be formed by doping polysilicon with impurities, or by including a conductive metal or metal silicide.

[0087] The patterning process can be carried out using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photographic process and a developing process, and the etching process may include selectively etching the underlying structure using such a photoresist pattern.

[0088] As a result, the well region 110 is positioned deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 on one or both sides of the gate electrode layer 120 between the drift region 107 and the source region 112.

[0089] Additionally, as shown in Figures 2 and 3, an interlayer insulating layer 130 can be formed on the gate electrode layer 120. Then, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by forming a conductive layer, such as a metal layer, on the interlayer insulating layer 130 and then patterning it.

[0090] On the other hand, the power semiconductor device 100a-1 shown in Figures 4 to 6 can be manufactured by adding or modifying some steps in the manufacturing process of the power semiconductor device 100-1 described above.

[0091] For example, during the manufacturing of the power semiconductor device 100a-1, the step of forming the source region 112 may include the step of forming a source contact region 112a connected to the source electrode layer 140, at least outside one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may not be separated from the source region 112.

[0092] Furthermore, a well contact region 114 can be formed within the source contact region 112a before forming the trench 116. For example, the well contact region 114 can be formed by injecting a second conductivity type impurity into a portion of the well region 110 at a higher concentration than in the well region 110.

[0093] During the manufacturing of the power semiconductor device 100a-1, the trenches 116 can be spaced apart in a single line in one direction. Furthermore, the well region 110, the channel region 110a, and the source region 112 can be formed in the semiconductor layer 105 between the trenches 116, respectively.

[0094] According to the manufacturing method described above, a power semiconductor element 100-1 can be economically manufactured using a silicon carbide semiconductor layer 105 and processes used for existing silicon substrates.

[0095] Figure 10 is a schematic perspective view showing a power semiconductor element 100-2 according to one embodiment of the present invention, Figure 11 is a plan view showing the power semiconductor element 100-2 cut along the line II-II in Figure 10, and Figure 12 is a cross-sectional view showing the power semiconductor element 100-2 cut along the line III-III in Figure 11.

[0096] Referring to Figures 10 to 12, the power semiconductor device 100-2 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-2 may have a power MOSFET structure.

[0097] The semiconductor layer 105 can refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 can refer to one or multiple epitaxial layers on a semiconductor substrate.

[0098] For example, the semiconductor layer 105 can be composed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one silicon carbide epitaxial layer.

[0099] Because silicon carbide (SiC) has a wider bandgap than silicon, it can maintain stability even at higher temperatures. Furthermore, because silicon carbide has a much higher dielectric breakdown field than silicon, it can operate stably even at high voltages. Therefore, the power semiconductor device 100-2 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage while also exhibiting superior heat dissipation characteristics and stable operating characteristics even at high temperatures, compared to the case using silicon.

[0100] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and can be formed by implanting an impurity of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 can be formed by doping an epitaxial layer of silicon carbide with an impurity of the first conductivity type.

[0101] The well region 110 is formed in the semiconductor layer 105 in contact with the drift region 107 and may have a second conductivity type. For example, the well region 110 can be formed by doping the drift region 107 with an impurity of a second conductivity type opposite to the first conductivity type.

[0102] For example, the well region 110 can be formed to surround at least a portion of the drift region 107. This allows the drift region 107 to include a vertical portion 107a that is at least partially surrounded by the well region 110. During operation of the power semiconductor element 100-2, the vertical portion 107a can provide a vertical path for charge movement.

[0103] Figure 10 shows that the well region 110 is formed so as to be separated into two regions, with the vertical portion 107a defined between them, but it can be modified in various other ways. For example, the vertical portion 107a may have a shape in which its sides are surrounded by the well region 110.

[0104] The pillar region 111 can be formed in the semiconductor layer 105 below the well region 110, in contact with the drift region 107, so as to form a superjunction with the drift region 107. For example, the pillar region 111 can be positioned below the well region 110, in contact with the well region 110, with both sides in contact with the drift region 107.

[0105] The pillar region 111 can be formed in the semiconductor layer 105 such that it has a different conductivity type than the drift region 107, so as to form a superjunction with the drift region 107. For example, the pillar region 111 may be opposite to the drift region 107 and have a second conductivity type, similar to the well region 110. For example, the doping concentration of the second conductivity type impurity in the pillar region 111 may be the same as or less than the doping concentration of the second conductivity type impurity in the well region 110.

[0106] In some embodiments, the pillar region 111 can be formed to have a width narrower than the width of the well region 110 with respect to one direction. In Figure 11, this direction can refer to the direction of the line III-III. Furthermore, both ends of the pillar region 111 can be positioned so as to be moved inward from both ends of the well region 110 with respect to one direction.

[0107] As a result, the pillar region 111 can be positioned below the well region 110, receding inward from both ends of the well region 110 and tangent to the well region 110. For example, if the pillar region 111 is formed along the well region 110 so as to be separated into two regions, the separation distance between the two pillar regions 111 may be greater than the separation distance between the two well regions 110.

[0108] In some embodiments, the sides and bottom surfaces of the pillar region 111 can be in contact with the drift region 107. For example, multiple pillar regions 111 and drift regions 107 can be arranged alternately so that their sides are in contact with each other, forming a superjunction structure. Furthermore, multiple pillar regions 111 and drift regions 107 can also be arranged alternately at the bottom of a single well region 110.

[0109] The source region 112 is formed within the well region 110 and may have a first conductivity type. For example, the source region 112 can be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 can be formed by doping the drift region 107 with an even higher concentration of the impurity of the first conductivity type.

[0110] The channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a has a second conductivity type, and an inversion channel can be formed along one direction during the operation of the power semiconductor element 100-2.

[0111] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction with the source region 112 and the drift region 107. Thus, the channel region 110a does not allow charge movement under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inverting channel is formed inside it, allowing charge movement.

[0112] In some embodiments, the channel region 110a may be part of the well region 110. In this case, the channel region 110a may be formed integrally with the well region 110 so as to be continuously connected to it. The doping concentration of the second conductivity type impurity in the channel region 110a may be the same as that of the other parts of the well region 110, or may differ to adjust the threshold voltage.

[0113] In some embodiments, the well region 110, pillar region 111, channel region 110a, and source region 112 can be formed symmetrically around the vertical portion 107a of the drift region 107. For example, the well region 110, pillar region 111, channel region 110a, and source region 112 can be formed at both ends of the vertical portion 107a of the drift region 107, and may each include a first and second portion formed symmetrically around the vertical portion 107a. The first and second portions of such well region 110, pillar region 111, channel region 110a, and source region 112 may be separated from each other or connected to each other.

[0114] Additionally, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, the drain region 102 can be doped to a higher concentration than the drift region 107.

[0115] In some embodiments, the drain region 102 may also be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0116] At least one trench 116 can be formed by recessing from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. The trench 116 can extend in one direction within the semiconductor layer 105. This one direction refers to the length direction of the trench 116, not the depth direction, and can refer to the III-III direction in Figure 11.

[0117] The gate insulating layer 118 can be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 can be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or the portion formed on the bottom of the trench 116 may be thicker than the portion formed on the side walls in order to reduce the electric field at the bottom of the trench 116.

[0118] For example, the gate insulating layer 118 may include or include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide.

[0119] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 so as to fill the trench 116. For example, the gate electrode layer 120 may include a suitable conductor, such as polysilicon, metal, metal nitride, metal silicide, or a laminated structure thereof.

[0120] The drift region 107 can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 can extend perpendicularly to the semiconductor layer 105 on one side of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Thus, the semiconductor layer 105 on one side of the gate electrode layer 120 can include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected along one direction.

[0121] In some embodiments, the drift region 107 can be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120. For example, the drift region 107 may include vertical portions 107a extending perpendicularly to the semiconductor layers 105 on both sides of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120 between the vertical portions 107a of the drift region 107 and the source region 112.

[0122] Such a channel region 110a can be called a lateral channel because it is formed along the side wall of the gate electrode layer 120.

[0123] The well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Furthermore, the well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120. As a result, both ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0124] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed not only inside the trench 116 but also to extend further outside the trench 116.

[0125] In some embodiments, one or more trenches 116 may be provided within the semiconductor layer 105. The number of trenches 116 may be appropriately selected and thus do not limit the scope of this embodiment.

[0126] For example, multiple trenches 116 can be formed in the semiconductor layer 105 along one direction. The trenches 116 can extend in one direction and be spaced apart in a direction perpendicular to that direction.

[0127] In this case, multiple gate electrode layers 120 can be formed on the gate insulating layer 118 so as to fill the inside of the trench 116. Thus, the gate electrode layers 120 can be formed in a trench type within the semiconductor layer 105 and arranged to extend in a unidirectional manner, similar to the trench 116.

[0128] Furthermore, the well region 110 and the source region 112 can extend across the gate electrode layer 120, respectively. The vertical portion 107a of the drift region 107 can be located in the semiconductor layer 105 between the gate electrode layers 120. The channel region 110a can be formed on one or both sides of the gate electrode layer 120 in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107.

[0129] The interlayer insulating layer 130 can be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an appropriate insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof.

[0130] The source electrode layer 140 is formed on the interlayer insulating layer 130 and can be connected to the source region 112. For example, the source electrode layer 140 can be formed from an appropriate conductive material, metal, or the like.

[0131] In the power semiconductor device 100-2 described above, the first conductivity type and the second conductivity type are opposite to each other, but each may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0132] More specifically, if the power semiconductor element 100-2 is an N-type MOSFET, the drift region 107 may be an N- region, the source region 112 and drain region 102 may be N+ regions, and the well region 110, pillar region 111, and channel region 110a may be P- regions.

[0133] During operation of the power semiconductor element 100-2, current can flow generally vertically from the drain region 102 along the vertical portion 107a of the drift region 107, and then through the channel region 110a along the side surface of the gate electrode layer 120 to the source region 112.

[0134] In the aforementioned power semiconductor device 100-2, the gate electrode layers 120 within the trench 116 can be densely arranged in parallel in a stripe or line type, and the channel region 110a can be located on the side of the gate electrode layer 120, thereby increasing the channel density.

[0135] Furthermore, in the aforementioned power semiconductor device 100-2, the well 110 structure can mitigate the problem of electric field concentration at the bottom of the trench 116, i.e., at the lower end of the gate electrode layer 120. This increases the electric field margin over the gate insulating layer 118 in the power semiconductor device 100-2, thereby improving the operational reliability of the power semiconductor device 100-2. Moreover, by lowering the electric field at the bottom of the trench 116 and the electric field over the gate insulating layer 118, there is room to lower the junction resistance of the vertical portion 107a of the drift region 107.

[0136] On the other hand, power semiconductor element 100-2 is used for high-power switching, so high breakdown voltage characteristics are required. When a high voltage is applied to the drain region 102, the depletion region expands from the semiconductor layer 105 adjacent to the drain region 102, and the voltage barrier of the channel can be lowered. This phenomenon is called DIBL (drain-induced barrier lowering).

[0137] Such DIBL can induce abnormal turn-on of the channel region 110a, and furthermore, it can lead to a punch-through phenomenon in which the depletion layer between the drain region 102 and the source region 112 expands and comes into contact.

[0138] However, the aforementioned power semiconductor element 100-2 can use the drift region 107 and the pillar region 111 that forms a superjunction to suppress abnormal current flow and punch-through phenomena caused by DIBL and ensure appropriate breakdown voltage characteristics. Such breakdown voltage characteristics can be further improved by adjusting the charge amount in the pillar region 111 and the charge amount in the drift region 107.

[0139] Figure 23 is a graph showing the change in the electric field with respect to the depth of the power semiconductor element 100-2. Referring to Figure 23, if the charge Qp in the pillar region 111 is made larger than the charge Qn in the drift region 107, the breakdown voltage can be increased by generating the maximum electric field in the drift region 107, which is on the same line as the bottom surface of the pillar region 111, during the operation of the power semiconductor element 100-2. In Figure 23, the gradient of the electric field strength between position A and position B can be controlled by adjusting the charge Qp in the pillar region 111.

[0140] For example, by making the doping concentration of the second conductivity type impurity in the pillar region 111 higher than the doping concentration of the first conductivity type impurity in the drift region 107, the charge amount Qp in the pillar region 111 can be made larger than the charge amount Qn in the drift region 107, thereby improving the breakdown voltage characteristics of the power semiconductor device 100-2.

[0141] Figure 13 is a perspective view showing a power semiconductor element 100a-2 according to another embodiment of the present invention. The power semiconductor element 100a-2 according to this embodiment uses or is a modified version of the power semiconductor element 100-2 shown in Figures 10 to 12, and therefore redundant explanations are omitted.

[0142] Referring to Figure 13, in power semiconductor device 100a-2, the channel region 107b can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b can have a first conductivity type, and an accumulation channel can be formed inside it when the power semiconductor device 100-2 is operating.

[0143] For example, the channel region 107b can be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b can have the same doping type as the source region 112 and the drift region 107.

[0144] In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connectable. However, in the structure of the silicon carbide semiconductor layer 105, the negative charge generated as carbon clusters form on the gate insulating layer 118 causes the band of the channel region 107b to bend upward, forming a potential barrier. As a result, a storage channel that allows the flow of charge or current can only be formed in the channel region 107b when an operating voltage is applied to the gate electrode layer 120.

[0145] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form a storage channel in the channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form an inversion channel in the channel region 110a in Figures 10 to 12.

[0146] In some embodiments, the channel region 107b may be part of the drift region 107. More specifically, the channel region 107b may be part of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be formed integrally with the drift region 107. In this case, the drift region 107 may be connected to the source region 112 via the channel region 107b. That is, in the channel region 107b portion, the drift region 107 and the source region 112 may be in contact with each other.

[0147] The doping concentration of the first conductivity type impurity in the channel region 107b may be the same as that of the rest of the drift region 107, or it may be different to adjust the threshold voltage.

[0148] In a modified version of this embodiment, the well region 110 is formed protruding from a portion of the source region 112 in the direction of the vertical portion 107a of the drift region 107, and the channel region 107b may also be formed in the semiconductor layer 105 on the protruding portion of the well region 110.

[0149] Furthermore, the well region 110 may further include a tapped portion extending toward the gate electrode layer 120 at the end of the protruding portion. The channel region 107b may be formed in a refractive shape on the protruding portion and the tapped portion of the well region 110.

[0150] Additionally, the vertical portion 107a of the drift region 107 can extend further between the lower part of the source region 112 and the well region 110. In this case, the channel region 107b can be formed by extending further between the lower part of the source region 112 and the well region 110.

[0151] Such a structure can be made so that the channel region 107b is further confined between the gate electrode layer 120 and the well region 110.

[0152] With power semiconductor device 100a-2, in addition to the advantages of power semiconductor device 100-2 shown in Figures 10 to 12, an additional effect of lowering the threshold voltage can be expected.

[0153] Figure 14 is a schematic perspective view showing a power semiconductor element 100b-2 according to another embodiment of the present invention; Figure 15 is a plan view showing the power semiconductor element 100b-2 cut along the line VI-VI in Figure 14; Figure 16 is a cross-sectional view showing the power semiconductor element 100b-2 cut along the line VII-VII in Figure 15; and Figure 17 is a cross-sectional view showing the power semiconductor element 100b-2 cut along the line VIII-VIII in Figure 15.

[0154] The power semiconductor element 100b-2 according to this embodiment is the same as or a modified version of the power semiconductor element 100-2 shown in Figures 10 to 12, and therefore, redundant explanations are omitted.

[0155] Referring to Figures 14 to 17, in the power semiconductor device 100b-2, the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a may refer to the portion to which the source electrode layer 140 is connected as part of the source region 112.

[0156] The well contact region 114 can be formed within the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 through the source region 112 and have a second conductivity type. One or more well contact regions 114 can be formed within the source contact region 112a.

[0157] For example, the well contact region 114 can be doped with a higher concentration of second-conductivity impurities than the well region 110 to reduce contact resistance when connected to the source electrode layer 140. The source electrode layer 140 can be connected in common to the source contact region 112a and the well contact region 114.

[0158] Figures 14 to 17 show that the source contact region 112a and the well contact region 114 are formed on one side of the source region 112 with respect to the vertical portion 107a of the drift region 107. However, if the source region 112 and the well region 110 are separated into multiple parts, the source contact region 112a and the well contact region 114 may be formed on each of them.

[0159] In some embodiments, the trenches 116 can be spaced apart in a single row along one direction. This allows the gate electrode layer 120 to also be spaced apart in a single row along one direction along the trenches 116. In this case, the well region 110, source region 112, source contact region 112a, and well contact region 114 can be formed in the semiconductor layer 105 between the trenches 116 spaced apart in a single row along one direction, respectively.

[0160] For example, the power semiconductor element 100b-2 can also be formed by arranging multiple power semiconductor element 100-2 structures shown in Figures 10 to 12 along one direction, with a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 placed between them.

[0161] For example, if the power semiconductor element 100-2 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

[0162] In the power semiconductor device 100b-2, by placing the source contact region 112a and the well contact region 114 outside the gate electrode layer 120 instead of between them, the gate electrode layer 120 can be arranged very densely. As a result, the channel density of the power semiconductor device 100a-2 can be significantly increased.

[0163] Figures 18 and 19 are cross-sectional views showing power semiconductor elements 100c-2 and 100d-2 according to yet another embodiment of the present invention. Power semiconductor elements 100c-2 and 100d-2 are modified versions of some of the configurations of power semiconductor element 100b-2 in Figures 14 to 17, and redundant explanations are omitted in these embodiments.

[0164] Referring to Figure 18, the power semiconductor element 100c-2 may include at least one groove 138 formed within the source contact region 112a of the source region 112, penetrating the source region 112 and recessed into the well region 110. At least the bottom surface of the groove 138 may have a well contact region 114a formed to contact the well region 110.

[0165] The source electrode layer 140a is formed to fill the groove 138 and can be connected to the well contact region 114a, the well region 110, and / or the source region 112. Such a structure can help to increase the contact area between the source electrode layer 140a and the well region 110, and between the source electrode layer 140a and the source region 112, thereby reducing the contact resistance between them.

[0166] In some embodiments, the well contact region 114a can be formed entirely on the surface of the well region 110 exposed by the groove 138. Thus, the well contact region 114a can be formed on the well region 110 exposed from the bottom and side walls of the groove 138. Such a structure of the well contact region 114a can further reduce the contact resistance between the source electrode layer 140a and the well region 110.

[0167] Referring to Figure 19, the power semiconductor device 100d-2 may include a channel region 107b that forms a storage channel instead of the channel region 110a of the power semiconductor 100b-2 in Figures 14-17. The structure of the power semiconductor device 100d-2 including such a channel region 107b can be seen in the description of Figure 13.

[0168] Therefore, the power semiconductor element 100d-2 can correspond to a structure in which multiple power semiconductor elements 100a-2 shown in Figure 13 are linked together, with a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 arranged between them.

[0169] Figures 20 to 22 are schematic perspective views showing a method for manufacturing a power semiconductor device 100-2 according to one embodiment of the present invention. Referring to Figure 20, a drift region 107 having a first conductivity type can be formed on a silicon carbide (SiC) semiconductor layer 105. For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 is provided as a substrate of the first conductivity type, and the drift region 107 can be formed on such a substrate as one or more epitaxial layers.

[0170] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the step of forming the well region 110 can be carried out by injecting an impurity of the second conductivity type into the semiconductor layer 105. The well region 110 can be formed substantially to a predetermined depth from the surface of the semiconductor layer 105.

[0171] For example, the well region 110 can be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a in which at least a portion is surrounded by the well region 11. More specifically, the well region 110 can be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107.

[0172] Next, a pillar region 111 having a second conductivity type can be formed in the semiconductor layer 105 below the well region 110, in contact with the drift region 107, so as to form a superjunction with the drift region 107. The pillar region 111 can be formed by implanting impurities of the same second conductivity type as the well region 110. The well region 110 and the pillar region 111 may be formed in any order.

[0173] Next, a source region 112 having a first conductivity type can be formed within the well region 110. For example, the step of forming the source region 112 can be carried out by injecting an impurity of the first conductivity type into the well region 110. The source region 112 can be formed substantially from the surface of the semiconductor layer 105 to a predetermined depth within the well region 110.

[0174] Along with the formation of the source region 112, a channel region 110a can be formed in the semiconductor layer 105 between the source region 112 and the drift region 107, where an inversion channel is formed along one direction. The channel region 110a can be formed between the source region 112 and the vertical portion 107a of the drift region 107. For example, the channel region 110a may be part of the well region 110 and can be formed by implanting a second conductivity type impurity into the semiconductor layer 105.

[0175] In a modified version of this embodiment, the formation order of the well region 110, pillar region 111, source region 112, and channel region 110a, or the impurity doping order, may be changed to any order.

[0176] In the manufacturing method described above, impurity implantation or impurity doping can be performed by ion implanting impurities into the semiconductor layer 105 or by introducing impurities during the formation of the epitaxial layer. However, for impurity implantation in selective regions, an ion implantation method using a mask pattern can be used. Selectively, after ion implantation, a heat treatment step may follow to activate or diffuse the impurities.

[0177] Referring to Figure 21, at least one trench 116 can be formed such that it is recessed from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. For example, the trench 116 can extend in one direction across the drift region 107 and be formed shallower than the well region 110.

[0178] Furthermore, at least one trench 116 can include multiple trenches 116, for example, trenches 116 can be formed simultaneously in the semiconductor layer 105 in a unidirectional arrangement. The trenches 116 can further restrict the channel region 110a.

[0179] For example, the trench 116 can be formed by creating a photomask using photolithography, and then etching the semiconductor layer 105 using such a photomask as an etching protective film.

[0180] Referring to Figure 22, a gate insulating layer 118 can be formed on the bottom and inner wall of the trench 116. For example, the gate insulating layer 118 can be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or nitride onto the semiconductor layer 105.

[0181] Next, a gate electrode layer 120 can be formed on the gate insulating layer 118 to fill the trench 116. For example, the gate electrode layer 120 can be formed by patterning a conductive layer after it has been formed on the gate insulating layer 118. The gate electrode layer 120 can be formed by doping polysilicon with impurities, or by including a conductive metal or metal silicide.

[0182] The patterning process can be carried out using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photographic process and a developing process, and the etching process may include selectively etching the underlying structure using such a photoresist pattern.

[0183] As a result, the well region 110 is positioned deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 on one or both sides of the gate electrode layer 120 between the drift region 107 and the source region 112.

[0184] Next, an interlayer insulating layer 130 can be formed on the gate electrode layer 120. Next, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by first forming a conductive layer, such as a metal layer, on the interlayer insulating layer 130 and then patterning it.

[0185] On the other hand, the power semiconductor device 100a-2 in Figure 13 can be manufactured by adding or modifying some steps in the manufacturing process of the power semiconductor device 100-2 described above. For example, the channel region 107b can be formed as part of the drift region 107 to form a storage channel.

[0186] The power semiconductor device 100b-2 shown in Figures 14 to 17 can be manufactured by adding or modifying some steps in the manufacturing process of the power semiconductor device 100-2 described above.

[0187] For example, during the manufacturing of the power semiconductor device 100b-2, the step of forming the source region 112 may include the step of forming a source contact region 112a connected to the source electrode layer 140, at least outside one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may be part of the source region 112.

[0188] Furthermore, a well contact region 114 can be formed within the source contact region 112a before forming the trench 116. For example, the well contact region 114 can be formed by injecting a second conductivity type impurity into a portion of the well region 110 at a higher concentration than in the well region 110.

[0189] During the manufacturing of the power semiconductor device 100b-2, the trenches 116 can be spaced apart in a single line in one direction. Furthermore, the well region 110, the channel region 110a, and the source region 112 can be formed in the semiconductor layer 105 between the trenches 116, respectively.

[0190] The manufacturing of the power semiconductor device 100c-2 in Figure 18 may include the additional step of forming at least one groove 138 in the source region 112 so as to penetrate the source region 112 and recess into the well region 110, forming a well contact region 114 on the bottom surface of the groove 138 so as to contact the well region 110, and forming a source electrode layer 140 so as to fill the groove 138 and connect the source region 112 and the well contact region 114.

[0191] According to the manufacturing method described above, a power semiconductor element 100-2 can be economically manufactured using a silicon carbide semiconductor layer 105 and processes used for existing silicon substrates.

[0192] Figure 24 is a schematic perspective view showing a power semiconductor element 100-3 according to one embodiment of the present invention; Figure 25 is a plan view showing the power semiconductor element 100-3 cut along the line II-II in Figure 24; Figure 26 is a cross-sectional view showing the power semiconductor element 100-3 cut along the line III-III in Figure 25; and Figure 27 is a cross-sectional view showing the power semiconductor element 100-3 cut along the line VI-VI in Figure 25.

[0193] Referring to Figures 24 to 27, the power semiconductor device 100-3 may include a semiconductor layer 105, a gate insulating layer 118, and at least one gate electrode layer 120. For example, the power semiconductor device 100-3 may have a power MOSFET structure.

[0194] The semiconductor layer 105 can refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 can refer to one or multiple epitaxial layers on a semiconductor substrate.

[0195] For example, the semiconductor layer 105 can be composed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one silicon carbide epitaxial layer.

[0196] Because silicon carbide (SiC) has a wider bandgap than silicon, it can maintain stability even at higher temperatures. Furthermore, because silicon carbide has a much higher dielectric breakdown field than silicon, it can operate stably even at high voltages. Therefore, the power semiconductor device 100-3 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage while also exhibiting superior heat dissipation characteristics and stable operating characteristics even at high temperatures, compared to the case using silicon.

[0197] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and can be formed by implanting an impurity of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 can be formed by doping an epitaxial layer of silicon carbide with an impurity of the first conductivity type.

[0198] The well region 110 is formed in the semiconductor layer 105 in contact with the drift region 107 and may have a second conductivity type. For example, the well region 110 can be formed by doping the drift region 107 with an impurity of a second conductivity type opposite to the first conductivity type.

[0199] For example, the well region 110 can be formed to surround at least a portion of the drift region 107. This allows the drift region 107 to include a vertical portion 107a that is at least partially surrounded by the well region 110. During operation of the power semiconductor element 100-3, the vertical portion 107a can provide a vertical path for charge movement.

[0200] Figure 24 shows that the well region 110 is formed so as to be separated into two regions, with the vertical portion 107a confined between them, but it can be modified in various other ways. For example, the vertical portion 107a may have a shape in which its sides are surrounded by the well region 110.

[0201] The field relaxation region 111 is formed at a predetermined depth in the semiconductor layer 105, separated from the well region 110, and may have a second conductivity type. The field relaxation region 111 can be formed by implanting impurities of the second conductivity type and may have the same doping concentration as the well region 110, or a lower doping concentration than the well region 110. The pillar region 111 may also be referred to as the field relaxation region or deep well region.

[0202] The source region 112 is formed within the well region 110 and may have a first conductivity type. For example, the source region 112 can be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 can be formed by doping the drift region 107 with an even higher concentration of the impurity of the first conductivity type.

[0203] The channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a has a second conductivity type, and an inversion channel can be formed along one direction during the operation of the power semiconductor element 100-3.

[0204] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction with the source region 112 and the drift region 107. Thus, the channel region 110a does not allow charge movement under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inverting channel is formed inside it, allowing charge movement.

[0205] In some embodiments, the channel region 110a may be part of the well region 110. In this case, the channel region 110a may be formed integrally with the well region 110 so as to be continuously connected to it. The doping concentration of the second conductivity type impurity in the channel region 110a may be the same as that of the other parts of the well region 110, or may differ to adjust the threshold voltage.

[0206] In some embodiments, the well region 110, the channel region 110a, and the source region 112 can be formed symmetrically around the vertical portion 107a of the drift region 107. For example, the well region 110, the channel region 110a, and the source region 112 can be formed at both ends of the vertical portion 107a of the drift region 107, and may each include a first and second portion formed symmetrically around the vertical portion 107a. The first and second portions of such well region 110, channel region 110a, and source region 112 may be separated from each other or connected to each other.

[0207] Additionally, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, the drain region 102 can be doped to a higher concentration than the drift region 107.

[0208] In some embodiments, the drain region 102 may also be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0209] At least one trench 116 can be formed by recessing from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. The trench 116 can extend in one direction within the semiconductor layer 105. This one direction refers to the length direction of the trench 116, not the depth direction, and can refer to the III-III direction in Figure 25.

[0210] The gate insulating layer 118 can be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 can be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or the portion formed on the bottom of the trench 116 may be thicker than the portion formed on the side walls in order to reduce the electric field at the bottom of the trench 116.

[0211] For example, the gate insulating layer 118 may include or include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide.

[0212] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 so as to fill the trench 116. For example, the gate electrode layer 120 may include a suitable conductor, such as polysilicon, metal, metal nitride, metal silicide, or a laminated structure thereof.

[0213] The drift region 107 can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 can extend perpendicularly to the semiconductor layer 105 on one side of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Thus, the semiconductor layer 105 on one side of the gate electrode layer 120 can include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected along one direction.

[0214] In some embodiments, the drift region 107 can be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120. For example, the drift region 107 may include vertical portions 107a extending perpendicularly to the semiconductor layers 105 on both sides of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120 between the vertical portions 107a of the drift region 107 and the source region 112.

[0215] Such a channel region 110a can be called a lateral channel because it is formed along the side wall of the gate electrode layer 120.

[0216] The well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Furthermore, the well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120. As a result, both ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0217] The field relaxation region 111 can be formed in the semiconductor layer 105 beneath the bottom surface of the gate electrode layer 120, separated from the well region 110. More specifically, the field relaxation region 111 can be in contact with the gate insulating layer 118 beneath the bottom surface of the gate electrode layer 120 and can be formed to surround the trench 116 or the bottom surface of the gate electrode layer 120. Since no external power supply is directly applied to the field relaxation region 111, it may have a floating structure.

[0218] According to this, the well region 110 surrounds the bottom surface at both ends of the gate electrode layer 120, and the field relaxation region 111 surrounds the bottom surface at the middle part of the gate electrode layer 120. Therefore, such a structure of the well region 110 and the arrangement of the field relaxation region 110 can further alleviate the problem that an electric field concentrates on the bottom surface of the trench 116, that is, at the lower end of the gate electrode layer 120.

[0219] Thereby, in the power semiconductor device 100-3, the electric field margin applied to the gate insulating layer 118 can be increased, and the operation reliability of the power semiconductor device 100-3 can be enhanced. Further, by reducing the electric field at the bottom surface of the trench 116 and reducing the electric field applied to the gate insulating layer 118, there is room to reduce the junction resistance of the vertical portion 107a of the drift region 107.

[0220] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 can be formed not only inside the trench 116 but also extend further outside the trench 116.

[0221] In some embodiments, one or more trenches 116 can be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected and thus does not limit the scope of this embodiment.

[0222] For example, a plurality of trenches 116 can be formed side by side in the semiconductor layer 105 along one direction. The trenches 116 can extend in one direction and be arranged side by side at intervals in a direction perpendicular to one direction.

[0223] In this case, a plurality of gate electrode layers 120 can be formed on the gate insulating layer 118 so as to fill the inside of the trench 116. Thereby, the gate electrode layer 120 can be formed in the semiconductor layer 105 in a trench type and be arranged to extend side by side in one direction similar to the trench 116.

[0224] Further, the field relaxation regions 111 can be respectively disposed in contact with the gate insulating layer 118 under the bottom surface of the trench 116 or under the bottom surface of the gate electrode layer 120. In this case, the field relaxation regions 111 can be generically referred to as a plurality of island regions.

[0225] Furthermore, the well region 110 and the source region 112 can respectively extend across the gate electrode layer 120. The vertical portion 107a of the drift region 107 can be disposed in the semiconductor layer 105 between the gate electrode layers 120. The channel region 110a can be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107 on one side or both sides of the gate electrode layer 120.

[0226] The interlayer insulating layer 130 can be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 can include an appropriate insulator, such as an oxide layer, a nitride layer, or a stacked structure thereof.

[0227] The source electrode layer 140 can be formed on the interlayer insulating layer 130 and can be connected to the source region 112. For example, the source electrode layer 140 can be formed of an appropriate conductor, such as a metal.

[0228] In the above-described power semiconductor device 100-3, the first conductivity type and the second conductivity type have opposite conductivity types, but can be any one of n-type and p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type can be p-type, or vice versa.

[0229] More specifically, when the power semiconductor device 100-3 is an N-type MOSFET, the drift region 107 can be an N-region, the source region 112 and the drain region 102 can be N+ regions, and the well region 110, the field relaxation regions 111, and the channel region 110a can be P-regions.

[0230] During operation of the power semiconductor element 100-3, current can flow generally vertically from the drain region 102 along the vertical portion 107a of the drift region 107, and then through the channel region 110a along the side surface of the gate electrode layer 120 to the source region 112.

[0231] In the aforementioned power semiconductor device 100-3, the gate electrode layers 120 within the trench 116 can be densely arranged in parallel in a stripe or line type, and the channel region 110a can be arranged on the side of the gate electrode layer 120, thereby increasing the channel density.

[0232] Figures 28 and 29 are cross-sectional views showing power semiconductor element 100a-3 according to another embodiment of the present invention. Power semiconductor element 100a-3 is a modified version of some of the configurations of power semiconductor element 100-3 in Figures 24 to 27, and therefore, redundant explanations in the two embodiments are omitted.

[0233] Referring to Figures 28 and 29, the field relaxation region 111a is located below the bottom surface of the gate electrode layer 120, but is positioned away from the gate insulating layer 118 located below the bottom surface of the gate electrode layer 120. Furthermore, the field relaxation region 111a can be arranged in an island or floating structure, surrounded by the drift region 107 beneath the gate electrode layer 120.

[0234] If there are multiple trenches 116, the field relaxation regions 111a can be located in a floating or island structure below the bottom surface of the trenches 116 or below the bottom surface of the gate electrode layer 120, respectively.

[0235] The field mitigation region 111a is still located below the bottom surface of the trench 116, which helps to mitigate the concentration of the field on the gate insulating layer 118 at the bottom surface of the trench 116.

[0236] Figure 30 is a cross-sectional view showing a power semiconductor element 100b-3 according to another embodiment of the present invention. Power semiconductor element 100b-3 uses or is a modified version of power semiconductor elements 100-3 and 100a-3 shown in Figures 24 to 29, and therefore redundant explanations in the embodiments are omitted.

[0237] Referring to Figure 30, in the power semiconductor device 100b-3, the channel region 107b can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b can have a first conductivity type, and an accumulation channel can be formed inside it when the power semiconductor device 100b-3 is operating.

[0238] For example, the channel region 107b can be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b can have the same doping type as the source region 112 and the drift region 107.

[0239] In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connectable. However, in the structure of the silicon carbide semiconductor layer 105, the negative charge generated as carbon clusters form on the gate insulating layer 118 causes the band of the channel region 107b to bend upward, forming a potential barrier. As a result, a storage channel that allows the flow of charge or current can only be formed in the channel region 107b when an operating voltage is applied to the gate electrode layer 120.

[0240] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form a storage channel in channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form an inversion channel in channel region 110a in Figures 24 to 28.

[0241] In some embodiments, the channel region 107b may be part of the drift region 107. More specifically, the channel region 107b may be part of the vertical portion 107a of the drift region 107. For example, the channel region 107b can be formed integrally with the drift region 107. In this case, the drift region 107 can be connected to the source region 112 through the channel region 107b. That is, in the channel region 107b portion, the drift region 107 and the source region 112 can be in contact with each other.

[0242] The doping concentration of the impurity of the first conductivity type in the channel region 107b may be the same as that of other parts of the drift region 107 or different for adjusting the threshold voltage.

[0243] In a modification of this embodiment, the well region 110 may be formed to protrude in the direction of the vertical portion 107a of the drift region 107 from a part of the source region 112, and the channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the well region 110.

[0244] Furthermore, the well region 110 may further include a tap portion extending in the direction of the gate electrode layer 120 at the end of the protruding portion. The channel region 107b can be formed in a bent shape on the protruding portion and the tap portion of the well region 110.

[0245] Additionally, the vertical portion 107a of the drift region 107 can further extend between the lower part of the source region 112 and the well region 110. In this case, the channel region 107b can be further extended and formed between the lower part of the source region 112 and the well region 110.

[0246] Such a structure can limit the channel region 107b further between the gate electrode layer 120 and the well region 110.

[0247] With power semiconductor device 100b-3, in addition to the advantages of power semiconductor devices 100-3 and 100a-3 shown in Figures 24 to 28, an additional effect of lowering the threshold voltage can be expected.

[0248] Figure 31 is a schematic perspective view showing a power semiconductor element 100c-3 according to another embodiment of the present invention; Figure 32 is a plan view showing the power semiconductor element 100c-3 cut along the line XI-XI in Figure 31; and Figure 33 is a cross-sectional view showing the power semiconductor element 100c-3 cut along the line XX in Figure 32.

[0249] The power semiconductor element 100c-3 according to this embodiment is either the same as or a modified version of the power semiconductor element 100-3 shown in Figures 24 to 27, and therefore, redundant explanations are omitted.

[0250] Referring to Figures 31 to 33, in the power semiconductor device 100c-3, the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a may refer to the portion to which the source electrode layer 140 is connected as part of the source region 112.

[0251] The well contact region 114 can be formed within the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 through the source region 112 and have a second conductivity type. One or more well contact regions 114 can be formed within the source contact region 112a.

[0252] For example, the well contact region 114 can be doped with a higher concentration of second-conductivity impurities than the well region 110 to reduce contact resistance when connected to the source electrode layer 140. The source electrode layer 140 can be connected to both the source contact region 112a and the well contact region 114.

[0253] The source contact region 112a and the well contact region 114 can be formed on one side of the source region 112 with respect to the vertical portion 107a of the drift region 107. In a modified version of this embodiment, the source contact region 112a and the well contact region 114 may be formed on each of the source region 112 and the well region 110 if they are separated into multiple parts.

[0254] In some embodiments, the trenches 116 can be spaced apart in a single row along one direction. This allows the gate electrode layer 120 to also be spaced apart in a single row along one direction along the trenches 116. In this case, the well region 110, source region 112, source contact region 112a, and well contact region 114 can be formed in the semiconductor layer 105 between the trenches 116 spaced apart in a single row along one direction, respectively.

[0255] For example, the power semiconductor element 100c-3 can also be formed by arranging multiple power semiconductor element 100-3 structures shown in Figures 24 to 27 along one direction, with a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 placed between them.

[0256] For example, if the power semiconductor element 100-3 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

[0257] In the power semiconductor device 100c-3, by placing the source contact region 112a and the well contact region 114 outside the gate electrode layer 120 instead of between them, the gate electrode layer 120 can be arranged very densely. As a result, the channel density of the power semiconductor device 100a-3 can be significantly increased.

[0258] On the other hand, the structure of power semiconductor element 100c-3 can also be applied to power semiconductor elements 100a-3 in Figures 28 and 29 and power semiconductor element 100b-3 in Figure 30. That is, multiple power semiconductor elements 100a-3 or power semiconductor elements 100b-3 can be arranged in a row, with well regions 110, source regions 112, source contact regions 112a, and well contact regions 114 arranged between them.

[0259] Figure 34 is a cross-sectional view showing a power semiconductor element 100d-3 according to yet another embodiment of the present invention. The power semiconductor element 100d-3 is a modified version of some of the configurations of the power semiconductor element 100c-3 shown in Figures 31 to 33, and therefore, redundant explanations in the embodiments are omitted.

[0260] Referring to Figure 34, the power semiconductor element 100d-3 may include at least one groove 138 formed within the source contact region 112a of the source region 112, penetrating the source region 112 and recessed into the well region 110. At least the bottom surface of the groove 138 may have a well contact region 114a formed to contact the well region 110.

[0261] The source electrode layer 140a is formed to fill the groove 138 and can be connected to the well contact region 114a, the well region 110, and / or the source region 112. Such a structure can help to increase the contact area between the source electrode layer 140a and the well region 110, and between the source electrode layer 140a and the source region 112, thereby reducing the contact resistance between them.

[0262] In some embodiments, the well contact region 114a can be formed entirely on the surface of the well region 110 exposed by the groove 138. Thus, the well contact region 114a can be formed on the well region 110 exposed from the bottom and side walls of the groove 138. Such a structure of the well contact region 114a can further reduce the contact resistance between the source electrode layer 140a and the well region 110.

[0263] On the other hand, in this embodiment, the field relaxation region 111 is positioned in contact with the gate insulating layer 118, but it may be modified to be separated from the gate insulating layer 118, as shown in Figures 28 and 29.

[0264] Figures 35 to 37 are schematic perspective views showing a method for manufacturing a power semiconductor device 100-3 according to one embodiment of the present invention. Referring to Figure 35, a drift region 107 having a first conductivity type can be formed on a silicon carbide (SiC) semiconductor layer 105. For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 is provided as a substrate of the first conductivity type, and the drift region 107 can be formed on such a substrate as one or more epitaxial layers.

[0265] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the step of forming the well region 110 can be carried out by injecting an impurity of the second conductivity type into the semiconductor layer 105. The well region 110 can be formed substantially to a predetermined depth from the surface of the semiconductor layer 105.

[0266] For example, the well region 110 can be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a in which at least a portion is surrounded by the well region 110. More specifically, the well region 110 can be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107.

[0267] Before or after the formation of the well region 110, a field relaxation region 111 having a second conductivity type can be formed at a predetermined depth in the semiconductor layer 105, separated from the well region 110. For example, the field relaxation region 111 can be formed by implanting an impurity of the second conductivity type into the semiconductor layer 105.

[0268] Next, a source region 112 having a first conductivity type can be formed within the well region 110. For example, the step of forming the source region 112 can be carried out by injecting an impurity of the first conductivity type into the well region 110. The source region 112 can be formed substantially from the surface of the semiconductor layer 105 to a predetermined depth within the well region 110.

[0269] Along with the formation of the source region 112, a channel region 110a can be formed in the semiconductor layer 105 between the source region 112 and the drift region 107, where an inversion channel is formed along one direction. The channel region 110a can be formed between the source region 112 and the vertical portion 107a of the drift region 107. For example, the channel region 110a may be part of the well region 110 and can be formed by implanting a second conductivity type impurity into the semiconductor layer 105.

[0270] In a modified version of this embodiment, the doping order of impurities in the well region 110, source region 112, channel region 110a, and field relaxation region 111 may be arbitrarily changed.

[0271] In the manufacturing method described above, impurity implantation or impurity doping can be performed by ion implanting impurities into the semiconductor layer 105 or by introducing impurities during the formation of the epitaxial layer. However, for impurity implantation in selective regions, an ion implantation method using a mask pattern can be used. Selectively, after ion implantation, a heat treatment step may follow to activate or diffuse the impurities.

[0272] Referring to Figure 36, at least one trench 116 can be formed such that it is recessed from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. For example, the trench 116 can extend in one direction across the drift region 107 and be formed shallower than the well region 110.

[0273] Furthermore, at least one trench 116 can include multiple trenches 116, for example, trenches 116 can be formed simultaneously in the semiconductor layer 105 in a unidirectional arrangement. The trenches 116 can further restrict the channel region 110a.

[0274] For example, the trench 116 can be formed by creating a photomask using photolithography, and then etching the semiconductor layer 105 using such a photomask as an etching protective film.

[0275] Referring to Figure 37, a gate insulating layer 118 can be formed on the bottom and inner wall of the trench 116. For example, the gate insulating layer 118 can be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or nitride onto the semiconductor layer 105.

[0276] Next, a gate electrode layer 120 can be formed on the gate insulating layer 118 to fill the trench 116. For example, the gate electrode layer 120 can be formed by patterning a conductive layer after it has been formed on the gate insulating layer 118. The gate electrode layer 120 can be formed by doping polysilicon with impurities, or by including a conductive metal or metal silicide.

[0277] The patterning process can be carried out using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photographic process and a developing process, and the etching process may include selectively etching the underlying structure using such a photoresist pattern.

[0278] As a result, the well region 110 is positioned deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 on one or both sides of the gate electrode layer 120 between the drift region 107 and the source region 112. In addition, the field relaxation region 111 can be positioned in contact with the gate insulating layer 118 below the bottom surface of the gate electrode layer 120.

[0279] Next, an interlayer insulating layer 130 can be formed on the gate electrode layer 120. Next, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by first forming a conductive layer, such as a metal layer, on the interlayer insulating layer 130 and then patterning it.

[0280] On the other hand, the power semiconductor device 100b-3 in Figure 30 can be manufactured by adding or modifying some steps in the manufacturing process of the power semiconductor device 100-3 described above. For example, the channel region 107b can be formed as part of the drift region 107 to form a storage channel.

[0281] The power semiconductor device 100c-3 shown in Figures 31 to 33 can be manufactured by adding or modifying some steps in the manufacturing process of the power semiconductor device 100-3 described above.

[0282] For example, during the manufacturing of the power semiconductor device 100c-3, the step of forming the source region 112 may include the step of forming a source contact region 112a connected to the source electrode layer 140, at least outside one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may be part of the source region 112.

[0283] Furthermore, a well contact region 114 can be formed within the source contact region 112a before forming the trench 116. For example, the well contact region 114 can be formed by injecting a second conductivity type impurity into a portion of the well region 110 at a higher concentration than in the well region 110.

[0284] During the manufacturing of the power semiconductor device 100c-3, the trenches 116 can be spaced apart in a single line in one direction. Furthermore, the well region 110, the channel region 110a, and the source region 112 can be formed in the semiconductor layer 105 between the trenches 116, respectively.

[0285] The manufacturing of the power semiconductor device 100d-3 in Figure 34 may include the additional step of forming at least one groove 138 in the source region 112 so as to penetrate the source region 112 and recess into the well region 110, forming a well contact region 114 on the bottom surface of the groove 138 so as to contact the well region 110, and forming a source electrode layer 140 so as to fill the groove 138 and connect the source region 112 and the well contact region 114.

[0286] According to the manufacturing method described above, a power semiconductor element 100-3 can be economically manufactured using a silicon carbide semiconductor layer 105 and processes used for existing silicon substrates.

[0287] Figure 38 is a schematic perspective view showing a power semiconductor element 100-4 according to one embodiment of the present invention; Figure 39 is a plan view showing the power semiconductor element 100-4 cut along the line II-II in Figure 38; Figure 40 is a cross-sectional view showing the power semiconductor element 100-4 cut along the line III-III in Figure 39; and Figure 41 is a cross-sectional view showing the power semiconductor element cut along the line IV-IV in Figure 39.

[0288] Referring to Figures 38 to 41, the power semiconductor device 100-4 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-4 may have a power MOSFET structure.

[0289] The semiconductor layer 105 can refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 can refer to one or multiple epitaxial layers on a semiconductor substrate.

[0290] For example, the semiconductor layer 105 can be composed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one silicon carbide epitaxial layer.

[0291] Because silicon carbide (SiC) has a wider bandgap than silicon, it can maintain stability even at higher temperatures. Furthermore, because silicon carbide has a much higher dielectric breakdown field than silicon, it can operate stably even at high voltages. Therefore, the power semiconductor element 100-4 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage while also exhibiting superior heat dissipation characteristics and stable operating characteristics even at high temperatures, compared to the case using silicon.

[0292] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and can be formed by implanting an impurity of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 can be formed by doping an epitaxial layer of silicon carbide with an impurity of the first conductivity type.

[0293] The well region 110 is formed in the semiconductor layer 105 in contact with the drift region 107 and may have a second conductivity type. For example, the well region 110 can be formed by doping the drift region 107 with an impurity of a second conductivity type opposite to the first conductivity type.

[0294] For example, the well region 110 can be formed to surround at least a portion of the drift region 107. Thus, the drift region 107 can include a vertical portion 107a that is at least partially surrounded by the well region 110. During the operation of the power semiconductor element 100-4, the vertical portion 107a can provide a vertical path for charge movement.

[0295] Figure 38 shows that the well region 110 is formed so as to be separated into two regions, with the vertical portion 107a confined between them, but it can be modified in various other ways. For example, the vertical portion 107a may have a shape in which its sides are surrounded by the well region 110.

[0296] The source region 112 is formed within the well region 110 and may have a first conductivity type. For example, the source region 112 can be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 can be formed by doping the drift region 107 with an even higher concentration of the impurity of the first conductivity type.

[0297] The channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a has a second conductivity type, and an inversion channel can be formed along one direction during the operation of the power semiconductor element 100-4.

[0298] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction with the source region 112 and the drift region 107. Thus, the channel region 110a does not allow charge movement under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inverting channel is formed inside it, allowing charge movement.

[0299] In some embodiments, the channel region 110a may be part of the well region 110. In this case, the channel region 110a may be formed integrally with the well region 110 so as to be continuously connected to it. The doping concentration of the second conductivity type impurity in the channel region 110a may be the same as that of the other parts of the well region 110, or may differ to adjust the threshold voltage.

[0300] In some embodiments, the well region 110, the channel region 110a, and the source region 112 can be formed symmetrically around the vertical portion 107a of the drift region 107. For example, the well region 110, the channel region 110a, and the source region 112 can be formed at both ends of the vertical portion 107a of the drift region 107, and may each include a first and second portion formed symmetrically around the vertical portion 107a. The first and second portions of such well region 110, channel region 110a, and source region 112 may be separated from each other or connected to each other.

[0301] Additionally, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, the drain region 102 can be doped to a higher concentration than the drift region 107.

[0302] In some embodiments, the drain region 102 may also be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0303] At least one trench 116 can be formed by recessing from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. The trench 116 can extend in one direction within the semiconductor layer 105. This one direction refers to the length direction of the trench 116, rather than the depth direction, and can refer to the III-III line or IV-IV line direction in Figure 39.

[0304] The gate insulating layer 118 can be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 can be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or the portion formed on the bottom of the trench 116 may be thicker than the portion formed on the side walls in order to reduce the electric field at the bottom of the trench 116.

[0305] For example, the gate insulating layer 118 may include or include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide.

[0306] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 so as to fill the trench 116. For example, the gate electrode layer 120 may include a suitable conductor, such as polysilicon, metal, metal nitride, metal silicide, or a laminated structure thereof.

[0307] The drift region 107 can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 can extend perpendicularly to the semiconductor layer 105 on one side of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Thus, the semiconductor layer 105 on one side of the gate electrode layer 120 can include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected along one direction.

[0308] In some embodiments, the drift region 107 can be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120. For example, the drift region 107 may include vertical portions 107a extending perpendicularly to the semiconductor layers 105 on both sides of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120 between the vertical portions 107a of the drift region 107 and the source region 112.

[0309] Such a channel region 110a can be called a lateral channel because it is formed along the side wall of the gate electrode layer 120.

[0310] The well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Furthermore, the well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120. As a result, both ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0311] Such a well 110 structure can further mitigate the problem of electric field concentration at the bottom of the trench 116, i.e., at the lower end of the gate electrode layer 120. Furthermore, by placing the deep well region 111 below the well region 110, it is possible to further reduce the electric field at the bottom of the trench 116, as well as the electric field applied to the gate insulating layer 118. This increases the electric field margin applied to the gate insulating layer 118 in the power semiconductor device 100-4, thereby improving the operational reliability of the power semiconductor device 100-4. Moreover, by reducing the electric field at the bottom of the trench 116 and the electric field applied to the gate insulating layer 118, there is room to reduce the junction resistance of the vertical portion 107a of the drift region 107.

[0312] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed not only inside the trench 116 but also to extend further outside the trench 116.

[0313] In some embodiments, one or more trenches 116 may be provided within the semiconductor layer 105. The number of trenches 116 may be appropriately selected and thus do not limit the scope of this embodiment.

[0314] For example, multiple trenches 116 can be formed in the semiconductor layer 105 along one direction. The trenches 116 can extend in one direction and be spaced apart in a direction perpendicular to that direction.

[0315] In this case, multiple gate electrode layers 120 can be formed on the gate insulating layer 118 so as to fill the inside of the trench 116. Thus, the gate electrode layers 120 can be formed in a trench type within the semiconductor layer 105 and arranged to extend in a unidirectional manner, similar to the trench 116.

[0316] Furthermore, the well region 110 and the source region 112 can extend across the gate electrode layer 120, respectively. The vertical portion 107a of the drift region 107 can be located in the semiconductor layer 105 between the gate electrode layers 120. The channel region 110a can be formed on one or both sides of the gate electrode layer 120 in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107.

[0317] In some embodiments, the well region 110 can be formed in the semiconductor layer 105 deeper than the gate electrode layer 120, so as to be in contact with the vertical portion 107a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120.

[0318] The interlayer insulating layer 130 can be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an appropriate insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof.

[0319] The source electrode layer 140 is formed on the interlayer insulating layer 130 and can be connected to the source region 112. For example, the source electrode layer 140 can be formed from an appropriate conductive material, metal, or the like.

[0320] Furthermore, the source electrode layer 140 can come into contact with a portion of the drift region 107 to form a Schottky barrier diode (SBD). A Schottky barrier diode (SBD) refers to a diode that uses a Schottky barrier formed by a junction between a metal and a semiconductor.

[0321] In addition to the Schottky barrier diode (SBD) described above, a body diode can be parasitically formed on the power semiconductor element 100-4. For example, a body diode can be formed between the well region 110 and the drift region 107. Such a body diode may be one of the PN diodes formed by joining semiconductors with opposite polarities.

[0322] As shown in Figure 48, Schottky barrier diodes (SBDs) have a lower forward voltage (VF) and faster switching characteristics compared to PN diodes.

[0323] Such Schottky barrier diodes (SBDs), together with body diodes, can reduce switching losses in the operation of power semiconductor device 100-4. For example, the Schottky barrier diode (SBD) and body diode can function as a free-wheeling diode in the operation of power semiconductor device 100-4.

[0324] In some embodiments, the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a may refer to a region of the semiconductor layer 105 to which the source electrode layer 140 is connected.

[0325] For example, the source contact region 112a may include a portion of the source region 112 outside at least one end of the gate electrode layer 120, a portion of the well region 110, and a protruding portion 107c of the drift region 107 exposed from the well region 110.

[0326] The well contact region 114 is formed on a portion of the well region 110 within the source contact region 112a and may have a second conductivity type. For example, one or more well contact regions 114 may be formed within the source contact region 112a. Furthermore, the well contact region 114 may be formed with a higher concentration of impurities of the second conductivity type than the well region 110 in order to reduce contact resistance when connected to the source electrode layer 140.

[0327] The source electrode layer 140 can be connected to the source contact region 112a and can be commonly connected to the source region 112, the well contact region 114, and the protruding portion 107c of the drift region 107.

[0328] In some embodiments, the trenches 116 can be spaced apart in a single row along one direction. This allows the gate electrode layer 120 to also be spaced apart in a single row along one direction along the trenches 116. In this case, the well region 110, source region 112, source contact region 112a, Schottky barrier diode (SBD), and well contact region 114 can be formed in the semiconductor layer 105 between the trenches 116 spaced apart in a single row along one direction, respectively.

[0329] In the power semiconductor device 100-4 described above, the first conductivity type and the second conductivity type are opposite to each other, but each may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0330] More specifically, if the power semiconductor element 100-4 is an N-type MOSFET, the drift region 107 may be an N- region, the source region 112 and drain region 102 may be N+ regions, the well region 110 and channel region 110a may be P- regions, and the well contact region 114 may be a P+ region.

[0331] During operation of the power semiconductor element 100-4, current can flow generally vertically from the drain region 102 along the vertical portion 107a of the drift region 107, and then through the channel region 110a along the side surface of the gate electrode layer 120 to the source region 112.

[0332] In the aforementioned power semiconductor device 100-4, the gate electrode layers 120 within the trench 116 can be densely arranged in parallel in a stripe or line type, and the channel region 110a can be placed on the side of the gate electrode layer 120, thereby increasing the channel density.

[0333] Furthermore, according to the aforementioned power semiconductor device 100-4, by placing the source contact region 112a and well contact region 114 outside the gate electrode layer 120 instead of between them, the gate electrode layer 120 can be arranged very densely. As a result, the channel density of the power semiconductor device 100-4 can be further increased.

[0334] Figures 42 and 43 are cross-sectional views showing a power semiconductor element 100a-4 according to another embodiment of the present invention. The power semiconductor element 100a-4 according to this embodiment is a modified version of some of the configurations of the power semiconductor element 100-4 in Figures 38 to 41, and therefore, redundant explanations in the two embodiments are omitted.

[0335] Referring to Figures 42 and 43, the power semiconductor elements 100a-4 may include at least one groove 138 formed by etching a portion of the drift region 107, for example, a protruding portion 107c, a portion of the source region 112, and a portion of the well region 110. For example, in the power semiconductor elements 100-4 shown in Figures 38-41, the groove 138 can be formed by etching the source contact region 112a.

[0336] The well contact region 114a can be formed on a portion of the well region 110 exposed from the groove 138. For example, the well contact region 114a can be formed on a portion of the well region 110 at the bottom of the groove 138. The well contact region 114a has a second conductivity type and can be doped to a higher concentration than the well region 110.

[0337] The source electrode layer 140a is formed to fill the groove 138 and can make common contact with the well contact region 114a, the protruding portion 107c of the drift region 107, and the source region 112 within the groove 138. The contact between the source electrode layer 140a and the protruding portion 107c of the drift region 107 can form a Schottky barrier diode (SBD).

[0338] Such a structure can help increase the contact area between the source electrode layer 140a and the source region 112 and well contact region 114a, thereby reducing the contact resistance between them.

[0339] In some embodiments, the well contact region 114a can be formed entirely on the surface of the well region 110 exposed by the groove 138. Thus, the well contact region 114a can be formed on the well region 110 exposed from the bottom and side walls of the groove 138. Such a structure of the well contact region 114a can further reduce the contact resistance between the source electrode layer 140a and the well region 110.

[0340] Figure 44 is a schematic cross-sectional view showing a power semiconductor element 100b-4 according to another embodiment of the present invention. The power semiconductor element 100b-4 according to this embodiment is a modified version of some of the configurations of the power semiconductor element 100-4 in Figures 38 to 41, and therefore, redundant explanations in the two embodiments are omitted.

[0341] Referring to Figure 44, the power semiconductor element 100b-4 may include a channel region 107b that forms a storage channel instead of the channel region 110a of the power semiconductor 100-4 in Figures 38-41.

[0342] In power semiconductor devices 100a-4, the channel region 107b can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b can have a first conductivity type, and an accumulation channel can be formed inside it when the power semiconductor device 100b-4 is in operation.

[0343] For example, the channel region 107b can be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b can have the same doping type as the source region 112 and the drift region 107.

[0344] In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connectable. However, in the structure of the silicon carbide semiconductor layer 105, the negative charge generated as carbon clusters form on the gate insulating layer 118 causes the band of the channel region 107b to bend upward, forming a potential barrier. As a result, a storage channel that allows the flow of charge or current can only be formed in the channel region 107b when an operating voltage is applied to the gate electrode layer 120.

[0345] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form a storage channel in channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form an inversion channel in channel region 110a in Figures 38 to 41.

[0346] In some embodiments, the channel region 107b may be part of the drift region 107. More specifically, the channel region 107b may be part of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be formed integrally with the drift region 107. In this case, the drift region 107 may be connected to the source region 112 via the channel region 107b. That is, in the channel region 107b portion, the drift region 107 and the source region 112 may be in contact with each other.

[0347] The doping concentration of the first conductivity type impurity in the channel region 107b may be the same as that of the rest of the drift region 107, or it may be different to adjust the threshold voltage.

[0348] In a modified version of this embodiment, the well region 110 is formed protruding from a portion of the source region 112 in the direction of the vertical portion 107a of the drift region 107, and the channel region 107b may also be formed in the semiconductor layer 105 on the protruding portion of the well region 110.

[0349] Furthermore, the well region 110 may further include a tapped portion extending toward the gate electrode layer 120 at the end of the protruding portion. The channel region 107b may be formed in a refractive shape on the protruding portion and the tapped portion of the well region 110.

[0350] Additionally, the vertical portion 107a of the drift region 107 can extend further between the lower part of the source region 112 and the well region 110. In this case, the channel region 107b can be formed by extending further between the lower part of the source region 112 and the well region 110.

[0351] Such a structure can be made so that the channel region 107b is further confined between the gate electrode layer 120 and the well region 110. In addition to the advantages of power semiconductor device 100-4 shown in Figures 38 to 41, power semiconductor device 100-4 can also be expected to have the effect of lowering the threshold voltage.

[0352] Figures 45 to 47 are schematic perspective views showing a method for manufacturing a power semiconductor device 100-4 according to one embodiment of the present invention. Referring to Figure 45, a drift region 107 having a first conductivity type can be formed on a silicon carbide (SiC) semiconductor layer 105. For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 is provided as a substrate of the first conductivity type, and the drift region 107 can be formed on such a substrate as one or more epitaxial layers.

[0353] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the step of forming the well region 110 can be performed by implanting an impurity of the second conductivity type into the semiconductor layer 105.

[0354] For example, the well region 110 can be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a in which at least a portion is surrounded by the well region 11. More specifically, the well region 110 can be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107.

[0355] Next, a source region 112 having a first conductivity type can be formed within the well region 110. For example, the step of forming the source region 112 can be performed by injecting an impurity of the first conductivity type into the well region 110.

[0356] Along with the formation of the source region 112, a channel region 110a can be formed in the semiconductor layer 105 between the source region 112 and the drift region 107, where an inversion channel is formed along one direction. The channel region 110a can be formed between the source region 112 and the vertical portion 107a of the drift region 107. For example, the channel region 110a may be part of the well region 110 and can be formed by implanting a second conductivity type impurity into the semiconductor layer 105.

[0357] Furthermore, when forming the source region 112, a source contact region 112a can be formed outside at least one end of the gate electrode layer 120, including a portion of the source region 112, a portion of the well region 110, and a protruding portion 107c of the drift region 107 exposed from the well region 110.

[0358] Furthermore, a well contact region 114 having a second conductivity type and doped at a higher concentration than the well region 110 can be formed on a portion of the well region 110. For example, the well contact region 114 can be formed by injecting an impurity of the second conductivity type into a portion of the well region 110 at a higher concentration than that of the well region 110.

[0359] In the steps described above, impurity implantation or impurity doping can be performed by ion implanting impurities into the semiconductor layer 105 or by introducing impurities during the formation of the epitaxial layer. However, for impurity implantation in selective regions, an ion implantation method using a mask pattern can be used. Selectively, after ion implantation, a heat treatment step may follow to activate or diffuse the impurities.

[0360] Referring to Figure 46, at least one trench 116 can be formed such that it is recessed from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. For example, the trench 116 can extend in one direction across the drift region 107 and be formed shallower than the well region 110.

[0361] Furthermore, at least one trench 116 can include multiple trenches 116, for example, trenches 116 can be formed simultaneously in the semiconductor layer 105 in a unidirectional arrangement. The trenches 116 can further restrict the channel region 110a.

[0362] For example, the trench 116 can be formed by creating a photomask using photolithography, and then etching the semiconductor layer 105 using such a photomask as an etching protective film.

[0363] In some embodiments, the trenches 116 can be spaced apart in a single line in one direction. Furthermore, the well region 110, the channel region 110a, and the source region 112 can be formed in the semiconductor layer 105 between the trenches 116, respectively.

[0364] Referring to Figure 47, a gate insulating layer 118 can be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 can be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or nitride onto the semiconductor layer 105.

[0365] Next, a gate electrode layer 120 can be formed on the gate insulating layer 118 to fill the trench 116. For example, the gate electrode layer 120 can be formed by patterning a conductive layer after it has been formed on the gate insulating layer 118. The gate electrode layer 120 can be formed by doping polysilicon with impurities, or by including a conductive metal or metal silicide.

[0366] The patterning process can be carried out using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photographic process and a developing process, and the etching process may include selectively etching the underlying structure using such a photoresist pattern.

[0367] As a result, the well region 110 is positioned deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 on one or both sides of the gate electrode layer 120 between the drift region 107 and the source region 112.

[0368] Next, an interlayer insulating layer 130 can be formed on the gate electrode layer 120. Next, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by first forming a conductive layer, such as a metal layer, on the interlayer insulating layer 130 and then patterning it.

[0369] For example, the source electrode layer 140 can be connected to the source region 112 and in contact with a portion of the drift region 107 to form a Schottky barrier diode (SBD). In some embodiments, the source electrode layer 140 can be connected to the source contact region 112 and in common contact with the source region 112, the well contact region 114, and the protruding portion 107c of the drift region 107.

[0370] The power semiconductor devices 100a-4 shown in Figures 42 and 43 can be manufactured by adding or modifying some steps to the manufacturing steps of the power semiconductor device 100-4 described above. For example, the manufacturing steps of the power semiconductor device 100a-4 can be modified by etching a portion of the drift region 107, for example, a protruding portion 107a of the drift region 107, a portion of the source region 112, and a portion of the well region 110 to form at least one groove 138, forming a well contact region 114a on a portion of the well region 110 at the bottom of the groove 138, and filling the groove 138 to form a source electrode layer 140 that is connected to the source region 112, the protruding portion 107c of the drift region 107, and the well contact region 114.

[0371] On the other hand, the power semiconductor device 100b-4 in Figure 44 can be manufactured by adding or modifying some steps to the manufacturing process of the power semiconductor device 100-4 described above. For example, the channel region 107b can be formed as part of the drift region 107 to form a storage channel.

[0372] According to the manufacturing method described above, a power semiconductor element 100-4 can be economically manufactured using a silicon carbide semiconductor layer 105 and processes used for existing silicon substrates.

[0373] Figure 49 is a schematic perspective view showing a power semiconductor element 100-5 according to one embodiment of the present invention, Figure 50 is a plan view showing the power semiconductor element 100-5 cut along the line II-II in Figure 49, and Figure 51 is a cross-sectional view showing the power semiconductor element 100-5 cut along the line III-III in Figure 50.

[0374] Referring to Figures 49 to 51, the power semiconductor device 100-5 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-5 may have a power MOSFET structure.

[0375] The semiconductor layer 105 can refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 can refer to one or multiple epitaxial layers on a semiconductor substrate.

[0376] For example, the semiconductor layer 105 can be composed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one silicon carbide epitaxial layer.

[0377] Because silicon carbide (SiC) has a wider bandgap than silicon, it can maintain stability even at higher temperatures. Furthermore, because silicon carbide has a much higher dielectric breakdown field than silicon, it can operate stably even at high voltages. Therefore, the power semiconductor element 100-5 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage while also exhibiting superior heat dissipation characteristics and stable operating characteristics even at high temperatures, compared to the case using silicon.

[0378] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and can be formed by implanting an impurity of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 can be formed by doping an epitaxial layer of silicon carbide with an impurity of the first conductivity type.

[0379] The well region 110 is formed in the semiconductor layer 105 in contact with the drift region 107 and may have a second conductivity type. For example, the well region 110 can be formed by doping the drift region 107 with an impurity of a second conductivity type opposite to the first conductivity type.

[0380] For example, the well region 110 can be formed to surround at least a portion of the drift region 107. Thus, the drift region 107 can include a vertical portion 107a that is at least partially surrounded by the well region 110. During operation of the power semiconductor element 100-5, the vertical portion 107a can provide a vertical path for charge movement.

[0381] Figure 49 shows that the well region 110 is formed so as to be separated into two regions, with the vertical portion 107a confined between them, but it can be modified in various other ways. For example, the vertical portion 107a may have a shape in which its sides are surrounded by the well region 110.

[0382] The deep well region 111 can be formed below the well region 110, in contact with the well region 110 and the drift region 107. The deep well region 111 can have a second conductivity type, similar to the well region 110. The doping concentration of the second conductivity type impurity in the deep well region 111 may be the same as or less than the doping concentration of the second conductivity type impurity in the well region 110.

[0383] For example, the deep well region 111 can be formed to have a width narrower than the width of the well region 110 with respect to one direction. In Figure 50, this direction can refer to the direction of the line III-III. Furthermore, both ends of the deep well region 111 can be positioned by moving them inward from both ends of the well region 110 with respect to one direction.

[0384] As a result, the deep well region 111 can be positioned below the well region 110, receding inward from both ends of the well region 110 and in contact with the well region 110. The sides and bottom surface of the deep well region 111 can be in contact with the drift region 107.

[0385] For example, if the deep well region 111 is formed to separate two regions along the well region 110, the separation distance between the two deep well regions 111 may be greater than the isolation distance between the two well regions 110.

[0386] The source region 112 is formed within the well region 110 and may have a first conductivity type. For example, the source region 112 can be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 can be formed by doping the drift region 107 with an even higher concentration of the impurity of the first conductivity type.

[0387] The channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a has a second conductivity type, and an inversion channel can be formed along one direction during the operation of the power semiconductor element 100-5.

[0388] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction with the source region 112 and the drift region 107. Thus, the channel region 110a does not allow charge movement under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inverting channel is formed inside it, allowing charge movement.

[0389] In some embodiments, the channel region 110a may be part of the well region 110. In this case, the channel region 110a may be formed integrally with the well region 110 so as to be continuously connected to it. The doping concentration of the second conductivity type impurity in the channel region 110a may be the same as that of the other parts of the well region 110, or may differ to adjust the threshold voltage.

[0390] In some embodiments, the well region 110, the deep well region 111, the channel region 110a, and the source region 112 can be formed symmetrically around the vertical portion 107a of the drift region 107. For example, the well region 110, the deep well region 111, the channel region 110a, and the source region 112 can be formed at both ends of the vertical portion 107a of the drift region 107, and may each include a first and second portion formed symmetrically around the vertical portion 107a. The first and second portions of such well region 110, deep well region 111, channel region 110a, and source region 112 may be separated from each other or connected to each other.

[0391] Additionally, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, the drain region 102 can be doped to a higher concentration than the drift region 107.

[0392] In some embodiments, the drain region 102 may also be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0393] At least one trench 116 can be formed by recessing from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. The trench 116 can extend in one direction within the semiconductor layer 105. This one direction refers to the length direction of the trench 116, not the depth direction, and can refer to the III-III direction in Figure 50.

[0394] The gate insulating layer 118 can be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 can be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or the portion formed on the bottom of the trench 116 may be thicker than the portion formed on the side walls in order to reduce the electric field at the bottom of the trench 116.

[0395] For example, the gate insulating layer 118 may include or include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide.

[0396] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 so as to fill the trench 116. For example, the gate electrode layer 120 may include a suitable conductor, such as polysilicon, metal, metal nitride, metal silicide, or a laminated structure thereof.

[0397] The drift region 107 can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 can extend perpendicularly to the semiconductor layer 105 on one side of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Thus, the semiconductor layer 105 on one side of the gate electrode layer 120 can include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected along one direction.

[0398] In some embodiments, the drift region 107 can be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120. For example, the drift region 107 may include vertical portions 107a extending perpendicularly to the semiconductor layers 105 on both sides of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120 between the vertical portions 107a of the drift region 107 and the source region 112.

[0399] Such a channel region 110a can be called a lateral channel because it is formed along the side wall of the gate electrode layer 120.

[0400] The well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Furthermore, the well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120. As a result, both ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0401] Such a well 110 structure can further mitigate the problem of electric field concentration at the bottom of the trench 116, i.e., at the lower end of the gate electrode layer 120. Furthermore, by placing the deep well region 111 below the well region 110, it is possible to further reduce the electric field at the bottom of the trench 116, as well as reduce the electric field applied to the gate insulating layer 118. This increases the electric field margin applied to the gate insulating layer 118 in the power semiconductor device 100-5, thereby improving the operational reliability of the power semiconductor device 100-5. Moreover, by reducing the electric field at the bottom of the trench 116 and the electric field applied to the gate insulating layer 118, there is room to reduce the junction resistance of the vertical portion 107a of the drift region 107.

[0402] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed not only inside the trench 116 but also to extend further outside the trench 116.

[0403] In some embodiments, one or more trenches 116 may be provided within the semiconductor layer 105. The number of trenches 116 may be appropriately selected and thus do not limit the scope of this embodiment.

[0404] For example, multiple trenches 116 can be formed in the semiconductor layer 105 along one direction. The trenches 116 can extend in one direction and be spaced apart in a direction perpendicular to that direction.

[0405] In this case, multiple gate electrode layers 120 can be formed on the gate insulating layer 118 so as to fill the inside of the trench 116. Thus, the gate electrode layers 120 can be formed in a trench type within the semiconductor layer 105 and arranged to extend in a unidirectional manner, similar to the trench 116.

[0406] Furthermore, the well region 110 and the source region 112 can extend across the gate electrode layer 120, respectively. The vertical portion 107a of the drift region 107 can be located in the semiconductor layer 105 between the gate electrode layers 120. The channel region 110a can be formed on one or both sides of the gate electrode layer 120 in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107.

[0407] In some embodiments, the well region 110 can be formed in the semiconductor layer 105 deeper than the gate electrode layer 120, so as to be in contact with the vertical portion 107a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120.

[0408] The interlayer insulating layer 130 can be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an appropriate insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof.

[0409] The source electrode layer 140 is formed on the interlayer insulating layer 130 and can be connected to the source region 112. For example, the source electrode layer 140 can be formed from an appropriate conductive material, metal, or the like.

[0410] In the power semiconductor device 100-5 described above, the first conductivity type and the second conductivity type are opposite to each other, but each may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type may be p-type, and vice versa.

[0411] More specifically, if the power semiconductor element 100-5 is an N-type MOSFET, the drift region 107 may be an N- region, the source region 112 and drain region 102 may be N+ regions, and the well region 110, deep well region 111, and channel region 110a may be P- regions.

[0412] During operation of the power semiconductor element 100-5, current can flow generally vertically from the drain region 102 along the vertical portion 107a of the drift region 107, and then through the channel region 110a along the side surface of the gate electrode layer 120 to the source region 112.

[0413] In the aforementioned power semiconductor device 100-5, the gate electrode layer 120 within the trench 116 can be densely arranged in parallel in a stripe or line type, and the channel region 110a can be arranged on the side of the gate electrode layer 120, thereby increasing the channel density.

[0414] Figure 52 is a cross-sectional view showing a power semiconductor element 100a-5 according to another embodiment of the present invention. The power semiconductor element 100a-5 according to this embodiment uses or is a modified version of the power semiconductor element 100-5 shown in Figures 49 to 51, and therefore, redundant explanations are omitted.

[0415] Referring to Figure 52, in power semiconductor devices 100a-5, the channel region 107b can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b can have a first conductivity type, and an accumulation channel can be formed inside it when the power semiconductor device 100-5 is in operation.

[0416] For example, the channel region 107b can be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b can have the same doping type as the source region 112 and the drift region 107.

[0417] In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connectable. However, in the structure of the silicon carbide semiconductor layer 105, the negative charge generated as carbon clusters form on the gate insulating layer 118 causes the band of the channel region 107b to bend upward, forming a potential barrier. As a result, a storage channel that allows the flow of charge or current can only be formed in the channel region 107b when an operating voltage is applied to the gate electrode layer 120.

[0418] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form a storage channel in the channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form an inversion channel in the channel region 110a shown in Figures 49 to 51.

[0419] In some embodiments, the channel region 107b may be part of the drift region 107. More specifically, the channel region 107b may be part of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be formed integrally with the drift region 107. In this case, the drift region 107 may be connected to the source region 112 via the channel region 107b. That is, in the channel region 107b portion, the drift region 107 and the source region 112 may be in contact with each other.

[0420] The doping concentration of the first conductivity type impurity in the channel region 107b may be the same as that of the rest of the drift region 107, or it may be different to adjust the threshold voltage.

[0421] In a modified version of this embodiment, the well region 110 is formed protruding from a portion of the source region 112 in the direction of the vertical portion 107a of the drift region 107, and the channel region 107b may also be formed in the semiconductor layer 105 on the protruding portion of the well region 110.

[0422] Furthermore, the well region 110 may further include a tapped portion extending toward the gate electrode layer 120 at the end of the protruding portion. The channel region 107b may be formed in a refractive shape on the protruding portion and the tapped portion of the well region 110.

[0423] Additionally, the vertical portion 107a of the drift region 107 can extend further between the lower part of the source region 112 and the well region 110. In this case, the channel region 107b can be formed by extending further between the lower part of the source region 112 and the well region 110.

[0424] Such a structure can be made so that the channel region 107b is further confined between the gate electrode layer 120 and the well region 110.

[0425] With power semiconductor device 100a-5, in addition to the advantages of power semiconductor device 100-5 shown in Figures 49 to 51, an additional effect of lowering the threshold voltage can be expected.

[0426] Figure 53 is a schematic perspective view showing a power semiconductor element 100b-5 according to another embodiment of the present invention; Figure 54 is a plan view showing the power semiconductor element 100b-5 cut along the line VI-VI in Figure 53; Figure 55 is a cross-sectional view showing the power semiconductor element 100b-5 cut along the line VII-VII in Figure 54; and Figure 56 is a cross-sectional view showing the power semiconductor element 100b-5 cut along the line VIII-VIII in Figure 54.

[0427] The power semiconductor element 100b-5 according to this embodiment is either the same as or a modified version of the power semiconductor element 100-5 shown in Figures 49 to 51, and therefore, redundant explanations are omitted.

[0428] Referring to Figures 53 to 56, in the power semiconductor devices 100b-5, the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a may refer to the portion to which the source electrode layer 140 is connected as part of the source region 112.

[0429] The well contact region 114 can be formed within the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 through the source region 112 and have a second conductivity type. One or more well contact regions 114 can be formed within the source contact region 112a.

[0430] For example, the well contact region 114 can be doped with a higher concentration of second-conductivity impurities than the well region 110 to reduce contact resistance when connected to the source electrode layer 140.

[0431] The source electrode layer 140 can be connected in common to the source contact region 112a and the well contact region 114.

[0432] Figures 53 to 56 show that the source contact region 112a and the well contact region 114 are formed on one side of the source region 112 with respect to the vertical portion 107a of the drift region 107. However, if the source region 112 and the well region 110 are separated into multiple parts, the source contact region 112a and the well contact region 114 may be formed on each of them.

[0433] In some embodiments, the trenches 116 can be spaced apart in a single row along one direction. This allows the gate electrode layer 120 to also be spaced apart in a single row along one direction along the trenches 116. In this case, the well region 110, source region 112, source contact region 112a, and well contact region 114 can be formed in the semiconductor layer 105 between the trenches 116 spaced apart in a single row along one direction, respectively.

[0434] For example, the power semiconductor element 100b-5 can also be formed by arranging multiple power semiconductor element 100-5 structures shown in Figures 49 to 51 along one direction, with a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 placed between them.

[0435] For example, if the power semiconductor element 100-5 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

[0436] In power semiconductor devices 100b-5, by placing the source contact region 112a and well contact region 114 outside the gate electrode layer 120 instead of between them, the gate electrode layer 120 can be arranged very densely. As a result, the channel density of power semiconductor devices 100a-5 can be significantly increased.

[0437] Figures 57 and 58 are cross-sectional views showing power semiconductor elements 100c-5 and 100d-5 according to yet another embodiment of the present invention. Referring to Figure 57, the power semiconductor element 100c-5 may include at least one groove 138 formed within the source contact region 112a of the source region 112, penetrating the source region 112 and recessed into the well region 110. At least the bottom surface of the groove 138 may have a well contact region 114a formed to contact the well region 110.

[0438] The source electrode layer 140a is formed to fill the groove 138 and can be connected to the well contact region 114a, the well region 110, and / or the source region 112. Such a structure can help to increase the contact area between the source electrode layer 140a and the well region 110, and between the source electrode layer 140a and the source region 112, thereby reducing the contact resistance between them.

[0439] In some embodiments, the well contact region 114a can be formed entirely on the surface of the well region 110 exposed by the groove 138. Thus, the well contact region 114a can be formed on the well region 110 exposed from the bottom and side walls of the groove 138. Such a structure of the well contact region 114a can further reduce the contact resistance between the source electrode layer 140a and the well region 110.

[0440] Referring to Figure 58, the power semiconductor device 100d-5 may include a channel region 107b that forms a storage channel instead of the channel region 110a of the power semiconductor devices 100b-5 in Figures 53-56. The structure of the power semiconductor device 100d-5 including such a channel region 107b can be seen in the description in Figure 52.

[0441] Therefore, the power semiconductor element 100d-5 can correspond to a structure in which multiple power semiconductor elements 100a-5 shown in Figure 52 are linked together, with a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 arranged between them.

[0442] Figures 59 to 61 are schematic perspective views showing a method for manufacturing a power semiconductor device 100-5 according to one embodiment of the present invention. Referring to Figure 59, a drift region 107 having a first conductivity type can be formed on a silicon carbide (SiC) semiconductor layer 105. For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 is provided as a substrate of the first conductivity type, and the drift region 107 can be formed on such a substrate as one or more epitaxial layers.

[0443] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the step of forming the well region 110 can be performed by implanting an impurity of the second conductivity type into the semiconductor layer 105.

[0444] For example, the well region 110 can be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a in which at least a portion is surrounded by the well region 11. More specifically, the well region 110 can be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107.

[0445] Next, a deep well region 111 having a second conductivity type can be formed below the well region 110, in contact with the well region 110 and the drift region 107. The deep well region 111 can be formed by injecting impurities of the same second conductivity type as the well region 110. The well region 110 and the deep well region 111 may be formed in any order.

[0446] Next, a source region 112 having a first conductivity type can be formed within the well region 110. For example, the step of forming the source region 112 can be performed by injecting an impurity of the first conductivity type into the well region 110.

[0447] Along with the formation of the source region 112, a channel region 110a can be formed in the semiconductor layer 105 between the source region 112 and the drift region 107, where an inversion channel is formed along one direction. The channel region 110a can be formed between the source region 112 and the vertical portion 107a of the drift region 107. For example, the channel region 110a may be part of the well region 110 and can be formed by implanting a second conductivity type impurity into the semiconductor layer 105.

[0448] In the manufacturing method described above, impurity implantation or impurity doping can be performed by ion implanting impurities into the semiconductor layer 105 or by introducing impurities during the formation of the epitaxial layer. However, for impurity implantation in selective regions, an ion implantation method using a mask pattern can be used. Selectively, after ion implantation, a heat treatment step may follow to activate or diffuse the impurities.

[0449] Referring to Figure 60, at least one trench 116 can be formed such that it is recessed from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. For example, the trench 116 can extend in one direction across the drift region 107 and be formed shallower than the well region 110.

[0450] Furthermore, at least one trench 116 can include multiple trenches 116, for example, trenches 116 can be formed simultaneously in the semiconductor layer 105 in a unidirectional arrangement. The trenches 116 can further restrict the channel region 110a.

[0451] For example, the trench 116 can be formed by creating a photomask using photolithography, and then etching the semiconductor layer 105 using such a photomask as an etching protective film.

[0452] Referring to Figure 61, a gate insulating layer 118 can be formed on the bottom and inner wall of the trench 116. For example, the gate insulating layer 118 can be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or nitride onto the semiconductor layer 105.

[0453] Next, a gate electrode layer 120 can be formed on the gate insulating layer 118 to fill the trench 116. For example, the gate electrode layer 120 can be formed by patterning a conductive layer after it has been formed on the gate insulating layer 118. The gate electrode layer 120 can be formed by doping polysilicon with impurities, or by including a conductive metal or metal silicide.

[0454] The patterning process can be carried out using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photographic process and a developing process, and the etching process may include selectively etching the underlying structure using such a photoresist pattern.

[0455] As a result, the well region 110 is positioned deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 on one or both sides of the gate electrode layer 120 between the drift region 107 and the source region 112.

[0456] Next, an interlayer insulating layer 130 can be formed on the gate electrode layer 120. Then, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by forming a conductive layer, such as a metal layer, on the interlayer insulating layer 130 and then patterning it.

[0457] On the other hand, the power semiconductor devices 100a-5 in Figure 52 can be manufactured by adding or modifying some steps to the manufacturing process of the power semiconductor device 100-5 described above. For example, the channel region 107b can be formed as part of the drift region 107 to form a storage channel.

[0458] The power semiconductor devices 100b-5 shown in Figures 53 to 56 can be manufactured by adding or modifying some steps in the manufacturing process of the power semiconductor device 100-5 described above.

[0459] For example, during the manufacturing of the power semiconductor device 100b-5, the step of forming the source region 112 may include the step of forming a source contact region 112a connected to the source electrode layer 140, at least outside one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may be part of the source region 112.

[0460] Furthermore, a well contact region 114 can be formed within the source contact region 112a before forming the trench 116. For example, the well contact region 114 can be formed by injecting a second conductivity type impurity into a portion of the well region 110 at a higher concentration than in the well region 110.

[0461] During the manufacturing of the power semiconductor elements 100b-5, the trenches 116 can be spaced apart in a single line in one direction. Furthermore, the well region 110, the channel region 110a, and the source region 112 can be formed in the semiconductor layer 105 between the trenches 116, respectively.

[0462] The manufacturing of the power semiconductor device 100c-5 in Figure 57 may include the additional step of forming at least one groove 138 in the source region 112 so as to penetrate the source region 112 and recess into the well region 110, forming a well contact region 114 on the bottom surface of the groove 138 so as to contact the well region 110, and forming a source electrode layer 140 so as to fill the groove 138 and connect the source region 112 and the well contact region 114.

[0463] According to the manufacturing method described above, power semiconductor elements 100-5 can be economically manufactured using a silicon carbide semiconductor layer 105 and processes used for existing silicon substrates.

[0464] Figure 62 is a schematic perspective view showing a power semiconductor element 100-6 according to one embodiment of the present invention, Figure 63 is a plan view showing the power semiconductor element 100-6 cut along the line II-II in Figure 62, and Figure 64 is a cross-sectional view showing the power semiconductor element 100-6 cut along the line III-III in Figure 63.

[0465] Referring to Figures 62 to 64, the power semiconductor device 100-6 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-6 may have a power MOSFET structure.

[0466] The semiconductor layer 105 can refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 can refer to one or multiple epitaxial layers on a semiconductor substrate.

[0467] For example, the semiconductor layer 105 can be composed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one silicon carbide epitaxial layer.

[0468] Because silicon carbide (SiC) has a wider bandgap than silicon, it can maintain stability even at higher temperatures. Furthermore, because silicon carbide has a much higher dielectric breakdown field than silicon, it can operate stably even at high voltages. Therefore, the power semiconductor device 100-6 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage while also exhibiting superior heat dissipation characteristics and stable operating characteristics even at high temperatures, compared to the case using silicon.

[0469] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and can be formed by implanting an impurity of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 can be formed by doping an epitaxial layer of silicon carbide with an impurity of the first conductivity type.

[0470] The well region 110 is formed in the semiconductor layer 105 in contact with the drift region 107 and may have a second conductivity type. For example, the well region 110 can be formed by doping the drift region 107 with an impurity of a second conductivity type opposite to the first conductivity type.

[0471] For example, the well region 110 can be formed to surround at least a portion of the drift region 107. Thus, the drift region 107 can include a vertical portion 107a that is at least partially surrounded by the well region 110. During the operation of the power semiconductor element 100-6, the vertical portion 107a can provide a vertical charge transfer path.

[0472] Figure 62 shows that the well region 110 is formed so as to be separated into two regions, with the vertical portion 107a confined between them, but it can be modified in various other ways. For example, the vertical portion 107a may have a shape in which its sides are surrounded by the well region 110.

[0473] The source region 112 is formed within the well region 110 and may have a first conductivity type. For example, the source region 112 can be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 can be formed by doping the drift region 107 with an even higher concentration of the impurity of the first conductivity type.

[0474] The channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a has a second conductivity type, and an inversion channel can be formed along one direction during the operation of the power semiconductor element 100-6. This one direction can refer to the III-III line direction in Figure 63.

[0475] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction with the source region 112 and the drift region 107. Thus, the channel region 110a does not allow charge movement under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inverting channel is formed inside it, allowing charge movement.

[0476] In some embodiments, the channel region 110a may be part of the well region 110. In this case, the channel region 110a may be formed integrally with the well region 110 so as to be continuously connected to it. The doping concentration of the second conductivity type impurity in the channel region 110a may be the same as that of the other parts of the well region 110, or may differ to adjust the threshold voltage.

[0477] In some embodiments, the well region 110, the channel region 110a, and the source region 112 can be formed symmetrically around the vertical portion 107a of the drift region 107. For example, the well region 110, the channel region 110a, and the source region 112 can be formed at both ends of the vertical portion 107a of the drift region 107, and may each include a first and second portion formed symmetrically around the vertical portion 107a. The first and second portions of such well region 110, channel region 110a, and source region 112 may be separated from each other or connected to each other.

[0478] Additionally, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, the drain region 102 can be doped to a higher concentration than the drift region 107.

[0479] In some embodiments, the drain region 102 may also be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0480] At least one trench 116 can be formed by recessing from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. The trench 116 can extend in one direction within the semiconductor layer 105. This one direction refers to the length direction of the trench 116, not the depth direction, and can refer to the III-III direction in Figure 63.

[0481] The gate insulating layer 118 can be formed on the bottom and inner wall of the trench 116. For example, the gate insulating layer 118 may include a first portion 118a formed to a first thickness from the bottom of the trench 116 and a second portion 118b formed to a second thickness on the inner wall of the trench 116.

[0482] For example, the first portion 118a can be formed in such a way that it partially fills the trench 116 from the bottom of the trench 116 with a first thickness. The second portion 118b can be formed substantially on the first portion 118a and can be formed on the side wall of the trench 116 without filling the trench 116. Thus, the second thickness of the second portion 118b may be less than the first thickness of the first portion 118a. For example, the first thickness may be between 1 / 5 and 1 / 2 of the depth of the trench 116, and the second thickness may be in the range of 1 / 5 to 1 / 30 of the first thickness.

[0483] For example, the gate insulating layer 118 may include or include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide.

[0484] In this way, by forming the first portion 118a of the gate insulating layer 118 thicker than the second portion 118b at the bottom of the trench 116, it is possible to mitigate the concentration of the electric field at the bottom of the trench 116 when the power semiconductor element 100-6 is operating.

[0485] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 so as to fill the trench 116. For example, the gate electrode layer 120 may include a suitable conductor, such as polysilicon, metal, metal nitride, metal silicide, or a laminated structure thereof.

[0486] The drift region 107 can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 can extend perpendicularly to the semiconductor layer 105 on one side of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Thus, the semiconductor layer 105 on one side of the gate electrode layer 120 can include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected along one direction.

[0487] In some embodiments, the drift region 107 can be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120. For example, the drift region 107 may include vertical portions 107a extending perpendicularly to the semiconductor layers 105 on both sides of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120 between the vertical portions 107a of the drift region 107 and the source region 112.

[0488] Such a channel region 110a can be called a lateral channel because it is formed along the side wall of the gate electrode layer 120.

[0489] The well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Furthermore, the well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120. As a result, both ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0490] Such a well 110 structure can further mitigate the problem of electric field concentration at the bottom of the trench 116, i.e., at the lower end of the gate electrode layer 120. Therefore, with the power semiconductor element 100-6, there is no need to form an additional deep well, and by forming the well region 110 deeper than the gate electrode layer 120, the problem of electric field concentration at the bottom of the trench 116 can be mitigated. In conventional vertical channel structures, there was a problem in that the junction resistance and threshold voltage increased when the distance between the deep well and the trench narrowed, but this can be solved with the power semiconductor element 100-6 of this embodiment.

[0491] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed not only inside the trench 116 but also to extend further outside the trench 116.

[0492] In some embodiments, one or more trenches 116 may be provided within the semiconductor layer 105. The number of trenches 116 may be appropriately selected and thus do not limit the scope of this embodiment.

[0493] For example, multiple trenches 116 can be formed in the semiconductor layer 105 along one direction. The trenches 116 can extend in one direction and be spaced apart in a direction perpendicular to that direction.

[0494] In this case, multiple gate electrode layers 120 can be formed on the gate insulating layer 118 so as to fill the inside of the trench 116. Thus, the gate electrode layers 120 can be formed in a trench type within the semiconductor layer 105 and arranged to extend in a unidirectional manner, similar to the trench 116.

[0495] Furthermore, the well region 110 and the source region 112 can extend across the gate electrode layer 120, respectively. The vertical portion 107a of the drift region 107 can be located in the semiconductor layer 105 between the gate electrode layers 120. The channel region 110a can be formed on one or both sides of the gate electrode layer 120 in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107.

[0496] In some embodiments, the well region 110 can be formed in the semiconductor layer 105 deeper than the gate electrode layer 120, so as to be in contact with the vertical portion 107a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120.

[0497] The interlayer insulating layer 130 can be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an appropriate insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof.

[0498] The source electrode layer 140 is formed on the interlayer insulating layer 130 and can be connected to the source region 112. For example, the source electrode layer 140 can be formed from an appropriate conductive material, metal, or the like.

[0499] In the power semiconductor device 100-6 described above, the first conductivity type and the second conductivity type are opposite to each other, but each may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0500] More specifically, if the power semiconductor element 100-6 is an N-type MOSFET, the drift region 107 may be an N- region, the source region 112 and drain region 102 may be N+ regions, and the well region 110 and channel region 110a may be P- regions.

[0501] During operation of the power semiconductor element 100-6, current can flow generally vertically from the drain region 102 along the vertical portion 107a of the drift region 107, and then through the channel region 110a along the side surface of the gate electrode layer 120 to the source region 112.

[0502] In the aforementioned power semiconductor device 100-6, the gate electrode layer 120 can be densely arranged in parallel in a stripe or line type, and the channel region 110a can be arranged on the side of the gate electrode layer 120, thereby increasing the channel density.

[0503] Furthermore, in the power semiconductor element 100-6, the thickness of the gate insulating layer 118 is increased at the bottom of the trench 116, and the bottom surface of the gate electrode layer 120 is surrounded by the well region 110. This mitigates the phenomenon of breakdown caused by electric field concentration at the corners of the trench 116. As a result, the breakdown characteristics of the power semiconductor element 100-6 are improved, and the operational reliability is enhanced.

[0504] Figure 65 is a cross-sectional view showing a power semiconductor element 100a-6 according to another embodiment of the present invention. The power semiconductor element 100a-6 according to this embodiment uses or is a modified version of the power semiconductor element 100-6 shown in Figures 62 to 64, and therefore, redundant explanations are omitted.

[0505] Referring to Figure 65, in power semiconductor devices 100a-6, the channel region 107b can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b can have a first conductivity type, and an accumulation channel can be formed inside it when the power semiconductor device 100-6 is in operation.

[0506] For example, the channel region 107b can be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b can have the same doping type as the source region 112 and the drift region 107.

[0507] In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connectable. However, in the structure of the silicon carbide semiconductor layer 105, the negative charge generated as carbon clusters form on the gate insulating layer 118 causes the band of the channel region 107b to bend upward, forming a potential barrier. As a result, a storage channel that allows the flow of charge or current can only be formed in the channel region 107b when an operating voltage is applied to the gate electrode layer 120.

[0508] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form a storage channel in the channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form an inversion channel in the channel region 110a shown in Figures 62 to 64.

[0509] In some embodiments, the channel region 107b may be part of the drift region 107. More specifically, the channel region 107b may be part of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be formed integrally with the drift region 107. In this case, the drift region 107 may be connected to the source region 112 via the channel region 107b. That is, in the channel region 107b portion, the drift region 107 and the source region 112 may be in contact with each other.

[0510] The doping concentration of the first conductivity type impurity in the channel region 107b may be the same as that of the rest of the drift region 107, or it may be different to adjust the threshold voltage.

[0511] In a modified version of this embodiment, the well region 110 is formed protruding from a portion of the source region 112 in the direction of the vertical portion 107a of the drift region 107, and the channel region 107b may also be formed in the semiconductor layer 105 on the protruding portion of the well region 110.

[0512] Furthermore, the well region 110 may further include a tapped portion extending toward the gate electrode layer 120 at the end of the protruding portion. The channel region 107b may be formed in a refractive shape on the protruding portion and the tapped portion of the well region 110.

[0513] Additionally, the vertical portion 107a of the drift region 107 can extend further between the lower part of the source region 112 and the well region 110. In this case, the channel region 107b can be formed by extending further between the lower part of the source region 112 and the well region 110.

[0514] Such a structure can be made so that the channel region 107b is further confined between the gate electrode layer 120 and the well region 110.

[0515] With power semiconductor device 100a-6, in addition to the advantages of power semiconductor device 100-6 shown in Figures 62 to 64, an additional effect of lowering the threshold voltage can be expected.

[0516] Figure 66 is a schematic perspective view showing a power semiconductor element 100b-6 according to another embodiment of the present invention; Figure 67 is a plan view showing the power semiconductor element 100b-6 cut along the line VI-VI in Figure 66; Figure 68 is a cross-sectional view showing the power semiconductor element 100b-6 cut along the line VII-VII in Figure 67; and Figure 69 is a cross-sectional view showing the power semiconductor element 100b-6 cut along the line VIII-VIII in Figure 67.

[0517] The power semiconductor element 100b-6 according to this embodiment is either the same as or a modified version of the power semiconductor element 100-6 shown in Figures 62 to 64, and therefore, redundant explanations are omitted.

[0518] Referring to Figures 66 to 69, in power semiconductor devices 100b-6, the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a may refer to the portion to which the source electrode layer 140 is connected as part of the source region 112.

[0519] The well contact region 114 can be formed within the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 through the source region 112 and have a second conductivity type. One or more well contact regions 114 can be formed within the source contact region 112a.

[0520] For example, the well contact region 114 can be doped with a higher concentration of second-conductivity impurities than the well region 110 to reduce contact resistance when connected to the source electrode layer 140. The source electrode layer 140 can be connected to both the source contact region 112a and the well contact region 114.

[0521] Figures 66 to 69 show that the source contact region 112a and the well contact region 114 are formed on one side of the source region 112 with respect to the vertical portion 107a of the drift region 107. However, if the source region 112 and the well region 110 are separated into multiple parts, the source contact region 112a and the well contact region 114 may be formed on each of them.

[0522] In some embodiments, the trenches 116 can be spaced apart in a single row along one direction. This allows the gate electrode layer 120 to also be spaced apart in a single row along one direction along the trenches 116. In this case, the well region 110, source region 112, source contact region 112a, and well contact region 114 can be formed in the semiconductor layer 105 between the trenches 116 spaced apart in a single row along one direction, respectively.

[0523] For example, power semiconductor elements 100b-6 can also be formed by arranging multiple power semiconductor elements 100-6 structures shown in Figures 62-64 along one direction, with well regions 110, source regions 112, source contact regions 112a, and well contact regions 114 placed between them.

[0524] For example, if the power semiconductor element 100-6 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

[0525] In power semiconductor devices 100b-6, by placing the source contact region 112a and well contact region 114 outside the gate electrode layer 120 instead of between them, the gate electrode layer 120 can be arranged very densely. As a result, the channel density of power semiconductor devices 100a-6 can be significantly increased.

[0526] Figures 70 and 71 are cross-sectional views showing power semiconductor elements 100c-6 and 100d-6 according to yet another embodiment of the present invention. Referring to Figure 70, the power semiconductor element 100c-6 may include at least one groove 138 formed within the source contact region 112a of the source region 112, penetrating the source region 112 and recessed into the well region 110. At least the bottom surface of the groove 138 may have a well contact region 114a formed to contact the well region 110.

[0527] The source electrode layer 140a is formed to fill the groove 138 and can be connected to the well contact region 114a, the well region 110, and / or the source region 112. Such a structure can help to increase the contact area between the source electrode layer 140a and the well region 110, and between the source electrode layer 140a and the source region 112, thereby reducing the contact resistance between them.

[0528] In some embodiments, the well contact region 114a can be formed entirely on the surface of the well region 110 exposed by the groove 138. Thus, the well contact region 114a can be formed on the well region 110 exposed from the bottom and side walls of the groove 138. Such a structure of the well contact region 114a can further reduce the contact resistance between the source electrode layer 140a and the well region 110.

[0529] Referring to Figure 71, the power semiconductor device 100d-6 may include a channel region 107b that forms a storage channel instead of the channel region 110a of the power semiconductor devices 100b-6 in Figures 66-69. The structure of the power semiconductor device 100d-6 including such a channel region 107b can be seen in the description in Figure 65.

[0530] Therefore, the power semiconductor element 100d-6 can correspond to a structure in which multiple power semiconductor elements 100a-6 shown in Figure 65 are linked together, with a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 arranged between them.

[0531] Figures 72 to 74 are schematic perspective views showing a method for manufacturing a power semiconductor device 100-6 according to one embodiment of the present invention. Referring to Figure 72, a drift region 107 having a first conductivity type can be formed on a silicon carbide (SiC) semiconductor layer 105. For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 is provided as a substrate of the first conductivity type, and the drift region 107 can be formed on such a substrate as one or more epitaxial layers.

[0532] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the step of forming the well region 110 can be performed by implanting an impurity of the second conductivity type into the semiconductor layer 105.

[0533] For example, the well region 110 can be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a in which at least a portion is surrounded by the well region 11. More specifically, the well region 110 can be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107.

[0534] Next, a source region 112 having a first conductivity type can be formed within the well region 110. For example, the step of forming the source region 112 can be performed by injecting an impurity of the first conductivity type into the well region 110.

[0535] Along with the formation of the source region 112, a channel region 110a can be formed in the semiconductor layer 105 between the source region 112 and the drift region 107, where an inversion channel is formed along one direction. The channel region 110a can be formed between the source region 112 and the vertical portion 107a of the drift region 107. For example, the channel region 110a may be part of the well region 110 and can be formed by implanting a second conductivity type impurity into the semiconductor layer 105.

[0536] In the manufacturing method described above, impurity implantation or impurity doping can be performed by ion implanting impurities into the semiconductor layer 105 or by introducing impurities during the formation of the epitaxial layer. However, for impurity implantation in selective regions, an ion implantation method using a mask pattern can be used. Selectively, after ion implantation, a heat treatment step may follow to activate or diffuse the impurities.

[0537] Referring to Figure 73, at least one trench 116 can be formed such that it is recessed from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. For example, the trench 116 can extend in one direction across the drift region 107 and be formed shallower than the well region 110.

[0538] Furthermore, at least one trench 116 can include multiple trenches 116, for example, trenches 116 can be formed simultaneously in the semiconductor layer 105 in a unidirectional arrangement. The trenches 116 can further restrict the channel region 110a.

[0539] For example, the trench 116 can be formed by creating a photomask using photolithography, and then etching the semiconductor layer 105 using such a photomask as an etching protective film.

[0540] Referring to Figure 74, a gate insulating layer 118 can be formed on the bottom and inner wall of the trench 116. For example, the step of forming the gate insulating layer 118 may include forming a first portion 118a with a first thickness from the bottom of the trench 116, and forming a second portion 118b with a second thickness on the inner wall of the trench 116.

[0541] For example, the gate insulating layer 118 can be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or nitride onto the semiconductor layer 105. In some embodiments, the first portion 118a can be formed by depositing an insulating material, and the second portion 118b can be formed by oxidizing the semiconductor layer 105 or by depositing an insulating material.

[0542] Next, a gate electrode layer 120 can be formed on the gate insulating layer 118 to fill the trench 116. For example, the gate electrode layer 120 can be formed by patterning a conductive layer after it has been formed on the gate insulating layer 118. The gate electrode layer 120 can be formed by doping polysilicon with impurities, or by including a conductive metal or metal silicide.

[0543] The patterning process can be carried out using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photographic process and a developing process, and the etching process may include selectively etching the underlying structure using such a photoresist pattern.

[0544] As a result, the well region 110 is positioned deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 on one or both sides of the gate electrode layer 120 between the drift region 107 and the source region 112.

[0545] Next, an interlayer insulating layer 130 can be formed on the gate electrode layer 120. Next, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by first forming a conductive layer, such as a metal layer, on the interlayer insulating layer 130 and then patterning it.

[0546] On the other hand, the power semiconductor devices 100a-6 in Figure 65 can be manufactured by adding or modifying some steps in the manufacturing process of the power semiconductor device 100-6 described above. For example, the channel region 107b can be formed as part of the drift region 107 to form a storage channel.

[0547] The power semiconductor devices 100b-6 shown in Figures 66 to 69 can be manufactured by adding or modifying some steps in the manufacturing process of the power semiconductor device 100-6 described above.

[0548] For example, during the manufacturing of the power semiconductor device 100b-6, the step of forming the source region 112 may include the step of forming a source contact region 112a connected to the source electrode layer 140, at least outside one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may be part of the source region 112.

[0549] Furthermore, a well contact region 114 can be formed within the source contact region 112a before forming the trench 116. For example, the well contact region 114 can be formed by injecting a second conductivity type impurity into a portion of the well region 110 at a higher concentration than in the well region 110.

[0550] During the manufacturing of power semiconductor devices 100b-6, the trenches 116 can be spaced apart in a single line in one direction. Furthermore, the well region 110, the channel region 110a, and the source region 112 can be formed in the semiconductor layer 105 between the trenches 116, respectively.

[0551] The manufacturing of the power semiconductor device 100c-6 in Figure 70 may include the additional step of forming at least one groove 138 in the source region 112 so as to penetrate the source region 112 and recess into the well region 110, forming a well contact region 114 on the bottom surface of the groove 138 so as to contact the well region 110, and forming a source electrode layer 140 so as to fill the groove 138 and connect the source region 112 and the well contact region 114.

[0552] According to the manufacturing method described above, power semiconductor elements 100-6 can be economically manufactured using a silicon carbide semiconductor layer 105 and processes used for existing silicon substrates.

[0553] Figure 75 is a schematic perspective view showing a power semiconductor element 100-7 according to one embodiment of the present invention; Figure 76 is a plan view showing the power semiconductor element 100-7 cut along the line II-II in Figure 75; Figure 77 is a cross-sectional view showing the power semiconductor element 100-7 cut along the line III-III in Figure 76; and Figure 78 is a cross-sectional view showing the power semiconductor element 100-7 cut along the line IV-IV in Figure 76.

[0554] Referring to Figures 75 to 78, the power semiconductor device 100-7 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-7 may have a power MOSFET structure.

[0555] The semiconductor layer 105 can refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 can refer to one or multiple epitaxial layers on a semiconductor substrate.

[0556] For example, the semiconductor layer 105 can be composed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one silicon carbide epitaxial layer.

[0557] Because silicon carbide (SiC) has a wider bandgap than silicon, it can maintain stability even at higher temperatures. Furthermore, because silicon carbide has a much higher dielectric breakdown field than silicon, it can operate stably even at high voltages. Therefore, the power semiconductor device 100-7 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage while also exhibiting superior heat dissipation characteristics and stable operating characteristics even at high temperatures, compared to the case using silicon.

[0558] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and can be formed by implanting an impurity of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 can be formed by doping an epitaxial layer of silicon carbide with an impurity of the first conductivity type.

[0559] The well region 110 is formed in the semiconductor layer 105 so as to be in contact with at least a portion of the drift region 107 and may have a second conductivity type. For example, the well region 110 can be formed by doping the drift region 107 with an impurity of a second conductivity type opposite to the first conductivity type.

[0560] For example, the well region 110 can be formed to surround at least a portion of the drift region 107. More specifically, the well region 110 may include a vertical portion 107a extending perpendicularly to one side of the semiconductor layer 105 of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 can be at least partially surrounded and limited by the well region 110. During the operation of the power semiconductor element 100-7, the vertical portion 107a can provide a vertical charge transfer path.

[0561] Figure 75 shows that the well region 110 is formed so as to be separated into two regions, with the vertical portion 107a confined between them, but it can be modified in various other ways. For example, the vertical portion 107a may have a shape in which its sides are surrounded by the well region 110.

[0562] The source region 112 is formed within the well region 110 and may have a first conductivity type. For example, the source region 112 can be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 can be formed by doping the drift region 107 with an even higher concentration of the impurity of the first conductivity type.

[0563] The channel region 107b can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the second channel region 107b may have a first conductivity type, and an accumulation channel can be formed inside it when the power semiconductor element 100-7 is in operation.

[0564] For example, the channel region 107b can be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b can have the same doping type as the source region 112 and the drift region 107.

[0565] In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connectable. However, in the structure of the silicon carbide semiconductor layer 105, the negative charge generated as carbon clusters form on the gate insulating layer 118 causes the band of the channel region 107b to bend upward, forming a potential barrier. As a result, when an operating voltage is applied to the gate electrode layer 120, a storage channel that allows the flow of charge or current can be formed in the channel region 107b.

[0566] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form a storage channel in the channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form a normal inverting channel.

[0567] In some embodiments, the channel region 107b may be part of the drift region 107. More specifically, the channel region 107b may be part of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be formed integrally with the drift region 107.

[0568] In this case, the drift region 107 can be connected to the source region 112 via the channel region 107b. That is, in the channel region 107b portion, the drift region 107 and the source region 112 can be in contact with each other.

[0569] For example, the doping concentration of the first conductivity type impurity in the channel region 107b may be the same as that of the rest of the drift region 107, or it may be different to adjust the threshold voltage.

[0570] In some embodiments, the well region 110, the channel region 107b, and the source region 112 can be formed symmetrically around the vertical portion 107a of the drift region 107. The well region 110, the channel region 107b, and the source region 112 can be formed on the semiconductor layers 105 on either side of the vertical portion 107a, and may each include a first and second portion formed symmetrically around the vertical portion 107a. The first and second portions of such well region 110, channel region 107b, and source region 112 may be separated from each other or connected to each other.

[0571] Additionally, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, the drain region 102 can be doped to a higher concentration than the drift region 107.

[0572] In some embodiments, the drain region 102 may also be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0573] At least one trench 116 can be formed by recessing from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. The trench 116 can extend in one direction within the semiconductor layer 105. This one direction refers to the length direction of the trench 116, not the depth direction, and can refer to the III-III line or IV-IV line direction in Figure 76.

[0574] The gate insulating layer 118 can be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 may include or include a laminated structure of insulators such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, and aluminum oxide. The thickness of the gate insulating layer 118 may be uniform, or the portion formed on the bottom of the trench 116 may be thicker than the portion formed on the side walls in order to reduce the electric field at the bottom of the trench 116.

[0575] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 so as to fill the trench 116. For example, the gate electrode layer 120 may include a suitable conductor, such as polysilicon, metal, metal nitride, metal silicide, or a laminated structure thereof.

[0576] The drift region 107 can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 can extend perpendicularly to the semiconductor layer 105 on one side of the gate electrode layer 120.

[0577] In some embodiments, the drift region 107 can be formed in the semiconductor layer 105 on both sides of the gate electrode layer 120. For example, the drift region 107 may include vertical portions 107a extending perpendicularly to the semiconductor layer 105 on both sides of the gate electrode layer 120.

[0578] The well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Furthermore, the well region 110 can be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120. As a result, both ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0579] Such a structure can mitigate the problem of electric field concentration at the bottom of the trench 116, i.e., at the lower end of the gate electrode layer 120. Therefore, according to the power semiconductor element 100-7 of this embodiment, there is no need to form an additional deep well, and by forming the well region 110 deeper than the gate electrode layer 120, the problem of electric field concentration at the bottom of the trench 116 can be mitigated. In conventional vertical channel structures, there was a problem in that the junction resistance and threshold voltage increased when the distance between the deep well and the trench narrowed, but this can be solved in the power semiconductor element 100-7 of this embodiment.

[0580] The channel region 107b can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Thus, the semiconductor layer 105 on one side of the gate electrode layer 120 can include a structure in which the source region 112, the channel region 107b, and the vertical portion 107a of the drift region 107 are connected along one direction.

[0581] Such a channel region 107b can be referred to as a lateral channel structure, as it is formed along the side wall of the gate electrode layer 120.

[0582] Furthermore, the channel region 107b can also be formed in the semiconductor layers 105 on both sides of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. In such embodiments, the channel region 107b may be a part of the vertical portion 107a of the drift region 107.

[0583] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed not only inside the trench 116 but also to extend further outside the trench 116.

[0584] In some embodiments, one or more trenches 116 may be provided within the semiconductor layer 105. The number of trenches 116 may be appropriately selected and thus do not limit the scope of this embodiment.

[0585] For example, multiple trenches 116 can be formed in the semiconductor layer 105 along one direction. The trenches 116 can extend in one direction and be spaced apart in a direction perpendicular to that direction.

[0586] In this case, multiple gate electrode layers 120 can be formed on the gate insulating layer 118 so as to fill the inside of the trench 116. Thus, the gate electrode layers 120 can be formed in a trench type within the semiconductor layer 105 and arranged to extend in a unidirectional manner, similar to the trench 116.

[0587] Furthermore, the gate insulating layer 118 and the gate electrode layer 120 can extend further outside the trench 116 and be formed broadly across the trench 116 on the semiconductor layer 105.

[0588] Furthermore, the well region 110 can extend across the gate electrode layer 120. The vertical portion 107a of the drift region 107 can be located in the semiconductor layer 105 between the gate electrode layers 120. The channel region 107b can be formed on one or both sides of the gate electrode layer 120 in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107.

[0589] In some embodiments, the source region 112 may be connected across the gate electrode layer 120 while surrounding the edge of the gate electrode layer 120. In some embodiments, the well region 110 may be formed in the semiconductor layer 105 deeper than the gate electrode layer 120, adjoining the vertical portion 107a of the drift region 107 and surrounding the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120.

[0590] The interlayer insulating layer 130 can be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an appropriate insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof.

[0591] The source electrode layer 140 is formed on the interlayer insulating layer 130 and can be connected to the source region 112. For example, the source electrode layer 140 can be formed from an appropriate conductive material, metal, or the like.

[0592] In the power semiconductor device 100-7 described above, the first conductivity type and the second conductivity type are opposite to each other, but each may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type may be p-type, and vice versa.

[0593] More specifically, if the power semiconductor element 100-7 is an N-type MOSFET, the drift region 107 and the channel region 107b may be N-regions, the source region 112 and the drain region 102 may be N+ regions, and the well region 110 may be a P-region.

[0594] During operation of the power semiconductor element 100-7, current can flow generally vertically from the drain region 102 along the vertical portion 107a of the drift region 107, and then through the channel region 107b along the side surface of the gate electrode layer 120 to the source region 112.

[0595] In the aforementioned power semiconductor device 100-7, the gate electrode layer 120 can be densely arranged in parallel in a stripe type, and the channel region 110a can be placed on the side surface of the gate electrode layer 120, thereby increasing the channel density.

[0596] Furthermore, in the power semiconductor element 100-7, since the bottom surface of the gate electrode layer 120 is surrounded by the well region 110, the phenomenon of breakdown occurring due to electric field concentration at the corners of the trench 116 can be mitigated. Therefore, the breakdown voltage characteristics of the power semiconductor element 100-7 can be improved, and the operational reliability can be enhanced.

[0597] Figure 79 is a schematic perspective view showing a power semiconductor element 100a-7 according to another embodiment of the present invention; Figure 80 is a plan view showing the power semiconductor element 100a-7 cut along the line VI-VI in Figure 79; Figure 81 is a cross-sectional view showing the power semiconductor element 100a-7 cut along the line VII-VII in Figure 80; and Figure 82 is a cross-sectional view showing the power semiconductor element 100a-7 cut along the line VIII-VIII in Figure 80.

[0598] The power semiconductor element 100a-7 according to this embodiment is either the same as or a modified version of the power semiconductor element 100-7 shown in Figures 75 to 78, and therefore, redundant explanations are omitted.

[0599] Referring to Figures 79 to 82, the source region 112 may include a source contact region 112a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120. For example, the source contact region 112a may refer to the portion to which the source electrode layer 140 is connected as part of the source region 112.

[0600] The well contact region 114 can be formed within the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 through the source region 112 and have a second conductivity type. One or more well contact regions 114 can be formed within the source contact region 112a.

[0601] For example, the well contact region 114 can be connected to the source electrode layer 140, and when connected to the source electrode layer 140, the well contact region 114 can be doped with a higher concentration of second-conductivity impurities than the well contact region 110 in order to reduce the contact resistance.

[0602] Figures 79 to 82 show that the source contact region 112a and the well contact region 114 are formed on one side of the source region 112 with respect to the vertical portion 107a of the drift region 107. However, the source contact region 112a and the well contact region 114 may be formed on both sides with respect to the vertical portion 107a of the drift region 107, or they may be formed on each of the source region 112 and the well region 110 if they are separated into multiple parts.

[0603] In some embodiments, the trenches 116 can be spaced apart in a single row along one direction. This allows the gate electrode layer 120 to also be spaced apart in a single row along the trenches 116 in one direction. In this case, the well region 110 and the source region 112 can be formed in the semiconductor layer 105 between the spaced trenches 116, respectively, which are spaced apart in a single row along one direction.

[0604] For example, multiple power semiconductor element structures 100-7 shown in Figures 75 to 77 can be arranged along one direction, and a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 can be formed between them.

[0605] For example, if the power semiconductor element 100a-7 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

[0606] According to the power semiconductor element 100a-7 of this embodiment, by placing the source contact region 112a and the well contact region 114 outside the gate electrode layer 120 instead of between them, the gate electrode layer 120 can be arranged very densely. As a result, the channel density of the power semiconductor element 100a-7 can be significantly increased.

[0607] Furthermore, with power semiconductor elements 110a-7, the threshold voltage can be lowered by using the channel region 107b that forms the storage channel, and the phenomenon of breakdown occurring due to electric field concentration at the corners of the trench 116 can be mitigated, thereby improving the breakdown characteristics of power semiconductor elements 100a-7 and enhancing operational reliability.

[0608] Figures 83 to 86 are cross-sectional views showing power semiconductor elements 100b-7, 100c-7, 100d-7, and 100e-7 according to yet another embodiment of the present invention. Power semiconductor elements 100b-7, 100c-7, 100d-7, and 100e-7 are modified versions of some of the configurations of power semiconductor elements 100 and 100a-7 shown in Figures 75 to 82, and therefore, redundant explanations in these embodiments are omitted.

[0609] Referring to Figure 83, in the power semiconductor device 100b-7, the well region 110 can protrude from a portion of the source region 112 in the direction of the vertical portion 107a of the drift region 107.

[0610] The channel region 107b1 can be formed in the semiconductor layer 105 on a protruding portion of the well region 110. For example, the vertical portion 107a of the drift region 107 can extend further into the groove between the well region 110 and the gate electrode layer 120, and the channel region 107b1 can be formed in this vertical portion 107a. Such a structure can be made such that the channel region 107b1 is limited to the area between the gate electrode layer 120 and the well region 110.

[0611] Referring to Figure 84, in the power semiconductor device 100c-7, the well region 110 protrudes from a portion of the source region 112 in the direction of the vertical portion 107a of the drift region 107, and further includes a tap portion at its end that extends in the direction of the gate electrode layer 120. For example, the well region 110 protrudes from the source region 112 in the direction of the vertical portion 107a of the drift region 107, and includes a tap portion at its end.

[0612] The channel region 107b2 can be formed on the semiconductor layer 105 on the protruding portion of the well region 110. For example, the channel region 107b2 can be formed in a refractive shape on the protruding portion and tap portion of the well region 110. Such a structure can be further confined so that the channel region 107b2 is between the gate electrode layer 120 and the well region 110.

[0613] Referring to Figure 85, in the power semiconductor device 100d-7, the well region 110 may protrude from a portion of the source region 112 in the direction of the vertical portion 107a of the drift region 107, and may further include a tap portion at its end that extends in the direction of the gate electrode layer 120. For example, the well region 110 may protrude from the source region 112 in the direction of the vertical portion 107a of the drift region 107, and may include a tap portion at its end. Furthermore, the vertical portion 107a of the drift region 107 may extend further between the lower part of the source region 112 and the well region 110.

[0614] The channel region 107b3 can be formed extending further between the lower part of the source region 112 and the well region 110. For example, the channel region 107b3 can be formed in a refracted shape from the tapped portion of the well region 110 to the lower part of the source region 112. Such a structure can increase the contact area between the channel region 107b3 and the source region 112.

[0615] Referring to Figure 86, the power semiconductor element 100e-7 may include at least one groove 138 formed within the source contact region 112a of the source region 112, penetrating the source region 112 and recessed into the well region 110. At least the bottom surface of the groove 138 may have a well contact region 114a formed to contact the well region 110.

[0616] The source electrode layer 140a is formed to fill the groove 138 and can be connected to the well contact region 114a, the well region 110, and / or the source region 112. Such a structure can help increase the contact area between the source electrode layer 140a and the well region 110 and the source region 112, thereby reducing the contact resistance between them.

[0617] In some embodiments, the well contact region 114a can be formed entirely on the surface of the well region 110 exposed by the groove 138. Thus, the well contact region 114a can be formed on the well region 110 exposed from the bottom and side walls of the groove 138. Such a structure of the well contact region 114a can further reduce the contact resistance between the source electrode layer 140a and the well region 110.

[0618] Figures 87 to 89 are schematic perspective views showing a method for manufacturing a power semiconductor device 100-7 according to one embodiment of the present invention. Referring to Figure 87, a drift region 107 having a first conductivity type can be formed on a silicon carbide (SiC) semiconductor layer 105. For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 is provided as a substrate of the first conductivity type, and the drift region 107 can be formed on such a substrate as one or more epitaxial layers.

[0619] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with at least a portion of the drift region 107. For example, the step of forming the well region 110 can be performed by implanting an impurity of the second conductivity type into the semiconductor layer 105.

[0620] For example, the well region 110 can be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a in which at least a portion is surrounded by the well region 11. More specifically, the well region 110 can be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107.

[0621] Next, a source region 112 having a first conductivity type can be formed within the well region 110. For example, the step of forming the source region 112 can be performed by injecting an impurity of the first conductivity type into the well region 110.

[0622] Along with the formation of the source region 112, a storage channel can be formed in one direction in the semiconductor layer 105 between the source region 112 and the drift region 107, thereby forming at least one channel region 107b having a second conductivity type. For example, the channel region 107b can be formed between the source region 112 and the vertical portion 107a of the drift region 107.

[0623] For example, if the channel region 107b is part of the drift region 107, the source region 112 can be formed to be in contact with the drift region 107 via the channel region 107b.

[0624] In the manufacturing method described above, impurity implantation or impurity doping can be performed by ion implanting impurities into the semiconductor layer 105 or by introducing impurities during the formation of the epitaxial layer. However, for impurity implantation in selective regions, an ion implantation method using a mask pattern can be used. Selectively, after ion implantation, a heat treatment step may follow to activate or diffuse the impurities.

[0625] Referring to Figure 88, at least one trench 116 can be formed such that it is recessed from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. For example, the trench 116 can extend in one direction across the drift region 107 and be formed shallower than the well region 110.

[0626] Furthermore, multiple trenches 116 can be formed in the semiconductor layer 105 in a unidirectional arrangement. For example, the trenches 116 can be formed by creating a photomask using photolithography, and then etching the semiconductor layer 105 using such a photomask as an etching protective film.

[0627] Referring to Figure 89, a gate insulating layer 118 can be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 can be formed by oxidizing the semiconductor layer 105 to form an oxide, or by depositing an insulating material such as an oxide or nitride onto the semiconductor layer 105.

[0628] Next, a gate electrode layer 120 can be formed on the gate insulating layer 118 to fill the trench 116. For example, the gate electrode layer 120 can be formed by patterning a conductive layer after it has been formed on the gate insulating layer 118. The gate electrode layer 120 can be formed by doping polysilicon with impurities, or by including a conductive metal or metal silicide.

[0629] For example, the gate insulating layer 118 and the gate electrode layer 120 can be formed to protrude further outside the trench 116. Furthermore, the gate insulating layer 118 and the gate electrode layer 120 can be formed broadly on the semiconductor layer 105 across the trench 116.

[0630] The patterning process can be carried out using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photographic process and a developing process, and the etching process may include selectively etching the underlying structure using such a photoresist pattern.

[0631] As a result, the well region 110 is positioned deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at at least one end of the gate electrode layer 120, and the channel region 107b can be formed in the semiconductor layer 105 on one or both sides of the gate electrode layer 120 between the drift region 107 and the source region 112.

[0632] Furthermore, an interlayer insulating layer 130 can be formed on the gate electrode layer 120. Next, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by first forming a conductive layer, such as a metal layer, on the interlayer insulating layer 130 and then patterning it.

[0633] On the other hand, the power semiconductor devices 100a-7 shown in Figures 79 to 82 can be manufactured by adding or modifying some steps in the manufacturing process of the power semiconductor device 100-7 described above.

[0634] For example, during the manufacturing of the power semiconductor device 100a-7, the step of forming the source region 112 may include the step of forming a source contact region 112a connected to the source electrode layer 140, at least outside one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may not be separated from the source region 112.

[0635] Furthermore, a well contact region 114 can be formed within the source contact region 112a before forming the trench 116. For example, the well contact region 114 can be formed by injecting a second conductivity type impurity into a portion of the well region 110 at a higher concentration than in the well region 110.

[0636] During the manufacturing of the power semiconductor elements 100a-7, the trenches 116 can be spaced apart in a single line in one direction. Furthermore, the well region 110, the channel region 107b, and the source region 112 can be formed in the semiconductor layer 105 between the trenches 116, respectively.

[0637] According to the manufacturing method described above, power semiconductor elements 100-7 can be economically manufactured using a silicon carbide semiconductor layer 105 and processes used for existing silicon substrates.

[0638] Figure 90 is a schematic perspective view showing a power semiconductor element 100-8 according to one embodiment of the present invention, Figure 91 is a plan view showing the power semiconductor element 100-8 cut along the line II-II in Figure 90, and Figure 92 is a cross-sectional view showing the power semiconductor element 100-8 cut along the line III-III in Figure 91.

[0639] Referring to Figures 90 to 92, the power semiconductor device 100-8 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-8 may have a power MOSFET structure.

[0640] The semiconductor layer 105 can refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 can refer to one or multiple epitaxial layers on a semiconductor substrate.

[0641] For example, the semiconductor layer 105 can be composed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one silicon carbide epitaxial layer.

[0642] Because silicon carbide (SiC) has a wider bandgap than silicon, it can maintain stability even at higher temperatures. Furthermore, because silicon carbide has a much higher dielectric breakdown field than silicon, it can operate stably even at high voltages. Therefore, the power semiconductor device 100-8 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage while also exhibiting superior heat dissipation characteristics and stable operating characteristics even at high temperatures, compared to the case using silicon.

[0643] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and can be formed by implanting an impurity of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 can be formed by doping an epitaxial layer of silicon carbide with an impurity of the first conductivity type.

[0644] The well region 110 is formed in the semiconductor layer 105 in contact with the drift region 107 and may have a second conductivity type. For example, the well region 110 can be formed by doping the drift region 107 with an impurity of a second conductivity type opposite to the first conductivity type. More specifically, the well region 110 can be placed on the drift region 107.

[0645] The source region 112 is formed on or within the well region 110 and may have a first conductivity type. For example, the source region 112 can be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 can be formed by doping the drift region 107 with an even higher concentration of impurity of the first conductivity type.

[0646] Additionally, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, the drain region 102 can be doped to a higher concentration than the drift region 107.

[0647] In some embodiments, the drain region 102 may also be provided as a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0648] At least one trench 116 can be formed by recessing from the surface of the semiconductor layer 105 into the interior of the semiconductor layer 105 to a predetermined depth. The trench 116 can extend in one direction within the semiconductor layer 105. This one direction refers to the length direction of the trench 116, not the depth direction, and can refer to the III-III direction in Figure 91.

[0649] The gate insulating layer 118 can be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 can be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or the portion formed on the bottom of the trench 116 may be thicker than the portion formed on the side walls in order to reduce the electric field at the bottom of the trench 116.

[0650] For example, the gate insulating layer 118 may include or include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide.

[0651] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 so as to fill the trench 116. For example, the gate electrode layer 120 may include a suitable conductor, such as polysilicon, metal, metal nitride, metal silicide, or a laminated structure thereof.

[0652] In some embodiments, the drift region 107 can be formed in the semiconductor layer 105 below the gate electrode layer 120. The well region 110 can be formed in the semiconductor layer 105 deeper than the gate electrode layer 120, so as to surround at least the side walls and bottom corners of the gate electrode layer 120 on the drift region 107.

[0653] The junction resistance reduction region 108 can be formed in the semiconductor layer 105 so as to be connected to the drift region 107 below the bottom surface of the gate electrode layer 120. The junction resistance reduction region 108 can have a first conductivity type, which can be formed, for example, by implanting an impurity of the first conductivity type into the semiconductor layer 105.

[0654] In some embodiments, the well region 110 is formed to surround the sidewall and bottom surface of the gate electrode layer 120, and the junction resistance reduction region 108 may be formed between the bottom surface of the gate electrode layer 120 and the drift region 107, penetrating the well region 110. In this case, the junction resistance reduction region 108 can be formed by injecting a first conductivity type impurity into the well region 110.

[0655] Such a well 110 structure can further mitigate the problem of electric field concentration at the bottom of the trench 116, i.e., at the lower corner of the gate electrode layer 120. As a result, such a structure can increase the electric field margin over the gate insulating layer 118 in the power semiconductor device 100-8, thereby improving the operational reliability of the power semiconductor device 100-8.

[0656] The channel region 110a can be formed in the semiconductor layer 105 between the junction resistance reduction region 108 and the source region 112. For example, the channel region 110a can be formed in the semiconductor layer 105 along the sidewall of the gate electrode layer 120 between the junction resistance reduction region 108 and the source region 112. For example, the channel region 110a has a second conductivity type, and an inversion channel can be formed along one direction during the operation of the power semiconductor element 100-8.

[0657] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction with the source region 112 and the drift region 107. Thus, the channel region 110a does not allow charge movement under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inverting channel is formed inside it, allowing charge movement.

[0658] In some embodiments, the channel region 110a may be part of the well region 110. In this case, the channel region 110a may be formed integrally with the well region 110 so as to be continuously connected to it. The doping concentration of the second conductivity type impurity in the channel region 110a may be the same as that of the other parts of the well region 110, or may differ to adjust the threshold voltage.

[0659] The doping concentration of the first conductivity type impurity in the junction resistance reduction region 108 may be the same as or higher than that in the drift region 107. In some embodiments, the doping concentration of the first conductivity type impurity in the junction resistance reduction region 108 may be higher than that in the drift region 107 to reduce the junction resistance. In this case, the junction resistance can be reduced by having the junction resistance reduction region 108, which has a lower resistance than the drift region 107, in contact with the channel region.

[0660] Furthermore, the doping concentration of the first conductivity type impurity in the junction resistance reduction region 108 may be the same as or lower than the doping concentration of the first conductivity type impurity in the source region 112 and the drain region 102.

[0661] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed not only inside the trench 116 but also to extend further outside the trench 116.

[0662] In some embodiments, one or more trenches 116 may be provided within the semiconductor layer 105. The number of trenches 116 may be appropriately selected and thus do not limit the scope of this embodiment.

[0663] For example, multiple trenches 116 can be formed in the semiconductor layer 105 along one direction. The trenches 116 can extend in one direction and be spaced apart in a direction perpendicular to that direction.

[0664] In this case, multiple gate electrode layers 120 can be formed on the gate insulating layer 118 so as to fill the inside of the trench 116. Thus, the gate electrode layers 120 can be formed in a trench type within the semiconductor layer 105 and arranged to extend in a unidirectional manner, similar to the trench 116.

[0665] The interlayer insulating layer 130 can be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an appropriate insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof.

[0666] The source electrode layer 140 is formed on the interlayer insulating layer 130 and can be connected to the source region 112. For example, the source electrode layer 140 can be formed from an appropriate conductive material, metal, or the like.

[0667] In the power semiconductor device 100-8 described above, the first conductivity type and the second conductivity type are opposite to each other, but each may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0668] More specifically, if the power semiconductor element 100-8 is an N-type MOSFET, the drift region 107 may be an N- region, the junction resistance reduction region 108 may be an No region, the source region 112 and drain region 102 may be N+ regions, and the well region 110 and channel region 110a may be P- regions.

[0669] During operation of the power semiconductor element 100-8, current can flow perpendicularly from the drain region 102 to the drift region 107 and the junction resistance reduction region 108, and then flow along the sidewall of the gate electrode layer 120, where the channel region is formed, to the source region 112.

[0670] In the aforementioned power semiconductor device 100-8, the gate electrode layer 120 within the trench 116 can be densely arranged in parallel in a stripe or line type, and the channel region can be located on the side of the gate electrode layer 120, thus increasing the channel density.

[0671] Figure 93 is a cross-sectional view showing a power semiconductor element 100a-8 according to another embodiment of the present invention. The power semiconductor element 100a-8 according to this embodiment uses or is a modified version of the power semiconductor element 100-8 shown in Figures 90 to 92, and therefore, redundant explanations are omitted.

[0672] Referring to Figure 93, in power semiconductor devices 100a-8, the source region 112 can be formed so as to be continuously connected along the extension direction of the gate electrode layer 120. For example, the source region 112 can be formed broadly so as to surround the upper region of the gate electrode layer 120. When the source region 112 is formed broadly in this way, the charge transfer path from the drain region 102 to the source region 112 can be widened.

[0673] Figure 94 is a schematic perspective view showing a power semiconductor element 100b-8 according to another embodiment of the present invention; Figure 95 is a plan view showing the power semiconductor element 100b-8 cut along the line VI-VI in Figure 94; Figure 96 is a cross-sectional view showing the power semiconductor element 100b-8 cut along the line VII-VII in Figure 95; and Figure 97 is a cross-sectional view showing the power semiconductor element 100b-8 cut along the line VIII-VIII in Figure 95.

[0674] The power semiconductor element 100b-8 according to this embodiment is either the same as or a modified version of the power semiconductor element 100-8 shown in Figures 90 to 92, and therefore, redundant explanations are omitted.

[0675] Referring to Figures 94 to 97, in power semiconductor devices 100b-8, the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a may refer to the portion to which the source electrode layer 140 is connected as part of the source region 112.

[0676] The well contact region 114 can be formed within the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 through the source region 112 and have a second conductivity type. One or more well contact regions 114 can be formed within the source contact region 112a.

[0677] For example, the well contact region 114 can be doped with a higher concentration of second-conductivity impurities than the well region 110 to reduce contact resistance when connected to the source electrode layer 140. The source electrode layer 140 can be connected to both the source contact region 112a and the well contact region 114.

[0678] In some embodiments, the trenches 116 can be spaced apart in a single row along one direction. This allows the gate electrode layer 120 to also be spaced apart in a single row along one direction along the trenches 116. In this case, the well region 110, source region 112, source contact region 112a, and well contact region 114 can be formed in the semiconductor layer 105 between the trenches 116 spaced apart in a single row along one direction, respectively.

[0679] For example, the power semiconductor element 100b-8 can also be formed by arranging multiple power semiconductor element 100-8 structures shown in Figures 90-92 along one direction, with a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 placed between them.

[0680] For example, if the power semiconductor element 100-8 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

[0681] In power semiconductor devices 100b-8, by placing the source contact region 112a and well contact region 114 outside the gate electrode layer 120 instead of between them, the gate electrode layer 120 can be arranged very densely. As a result, the channel density of power semiconductor devices 100a-8 can be significantly increased.

[0682] Figure 98 is a cross-sectional view showing a power semiconductor element 100c-8 according to yet another embodiment of the present invention. The power semiconductor element 100c-8 is a modified version of some of the configurations of the power semiconductor element 100b-8 shown in Figures 94 to 97, and therefore can be referenced from each other, thus omitting redundant explanations.

[0683] Referring to Figure 98, the power semiconductor element 100c-8 may include at least one groove 138 formed within the source contact region 112a of the source region 112, penetrating the source region 112 and recessed into the well region 110. At least the bottom surface of the groove 138 may have a well contact region 114a formed to contact the well region 110.

[0684] The source electrode layer 140a is formed to fill the groove 138 and can be connected to the well contact region 114a, the well region 110, and / or the source region 112. Such a structure can help to increase the contact area between the source electrode layer 140a and the well region 110, and between the source electrode layer 140a and the source region 112, thereby reducing the contact resistance between them.

[0685] In some embodiments, the well contact region 114a can be formed entirely on the surface of the well region 110 exposed by the groove 138. Thus, the well contact region 114a can be formed on the well region 110 exposed from the bottom and side walls of the groove 138. Such a structure of the well contact region 114a can further reduce the contact resistance between the source electrode layer 140a and the well region 110.

[0686] Figure 99 is a perspective view showing a power semiconductor element 100d-8 according to yet another embodiment of the present invention. The power semiconductor element 100d-8 is a modified version of some of the configurations of the power semiconductor element 100b-8 in Figure 94, and therefore can be referenced from each other, thus omitting redundant explanations.

[0687] Referring to Figure 99, in the power semiconductor device 100d-8, the source region 112 can be formed to be continuously connected along the direction of extension of the gate electrode layer 120. For example, the source region 112 can extend along the top of the gate electrode layer 120 and further extend beyond the gaps between gate electrode layers 120 arranged in a row.

[0688] The source region 112 can be formed broadly so as to surround the upper region of the gate electrode layer 120. When the source region 112 is formed broadly in this way, the charge transfer path from the drain region 102 to the source region 112 can be widened.

[0689] Although the present invention has been described with reference to the embodiments shown in the drawings, these are merely illustrative, and a person with ordinary skill in the art will understand that a wider variety of modifications and equivalent other embodiments are possible. Therefore, the true scope of technical protection of the present invention must be determined by the technical idea of ​​the appended claims.

Claims

1. A silicon carbide (SiC) semiconductor layer, A trench is formed in the interior of the semiconductor layer from the surface of the semiconductor layer to a predetermined depth, and extends in one direction, A gate insulating layer formed on at least the inner wall of at least one of the trenches, At least one gate electrode layer formed on the gate insulating layer so as to fill the at least one trench, A drift region having a first conductivity type is formed in the semiconductor layer and includes a vertical portion extending perpendicularly to the semiconductor layer on one side of the at least one gate electrode layer, A well region having a second conductivity type is formed in the semiconductor layer, in contact with the drift region and extending deeper than the at least one gate electrode layer, so as to surround the bottom surface of the at least one gate electrode layer at one end of the at least one gate electrode layer, A source region having a first conductivity type is formed within the well region, A channel region having a first conductivity type, formed in the semiconductor layer on one side of the at least one gate electrode layer between the vertical portion of the drift region and the source region, wherein a storage channel is formed along the one direction, Includes, The channel region is a part of the vertical portion of the drift region, The well region includes a protrusion that further protrudes from the source region in the direction of the vertical portion of the drift region, The channel region is formed on the protruding portion of the well region within the semiconductor layer, and is a power semiconductor element.

2. The power semiconductor element according to claim 1, wherein the well region protrudes from a portion of the source region in the direction of the vertical portion of the drift region, and the end of the well region includes a tap portion extending in the direction of the gate electrode layer.

3. The power semiconductor element according to claim 2, wherein the channel region is formed in a refractive shape on the protruding portion and the tap portion of the well region.

4. The power semiconductor element according to claim 3, wherein the vertical portion of the drift region extends further between the lower part of the source region and the well region.

5. The power semiconductor device according to claim 4, wherein the channel region is formed to extend further between the lower part of the source region and the well region.

6. The power semiconductor element according to claim 4, wherein the channel region is formed in a refractive shape from above the tap portion of the well region to below the source region.

7. The at least one trench includes a plurality of trenches formed in the semiconductor layer in the same direction, The at least one gate electrode layer includes a plurality of gate electrode layers formed by filling the plurality of trenches, The well region and the source region are connected across the plurality of gate electrode layers, The power semiconductor device according to claim 1, wherein the channel region is formed in the semiconductor layer on one side of the plurality of gate electrode layers.

8. The at least one trench includes a plurality of trenches spaced apart in a line in one direction, The at least one gate electrode layer includes a plurality of gate electrode layers formed by filling the plurality of trenches, The power semiconductor element according to claim 1, wherein the well region and the source region are formed in the semiconductor layer between at least the plurality of trenches, respectively.

9. The semiconductor layer below the drift region further includes a drain region having the first conductivity type, The power semiconductor device according to claim 1, wherein the drain region is doped with a higher concentration than the drift region.

10. The steps include forming a drift region having a first conductivity type in a silicon carbide (SiC) semiconductor layer, The steps include forming a well region in the semiconductor layer that is in contact with at least a portion of the drift region and has a second conductivity type, The steps include forming a source region having the first conductivity type within the well region, The steps include forming a channel region in the semiconductor layer between the drift region and the source region, which is formed on one side of the at least one gate electrode layer and extends in one direction, The steps include forming a plurality of trenches, each of which is formed as a depression in the interior of the semiconductor layer from the surface of the semiconductor layer to a predetermined depth, and which extend across the drift region in one direction, The steps include forming a gate insulating layer on at least the inner wall of each of the plurality of trenches, The steps include forming at least one gate electrode layer on the gate insulating layer so as to fill each of the plurality of trenches, Includes, The drift region includes vertical portions extending perpendicularly to the semiconductor layers on both sides of the at least one gate electrode layer, The channel region is a part of the vertical portion of the drift region, and an accumulation channel is formed along the one direction. The well region is formed at one end of the at least one gate electrode layer so as to surround a portion of the bottom surface of the at least one gate electrode layer and a portion of the side surface of the at least one gate electrode layer, and the well region includes a projection that further protrudes from the source region in the direction of the vertical portion of the drift region. The channel region is formed on the protruding portion of the well region, a method for manufacturing a power semiconductor device.

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