Semiconductor equipment

Abstract

This suppresses overheating in the central part of the cell region. [Solution] The semiconductor substrate 30 has a cell region 10 and an outer peripheral region 20 surrounding the cell region 10, an IGBT region 11 formed in the cell region 10 and having IGBT elements, and an FWD region 12 formed in the cell region 10 and having FWD elements. The IGBT region 11 and the FWD region 12 are formed alternately in one direction in the planar direction of the semiconductor substrate 10, with three or more IGBT regions 11 being formed, and the width is such that the width of the region located towards the center in one direction is narrower than the width of the region located towards the edge in one direction, if the length along one direction is taken as the width.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device in which an insulated-gate bipolar transistor (hereinafter referred to as IGBT) element having an insulated-gate structure and a freewheeling diode (hereinafter referred to as FWD) element are formed on a common semiconductor substrate. [Background technology]

[0002] Conventionally, semiconductor devices having IGBT regions on which IGBT elements are formed and FWD regions on which FWD elements are formed have been proposed (see, for example, Patent Document 1). Specifically, this semiconductor device has a configuration having a cell region and an outer peripheral region surrounding the cell region, and multiple IGBT regions and FWD regions are formed in the cell region. In this semiconductor device, each IGBT region and each FWD region is a planar rectangle with one direction as the longitudinal direction, and the IGBT regions and FWD regions are arranged alternately along the intersecting direction that intersects the longitudinal direction. Furthermore, in this semiconductor device, the width along the intersecting direction of each IGBT region is equal to each other, and the width along the intersecting direction of each FWD region is equal to each other. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2016-72359 [Overview of the project] [Problems that the invention aims to solve]

[0004] In the semiconductor device described above, current flows through the IGBT region when the IGBT element is turned on, and current flows through the FWD region when the FWD element is turned on. In this case, when the IGBT element is turned on, the amount of heat generated in each IGBT region is approximately equal because the widths of each IGBT region are equal. Similarly, when the FWD element is turned on, the amount of heat generated in each FWD region is approximately equal because the widths of each FWD region are equal.

[0005] However, in such semiconductor devices, the regions located at the edges in the intersecting direction tend to dissipate heat more easily to the outer region. Therefore, the amount of heat dissipated in the regions located at the edges in the intersecting direction tends to be greater than that of the regions located in the central part in the intersecting direction. Consequently, in such semiconductor devices, the region located in the central part in the intersecting direction of the cell region tends to become hotter than the region located at the edges in the intersecting direction, potentially leading to damage to the central region.

[0006] The present disclosure aims to provide a semiconductor device that can suppress the temperature rise of the region located towards the center of the cell region. [Means for solving the problem]

[0007] According to one aspect of this disclosure, the semiconductor device comprises a semiconductor substrate (30) having a cell region (10) and an outer peripheral region (20) surrounding the cell region, an IGBT region (11) formed in the cell region and having an IGBT element, and an FWD region (12) formed in the cell region and having an FWD element, wherein the IGBT region and the FWD region are alternately formed in one direction in the plane direction of the semiconductor substrate, and three or more IGBT regions are formed in one direction, and if the length along one direction is defined as the width, the width of the region located towards the center in one direction is narrower than the width of the region located towards the edge in one direction. Furthermore, in one aspect of this disclosure, the number of IGBT regions along one direction is X, which is an odd number of 3 or more, and the width of the IGBT region is narrowest in the {(X+1) / 2}th region along one direction, and three or more FWD regions are formed in one direction, with the width of the region located towards the center in one direction being narrower than the width of the region located towards the edge in one direction. In another aspect of this disclosure, the number of IGBT regions along one direction is X, which is an even number of 4 or more, and the IGBT regions are such that the width of the (X / 2)-th region and the {(X / 2)+1}-th region along one direction are equal and the narrowest, and three or more FWD regions are formed in one direction, with the width of the region located towards the center in one direction being narrower than the width of the region located towards the edge in one direction.

[0008] According to this design, the width of the IGBT region located in the central part in one direction is narrower than the width of the region located at the edge in the same direction. Therefore, compared to the case where the widths of each IGBT region are equal, it is possible to prevent the temperature of the IGBT region in the central part in one direction from becoming too high compared to the temperature of the IGBT region at the edge in the same direction.

[0009] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0010] [Figure 1] This is a plan view of the semiconductor device in the first embodiment. [Figure 2] This is a cross-sectional view along the line II-II in Figure 1. [Figure 3] This is a plan view of the comparative example semiconductor device. [Figure 4] This figure shows the temperature distribution along the IV-IV line in Figures 1 and 3. [Figure 5]It is a diagram showing the relationship between the ratio of the maximum width of the IGBT region to the minimum width of the IGBT region and the maximum temperature of the semiconductor device. [Figure 6] It is a plan view of the semiconductor device used for performing the simulation of FIG. 5. [Figure 7] It is a cross-sectional view of the semiconductor module. [Figure 8] It is a plan view of the semiconductor device in a modified example of the first embodiment. [Figure 9] It is a plan view of the semiconductor device in a modified example of the first embodiment. [Figure 10] It is a plan view of the semiconductor device in a modified example of the first embodiment. [Figure 11] It is a plan view of the semiconductor device in a modified example of the first embodiment. [Figure 12] It is a plan view of the semiconductor device in a modified example of the first embodiment. [Figure 13] It is a plan view of the semiconductor device in the second embodiment. [Figure 14] It is a plan view of the semiconductor device in the third embodiment. [Figure 15] It is a plan view of the semiconductor device in the fourth embodiment. [Figure 16] It is a plan view of the semiconductor device in the fifth embodiment. [Figure 17] It is a plan view of the semiconductor device in the sixth embodiment. [Figure 18] It is a plan view of the semiconductor device in a modified example of the sixth embodiment. [Figure 19] It is a plan view of the semiconductor device in a modified example of the sixth embodiment. [Figure 20] It is a plan view of the semiconductor device in the seventh embodiment.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present disclosure will be described based on the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals for description.

[0012] (First Embodiment) The first embodiment will be described with reference to the drawings. The semiconductor device 1 of this embodiment is preferably used as a power switching element in a power supply circuit such as an inverter or DC / DC converter. Furthermore, in this embodiment, an example will be described in which the temperature of the semiconductor device 1 is highest when the IGBT element is in the ON state, specifically when the IGBT element is ON.

[0013] As shown in Figure 1, the semiconductor device 1 has a cell region 10 and an outer peripheral region 20 surrounding the cell region 10. The cell region 10 is configured to have an IGBT region 11 on which IGBT elements are formed and an FWD region 12 on which FWD elements are formed. In other words, the semiconductor device 1 of this embodiment is an RC (Reverse Conducting)-IGBT in which the IGBT region 11 and the FWD region 12 are formed within a common semiconductor substrate 30, which will be described later. Specifically, as will be described later, in this embodiment, the portion on the collector layer 41 located on the other side 30b of the semiconductor substrate 30 is the IGBT region 11, and the portion on the cathode layer 42 located on the other side 30b of the semiconductor substrate 30 is the FWD region 12.

[0014] First, the planar configuration of the semiconductor device 1 in this embodiment will be described. In this embodiment, the cell region 10 is substantially rectangular in shape. The IGBT region 11 and the FWD region 12 are formed to have portions that are alternately arranged along one direction within the cell region 10. In other words, the IGBT region 11 and the FWD region 12 are formed to have portions that are alternately arranged along one direction in the planar direction of the semiconductor substrate 30, which will be described later.

[0015] In this embodiment, the IGBT region 11 and the FWD region 12 are each rectangular regions having a longitudinal direction, and are formed alternately along the intersecting direction that crosses the longitudinal direction. Hereinafter, the longitudinal direction of the IGBT region 11 and the FWD region 12 will be referred to as the first direction, and the intersecting direction as the second direction. In Figure 1, the left-right direction of the paper is the first direction, and the up-down direction of the paper is the second direction.

[0016] The first direction can also be defined as one direction in the plane direction of the semiconductor substrate 30, which will be described later, and the second direction can be defined as a direction perpendicular to the first direction and along the plane direction of the semiconductor substrate 30, which will be described later. In addition, the IGBT region 11 and the FWD region 12 in this embodiment are arranged alternately such that the IGBT region 11 is located at both ends in the second direction.

[0017] In this embodiment, five IGBT regions 11 are formed along the second direction, and four FWD regions 12 are formed along the second direction. In other words, in this embodiment, an odd number of IGBT regions 11 are formed, and an even number of FWD regions 12 are formed. The central part of the cell region 10 in the second direction is defined as an IGBT region 11.

[0018] In this embodiment, the five IGBT regions 11 arranged along the second direction are also referred to as the first IGBT region 11a, the second IGBT region 11b, the third IGBT region 11c, the fourth IGBT region 11d, and the fifth IGBT region 11e, in order along the second direction. Similarly, the four FWD regions 12 arranged along the second direction are also referred to as the first FWD region 12a, the second FWD region 12b, the third FWD region 12c, and the fourth FWD region 12d, in order along the second direction. In this embodiment, the third IGBT region 11c is located in the center of the cell region 10 in the second direction.

[0019] Furthermore, in the following, the length along the second direction will also be referred to as the width. The widths La to Le of the first to fifth IGBT regions 11a to 11e, and the widths Da to De of the first to fourth FWD regions 12a to 12d are adjusted as follows.

[0020] Specifically, in the IGBT region 11, the width of the region located towards the center in the second direction is narrower than the width of the region located towards the edge in the second direction. More specifically, the first to fifth IGBT regions 11a to 11e are formed such that the width Lc of the third IGBT region 11c is the narrowest, followed by the widths Lb and Ld of the second and fourth IGBT regions 11b and 11d, and then the widths La and Le of the first and fifth IGBT regions 11a and 11e, respectively. In this embodiment, the width Lb of the second IGBT region 11b and the width Ld of the fourth IGBT region 11d are equal, and the width La of the first IGBT region 11a and the width Le of the fifth IGBT region 11e are equal.

[0021] In this embodiment, the first to fourth FWD regions 12a to 12d are formed such that their respective widths Da to Dd are equal.

[0022] Multiple pad portions 21 are formed in the outer peripheral region 20, which are connected to a gate electrode 35 (described later) and a temperature sensing element (not shown). In this embodiment, three pad portions 21 are arranged, and they are positioned along the first direction in the portion of the outer peripheral region 20 on the fifth IGBT region 11e side.

[0023] The above describes the planar configuration of the semiconductor device 1 in this embodiment. Next, the cross-sectional configuration of the semiconductor device 1 will be described.

[0024] The semiconductor device 1 is as shown in Figure 2, N - The semiconductor substrate 30 comprises a P-type drift layer 31. In this embodiment, the semiconductor substrate 30 is made of silicon. A P-type base layer 32 is formed on the drift layer 31. In other words, the base layer 32 is formed on one side 30a of the semiconductor substrate 30.

[0025] Multiple trenches 33 are formed in the semiconductor substrate 30, penetrating the base layer 32 from one side 30a and reaching the drift layer 31. As a result, the base layer 32 is separated into multiple sections by the trenches 33. In this embodiment, the multiple trenches 33 are formed in the IGBT region 11 and the FWD region 12, respectively. In this embodiment, the multiple trenches 33 are formed in a stripe pattern with the first direction as the longitudinal direction.

[0026] Each trench 33 is embedded by a gate insulating film 34 formed to cover the wall surface of each trench 33, and a gate electrode 35 made of polysilicon or the like formed on the gate insulating film 34. This constitutes a trench gate structure.

[0027] The gate electrode 35 located in the trench 33 formed in the IGBT region 11 is connected to one of the pad portions 21 shown in Figure 1 via gate wiring (not shown), so that a predetermined gate voltage is applied. Furthermore, the gate electrode 35 located in the trench 33 formed in the FWD region 12 is electrically connected to the upper electrode 39, which will be described later. In other words, the gate electrode 35 in the FWD region 12 is maintained at a predetermined potential.

[0028] The surface layer of the base layer 32 of the IGBT region 11 and FWD region 12 (i.e., one side 30a of the semiconductor substrate 30) has a higher impurity concentration of N than the drift layer 31. + A type emitter region 36 is formed. In addition, the surface layer of the base layer 32 of the IGBT region 11 and FWD region 12 has a higher impurity concentration of P than the base layer 32. + A type of contact region 37 is formed. Specifically, the emitter region 36 is formed to terminate within the base layer 32 and to be in contact with the side surface of the trench 33. Similarly, the contact region 37 is formed to terminate within the base layer 32, just like the emitter region 36.

[0029] More specifically, the emitter region 36 extends in a rod-like shape along the longitudinal direction of the trenches 33 in the region between the trenches 33, in contact with the sides of the trenches 33, and terminates inside the tip of the trenches 33. The contact region 37 is sandwiched between the two emitter regions 36 and extends in a rod-like shape along the longitudinal direction of the trenches 33 (i.e., the emitter region 36).

[0030] In this embodiment, the portion of the trench 33 wall located between the emitter region 36 and the drift layer 31 becomes the surface of the base layer 32 located between the emitter region 36 and the drift layer 31. Furthermore, the contact region 37 in this embodiment is formed deeper than the emitter region 36 with respect to one surface 30a of the semiconductor substrate 30.

[0031] An interlayer insulating film 38, made of BPSG (abbreviation for Borophosphosilicate Glass) or the like, is formed on one surface 30a of the semiconductor substrate 30. An upper electrode 39 is formed on the interlayer insulating film 38, which is electrically connected to the emitter region 36 and the contact region 37 (i.e., the base layer 32) through a contact hole 38a formed in the interlayer insulating film 38. In other words, an upper electrode 39 is formed on the interlayer insulating film 38 that functions as an emitter electrode in the IGBT region 11 and as an anode electrode in the FWD region 12.

[0032] In this embodiment, the interlayer insulating film 38 has a contact hole 38b in the FWD region 12 that exposes the gate electrode 35. The upper electrode 39 is also connected to the gate electrode 35 through this contact hole 38b. As a result, the gate electrode 35 formed in the FWD region 12 is maintained at the same potential as the upper electrode 39.

[0033] On the drift layer 31 opposite to the base layer 32 (i.e., the other side 30b of the semiconductor substrate 30), an N-type field stop layer (hereinafter referred to as the FS layer) 40 is formed, which has a higher impurity concentration than the drift layer 31.

[0034] Then, in the IGBT region 11, P is located on the opposite side of the drift layer 31, with the FS layer 40 in between. + A collector layer 41 of type N is formed, and in the FWD region 12, on the opposite side of the drift layer 31 with the FS layer 40 in between, N + A cathode layer 42 of type 1 is formed. In other words, the IGBT region 11 and the FWD region 12 are separated by whether the layer formed on the other side 30b of the semiconductor substrate 30 is a collector layer 41 or a cathode layer 42. In the outer peripheral region 20, the collector layer 41 is formed on the opposite side of the drift layer 31, with the FS layer 40 in between.

[0035] On the side opposite the drift layer 31 (i.e., the other side 30b of the semiconductor substrate 30) with the collector layer 41 and cathode layer 42 in between, a lower electrode 43 is formed that is electrically connected to the collector layer 41 and cathode layer 42. In other words, a lower electrode 43 is formed that functions as a collector electrode in the IGBT region 11 and as a cathode electrode in the FWD region 12. Furthermore, the lower electrode 43 is also connected to the collector layer 41 in the outer peripheral region 20.

[0036] As a result of the above configuration, in the FWD region 12, an FWD element is formed by PN junction with the base layer 32 and contact region 37 as the anode and the drift layer 31, FS layer 40, and cathode layer 42 as the cathode.

[0037] The outer peripheral region 20 has a drift layer 31 similar to that of the cell region 10. The surface portion of the drift layer 31 is formed at the boundary with the cell region 10 and connected to the base layer 32, with a higher impurity concentration than the base layer 32, in order to suppress electric field concentration in the cell region 10. +A deep layer 44 of a certain type is formed. In this embodiment, the deep layer 44 is formed deeper than the base layer 32 and is formed in a frame shape so as to surround the cell region 10. In addition, in this embodiment, in order to suppress the occurrence of electric field concentration at the corners in the planar shape of the deep layer 44, the parts located at the corners have a rounded curvature and are R-shaped. In other words, the deep layer 44 has a planar frame shape such as a square frame shape or a circular frame shape with rounded corners.

[0038] Furthermore, in the outer peripheral region 20, a guard ring 45 is formed on the surface of the drift layer 31 so as to surround the deep layer 44. In fact, multiple guard rings 45 are formed, each forming an annular structure that surrounds the cell region 10. In other words, the guard rings 45 are formed to constitute a multi-ring structure. In addition, each guard ring 45, like the deep layer 44, has a planar shape such as a square frame with rounded corners or a circular frame.

[0039] The pad portion 21, which is located in the outer peripheral region 20, is positioned on the deep layer 44.

[0040] Furthermore, in the outer peripheral region 20, similar to the cell region 10, an interlayer insulating film 38 is formed on one surface 30a of the semiconductor substrate 30. Contact holes 38c are formed in the interlayer insulating film 38 to expose the deep layer 44, and the upper electrode 39 is also connected to the deep layer 44 through the contact holes 38c.

[0041] Furthermore, a protective film 46 made of polyimide or the like is formed on one side 30a of the semiconductor substrate 30. The protective film 46 has a contact hole 46a that exposes the upper electrode 39 in the cell region 10, and a contact hole 46b that exposes the pad portion 21 in the outer peripheral region 20. In this embodiment, the contact hole 46a is formed to expose the entire cell region 10, and the opening is formed to be approximately rectangular in shape in the plan to match the cell region 10.

[0042] The above is the configuration of the semiconductor device 1 in this embodiment. In this embodiment, the N-type, N + -type, N - -type correspond to the first conductivity type, and the P-type, P + -type correspond to the second conductivity type. Also, in this embodiment, due to the semiconductor device 1 being configured as described above, the semiconductor substrate 30 has a configuration including a collector layer 41, a cathode layer 42, a drift layer 31, a base layer 32, an emitter region 36, a contact region 37, and the like.

[0043] Next, while explaining the operation of the semiconductor device 1, the detailed configuration of the semiconductor device 1 will be further described.

[0044] When a voltage higher than the upper electrode 39 is applied to the lower electrode 43 in the semiconductor device 1 as described above, the PN junction formed between the base layer 32 and the drift layer 31 becomes in the reverse conduction state and a depletion layer is formed. And when a gate voltage of a low level (for example, 0V) lower than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 35, no current flows between the upper electrode 39 and the lower electrode 43.

[0045] To turn on the IGBT element, with a voltage higher than the upper electrode 39 applied to the lower electrode 43, a high-level gate voltage equal to or higher than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 35 of the IGBT region 11. Thereby, in the IGBT region 11, an inversion layer is formed in the portion of the base layer 32 in contact with the trench 33 where the gate electrode 35 is disposed. And in the IGBT element, electrons are supplied from the emitter region 36 to the drift layer 31 through the inversion layer, holes are supplied from the collector layer 41 to the drift layer 31, and the resistance value of the drift layer 31 decreases due to conductivity modulation. As a result, a current flows between the upper electrode 39 and the lower electrode 43 in the IGBT element.

[0046] In this embodiment, the width of the IGBT region 11 located on the central side in the second direction is narrower than the width of the region located on the edge side in the second direction. Therefore, the IGBT region 11 has a lower current flow and generates less heat in the central side in the second direction than in the edge side in the second direction. In other words, the part of the IGBT region 11 that is difficult to dissipate heat, located on the central side in the second direction, generates less heat than the part that is easy to dissipate heat, located on the edge side in the second direction. Therefore, when the IGBT element is in the ON state, it is possible to suppress the central side of the cell region 10 in the second direction from becoming hot.

[0047] Here, as shown in Figure 3, a semiconductor device in which the widths La to Le of the first to fifth IGBT regions 11a to 11e are equal is defined as the comparative semiconductor device J1. According to the inventors' investigation, when the IGBT elements are turned on, the temperatures of the semiconductor device 1 of this embodiment and the comparative semiconductor device J1 are as shown in Figure 4. Note that the temperatures in Figure 4 represent the temperatures along the line IV-IV in Figures 1 and 3. Also, 11a to 11e in Figure 4 represent the centers of the second direction in the first to fifth IGBT regions 11a to 11e.

[0048] As shown in Figure 4, in the comparative example semiconductor device J1, the widths La to Le of the first to fifth IGBT regions 11a to 11e are equal, so it is confirmed that the temperature is higher in the central part in the second direction. Specifically, the temperature of the third IGBT region 11c becomes extremely high.

[0049] In contrast, in the semiconductor device 1 of this embodiment, the width of the portion located towards the center in the second direction is narrower than the width of the portion located towards the edge in the second direction. In other words, in the semiconductor device 1 of this embodiment, the width Lc of the third IGBT region 11c is narrower than that of the first, second, fourth, and fifth IGBT regions 11a, 11b, 11d, and 11e. Therefore, it is possible to suppress the temperature of the third IGBT region 11c, which is the most difficult to dissipate heat from, from becoming too high.

[0050] Furthermore, in this embodiment, as shown in Figure 4, the widths La to Le of the first to fifth IGBT regions 11a to 11e are adjusted so that the average temperatures of the first to fifth IGBT regions 11a to 11e are approximately equal. Specifically, the semiconductor device 1 has greater heat dissipation towards the edges in the second direction. For this reason, in this embodiment, the width Lc of the third IGBT region 11c is the narrowest, followed by the widths Lb and Ld of the second and fourth IGBT regions 11b and 11d, and then the widths La and Le of the first and fifth IGBT regions 11a and 11e, which increase in that order. This makes it possible to suppress variations in the lifetime of the gate insulating film 34 in the first to fifth IGBT regions 11a to 11e.

[0051] Furthermore, the inventors conducted further investigations into the width of the IGBT region 11 and obtained the results shown in Figure 5. Figure 5 shows the results when the widths La, Lb, Ld, and Le of the first, second, fourth, and fifth IGBT regions 11a, 11b, 11d, and 11e are made equal, while the width Lc of the third IGBT region 11c is made as narrow as possible, as shown in Figure 6. The maximum temperature of the semiconductor device 1 in Figure 5 is the temperature of the third IGBT region 11c when the IGBT element is turned on.

[0052] As shown in Figure 5, the maximum temperature of the semiconductor device 1 decreases sharply as the ratio of the maximum width of the IGBT region 11 to the minimum width of the IGBT region 11 (hereinafter simply referred to as the IGBT region width ratio) increases, when the ratio is less than 1.5. However, the maximum temperature of the semiconductor device 1 remains almost unchanged when the IGBT region width ratio is in the range of 1.5 to 4.5. Therefore, it is preferable that the IGBT region width ratio be in the range of 1.5 to 4.5. This allows the temperature of the third IGBT region 11c to be sufficiently low.

[0053] Furthermore, when turning the IGBT element off and turning the FWD element on (i.e., making the FWD element operate as a diode), the voltages applied to the upper electrode 39 and the lower electrode 43 are switched, and a forward voltage is applied to the upper electrode 39 that is higher than the voltage applied to the lower electrode 43. As a result, holes are supplied to the base layer 32 and electrons are supplied to the cathode layer 42, causing the FWD element to operate as a diode.

[0054] The semiconductor device 1 described above can be used, for example, to constitute a semiconductor module for driving a motor as a load.

[0055] For example, as shown in Figure 7, the semiconductor module is configured to include a first support member 110, a semiconductor device 1, a terminal 120, a second support member 130, a control terminal section 140, a sealing member 160, and the like.

[0056] The first support member 110 is made of, for example, a lead frame made of copper, iron, or an alloy thereof. The first support member 110 in this embodiment has a first mounting portion 111 having a surface 111a and a back surface 111b opposite to the surface 111a, and a first connection terminal portion 112 connected to the first mounting portion 111. The first connection terminal portion 112 extends along the surface direction of the surface 111a of the first mounting portion 111 and is integrated with the first mounting portion 111 in this embodiment. Furthermore, the first connection terminal portion 112 in this embodiment extends on the side opposite to the control terminal portion 140, which will be described later.

[0057] The semiconductor device 1 has the configuration described above, and is positioned on the surface 111a of the first mounting portion 111 via a first bonding member 201 made of solder or the like, with the lower electrode 43 facing the first mounting portion 111.

[0058] The terminal 120 is made of, for example, copper, iron, or an alloy thereof, and has a shape that corresponds to the planar shape of the upper electrode 39 exposed from the protective film 46 of the semiconductor device 1. In this embodiment, since the opening of the contact hole 46a formed in the protective film 46 is substantially rectangular, the terminal 120 has a planar substantially rectangular shape. The terminal 120 is then placed on the upper electrode 39 of the semiconductor device 1 via a second joining member 202 made of solder or the like.

[0059] More specifically, the semiconductor device 1 has a plating layer formed on the portion exposed from the contact hole 46a of the protective film 46 to improve wettability with the solder constituting the second bonding member 202. The terminal 120 is then placed on this plating layer via the second bonding member 202.

[0060] The second support member 130 is composed of a lead frame or the like, similar to the first support member 110, and has a second mounting portion 131 having a surface 131a and a back surface 131b opposite to the surface 131a, and a second connection terminal portion 132 connected to the second mounting portion 131.

[0061] The second support member 130 is connected to the terminal 120 via a third joining member 203, the surface 131a of the second mounting portion 131 is made of solder or the like. In other words, the first support member 110 and the second support member 130 are arranged to face each other with the semiconductor device 1 in between. The second connection terminal portion 132 extends along the surface direction of the surface 131a of the second mounting portion 131, and in this embodiment, it extends in the same direction as the first connection terminal portion 112. In this embodiment, the second connection terminal portion 132 is integrated with the second mounting portion 131.

[0062] The control terminal section 140 is connected to the pad section 21 formed on the semiconductor device 1 via a bonding wire 150. In this embodiment, the control terminal section 140 corresponds to the external terminal section.

[0063] The sealing member 160 is made of molded resin, potting resin, or the like, and is formed to seal the first support member 110, the semiconductor device 1, the second support member 130, the control terminal portion 140, etc. Specifically, the sealing member 160 is formed so that the back surface 111b of the first mounting portion 111 on the first support member 110, the back surface 131b of the second mounting portion 131 on the second support member 130, and parts of each terminal portion 112, 132, 140 are exposed.

[0064] According to the embodiment described above, the width of the IGBT region 11 located in the central part in the second direction is narrower than the width of the region located at the edge in the second direction. Therefore, compared to the case where the widths of each IGBT region 11 are equal, it is possible to suppress the temperature of the central IGBT region 11 in the second direction from becoming too high compared to the temperature of the edge IGBT region 11 in the second direction. Accordingly, for example, compared to the semiconductor device J1 of the comparative example, it is possible to increase the amount of current that can be passed until the maximum temperature is the same, thereby increasing the selectivity of applications.

[0065] (1) In this embodiment, the width Lc of the third IGBT region 11c, located in the central part of the second direction, is the narrowest among the first to fifth IGBT regions 11a to 11e. This prevents the temperature of the IGBT region 11 located in the central part of the second direction from becoming too high. In addition, if X IGBT regions 11 are arranged along the second direction (an odd number of 3 or more), then the width of the region located at the {(X+1) / 2}th position along the second direction is the narrowest.

[0066] (2) In this embodiment, by setting the IGBT region width ratio to 1.5 to 4.5, the maximum temperature of the semiconductor device 1 can be sufficiently lowered.

[0067] (Modification of the first embodiment) A modified version of the first embodiment described above will now be explained. In the first embodiment, the number and arrangement of the IGBT regions 11 and FWD regions 12 can be changed as appropriate. For example, as shown in Figure 8, four IGBT regions 11 (1st to 4th IGBT regions 11a to 11d) and three FWD regions 12 (1st to 3rd FWD regions 12a to 12c) may be formed along the second direction. In other words, in this example, an even number of IGBT regions 11 are formed, and an odd number of FWD regions 12 are formed. Also, an FWD region 12 is located in the central part of the cell region 10 in the second direction.

[0068] Furthermore, in the IGBT region 11, the width of the portion located towards the center in the second direction is narrower than the width of the portion located towards the edge in the second direction. Specifically, in the first to fourth IGBT regions 11a to 11d, the widths Lb and Lc of the second and third IGBT regions 11b and 11c are narrower than the widths La and Ld of the first and fourth IGBT regions 11a and 11d. Thus, the first embodiment described above can also be applied when the number of IGBT regions 11 along the second direction is an even number of four or more. It should also be said that in this configuration, if X IGBT regions 11 are arranged along the second direction (an even number of four or more), the widths of the region located at the (X / 2)th position and the region located at the {(X / 2)+1}th position along the second direction are the narrowest.

[0069] Furthermore, in the first embodiment described above, the semiconductor device 1 may be divided in the first direction, as shown in Figure 9, with the IGBT region 11 and the FWD region 12 being separated. In this case, a gate liner connected to the gate electrode 35 may be placed in the separated portion, or a temperature sensor may be placed therein.

[0070] Furthermore, as shown in Figure 10, the semiconductor device 1 may have the IGBT region 11 and the FWD region 12 extending in the second direction as the longitudinal direction and arranged alternately along the first direction. In this case, the first direction corresponds to one direction along the plane direction of the semiconductor substrate 30.

[0071] Furthermore, the semiconductor device 1 may have IGBT regions 11 and FWD regions 12 formed alternately in a concentric frame shape, as shown in Figures 11 and 12. In this case, if the first and second directions are set as in the first embodiment described above, it can be said that the IGBT regions 11 and FWD regions 12 are formed alternately along the first and second directions.

[0072] For example, in Figure 11, three IGBT regions 11 (first to third IGBT regions 11a to 11c) and two FWD regions 12 (first and second FWD regions 12a and 12b) are formed in a concentric frame. In Figure 11, it can be said that three IGBT regions 11 (i.e., an odd number) are formed along the second direction. In Figure 12, the first and second IGBT regions 11a and 11b and two FWD regions 12a and 12b are formed in a concentric frame. In Figure 12, it can be said that four IGBT regions 11 (i.e., an even number) are formed along the second direction.

[0073] (Second Embodiment) A second embodiment will now be described. This embodiment is a modification of the first embodiment in which the width of the FWD region 12 is changed. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.

[0074] In the first embodiment described above, it was assumed that the temperature of the semiconductor device 1 is highest when the IGBT element is turned on, and therefore a configuration for changing the width of the IGBT region 11 was described. However, depending on the operating conditions and the impurity concentration of each region, it is also possible that the temperature of the semiconductor device 1 is highest when the FWD element is turned on. In this embodiment, an example in which the temperature of the semiconductor device 1 is highest when the FWD element is turned on will be described.

[0075] In the semiconductor device 1 of this embodiment, as shown in Figure 13, the widths La to Le of the first to fifth IGBT regions 11a to 11e are equal. Furthermore, in the first to fifth FWD regions 12a to 12d, the width of the portion located towards the center in the second direction is narrower than the width of the portion located towards the edge in the second direction. Specifically, in this embodiment, the widths Db and Dc of the second and third FWD regions 12b and 12c are narrower than the widths Da and Dd of the first and fourth FWD regions 12a and 12d.

[0076] Furthermore, when the inventors turned on the FWD element and investigated the maximum temperature of the semiconductor device 1, they obtained results similar to those in Figure 5, although these results are not shown in the diagram. Specifically, it was confirmed that the maximum temperature of the semiconductor device 1 decreases sharply as the ratio of the maximum width of the FWD region 12 to the minimum width of the FWD region 12 (hereinafter also simply referred to as the FWD region width ratio) increases, when the ratio is less than 1.5. It was also confirmed that the maximum temperature of the semiconductor device 1 remains almost unchanged when the FWD region width ratio is in the range of 1.5 to 4.5. Therefore, it is preferable that the FWD region width ratio be in the range of 1.5 to 4.5. The maximum temperature in the semiconductor device 1 of this embodiment is the temperature of the second and third FWD regions 12b and 12c.

[0077] According to the embodiment described above, in the FWD region 12, the width of the region located in the central part in the second direction is narrower than the width of the region located at the edge in the second direction. Therefore, compared to the case where the widths of each FWD region 12 are equal, it is possible to suppress the temperature of the central FWD region 12 in the second direction from becoming too high compared to the temperature of the edge FWD region 12 in the second direction.

[0078] (1) In this embodiment, the widths Db and Dc of the second and third FWD regions 12b and 12c, which are located in the central part of the second direction, are the narrowest among the first to fourth FWD regions 12a to 12d. Therefore, it is possible to suppress the temperature of the FWD region 12 located in the central part of the second direction from becoming too high. It should also be said that in this configuration, if X FWD regions 12 are arranged along the second direction in an even number of four or more positions, the widths of the region located at the (X / 2)th position and the region located at the {(X / 2)+1}th position along the second direction are the narrowest.

[0079] (2) In this embodiment, by setting the FWD region width ratio to 1.5 to 4.5, the maximum temperature of the semiconductor device 1 can be sufficiently lowered.

[0080] (Modified version of the second embodiment) A modified version of the second embodiment described above will now be explained. In the second embodiment, although not specifically shown, the arrangement of the IGBT region 11 and the FWD region 12 can be changed as appropriate, similar to the modified version of the first embodiment.

[0081] For example, the FWD regions 12 may be arranged in an odd number of locations along the second direction. In this case, if there are X FWD regions 12 arranged along the second direction (an odd number of 3 or more), then the width of the region located at the {(X+1) / 2}th position along the second direction should be the narrowest.

[0082] (Third embodiment) A third embodiment will now be described. This embodiment combines the first and second embodiments. Other aspects are the same as in the first embodiment, so further explanation will be omitted here.

[0083] As shown in Figure 14, the semiconductor device 1 of this embodiment is configured by combining the first embodiment and the second embodiment described above. Specifically, the first to fifth IGBT regions 11a to 11e are formed such that the width Lc of the third IGBT region 11c is the narrowest, followed by the widths Lb and Ld of the second and fourth IGBT regions 11b and 11d, and then the widths La and Le of the first and fifth IGBT regions 11a and 11e, which are the widest. In addition, the first to fourth FWD regions 12a to 12d are formed such that the widths Db and Dc of the second and third FWD regions 12b and 12c are narrower than the widths Da and Dd of the first and fourth FWD regions 12a and 12d.

[0084] According to the embodiment described above, the same effects as those of the first and second embodiments can be obtained.

[0085] (Fourth Embodiment) A fourth embodiment will now be described. This embodiment is a modification of the first embodiment in which the width Le of the fifth IGBT region 11e is changed. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.

[0086] As shown in Figure 15, the semiconductor device 1 of this embodiment has first to fifth IGBT regions 11a to 11e and first to fourth FWD regions 12a to 12d, similar to the first embodiment. The pad portion 21 is located in the outer peripheral region 20, on the side opposite to the fourth FWD region 12d, with the fifth IGBT region 11e in between. In other words, the pad portion 21 is located in the vicinity of the fifth IGBT region 11e.

[0087] In such a semiconductor device 1, when the IGBT elements are turned on, both the first IGBT region 11a and the fifth IGBT region 11e tend to have high heat dissipation performance because heat can easily be dissipated to the outer peripheral region 20. However, because the pad portion 21 of the outer peripheral region 20 is located near the fifth IGBT region 11e, the portion located on the fifth IGBT region 11e side is wider than the portion located on the first IGBT region 11a side. Therefore, when comparing the first IGBT region 11a and the fifth IGBT region 11e, the fifth IGBT region 11e has higher heat dissipation performance than the first IGBT region 11a.

[0088] Therefore, in this embodiment, the width Le of the fifth IGBT region 11e is wider than the width La of the first IGBT region 11a. However, the width La of the first IGBT region 11a is wider than the widths Lb to Ld of the second to fourth IGBT regions 11b to 11d.

[0089] According to the embodiment described above, in the IGBT region 11, the width of the region located in the central part in the second direction is narrower than the width of the region located at the edge in the second direction. Therefore, the same effects as in the first embodiment can be obtained.

[0090] (1) In this embodiment, the width Le of the fifth IGBT region 11e located on the pad portion 21 side of the IGBT region 11 is wider than the width La of the first IGBT region 11a. Therefore, it is possible to suppress the temperature of the first IGBT region 11a, which has lower heat dissipation than the fifth IGBT region 11e, from becoming higher than the temperature of the fifth IGBT region 11e.

[0091] (Fifth embodiment) The fifth embodiment will now be described. This embodiment combines the second and fourth embodiments. Other aspects are the same as in the second embodiment, so their explanation will be omitted here.

[0092] As shown in Figure 16, the semiconductor device 1 of this embodiment has first to fifth IGBT regions 11a to 11e and first to fourth FWD regions 12a to 12d, similar to the second embodiment. The pad portion 21 is located on the fourth FWD region 12d side. In this case, similar to the fourth embodiment, when comparing the first FWD region 12a and the fourth FWD region 12d, the fourth FWD region 12d has higher heat dissipation than the first FWD region 12a.

[0093] Therefore, in this embodiment, the width Dd of the fourth FWD region 12d is wider than the width Da of the first FWD region 12a. However, the width Da of the first FWD region 12a is wider than the widths Db and Dc of the second and third FWD regions 12b and 12c.

[0094] According to the embodiment described above, in the FWD region 12, the width of the region located in the central part in the second direction is narrower than the width of the region located at the edge in the second direction. Therefore, the same effects as in the second embodiment can be obtained.

[0095] (1) In this embodiment, the width Dd of the fourth FWD region 12d located on the pad portion 21 side of the FWD region 12 is wider than the width Da of the first FWD region 12a. Therefore, it is possible to suppress the temperature of the first FWD region 12a, which has lower heat dissipation than the fourth FWD region 12d, from becoming higher than the temperature of the fourth FWD region 12d.

[0096] (Sixth Embodiment) A sixth embodiment will now be described. This embodiment adds an FWD region 12 adjacent to the pad portion 21 in the first direction compared to the third embodiment. Other aspects are the same as in the third embodiment, so a detailed explanation will be omitted here.

[0097] In the semiconductor device 1 of this embodiment, as shown in Figure 17, the FWD region 12 has a fifth FWD region 12e that is located on the opposite side of the fourth FWD region 12d, with the fifth IGBT region 11e in between. The fifth FWD region 12e is arranged to be adjacent to the pad portion 21 in the first direction.

[0098] In this embodiment, the fifth FWD region 12e is rectangular in shape and consists of two portions, formed to sandwich the pad portion 21 in the first direction. In other words, the fifth FWD region 12e is divided in the first direction, and the pad portion 21 is located in the divided portion of the fifth FWD region 12e. That is, in the cell region 10, the area adjacent to the pad portion 21 in the second direction is the IGBT region 11, and the area adjacent to the pad portion 21 in the first direction is the FWD region 12. In other words, if a predetermined range including the area where the pad portion 21 is located is called the placement region RP, then in the cell region 10, the area adjacent to the placement region RP in the second direction is the IGBT region 11, and the area adjacent to the placement region RP in the first direction is the FWD region 12. In this embodiment, the fifth FWD region 12e corresponds to the additional FWD region.

[0099] Furthermore, in the semiconductor device 1 of this embodiment, the contact holes 46a formed in the protective film 46 have an opening shape that is substantially rectangular in plan, similar to the first embodiment. In other words, the contact holes 46a formed in the protective film 46 are formed to expose the first to fifth IGBT regions 11a to 11e and the first to fourth FWD regions 12a to 12d, and to cover the fifth FWD region 12e.

[0100] In this way, by making the shape of the opening of the contact hole 46a approximately rectangular in plan, the following effects can be obtained compared to the case in which the contact hole 46a is formed so as to expose the fifth FWD region 12e. That is, it becomes easier to control the spread of the second bonding member 202 (i.e., solder) when constructing the semiconductor module. As a result, variations in bonding strength between the terminal 120 and the semiconductor device 1, and heat dissipation to the terminal 120 can be suppressed.

[0101] In this case, the fifth FWD region 12e is covered by the protective film 46, and therefore its heat dissipation tends to be lower compared to the first to fourth FWD regions 12a to 12d that are exposed through the contact holes 46a of the protective film 46. Accordingly, in this embodiment, the width De of the fifth FWD region 12e is narrower than the widths Da to Dd of the first to fourth FWD regions 12a to 12d.

[0102] In this embodiment, the FWD region 12, in the region exposed from the contact hole 46a, has a width that is narrower in the central part in the second direction than in the width that is narrower in the edge part in the second direction.

[0103] According to the embodiment described above, since the widths of the IGBT region 11 and the FWD region 12 are the same as those of the third embodiment, the same effects as those of the third embodiment can be obtained.

[0104] (1) In this embodiment, the fifth FWD region 12e is positioned adjacent to the pad portion 21 in the first direction. Therefore, since the FWD region 12 is positioned in the region that was the outer peripheral region 20 in the first embodiment, the thermal resistance of the FWD region 12 can be reduced.

[0105] Furthermore, a deep layer 44 is formed in the outer peripheral region 20, surrounding the cell region 10 and connected to the base layer 32. Therefore, when the FWD element is turned on, holes can also be supplied from the deep layer 44. In this case, if the FWD region 12 is positioned adjacent to the pad region 21 in the second direction, the amount of holes supplied when the FWD element is turned on may become too large, potentially reducing the recovery tolerance. Therefore, in this embodiment, an IGBT region 11 is positioned adjacent to the pad region 21 in the second direction. This allows for an increase in the active region of the FWD region 12 while suppressing a decrease in recovery tolerance.

[0106] (2) In this embodiment, the width De of the fifth FWD region 12e is narrower than the widths Da to Dd of the first to fourth FWD regions 12a to 12d. Therefore, it is possible to suppress the temperature of the fifth FWD region 12e covered with the protective film 46 from rising.

[0107] (Modified version of the sixth embodiment) A modified version of the sixth embodiment described above will now be explained. In the sixth embodiment, as shown in Figure 18, the pad portion 21 may be arranged on one end side in the first direction of the cell region 10, adjacent to the fifth IGBT region 11e in the second direction.

[0108] Furthermore, as shown in Figure 19, the configuration in which the fifth FWD region 12e is arranged can also be applied to a configuration in which the IGBT region 11 and the FWD region 12 are arranged in a concentric frame.

[0109] Furthermore, in the sixth embodiment described above, the contact holes 46a formed in the protective film 46 may be formed to expose the fifth FWD region 12e. In this case, if the heat dissipation is higher than that of the first FWD region 12a due to the exposure of the fifth FWD region 12e from the protective film 46, the width De of the fifth FWD region 12e may be wider than the width Da of the first FWD region 12a.

[0110] Furthermore, in the sixth embodiment described above, the FWD region 12 may be positioned adjacent to the pad portion 21 in the second direction.

[0111] (Seventh Embodiment) The seventh embodiment will now be described. This embodiment is a modification of the sixth embodiment in which the shape of the fifth FWD region 12e is changed. Other aspects are the same as in the sixth embodiment, so their explanation will be omitted here.

[0112] First, the deep layer 44 is a planar frame shape, such as a square or circular shape with rounded corners. In this case, as in the sixth embodiment described above, if the fifth FWD region 12e is a rectangular frame shape, then at the end of the fifth FWD region 12e opposite to the pad portion 21 side, there are parts that are close and parts that are far in distance from the cathode layer 42 and the deep layer 44, and the electric field tends to concentrate in the part where the distance between the cathode layer 42 and the deep layer 44 is close. For this reason, in this embodiment, as shown in Figure 20, the fifth FWD region 12e is a planar shape in which the end C opposite to the pad portion 21 side in the first direction is rounded to correspond to the shape of the deep layer 44. This configuration is achieved by adjusting the planar shape of the cathode layer 42.

[0113] According to the embodiment described above, since the widths of the IGBT region 11 and the FWD region 12 are the same as those of the third embodiment, the same effects as those of the third embodiment can be obtained.

[0114] (1) In this embodiment, the fifth FWD region 12e has a planar shape in which the end C opposite to the pad portion 21 side in the first direction is rounded so as to correspond to the corner of the deep layer 44. Therefore, variations in the distance between the cathode layer 42 and the deep layer 44 can be reduced, making it difficult to generate electric field concentration.

[0115] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure.

[0116] For example, in the embodiments described above, an example was described in which the first conductivity type was N-type and the second conductivity type was P-type, but it is also possible to set the first conductivity type to P-type and the second conductivity type to N-type.

[0117] Furthermore, in each of the above embodiments, the semiconductor device 1 may be a planar type in which the gate electrode 35 is arranged on one surface 30a of the semiconductor substrate 30, rather than a trench gate type.

[0118] Furthermore, in each of the above embodiments, the gate electrode 35 of the FWD region 12 does not have to be connected to the upper electrode 39. Also, in each of the above embodiments, the FWD region 12 does not have to have a trench gate structure, nor does it have to have an emitter region 36.

[0119] Furthermore, the above embodiments can be combined as appropriate. For example, the second embodiment may be combined as appropriate so that the width of the region located in the central part in the second direction of the FWD region 12 is narrower than the width of the region located on the edge side in the second direction. In this case, the widths of each IGBT region 11 may be equal to each other. Also, the fourth embodiment may be combined as appropriate so that the width Le of the fifth IGBT region 11e located on the pad portion 21 side is narrower than the width La of the first IGBT region 11a. The fifth embodiment may be combined as appropriate so that the width Dd of the fourth FWD region 12d located on the pad portion 21 side is narrower than the width Da of the first FWD region 12a.

[0120] [Disclosure of the Invention] The above disclosure can be understood from the following perspectives, for example. [First point of view] A semiconductor device, A semiconductor substrate (30) having a cell region (10) and an outer peripheral region (20) surrounding the cell region, An IGBT region (11) formed in the cell region and having an IGBT element, The cell region comprises an FWD region (12) formed therein and having an FWD element, In one direction in the planar direction of the semiconductor substrate, the IGBT region and the FWD region are formed alternately. A semiconductor device in which three or more IGBT regions are formed in one direction, and when the length along the one direction is defined as the width, the width of the region located towards the center in the one direction is narrower than the width of the region located towards the edge in the one direction.

[0121] [Second perspective] The number of IGBT regions along the aforementioned one direction is set to X, which is an odd number of 3 or more. The semiconductor device according to the first aspect, wherein the IGBT region is narrowest in width in the region located at the {(X+1) / 2}th position along the one direction.

[0122] [Third perspective] The number of IGBT regions along the aforementioned one direction is set to X, which is an even number of 4 or more. The semiconductor device according to the first aspect, wherein the IGBT region is narrowest and has the same width as the (X / 2)th region and the {(X / 2)+1}th region along the one direction.

[0123] [Fourth perspective] The outer peripheral region has a pad portion (21) that is connected to an external terminal portion (140), The semiconductor device according to any one of the first to third aspects, wherein the IGBT region has a width that is greater in the region closest to the pad portion than in the region furthest from the pad portion.

[0124] [Fifth perspective] The semiconductor device according to any one of the first to fourth views, wherein the IGBT region has a ratio of 1.5 to 4.5 between the width of the region located on the edge side in one direction and the width of the region located on the central side in one direction.

[0125] [Sixth perspective] The semiconductor device according to any one of the first to fifth views, wherein three or more FWD regions are formed in one direction, and the width of the region located on the central side in one direction is narrower than the width of the region located on the edge side in one direction.

[0126] [Seventh perspective] A semiconductor device, A semiconductor substrate (30) having a cell region (10) and an outer peripheral region (20) surrounding the cell region, An IGBT region (11) formed in the cell region and having an IGBT element, The cell region comprises an FWD region (12) having an FWD element, In one direction in the planar direction of the semiconductor substrate, the IGBT region and the FWD region are formed alternately. A semiconductor device wherein three or more FWD regions are formed in one direction, and when the length along the one direction is defined as the width, the width of the region located towards the center in the one direction is narrower than the width of the region located towards the edge in the one direction.

[0127] [Perspective 8] The number of FWD regions along the aforementioned one direction is set to X, which is an odd number of 3 or more. The semiconductor device according to the sixth or seventh aspect, wherein the FWD region is the narrowest in width of the region located at the {(X+1) / 2}th position along the one direction.

[0128] [Perspective 9] The number of FWD regions along the aforementioned one direction is set to X, which is an even number of 4 or more. The semiconductor device according to the sixth or seventh aspect, wherein the FWD region is narrowest and has the same width as the (X / 2)th region and the {(X / 2)+1}th region along the one direction.

[0129] [Perspective 10] The outer peripheral region has a pad portion (21) that is connected to an external terminal portion (140), The semiconductor device according to the sixth or seventh aspect, wherein the FWD region has a width that is greater in the region closest to the pad portion than in the region furthest from the pad portion.

[0130] [Perspective 11] The semiconductor device according to any one of the sixth to tenth views, wherein the FWD region has a ratio of 1.5 to 4.5 between the width of the region located on the edge side in one direction and the width of the region located on the central side in one direction.

[0131] [Perspective 12] The outer peripheral region has a pad portion (21) that is connected to an external terminal portion (140), The FWD region has an additional FWD region (12e) adjacent to the pad portion in an intersecting direction that intersects with the aforementioned one direction. The semiconductor device according to any one of the sixth to eleventh views, wherein the IGBT region is located at a position adjacent to the pad portion in one direction.

[0132] [Perspective 13] The protective film (46) has contact holes (46a) formed therein that expose the cell region, The additional FWD region is covered with the protective film. The semiconductor device according to the twelfth aspect, wherein the FWD region is a region exposed from the contact hole, and the width of the region located on the central side in one direction is narrower than the width of the region located on the edge side in one direction, and the width of the additional FWD region is narrower than the width of the FWD region exposed from the contact hole.

[0133] [Perspective 14] The aforementioned semiconductor substrate is The IGBT comprises a first conductivity type drift layer (31), a second conductivity type base layer (32) formed on the surface of the drift layer in the cell region, a first conductivity type emitter region (36) formed on the surface of the base layer in the IGBT region, spaced apart from the drift layer and having a higher impurity concentration than the drift layer, a second conductivity type collector layer (41) formed on the side of the drift layer opposite to the base layer in the IGBT region, and a first conductivity type cathode layer (42) formed on the side of the drift layer opposite to the base layer in the FWD region. In the outer peripheral region, a second conductive deep layer (44) is formed at the boundary with the cell region, connecting to the base layer and surrounding the cell region. The deep layer is shaped like a flat frame with rounded corners. The semiconductor device according to the 12th or 13th aspect, wherein the additional FWD region has a planar shape, with the end (C) in the crossing direction being rounded so as to correspond to the corner of the deep layer, with the end opposite to the pad portion side being rounded. [Explanation of Symbols]

[0134] 10 cell area 11 IGBT area 12 FWD area 20 Outer area

Claims

1. A semiconductor device, A semiconductor substrate (30) having a cell region (10) and an outer peripheral region (20) surrounding the cell region, An IGBT region (11) formed in the cell region and having an IGBT element, The cell region comprises an FWD region (12) having an FWD element, In one direction in the plane direction of the semiconductor substrate, the IGBT region and the FWD region are formed alternately. The IGBT region is formed in three or more directions, and if the length along the direction is defined as the width, the width of the region located towards the center in the direction is narrower than the width of the region located towards the end in the direction. The number of IGBT regions along the aforementioned one direction is set to X, which is an odd number of 3 or more. The IGBT region has the narrowest width in the region located at the {(X+1) / 2}th position along the aforementioned direction. The semiconductor device is characterized in that three or more FWD regions are formed in one direction, and the width of the region located towards the central part in that direction is narrower than the width of the region located towards the edge in that direction.

2. A semiconductor device, A semiconductor substrate (30) having a cell region (10) and an outer peripheral region (20) surrounding the cell region, An IGBT region (11) formed in the cell region and having an IGBT element, The cell region comprises an FWD region (12) having an FWD element, In one direction in the plane direction of the semiconductor substrate, the IGBT region and the FWD region are formed alternately. The IGBT region is formed in three or more directions, and if the length along the direction is defined as the width, the width of the region located towards the center in the direction is narrower than the width of the region located towards the end in the direction. The number of IGBT regions along the aforementioned one direction is set to X, which is an even number of 4 or more. The IGBT region is such that the width of the region located at the (X / 2)th position and the region located at the {(X / 2)+1}th position along the one direction are equal and the region is as narrow as possible. The semiconductor device is characterized in that three or more FWD regions are formed in one direction, and the width of the region located towards the central part in that direction is narrower than the width of the region located towards the edge in that direction.

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